linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.460108                       # Number of seconds simulated
sim_ticks                                460107924500                       # Number of ticks simulated
final_tick                               460107924500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  59697                       # Simulator instruction rate (inst/s)
host_op_rate                                   110386                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               33217787                       # Simulator tick rate (ticks/s)
host_mem_usage                                 263000                       # Number of bytes of host memory used
host_seconds                                 13851.25                       # Real time elapsed on the host
sim_insts                                   826877144                       # Number of instructions simulated
sim_ops                                    1528988756                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read                    37486912                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                 378624                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                 26317760                       # Number of bytes written to this memory
system.physmem.num_reads                       585733                       # Number of read requests responded to by this memory
system.physmem.num_writes                      411215                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                       81474172                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                    822903                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write                      57199102                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total                     138673273                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                        920215850                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                225637815                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted          225637815                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect           14289291                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups             160516526                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                155855542                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles          191547382                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1262992642                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   225637815                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          155855542                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     392021264                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                98465808                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              234027765                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                26184                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        270251                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                 183405801                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               3663632                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          901816172                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.595997                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.389419                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                514254997     57.02%     57.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 25968939      2.88%     59.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 29098594      3.23%     63.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 30321386      3.36%     66.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 19622378      2.18%     68.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 25616419      2.84%     71.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 32613002      3.62%     75.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 30831455      3.42%     78.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                193489002     21.46%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            901816172                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.245201                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.372496                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                252794809                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             186036258                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 330006285                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              49055494                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               83923326                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2290111824                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles               83923326                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                289463344                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                42750657                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          14592                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 340217218                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             145447035                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2240140505                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  3227                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               23735126                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents             104491412                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands          2078098051                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5261736827                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       5260872310                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups            864517                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1427299027                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                650799024                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               1282                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           1271                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 348171673                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            540080847                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           217272434                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         215393524                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         63213343                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2142982647                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               62293                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1846789239                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1603792                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       612307626                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    971971651                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          61740                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     901816172                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.047856                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.805282                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           246447632     27.33%     27.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           157137359     17.42%     44.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           150782303     16.72%     61.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           147402025     16.35%     77.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           103278327     11.45%     89.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            58944184      6.54%     95.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            27765839      3.08%     98.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             9016087      1.00%     99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1042416      0.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       901816172                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 2649753     16.80%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.80% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                9923154     62.91%     79.71% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3201078     20.29%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2725633      0.15%      0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1219452054     66.03%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.18% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            447143707     24.21%     90.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           177467845      9.61%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1846789239                       # Type of FU issued
system.cpu.iq.rate                           2.006909                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    15773985                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.008541                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         4612764501                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2755319104                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1806286815                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                7926                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             295108                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          254                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1859834785                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                    2806                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        168142861                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    155978687                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       426493                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       273307                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     68112538                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         6604                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked             5                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               83923326                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 7067341                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1165909                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2143044940                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           2779083                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             540080847                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            217272723                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               5880                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 921481                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 15876                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         273307                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       10083404                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      5246002                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             15329406                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1818781271                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             438673892                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          28007968                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    610552632                       # number of memory reference insts executed
system.cpu.iew.exec_branches                170822936                       # Number of branches executed
system.cpu.iew.exec_stores                  171878740                       # Number of stores executed
system.cpu.iew.exec_rate                     1.976472                       # Inst execution rate
system.cpu.iew.wb_sent                     1813583044                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1806287069                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1379599827                       # num instructions producing a value
system.cpu.iew.wb_consumers                2050187147                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.962895                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.672914                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      826877144                       # The number of committed instructions
system.cpu.commit.commitCommittedOps       1528988756                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts       614080092                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          14315856                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    817892846                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.869424                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.327438                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    301647537     36.88%     36.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    204220955     24.97%     61.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     73668560      9.01%     70.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     95020529     11.62%     82.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     30882746      3.78%     86.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     28791442      3.52%     89.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     16321974      2.00%     91.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     11763768      1.44%     93.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     55575335      6.79%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    817892846                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            826877144                       # Number of instructions committed
system.cpu.commit.committedOps             1528988756                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      533262345                       # Number of memory references committed
system.cpu.commit.loads                     384102160                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  149758588                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
system.cpu.commit.function_calls                    0                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              55575335                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   2905386359                       # The number of ROB reads
system.cpu.rob.rob_writes                  4370176424                       # The number of ROB writes
system.cpu.timesIdled                          410524                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        18399678                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   826877144                       # Number of Instructions Simulated
system.cpu.committedOps                    1528988756                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             826877144                       # Number of Instructions Simulated
system.cpu.cpi                               1.112881                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.112881                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.898569                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.898569                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3086863683                       # number of integer regfile reads
system.cpu.int_regfile_writes              1679046201                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       253                       # number of floating regfile reads
system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
system.cpu.misc_regfile_reads              1001956200                       # number of misc regfile reads
system.cpu.icache.replacements                  10582                       # number of replacements
system.cpu.icache.tagsinuse                994.041407                       # Cycle average of tags in use
system.cpu.icache.total_refs                183174422                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  12099                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               15139.633193                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     994.041407                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.485372                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.485372                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    183181303                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       183181303                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     183181303                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        183181303                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    183181303                       # number of overall hits
system.cpu.icache.overall_hits::total       183181303                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       224498                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        224498                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       224498                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         224498                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       224498                       # number of overall misses
system.cpu.icache.overall_misses::total        224498                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1640944500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1640944500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1640944500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1640944500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1640944500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1640944500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    183405801                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    183405801                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    183405801                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    183405801                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    183405801                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    183405801                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001224                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.001224                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.001224                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  7309.394738                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  7309.394738                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  7309.394738                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks            8                       # number of writebacks
system.cpu.icache.writebacks::total                 8                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2528                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2528                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2528                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2528                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2528                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2528                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       221970                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       221970                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       221970                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       221970                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       221970                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       221970                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    915300500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    915300500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    915300500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    915300500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    915300500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    915300500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001210                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001210                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001210                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4123.532459                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4123.532459                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4123.532459                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                2526943                       # number of replacements
system.cpu.dcache.tagsinuse               4087.013788                       # Cycle average of tags in use
system.cpu.dcache.total_refs                415067708                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                2531039                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 163.991036                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             2117980000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4087.013788                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.997806                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.997806                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    266225231                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       266225231                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148171071                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148171071                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     414396302                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        414396302                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    414396302                       # number of overall hits
system.cpu.dcache.overall_hits::total       414396302                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2666540                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2666540                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       989130                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       989130                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      3655670                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3655670                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3655670                       # number of overall misses
system.cpu.dcache.overall_misses::total       3655670                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  38988147500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  38988147500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  20140670500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  20140670500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  59128818000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  59128818000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  59128818000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  59128818000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    268891771                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    268891771                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160201                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    418051972                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    418051972                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    418051972                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    418051972                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009917                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006631                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.008745                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.008745                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14621.249822                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20362.005500                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16174.550219                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16174.550219                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2228961                       # number of writebacks
system.cpu.dcache.writebacks::total           2228961                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       905583                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       905583                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         9205                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         9205                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       914788                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       914788                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       914788                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       914788                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1760957                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1760957                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       979925                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       979925                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2740882                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2740882                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2740882                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2740882                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  14913752500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  14913752500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17128067500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  17128067500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  32041820000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  32041820000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  32041820000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  32041820000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006549                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006570                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006556                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006556                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8469.117928                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17478.957573                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11690.331798                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11690.331798                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                574923                       # number of replacements
system.cpu.l2cache.tagsinuse             21610.762617                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3193774                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                594114                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  5.375692                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          253017747000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 13759.541955                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst     63.216767                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   7788.003895                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.419908                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.001929                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.237671                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.659508                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         6104                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1427022                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1433126                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      2228969                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2228969                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         1305                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         1305                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       524074                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       524074                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         6104                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1951096                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1957200                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         6104                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1951096                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1957200                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         5916                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       332816                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       338732                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data       208530                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total       208530                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       247038                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       247038                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         5916                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       579854                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        585770                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         5916                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       579854                       # number of overall misses
system.cpu.l2cache.overall_misses::total       585770                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    202632500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11362833000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  11565465500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      9919500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      9919500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8463656500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8463656500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    202632500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  19826489500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  20029122000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    202632500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  19826489500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  20029122000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        12020                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1759838                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1771858                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      2228969                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2228969                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data       209835                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total       209835                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       771112                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       771112                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        12020                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2530950                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2542970                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        12020                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2530950                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2542970                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.492180                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.189117                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.993781                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.320366                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.492180                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.229105                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.492180                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.229105                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34251.605815                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34141.486587                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    47.568695                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34260.544936                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34251.605815                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34192.209591                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34251.605815                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34192.209591                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       411215                       # number of writebacks
system.cpu.l2cache.writebacks::total           411215                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         5916                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       332816                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       338732                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       208530                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total       208530                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       247038                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       247038                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         5916                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       579854                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       585770                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         5916                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       579854                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       585770                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    183580000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10325106000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10508686000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   6464792000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   6464792000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7658792000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7658792000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    183580000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  17983898000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  18167478000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    183580000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  17983898000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  18167478000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.492180                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.189117                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.993781                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.320366                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.492180                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229105                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.492180                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229105                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31031.102096                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.466420                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.735961                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.485448                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31031.102096                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.527795                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31031.102096                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.527795                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------