stats.txt revision 11441:0edcf757b6a2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.481958 # Number of seconds simulated 4sim_ticks 481957625500 # Number of ticks simulated 5final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 104668 # Simulator instruction rate (inst/s) 8host_op_rate 193689 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 61009723 # Simulator tick rate (ticks/s) 10host_mem_usage 318640 # Number of bytes of host memory used 11host_seconds 7899.69 # Real time elapsed on the host 12sim_insts 826847303 # Number of instructions simulated 13sim_ops 1530082520 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 154624 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18874880 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18874880 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2416 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 384439 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 386855 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 294920 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 294920 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 320825 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 51050330 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 51371155 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 320825 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 320825 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 39162945 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 39162945 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 39162945 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 320825 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 51050330 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 90534100 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 386855 # Number of read requests accepted 40system.physmem.writeReqs 294920 # Number of write requests accepted 41system.physmem.readBursts 386855 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 294920 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24737792 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 20928 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18873280 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24758720 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18874880 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 327 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24516 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26460 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24685 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24442 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23203 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23588 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24636 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24397 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23786 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23509 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24817 # Per bank write bursts 62system.physmem.perBankRdBursts::11 23975 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23290 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22963 # Per bank write bursts 65system.physmem.perBankRdBursts::14 23965 # Per bank write bursts 66system.physmem.perBankRdBursts::15 24296 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18881 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19925 # Per bank write bursts 69system.physmem.perBankWrBursts::2 19022 # Per bank write bursts 70system.physmem.perBankWrBursts::3 18969 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18086 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18421 # Per bank write bursts 73system.physmem.perBankWrBursts::6 19142 # Per bank write bursts 74system.physmem.perBankWrBursts::7 19085 # Per bank write bursts 75system.physmem.perBankWrBursts::8 18675 # Per bank write bursts 76system.physmem.perBankWrBursts::9 17903 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18899 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17761 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17398 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16983 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17797 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17948 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 481957508500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 386855 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 294920 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 381052 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 5169 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 278 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 6623 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 7003 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16980 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17588 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17593 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17583 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 17584 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 17617 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 17604 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 17655 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17615 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17685 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17703 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 17675 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 17789 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17559 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17489 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 33 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 150272 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 290.205707 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 171.657717 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 319.431199 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 56562 37.64% 37.64% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 41303 27.49% 65.13% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13716 9.13% 74.25% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7600 5.06% 79.31% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5568 3.71% 83.02% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 3790 2.52% 85.54% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 2987 1.99% 87.53% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2640 1.76% 89.28% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16106 10.72% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 150272 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17470 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.124900 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 243.906372 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17461 99.95% 99.95% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::29696-30719 1 0.01% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 17470 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 17470 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.880080 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.823698 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 2.084974 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16-19 17271 98.86% 98.86% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::20-23 152 0.87% 99.73% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-27 24 0.14% 99.87% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::28-31 6 0.03% 99.90% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::36-39 4 0.02% 99.94% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-43 4 0.02% 99.97% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::44-47 1 0.01% 99.97% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-51 1 0.01% 99.98% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-59 1 0.01% 99.98% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::60-63 1 0.01% 99.99% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::88-91 1 0.01% 99.99% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::total 17470 # Writes before turning the bus around for reads 237system.physmem.totQLat 4249579000 # Total ticks spent queuing 238system.physmem.totMemAccLat 11496979000 # Total ticks spent from burst creation until serviced by the DRAM 239system.physmem.totBusLat 1932640000 # Total ticks spent in databus transfers 240system.physmem.avgQLat 10994.23 # Average queueing delay per DRAM burst 241system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 242system.physmem.avgMemAccLat 29744.23 # Average memory access latency per DRAM burst 243system.physmem.avgRdBW 51.33 # Average DRAM read bandwidth in MiByte/s 244system.physmem.avgWrBW 39.16 # Average achieved write bandwidth in MiByte/s 245system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s 246system.physmem.avgWrBWSys 39.16 # Average system write bandwidth in MiByte/s 247system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 248system.physmem.busUtil 0.71 # Data bus utilization in percentage 249system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads 250system.physmem.busUtilWrite 0.31 # Data bus utilization in percentage for writes 251system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 252system.physmem.avgWrQLen 20.94 # Average write queue length when enqueuing 253system.physmem.readRowHits 315674 # Number of row buffer hits during reads 254system.physmem.writeRowHits 215465 # Number of row buffer hits during writes 255system.physmem.readRowHitRate 81.67 # Row buffer hit rate for reads 256system.physmem.writeRowHitRate 73.06 # Row buffer hit rate for writes 257system.physmem.avgGap 706915.78 # Average gap between requests 258system.physmem.pageHitRate 77.94 # Row buffer hit rate, read and write combined 259system.physmem_0.actEnergy 581999040 # Energy for activate commands per rank (pJ) 260system.physmem_0.preEnergy 317559000 # Energy for precharge commands per rank (pJ) 261system.physmem_0.readEnergy 1528152600 # Energy for read commands per rank (pJ) 262system.physmem_0.writeEnergy 981784800 # Energy for write commands per rank (pJ) 263system.physmem_0.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) 264system.physmem_0.actBackEnergy 70268579415 # Energy for active background per rank (pJ) 265system.physmem_0.preBackEnergy 227533024500 # Energy for precharge background per rank (pJ) 266system.physmem_0.totalEnergy 332689946235 # Total energy per rank (pJ) 267system.physmem_0.averagePower 690.294629 # Core power per rank (mW) 268system.physmem_0.memoryStateTime::IDLE 377929772750 # Time in different power states 269system.physmem_0.memoryStateTime::REF 16093480000 # Time in different power states 270system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 271system.physmem_0.memoryStateTime::ACT 87930818250 # Time in different power states 272system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 273system.physmem_1.actEnergy 553777560 # Energy for activate commands per rank (pJ) 274system.physmem_1.preEnergy 302160375 # Energy for precharge commands per rank (pJ) 275system.physmem_1.readEnergy 1486375800 # Energy for read commands per rank (pJ) 276system.physmem_1.writeEnergy 928823760 # Energy for write commands per rank (pJ) 277system.physmem_1.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) 278system.physmem_1.actBackEnergy 68021430795 # Energy for active background per rank (pJ) 279system.physmem_1.preBackEnergy 229504207500 # Energy for precharge background per rank (pJ) 280system.physmem_1.totalEnergy 332275622670 # Total energy per rank (pJ) 281system.physmem_1.averagePower 689.434954 # Core power per rank (mW) 282system.physmem_1.memoryStateTime::IDLE 381228600750 # Time in different power states 283system.physmem_1.memoryStateTime::REF 16093480000 # Time in different power states 284system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states 286system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 287system.cpu.branchPred.lookups 297786504 # Number of BP lookups 288system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted 289system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect 290system.cpu.branchPred.BTBLookups 229702188 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 0 # Number of BTB hits 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 293system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 40293529 # Number of times the RAS was used to get a target. 295system.cpu.branchPred.RASInCorrect 4405587 # Number of incorrect RAS predictions. 296system.cpu.branchPred.indirectLookups 229702188 # Number of indirect predictor lookups. 297system.cpu.branchPred.indirectHits 119907455 # Number of indirect target hits. 298system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. 299system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. 300system.cpu_clk_domain.clock 500 # Clock period in ticks 301system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 302system.cpu.workload.num_syscalls 551 # Number of system calls 303system.cpu.numCycles 963915252 # number of cpu cycles simulated 304system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 305system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 306system.cpu.fetch.icacheStallCycles 229572933 # Number of cycles fetch is stalled on an Icache miss 307system.cpu.fetch.Insts 1587362959 # Number of instructions fetch has processed 308system.cpu.fetch.Branches 297786504 # Number of branches that fetch encountered 309system.cpu.fetch.predictedBranches 160200984 # Number of branches that fetch has predicted taken 310system.cpu.fetch.Cycles 709710694 # Number of cycles fetch has run and was not squashing or blocked 311system.cpu.fetch.SquashCycles 48100941 # Number of cycles fetch has spent squashing 312system.cpu.fetch.TlbCycles 1387 # Number of cycles fetch has spent waiting for tlb 313system.cpu.fetch.MiscStallCycles 31814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 314system.cpu.fetch.PendingTrapStallCycles 398605 # Number of stall cycles due to pending traps 315system.cpu.fetch.PendingQuiesceStallCycles 6640 # Number of stall cycles due to pending quiesce instructions 316system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR 317system.cpu.fetch.CacheLines 216353847 # Number of cache lines fetched 318system.cpu.fetch.IcacheSquashes 6306355 # Number of outstanding Icache misses that were squashed 319system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed 320system.cpu.fetch.rateDist::samples 963772561 # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::mean 3.083618 # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::stdev 3.495232 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::0 472321182 49.01% 49.01% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::1 36440853 3.78% 52.79% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::2 36199829 3.76% 56.54% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::3 33073350 3.43% 59.98% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::4 28557183 2.96% 62.94% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::5 29987754 3.11% 66.05% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::6 40189317 4.17% 70.22% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::7 37482048 3.89% 74.11% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::8 249521045 25.89% 100.00% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::total 963772561 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.branchRate 0.308934 # Number of branch fetches per cycle 338system.cpu.fetch.rate 1.646787 # Number of inst fetches per cycle 339system.cpu.decode.IdleCycles 165558629 # Number of cycles decode is idle 340system.cpu.decode.BlockedCycles 380809572 # Number of cycles decode is blocked 341system.cpu.decode.RunCycles 312283336 # Number of cycles decode is running 342system.cpu.decode.UnblockCycles 81070554 # Number of cycles decode is unblocking 343system.cpu.decode.SquashCycles 24050470 # Number of cycles decode is squashing 344system.cpu.decode.DecodedInsts 2743818074 # Number of instructions handled by decode 345system.cpu.rename.SquashCycles 24050470 # Number of cycles rename is squashing 346system.cpu.rename.IdleCycles 201592178 # Number of cycles rename is idle 347system.cpu.rename.BlockCycles 193949048 # Number of cycles rename is blocking 348system.cpu.rename.serializeStallCycles 12373 # count of cycles rename stalled for serializing inst 349system.cpu.rename.RunCycles 351358358 # Number of cycles rename is running 350system.cpu.rename.UnblockCycles 192810134 # Number of cycles rename is unblocking 351system.cpu.rename.RenamedInsts 2626442761 # Number of instructions processed by rename 352system.cpu.rename.ROBFullEvents 758361 # Number of times rename has blocked due to ROB full 353system.cpu.rename.IQFullEvents 120779385 # Number of times rename has blocked due to IQ full 354system.cpu.rename.LQFullEvents 21914925 # Number of times rename has blocked due to LQ full 355system.cpu.rename.SQFullEvents 41340162 # Number of times rename has blocked due to SQ full 356system.cpu.rename.RenamedOperands 2707324732 # Number of destination operands rename has renamed 357system.cpu.rename.RenameLookups 6591643908 # Number of register rename lookups that rename has made 358system.cpu.rename.int_rename_lookups 4206582921 # Number of integer rename lookups 359system.cpu.rename.fp_rename_lookups 2532048 # Number of floating rename lookups 360system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed 361system.cpu.rename.UndoneMaps 1090363160 # Number of HB maps that are undone due to squashing 362system.cpu.rename.serializingInsts 921 # count of serializing insts renamed 363system.cpu.rename.tempSerializingInsts 827 # count of temporary serializing insts renamed 364system.cpu.rename.skidInsts 369363812 # count of insts added to the skid buffer 365system.cpu.memDep0.insertedLoads 608309859 # Number of loads inserted to the mem dependence unit. 366system.cpu.memDep0.insertedStores 244105032 # Number of stores inserted to the mem dependence unit. 367system.cpu.memDep0.conflictingLoads 253215291 # Number of conflicting loads. 368system.cpu.memDep0.conflictingStores 76456984 # Number of conflicting stores. 369system.cpu.iq.iqInstsAdded 2419527437 # Number of instructions added to the IQ (excludes non-spec) 370system.cpu.iq.iqNonSpecInstsAdded 123521 # Number of non-speculative instructions added to the IQ 371system.cpu.iq.iqInstsIssued 1999245990 # Number of instructions issued 372system.cpu.iq.iqSquashedInstsIssued 3630215 # Number of squashed instructions issued 373system.cpu.iq.iqSquashedInstsExamined 889568438 # Number of squashed instructions iterated over during squash; mainly for profiling 374system.cpu.iq.iqSquashedOperandsExamined 1509945066 # Number of squashed operands that are examined and possibly removed from graph 375system.cpu.iq.iqSquashedNonSpecRemoved 122969 # Number of squashed non-spec instructions that were removed 376system.cpu.iq.issued_per_cycle::samples 963772561 # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::mean 2.074396 # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::stdev 2.106547 # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::0 335335755 34.79% 34.79% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::1 135420425 14.05% 48.85% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::2 129949182 13.48% 62.33% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::3 118520110 12.30% 74.63% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::4 97996233 10.17% 84.79% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::5 67311922 6.98% 91.78% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::6 45709014 4.74% 96.52% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::7 22671115 2.35% 98.87% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::8 10858805 1.13% 100.00% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::total 963772561 # Number of insts issued each cycle 393system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 394system.cpu.iq.fu_full::IntAlu 11256438 43.50% 43.50% # attempts to use FU when none available 395system.cpu.iq.fu_full::IntMult 0 0.00% 43.50% # attempts to use FU when none available 396system.cpu.iq.fu_full::IntDiv 0 0.00% 43.50% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.50% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.50% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.50% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatMult 0 0.00% 43.50% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.50% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.50% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.50% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.50% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.50% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.50% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.50% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.50% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdMult 0 0.00% 43.50% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.50% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdShift 0 0.00% 43.50% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.50% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.50% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.50% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.50% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.50% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.50% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.50% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.50% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.50% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.50% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.50% # attempts to use FU when none available 423system.cpu.iq.fu_full::MemRead 11830784 45.72% 89.22% # attempts to use FU when none available 424system.cpu.iq.fu_full::MemWrite 2789302 10.78% 100.00% # attempts to use FU when none available 425system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 426system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 427system.cpu.iq.FU_type_0::No_OpClass 2910372 0.15% 0.15% # Type of FU issued 428system.cpu.iq.FU_type_0::IntAlu 1333563815 66.70% 66.85% # Type of FU issued 429system.cpu.iq.FU_type_0::IntMult 358658 0.02% 66.87% # Type of FU issued 430system.cpu.iq.FU_type_0::IntDiv 4798558 0.24% 67.11% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 67.11% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued 457system.cpu.iq.FU_type_0::MemRead 471264290 23.57% 90.68% # Type of FU issued 458system.cpu.iq.FU_type_0::MemWrite 186350287 9.32% 100.00% # Type of FU issued 459system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 460system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 461system.cpu.iq.FU_type_0::total 1999245990 # Type of FU issued 462system.cpu.iq.rate 2.074089 # Inst issue rate 463system.cpu.iq.fu_busy_cnt 25876524 # FU busy when requested 464system.cpu.iq.fu_busy_rate 0.012943 # FU busy rate (busy events/executed inst) 465system.cpu.iq.int_inst_queue_reads 4990508159 # Number of integer instruction queue reads 466system.cpu.iq.int_inst_queue_writes 3305732748 # Number of integer instruction queue writes 467system.cpu.iq.int_inst_queue_wakeup_accesses 1923901013 # Number of integer instruction queue wakeup accesses 468system.cpu.iq.fp_inst_queue_reads 1263121 # Number of floating instruction queue reads 469system.cpu.iq.fp_inst_queue_writes 4059650 # Number of floating instruction queue writes 470system.cpu.iq.fp_inst_queue_wakeup_accesses 238029 # Number of floating instruction queue wakeup accesses 471system.cpu.iq.int_alu_accesses 2021668252 # Number of integer alu accesses 472system.cpu.iq.fp_alu_accesses 543890 # Number of floating point alu accesses 473system.cpu.iew.lsq.thread0.forwLoads 179792885 # Number of loads that had data forwarded from stores 474system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 475system.cpu.iew.lsq.thread0.squashedLoads 224226629 # Number of loads squashed 476system.cpu.iew.lsq.thread0.ignoredResponses 339387 # Number of memory responses ignored because the instruction is squashed 477system.cpu.iew.lsq.thread0.memOrderViolation 641597 # Number of memory ordering violations 478system.cpu.iew.lsq.thread0.squashedStores 94946837 # Number of stores squashed 479system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 480system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 481system.cpu.iew.lsq.thread0.rescheduledLoads 32049 # Number of loads that were rescheduled 482system.cpu.iew.lsq.thread0.cacheBlocked 734 # Number of times an access to memory failed due to the cache being blocked 483system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 484system.cpu.iew.iewSquashCycles 24050470 # Number of cycles IEW is squashing 485system.cpu.iew.iewBlockCycles 144665099 # Number of cycles IEW is blocking 486system.cpu.iew.iewUnblockCycles 6487735 # Number of cycles IEW is unblocking 487system.cpu.iew.iewDispatchedInsts 2419650958 # Number of instructions dispatched to IQ 488system.cpu.iew.iewDispSquashedInsts 1303031 # Number of squashed instructions skipped by dispatch 489system.cpu.iew.iewDispLoadInsts 608309942 # Number of dispatched load instructions 490system.cpu.iew.iewDispStoreInsts 244105032 # Number of dispatched store instructions 491system.cpu.iew.iewDispNonSpecInsts 42573 # Number of dispatched non-speculative instructions 492system.cpu.iew.iewIQFullEvents 1493780 # Number of times the IQ has become full, causing a stall 493system.cpu.iew.iewLSQFullEvents 4140484 # Number of times the LSQ has become full, causing a stall 494system.cpu.iew.memOrderViolationEvents 641597 # Number of memory order violations 495system.cpu.iew.predictedTakenIncorrect 8724662 # Number of branches that were predicted taken incorrectly 496system.cpu.iew.predictedNotTakenIncorrect 20631512 # Number of branches that were predicted not taken incorrectly 497system.cpu.iew.branchMispredicts 29356174 # Number of branch mispredicts detected at execute 498system.cpu.iew.iewExecutedInsts 1945805936 # Number of executed instructions 499system.cpu.iew.iewExecLoadInsts 456837338 # Number of load instructions executed 500system.cpu.iew.iewExecSquashedInsts 53440054 # Number of squashed instructions skipped in execute 501system.cpu.iew.exec_swp 0 # number of swp insts executed 502system.cpu.iew.exec_nop 0 # number of nop insts executed 503system.cpu.iew.exec_refs 635668777 # number of memory reference insts executed 504system.cpu.iew.exec_branches 185171662 # Number of branches executed 505system.cpu.iew.exec_stores 178831439 # Number of stores executed 506system.cpu.iew.exec_rate 2.018648 # Inst execution rate 507system.cpu.iew.wb_sent 1934669445 # cumulative count of insts sent to commit 508system.cpu.iew.wb_count 1924139042 # cumulative count of insts written-back 509system.cpu.iew.wb_producers 1457092334 # num instructions producing a value 510system.cpu.iew.wb_consumers 2203939353 # num instructions consuming a value 511system.cpu.iew.wb_rate 1.996170 # insts written-back per cycle 512system.cpu.iew.wb_fanout 0.661131 # average fanout of values written-back 513system.cpu.commit.commitSquashedInsts 889643735 # The number of squashed insts skipped by commit 514system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards 515system.cpu.commit.branchMispredicts 23627115 # The number of times a branch was mispredicted 516system.cpu.commit.committed_per_cycle::samples 831081217 # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::mean 1.841075 # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::stdev 2.465971 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::0 351390819 42.28% 42.28% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::1 184611364 22.21% 64.49% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::2 57978208 6.98% 71.47% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::3 87188862 10.49% 81.96% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::4 30418140 3.66% 85.62% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::5 26591078 3.20% 88.82% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::6 10434720 1.26% 90.08% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::7 9032324 1.09% 91.16% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::8 73435702 8.84% 100.00% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::total 831081217 # Number of insts commited each cycle 533system.cpu.commit.committedInsts 826847303 # Number of instructions committed 534system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed 535system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 536system.cpu.commit.refs 533241508 # Number of memory references committed 537system.cpu.commit.loads 384083313 # Number of loads committed 538system.cpu.commit.membars 0 # Number of memory barriers committed 539system.cpu.commit.branches 149981740 # Number of branches committed 540system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 541system.cpu.commit.int_insts 1527470225 # Number of committed integer instructions. 542system.cpu.commit.function_calls 17673145 # Number of function calls committed. 543system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% # Class of committed instruction 544system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% # Class of committed instruction 545system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% # Class of committed instruction 546system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% # Class of committed instruction 547system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Class of committed instruction 548system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction 549system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction 550system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction 551system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction 552system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction 554system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction 555system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% # Class of committed instruction 556system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% # Class of committed instruction 559system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% # Class of committed instruction 560system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% # Class of committed instruction 561system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% # Class of committed instruction 562system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% # Class of committed instruction 563system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% # Class of committed instruction 564system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% # Class of committed instruction 567system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% # Class of committed instruction 568system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% # Class of committed instruction 569system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% # Class of committed instruction 570system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction 571system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction 573system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction 574system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction 575system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 576system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 577system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction 578system.cpu.commit.bw_lim_events 73435702 # number cycles where commit BW limit reached 579system.cpu.rob.rob_reads 3177371770 # The number of ROB reads 580system.cpu.rob.rob_writes 4973814894 # The number of ROB writes 581system.cpu.timesIdled 2014 # Number of times that the entire CPU went into an idle state and unscheduled itself 582system.cpu.idleCycles 142691 # Total number of cycles that the CPU has spent unscheduled due to idling 583system.cpu.committedInsts 826847303 # Number of Instructions Simulated 584system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated 585system.cpu.cpi 1.165772 # CPI: Cycles Per Instruction 586system.cpu.cpi_total 1.165772 # CPI: Total CPI of All Threads 587system.cpu.ipc 0.857801 # IPC: Instructions Per Cycle 588system.cpu.ipc_total 0.857801 # IPC: Total IPC of All Threads 589system.cpu.int_regfile_reads 2928585667 # number of integer regfile reads 590system.cpu.int_regfile_writes 1576867903 # number of integer regfile writes 591system.cpu.fp_regfile_reads 239177 # number of floating regfile reads 592system.cpu.fp_regfile_writes 8 # number of floating regfile writes 593system.cpu.cc_regfile_reads 617820038 # number of cc regfile reads 594system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes 595system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads 596system.cpu.misc_regfile_writes 1 # number of misc regfile writes 597system.cpu.dcache.tags.replacements 2545945 # number of replacements 598system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use 599system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. 600system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks. 601system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks. 602system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit. 603system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor 604system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy 605system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy 606system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 607system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 608system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 609system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id 610system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id 611system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 612system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses 613system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses 614system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits 615system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits 616system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits 617system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits 618system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits 619system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits 620system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits 621system.cpu.dcache.overall_hits::total 421064470 # number of overall hits 622system.cpu.dcache.ReadReq_misses::cpu.data 2566340 # number of ReadReq misses 623system.cpu.dcache.ReadReq_misses::total 2566340 # number of ReadReq misses 624system.cpu.dcache.WriteReq_misses::cpu.data 791267 # number of WriteReq misses 625system.cpu.dcache.WriteReq_misses::total 791267 # number of WriteReq misses 626system.cpu.dcache.demand_misses::cpu.data 3357607 # number of demand (read+write) misses 627system.cpu.dcache.demand_misses::total 3357607 # number of demand (read+write) misses 628system.cpu.dcache.overall_misses::cpu.data 3357607 # number of overall misses 629system.cpu.dcache.overall_misses::total 3357607 # number of overall misses 630system.cpu.dcache.ReadReq_miss_latency::cpu.data 57037182000 # number of ReadReq miss cycles 631system.cpu.dcache.ReadReq_miss_latency::total 57037182000 # number of ReadReq miss cycles 632system.cpu.dcache.WriteReq_miss_latency::cpu.data 24501570500 # number of WriteReq miss cycles 633system.cpu.dcache.WriteReq_miss_latency::total 24501570500 # number of WriteReq miss cycles 634system.cpu.dcache.demand_miss_latency::cpu.data 81538752500 # number of demand (read+write) miss cycles 635system.cpu.dcache.demand_miss_latency::total 81538752500 # number of demand (read+write) miss cycles 636system.cpu.dcache.overall_miss_latency::cpu.data 81538752500 # number of overall miss cycles 637system.cpu.dcache.overall_miss_latency::total 81538752500 # number of overall miss cycles 638system.cpu.dcache.ReadReq_accesses::cpu.data 275263866 # number of ReadReq accesses(hits+misses) 639system.cpu.dcache.ReadReq_accesses::total 275263866 # number of ReadReq accesses(hits+misses) 640system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) 641system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) 642system.cpu.dcache.demand_accesses::cpu.data 424422077 # number of demand (read+write) accesses 643system.cpu.dcache.demand_accesses::total 424422077 # number of demand (read+write) accesses 644system.cpu.dcache.overall_accesses::cpu.data 424422077 # number of overall (read+write) accesses 645system.cpu.dcache.overall_accesses::total 424422077 # number of overall (read+write) accesses 646system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009323 # miss rate for ReadReq accesses 647system.cpu.dcache.ReadReq_miss_rate::total 0.009323 # miss rate for ReadReq accesses 648system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses 649system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses 650system.cpu.dcache.demand_miss_rate::cpu.data 0.007911 # miss rate for demand accesses 651system.cpu.dcache.demand_miss_rate::total 0.007911 # miss rate for demand accesses 652system.cpu.dcache.overall_miss_rate::cpu.data 0.007911 # miss rate for overall accesses 653system.cpu.dcache.overall_miss_rate::total 0.007911 # miss rate for overall accesses 654system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.107351 # average ReadReq miss latency 655system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.107351 # average ReadReq miss latency 656system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30964.984639 # average WriteReq miss latency 657system.cpu.dcache.WriteReq_avg_miss_latency::total 30964.984639 # average WriteReq miss latency 658system.cpu.dcache.demand_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency 659system.cpu.dcache.demand_avg_miss_latency::total 24284.781542 # average overall miss latency 660system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency 661system.cpu.dcache.overall_avg_miss_latency::total 24284.781542 # average overall miss latency 662system.cpu.dcache.blocked_cycles::no_mshrs 8528 # number of cycles access was blocked 663system.cpu.dcache.blocked_cycles::no_targets 1295 # number of cycles access was blocked 664system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked 665system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked 666system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked 667system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked 668system.cpu.dcache.fast_writes 0 # number of fast writes performed 669system.cpu.dcache.cache_copies 0 # number of cache copies performed 670system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks 671system.cpu.dcache.writebacks::total 2337968 # number of writebacks 672system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits 673system.cpu.dcache.ReadReq_mshr_hits::total 800154 # number of ReadReq MSHR hits 674system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5753 # number of WriteReq MSHR hits 675system.cpu.dcache.WriteReq_mshr_hits::total 5753 # number of WriteReq MSHR hits 676system.cpu.dcache.demand_mshr_hits::cpu.data 805907 # number of demand (read+write) MSHR hits 677system.cpu.dcache.demand_mshr_hits::total 805907 # number of demand (read+write) MSHR hits 678system.cpu.dcache.overall_mshr_hits::cpu.data 805907 # number of overall MSHR hits 679system.cpu.dcache.overall_mshr_hits::total 805907 # number of overall MSHR hits 680system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766186 # number of ReadReq MSHR misses 681system.cpu.dcache.ReadReq_mshr_misses::total 1766186 # number of ReadReq MSHR misses 682system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785514 # number of WriteReq MSHR misses 683system.cpu.dcache.WriteReq_mshr_misses::total 785514 # number of WriteReq MSHR misses 684system.cpu.dcache.demand_mshr_misses::cpu.data 2551700 # number of demand (read+write) MSHR misses 685system.cpu.dcache.demand_mshr_misses::total 2551700 # number of demand (read+write) MSHR misses 686system.cpu.dcache.overall_mshr_misses::cpu.data 2551700 # number of overall MSHR misses 687system.cpu.dcache.overall_mshr_misses::total 2551700 # number of overall MSHR misses 688system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33673145000 # number of ReadReq MSHR miss cycles 689system.cpu.dcache.ReadReq_mshr_miss_latency::total 33673145000 # number of ReadReq MSHR miss cycles 690system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23618473500 # number of WriteReq MSHR miss cycles 691system.cpu.dcache.WriteReq_mshr_miss_latency::total 23618473500 # number of WriteReq MSHR miss cycles 692system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57291618500 # number of demand (read+write) MSHR miss cycles 693system.cpu.dcache.demand_mshr_miss_latency::total 57291618500 # number of demand (read+write) MSHR miss cycles 694system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57291618500 # number of overall MSHR miss cycles 695system.cpu.dcache.overall_mshr_miss_latency::total 57291618500 # number of overall MSHR miss cycles 696system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses 697system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses 698system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005266 # mshr miss rate for WriteReq accesses 699system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005266 # mshr miss rate for WriteReq accesses 700system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses 701system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses 702system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses 703system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses 704system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998 # average ReadReq mshr miss latency 705system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998 # average ReadReq mshr miss latency 706system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853 # average WriteReq mshr miss latency 707system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853 # average WriteReq mshr miss latency 708system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency 709system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency 710system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency 711system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency 712system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 713system.cpu.icache.tags.replacements 4014 # number of replacements 714system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use 715system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. 716system.cpu.icache.tags.sampled_refs 5738 # Sample count of references to valid blocks. 717system.cpu.icache.tags.avg_refs 37703.714883 # Average number of references to valid blocks. 718system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 719system.cpu.icache.tags.occ_blocks::cpu.inst 1083.903563 # Average occupied blocks per requestor 720system.cpu.icache.tags.occ_percent::cpu.inst 0.529250 # Average percentage of cache occupancy 721system.cpu.icache.tags.occ_percent::total 0.529250 # Average percentage of cache occupancy 722system.cpu.icache.tags.occ_task_id_blocks::1024 1724 # Occupied blocks per task id 723system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 724system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id 725system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 726system.cpu.icache.tags.age_task_id_blocks_1024::3 78 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::4 1566 # Occupied blocks per task id 728system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id 729system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses 730system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses 731system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits 732system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits 733system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits 734system.cpu.icache.demand_hits::total 216344175 # number of demand (read+write) hits 735system.cpu.icache.overall_hits::cpu.inst 216344175 # number of overall hits 736system.cpu.icache.overall_hits::total 216344175 # number of overall hits 737system.cpu.icache.ReadReq_misses::cpu.inst 9672 # number of ReadReq misses 738system.cpu.icache.ReadReq_misses::total 9672 # number of ReadReq misses 739system.cpu.icache.demand_misses::cpu.inst 9672 # number of demand (read+write) misses 740system.cpu.icache.demand_misses::total 9672 # number of demand (read+write) misses 741system.cpu.icache.overall_misses::cpu.inst 9672 # number of overall misses 742system.cpu.icache.overall_misses::total 9672 # number of overall misses 743system.cpu.icache.ReadReq_miss_latency::cpu.inst 343660500 # number of ReadReq miss cycles 744system.cpu.icache.ReadReq_miss_latency::total 343660500 # number of ReadReq miss cycles 745system.cpu.icache.demand_miss_latency::cpu.inst 343660500 # number of demand (read+write) miss cycles 746system.cpu.icache.demand_miss_latency::total 343660500 # number of demand (read+write) miss cycles 747system.cpu.icache.overall_miss_latency::cpu.inst 343660500 # number of overall miss cycles 748system.cpu.icache.overall_miss_latency::total 343660500 # number of overall miss cycles 749system.cpu.icache.ReadReq_accesses::cpu.inst 216353847 # number of ReadReq accesses(hits+misses) 750system.cpu.icache.ReadReq_accesses::total 216353847 # number of ReadReq accesses(hits+misses) 751system.cpu.icache.demand_accesses::cpu.inst 216353847 # number of demand (read+write) accesses 752system.cpu.icache.demand_accesses::total 216353847 # number of demand (read+write) accesses 753system.cpu.icache.overall_accesses::cpu.inst 216353847 # number of overall (read+write) accesses 754system.cpu.icache.overall_accesses::total 216353847 # number of overall (read+write) accesses 755system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 756system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 757system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 758system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 759system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 760system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 761system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35531.482630 # average ReadReq miss latency 762system.cpu.icache.ReadReq_avg_miss_latency::total 35531.482630 # average ReadReq miss latency 763system.cpu.icache.demand_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency 764system.cpu.icache.demand_avg_miss_latency::total 35531.482630 # average overall miss latency 765system.cpu.icache.overall_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency 766system.cpu.icache.overall_avg_miss_latency::total 35531.482630 # average overall miss latency 767system.cpu.icache.blocked_cycles::no_mshrs 348 # number of cycles access was blocked 768system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 769system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked 770system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 771system.cpu.icache.avg_blocked_cycles::no_mshrs 43.500000 # average number of cycles each access was blocked 772system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 773system.cpu.icache.fast_writes 0 # number of fast writes performed 774system.cpu.icache.cache_copies 0 # number of cache copies performed 775system.cpu.icache.writebacks::writebacks 4014 # number of writebacks 776system.cpu.icache.writebacks::total 4014 # number of writebacks 777system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2282 # number of ReadReq MSHR hits 778system.cpu.icache.ReadReq_mshr_hits::total 2282 # number of ReadReq MSHR hits 779system.cpu.icache.demand_mshr_hits::cpu.inst 2282 # number of demand (read+write) MSHR hits 780system.cpu.icache.demand_mshr_hits::total 2282 # number of demand (read+write) MSHR hits 781system.cpu.icache.overall_mshr_hits::cpu.inst 2282 # number of overall MSHR hits 782system.cpu.icache.overall_mshr_hits::total 2282 # number of overall MSHR hits 783system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7390 # number of ReadReq MSHR misses 784system.cpu.icache.ReadReq_mshr_misses::total 7390 # number of ReadReq MSHR misses 785system.cpu.icache.demand_mshr_misses::cpu.inst 7390 # number of demand (read+write) MSHR misses 786system.cpu.icache.demand_mshr_misses::total 7390 # number of demand (read+write) MSHR misses 787system.cpu.icache.overall_mshr_misses::cpu.inst 7390 # number of overall MSHR misses 788system.cpu.icache.overall_mshr_misses::total 7390 # number of overall MSHR misses 789system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243725000 # number of ReadReq MSHR miss cycles 790system.cpu.icache.ReadReq_mshr_miss_latency::total 243725000 # number of ReadReq MSHR miss cycles 791system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243725000 # number of demand (read+write) MSHR miss cycles 792system.cpu.icache.demand_mshr_miss_latency::total 243725000 # number of demand (read+write) MSHR miss cycles 793system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243725000 # number of overall MSHR miss cycles 794system.cpu.icache.overall_mshr_miss_latency::total 243725000 # number of overall MSHR miss cycles 795system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses 796system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses 797system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses 798system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses 799system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses 800system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses 801system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # average ReadReq mshr miss latency 802system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890 # average ReadReq mshr miss latency 803system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency 804system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency 805system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency 806system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency 807system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 808system.cpu.l2cache.tags.replacements 355161 # number of replacements 809system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use 810system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks. 811system.cpu.l2cache.tags.sampled_refs 387527 # Sample count of references to valid blocks. 812system.cpu.l2cache.tags.avg_refs 10.087813 # Average number of references to valid blocks. 813system.cpu.l2cache.tags.warmup_cycle 233930910500 # Cycle when the warmup percentage was hit. 814system.cpu.l2cache.tags.occ_blocks::writebacks 20962.660906 # Average occupied blocks per requestor 815system.cpu.l2cache.tags.occ_blocks::cpu.inst 196.060575 # Average occupied blocks per requestor 816system.cpu.l2cache.tags.occ_blocks::cpu.data 8445.972818 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_percent::writebacks 0.639730 # Average percentage of cache occupancy 818system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005983 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_percent::cpu.data 0.257751 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::total 0.903464 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_task_id_blocks::1024 32366 # Occupied blocks per task id 822system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 823system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 824system.cpu.l2cache.tags.age_task_id_blocks_1024::2 235 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11314 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20752 # Occupied blocks per task id 827system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987732 # Percentage of cache occupancy per task id 828system.cpu.l2cache.tags.tag_accesses 41979246 # Number of tag accesses 829system.cpu.l2cache.tags.data_accesses 41979246 # Number of data accesses 830system.cpu.l2cache.WritebackDirty_hits::writebacks 2337968 # number of WritebackDirty hits 831system.cpu.l2cache.WritebackDirty_hits::total 2337968 # number of WritebackDirty hits 832system.cpu.l2cache.WritebackClean_hits::writebacks 3923 # number of WritebackClean hits 833system.cpu.l2cache.WritebackClean_hits::total 3923 # number of WritebackClean hits 834system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits 835system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits 836system.cpu.l2cache.ReadExReq_hits::cpu.data 577397 # number of ReadExReq hits 837system.cpu.l2cache.ReadExReq_hits::total 577397 # number of ReadExReq hits 838system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3252 # number of ReadCleanReq hits 839system.cpu.l2cache.ReadCleanReq_hits::total 3252 # number of ReadCleanReq hits 840system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588195 # number of ReadSharedReq hits 841system.cpu.l2cache.ReadSharedReq_hits::total 1588195 # number of ReadSharedReq hits 842system.cpu.l2cache.demand_hits::cpu.inst 3252 # number of demand (read+write) hits 843system.cpu.l2cache.demand_hits::cpu.data 2165592 # number of demand (read+write) hits 844system.cpu.l2cache.demand_hits::total 2168844 # number of demand (read+write) hits 845system.cpu.l2cache.overall_hits::cpu.inst 3252 # number of overall hits 846system.cpu.l2cache.overall_hits::cpu.data 2165592 # number of overall hits 847system.cpu.l2cache.overall_hits::total 2168844 # number of overall hits 848system.cpu.l2cache.UpgradeReq_misses::cpu.data 1342 # number of UpgradeReq misses 849system.cpu.l2cache.UpgradeReq_misses::total 1342 # number of UpgradeReq misses 850system.cpu.l2cache.ReadExReq_misses::cpu.data 206686 # number of ReadExReq misses 851system.cpu.l2cache.ReadExReq_misses::total 206686 # number of ReadExReq misses 852system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2416 # number of ReadCleanReq misses 853system.cpu.l2cache.ReadCleanReq_misses::total 2416 # number of ReadCleanReq misses 854system.cpu.l2cache.ReadSharedReq_misses::cpu.data 177763 # number of ReadSharedReq misses 855system.cpu.l2cache.ReadSharedReq_misses::total 177763 # number of ReadSharedReq misses 856system.cpu.l2cache.demand_misses::cpu.inst 2416 # number of demand (read+write) misses 857system.cpu.l2cache.demand_misses::cpu.data 384449 # number of demand (read+write) misses 858system.cpu.l2cache.demand_misses::total 386865 # number of demand (read+write) misses 859system.cpu.l2cache.overall_misses::cpu.inst 2416 # number of overall misses 860system.cpu.l2cache.overall_misses::cpu.data 384449 # number of overall misses 861system.cpu.l2cache.overall_misses::total 386865 # number of overall misses 862system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2044500 # number of UpgradeReq miss cycles 863system.cpu.l2cache.UpgradeReq_miss_latency::total 2044500 # number of UpgradeReq miss cycles 864system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16338042000 # number of ReadExReq miss cycles 865system.cpu.l2cache.ReadExReq_miss_latency::total 16338042000 # number of ReadExReq miss cycles 866system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195535500 # number of ReadCleanReq miss cycles 867system.cpu.l2cache.ReadCleanReq_miss_latency::total 195535500 # number of ReadCleanReq miss cycles 868system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14302139500 # number of ReadSharedReq miss cycles 869system.cpu.l2cache.ReadSharedReq_miss_latency::total 14302139500 # number of ReadSharedReq miss cycles 870system.cpu.l2cache.demand_miss_latency::cpu.inst 195535500 # number of demand (read+write) miss cycles 871system.cpu.l2cache.demand_miss_latency::cpu.data 30640181500 # number of demand (read+write) miss cycles 872system.cpu.l2cache.demand_miss_latency::total 30835717000 # number of demand (read+write) miss cycles 873system.cpu.l2cache.overall_miss_latency::cpu.inst 195535500 # number of overall miss cycles 874system.cpu.l2cache.overall_miss_latency::cpu.data 30640181500 # number of overall miss cycles 875system.cpu.l2cache.overall_miss_latency::total 30835717000 # number of overall miss cycles 876system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337968 # number of WritebackDirty accesses(hits+misses) 877system.cpu.l2cache.WritebackDirty_accesses::total 2337968 # number of WritebackDirty accesses(hits+misses) 878system.cpu.l2cache.WritebackClean_accesses::writebacks 3923 # number of WritebackClean accesses(hits+misses) 879system.cpu.l2cache.WritebackClean_accesses::total 3923 # number of WritebackClean accesses(hits+misses) 880system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1659 # number of UpgradeReq accesses(hits+misses) 881system.cpu.l2cache.UpgradeReq_accesses::total 1659 # number of UpgradeReq accesses(hits+misses) 882system.cpu.l2cache.ReadExReq_accesses::cpu.data 784083 # number of ReadExReq accesses(hits+misses) 883system.cpu.l2cache.ReadExReq_accesses::total 784083 # number of ReadExReq accesses(hits+misses) 884system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5668 # number of ReadCleanReq accesses(hits+misses) 885system.cpu.l2cache.ReadCleanReq_accesses::total 5668 # number of ReadCleanReq accesses(hits+misses) 886system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1765958 # number of ReadSharedReq accesses(hits+misses) 887system.cpu.l2cache.ReadSharedReq_accesses::total 1765958 # number of ReadSharedReq accesses(hits+misses) 888system.cpu.l2cache.demand_accesses::cpu.inst 5668 # number of demand (read+write) accesses 889system.cpu.l2cache.demand_accesses::cpu.data 2550041 # number of demand (read+write) accesses 890system.cpu.l2cache.demand_accesses::total 2555709 # number of demand (read+write) accesses 891system.cpu.l2cache.overall_accesses::cpu.inst 5668 # number of overall (read+write) accesses 892system.cpu.l2cache.overall_accesses::cpu.data 2550041 # number of overall (read+write) accesses 893system.cpu.l2cache.overall_accesses::total 2555709 # number of overall (read+write) accesses 894system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808921 # miss rate for UpgradeReq accesses 895system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808921 # miss rate for UpgradeReq accesses 896system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263602 # miss rate for ReadExReq accesses 897system.cpu.l2cache.ReadExReq_miss_rate::total 0.263602 # miss rate for ReadExReq accesses 898system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.426253 # miss rate for ReadCleanReq accesses 899system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.426253 # miss rate for ReadCleanReq accesses 900system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100661 # miss rate for ReadSharedReq accesses 901system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100661 # miss rate for ReadSharedReq accesses 902system.cpu.l2cache.demand_miss_rate::cpu.inst 0.426253 # miss rate for demand accesses 903system.cpu.l2cache.demand_miss_rate::cpu.data 0.150762 # miss rate for demand accesses 904system.cpu.l2cache.demand_miss_rate::total 0.151373 # miss rate for demand accesses 905system.cpu.l2cache.overall_miss_rate::cpu.inst 0.426253 # miss rate for overall accesses 906system.cpu.l2cache.overall_miss_rate::cpu.data 0.150762 # miss rate for overall accesses 907system.cpu.l2cache.overall_miss_rate::total 0.151373 # miss rate for overall accesses 908system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1523.472429 # average UpgradeReq miss latency 909system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1523.472429 # average UpgradeReq miss latency 910system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79047.647156 # average ReadExReq miss latency 911system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79047.647156 # average ReadExReq miss latency 912system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80933.567881 # average ReadCleanReq miss latency 913system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80933.567881 # average ReadCleanReq miss latency 914system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80456.222611 # average ReadSharedReq miss latency 915system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80456.222611 # average ReadSharedReq miss latency 916system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80933.567881 # average overall miss latency 917system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency 918system.cpu.l2cache.demand_avg_miss_latency::total 79706.659946 # average overall miss latency 919system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80933.567881 # average overall miss latency 920system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency 921system.cpu.l2cache.overall_avg_miss_latency::total 79706.659946 # average overall miss latency 922system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 923system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 924system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 925system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 926system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 927system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 928system.cpu.l2cache.fast_writes 0 # number of fast writes performed 929system.cpu.l2cache.cache_copies 0 # number of cache copies performed 930system.cpu.l2cache.writebacks::writebacks 294920 # number of writebacks 931system.cpu.l2cache.writebacks::total 294920 # number of writebacks 932system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses 933system.cpu.l2cache.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses 934system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1342 # number of UpgradeReq MSHR misses 935system.cpu.l2cache.UpgradeReq_mshr_misses::total 1342 # number of UpgradeReq MSHR misses 936system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206686 # number of ReadExReq MSHR misses 937system.cpu.l2cache.ReadExReq_mshr_misses::total 206686 # number of ReadExReq MSHR misses 938system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2416 # number of ReadCleanReq MSHR misses 939system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2416 # number of ReadCleanReq MSHR misses 940system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 177763 # number of ReadSharedReq MSHR misses 941system.cpu.l2cache.ReadSharedReq_mshr_misses::total 177763 # number of ReadSharedReq MSHR misses 942system.cpu.l2cache.demand_mshr_misses::cpu.inst 2416 # number of demand (read+write) MSHR misses 943system.cpu.l2cache.demand_mshr_misses::cpu.data 384449 # number of demand (read+write) MSHR misses 944system.cpu.l2cache.demand_mshr_misses::total 386865 # number of demand (read+write) MSHR misses 945system.cpu.l2cache.overall_mshr_misses::cpu.inst 2416 # number of overall MSHR misses 946system.cpu.l2cache.overall_mshr_misses::cpu.data 384449 # number of overall MSHR misses 947system.cpu.l2cache.overall_mshr_misses::total 386865 # number of overall MSHR misses 948system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 25553999 # number of UpgradeReq MSHR miss cycles 949system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 25553999 # number of UpgradeReq MSHR miss cycles 950system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14271182000 # number of ReadExReq MSHR miss cycles 951system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14271182000 # number of ReadExReq MSHR miss cycles 952system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 171375500 # number of ReadCleanReq MSHR miss cycles 953system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 171375500 # number of ReadCleanReq MSHR miss cycles 954system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12524509500 # number of ReadSharedReq MSHR miss cycles 955system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12524509500 # number of ReadSharedReq MSHR miss cycles 956system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171375500 # number of demand (read+write) MSHR miss cycles 957system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26795691500 # number of demand (read+write) MSHR miss cycles 958system.cpu.l2cache.demand_mshr_miss_latency::total 26967067000 # number of demand (read+write) MSHR miss cycles 959system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171375500 # number of overall MSHR miss cycles 960system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26795691500 # number of overall MSHR miss cycles 961system.cpu.l2cache.overall_mshr_miss_latency::total 26967067000 # number of overall MSHR miss cycles 962system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 963system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 964system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808921 # mshr miss rate for UpgradeReq accesses 965system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808921 # mshr miss rate for UpgradeReq accesses 966system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263602 # mshr miss rate for ReadExReq accesses 967system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263602 # mshr miss rate for ReadExReq accesses 968system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for ReadCleanReq accesses 969system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.426253 # mshr miss rate for ReadCleanReq accesses 970system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100661 # mshr miss rate for ReadSharedReq accesses 971system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100661 # mshr miss rate for ReadSharedReq accesses 972system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for demand accesses 973system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for demand accesses 974system.cpu.l2cache.demand_mshr_miss_rate::total 0.151373 # mshr miss rate for demand accesses 975system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for overall accesses 976system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for overall accesses 977system.cpu.l2cache.overall_mshr_miss_rate::total 0.151373 # mshr miss rate for overall accesses 978system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19041.728018 # average UpgradeReq mshr miss latency 979system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19041.728018 # average UpgradeReq mshr miss latency 980system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69047.647156 # average ReadExReq mshr miss latency 981system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69047.647156 # average ReadExReq mshr miss latency 982system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70933.567881 # average ReadCleanReq mshr miss latency 983system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70933.567881 # average ReadCleanReq mshr miss latency 984system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611 # average ReadSharedReq mshr miss latency 985system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611 # average ReadSharedReq mshr miss latency 986system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency 987system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency 988system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency 989system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency 990system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency 991system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency 992system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 993system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter. 994system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data. 995system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 996system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. 997system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 998system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 999system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution 1000system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution 1001system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution 1002system.cpu.toL2Bus.trans_dist::CleanEvict 268218 # Transaction distribution 1003system.cpu.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution 1004system.cpu.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution 1005system.cpu.toL2Bus.trans_dist::ReadExReq 784083 # Transaction distribution 1006system.cpu.toL2Bus.trans_dist::ReadExResp 784083 # Transaction distribution 1007system.cpu.toL2Bus.trans_dist::ReadCleanReq 7390 # Transaction distribution 1008system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765958 # Transaction distribution 1009system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17072 # Packet count per connected master and slave (bytes) 1010system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649345 # Packet count per connected master and slave (bytes) 1011system.cpu.toL2Bus.pkt_count::total 7666417 # Packet count per connected master and slave (bytes) 1012system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 619648 # Cumulative packet size per connected master and slave (bytes) 1013system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312832576 # Cumulative packet size per connected master and slave (bytes) 1014system.cpu.toL2Bus.pkt_size::total 313452224 # Cumulative packet size per connected master and slave (bytes) 1015system.cpu.toL2Bus.snoops 356883 # Total snoops (count) 1016system.cpu.toL2Bus.snoop_fanout::samples 2914251 # Request fanout histogram 1017system.cpu.toL2Bus.snoop_fanout::mean 0.004390 # Request fanout histogram 1018system.cpu.toL2Bus.snoop_fanout::stdev 0.066139 # Request fanout histogram 1019system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1020system.cpu.toL2Bus.snoop_fanout::0 2901462 99.56% 99.56% # Request fanout histogram 1021system.cpu.toL2Bus.snoop_fanout::1 12784 0.44% 100.00% # Request fanout histogram 1022system.cpu.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram 1023system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1024system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1025system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1026system.cpu.toL2Bus.snoop_fanout::total 2914251 # Request fanout histogram 1027system.cpu.toL2Bus.reqLayer0.occupancy 4896549913 # Layer occupancy (ticks) 1028system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 1029system.cpu.toL2Bus.respLayer0.occupancy 11087994 # Layer occupancy (ticks) 1030system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1031system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) 1032system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 1033system.membus.trans_dist::ReadResp 180179 # Transaction distribution 1034system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution 1035system.membus.trans_dist::CleanEvict 57436 # Transaction distribution 1036system.membus.trans_dist::UpgradeReq 1352 # Transaction distribution 1037system.membus.trans_dist::ReadExReq 206676 # Transaction distribution 1038system.membus.trans_dist::ReadExResp 206676 # Transaction distribution 1039system.membus.trans_dist::ReadSharedReq 180179 # Transaction distribution 1040system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127418 # Packet count per connected master and slave (bytes) 1041system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127418 # Packet count per connected master and slave (bytes) 1042system.membus.pkt_count::total 1127418 # Packet count per connected master and slave (bytes) 1043system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633600 # Cumulative packet size per connected master and slave (bytes) 1044system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633600 # Cumulative packet size per connected master and slave (bytes) 1045system.membus.pkt_size::total 43633600 # Cumulative packet size per connected master and slave (bytes) 1046system.membus.snoops 0 # Total snoops (count) 1047system.membus.snoop_fanout::samples 740563 # Request fanout histogram 1048system.membus.snoop_fanout::mean 0 # Request fanout histogram 1049system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1050system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1051system.membus.snoop_fanout::0 740563 100.00% 100.00% # Request fanout histogram 1052system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1053system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1054system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1055system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1056system.membus.snoop_fanout::total 740563 # Request fanout histogram 1057system.membus.reqLayer0.occupancy 1999132580 # Layer occupancy (ticks) 1058system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) 1059system.membus.respLayer1.occupancy 2047220500 # Layer occupancy (ticks) 1060system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 1061 1062---------- End Simulation Statistics ---------- 1063