stats.txt revision 10409:8c80b91944c5
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.451764 # Number of seconds simulated 4sim_ticks 451764406000 # Number of ticks simulated 5final_tick 451764406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 99375 # Simulator instruction rate (inst/s) 8host_op_rate 183755 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 54293474 # Simulator tick rate (ticks/s) 10host_mem_usage 421524 # Number of bytes of host memory used 11host_seconds 8320.79 # Real time elapsed on the host 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 224064 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24540544 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24764608 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 224064 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 224064 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18820736 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18820736 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3501 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 383446 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 386947 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 294074 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 294074 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 495975 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 54321553 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 54817528 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 495975 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 495975 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 41660511 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 41660511 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 41660511 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 495975 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 54321553 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 96478039 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 386948 # Number of read requests accepted 40system.physmem.writeReqs 294074 # Number of write requests accepted 41system.physmem.readBursts 386948 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 294074 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 24743168 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 21504 # Total number of bytes read from write queue 45system.physmem.bytesWritten 18819072 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 24764672 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 18820736 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 336 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 179060 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 24122 # Per bank write bursts 52system.physmem.perBankRdBursts::1 26505 # Per bank write bursts 53system.physmem.perBankRdBursts::2 24681 # Per bank write bursts 54system.physmem.perBankRdBursts::3 24611 # Per bank write bursts 55system.physmem.perBankRdBursts::4 23302 # Per bank write bursts 56system.physmem.perBankRdBursts::5 23732 # Per bank write bursts 57system.physmem.perBankRdBursts::6 24448 # Per bank write bursts 58system.physmem.perBankRdBursts::7 24311 # Per bank write bursts 59system.physmem.perBankRdBursts::8 23620 # Per bank write bursts 60system.physmem.perBankRdBursts::9 23937 # Per bank write bursts 61system.physmem.perBankRdBursts::10 24812 # Per bank write bursts 62system.physmem.perBankRdBursts::11 24076 # Per bank write bursts 63system.physmem.perBankRdBursts::12 23393 # Per bank write bursts 64system.physmem.perBankRdBursts::13 22985 # Per bank write bursts 65system.physmem.perBankRdBursts::14 24096 # Per bank write bursts 66system.physmem.perBankRdBursts::15 23981 # Per bank write bursts 67system.physmem.perBankWrBursts::0 18558 # Per bank write bursts 68system.physmem.perBankWrBursts::1 19850 # Per bank write bursts 69system.physmem.perBankWrBursts::2 18948 # Per bank write bursts 70system.physmem.perBankWrBursts::3 18946 # Per bank write bursts 71system.physmem.perBankWrBursts::4 18040 # Per bank write bursts 72system.physmem.perBankWrBursts::5 18437 # Per bank write bursts 73system.physmem.perBankWrBursts::6 18993 # Per bank write bursts 74system.physmem.perBankWrBursts::7 18991 # Per bank write bursts 75system.physmem.perBankWrBursts::8 18543 # Per bank write bursts 76system.physmem.perBankWrBursts::9 18160 # Per bank write bursts 77system.physmem.perBankWrBursts::10 18841 # Per bank write bursts 78system.physmem.perBankWrBursts::11 17736 # Per bank write bursts 79system.physmem.perBankWrBursts::12 17380 # Per bank write bursts 80system.physmem.perBankWrBursts::13 16967 # Per bank write bursts 81system.physmem.perBankWrBursts::14 17832 # Per bank write bursts 82system.physmem.perBankWrBursts::15 17826 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 451764392500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 386948 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 294074 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 381637 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 4588 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 337 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 38 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 6121 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 6527 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 16919 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 17566 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 17579 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 17557 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 17609 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 17628 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 17613 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 17619 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 17776 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 17688 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 17635 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 17848 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 17586 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 17479 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 44 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 26 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 21 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 14 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 147402 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 295.521852 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 174.115334 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 323.715133 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 54829 37.20% 37.20% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 40372 27.39% 64.59% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 13383 9.08% 73.67% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7515 5.10% 78.76% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 5234 3.55% 82.31% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 3732 2.53% 84.85% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 3157 2.14% 86.99% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 2805 1.90% 88.89% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 16375 11.11% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 147402 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 17447 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 22.158537 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 209.201153 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 17434 99.93% 99.93% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 17447 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 17447 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.853786 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.774474 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 2.995315 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16-19 17244 98.84% 98.84% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::20-23 149 0.85% 99.69% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-27 24 0.14% 99.83% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::32-35 4 0.02% 99.89% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::36-39 4 0.02% 99.91% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::200-203 1 0.01% 99.99% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::total 17447 # Writes before turning the bus around for reads 242system.physmem.totQLat 4338654000 # Total ticks spent queuing 243system.physmem.totMemAccLat 11587629000 # Total ticks spent from burst creation until serviced by the DRAM 244system.physmem.totBusLat 1933060000 # Total ticks spent in databus transfers 245system.physmem.avgQLat 11222.24 # Average queueing delay per DRAM burst 246system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 247system.physmem.avgMemAccLat 29972.24 # Average memory access latency per DRAM burst 248system.physmem.avgRdBW 54.77 # Average DRAM read bandwidth in MiByte/s 249system.physmem.avgWrBW 41.66 # Average achieved write bandwidth in MiByte/s 250system.physmem.avgRdBWSys 54.82 # Average system read bandwidth in MiByte/s 251system.physmem.avgWrBWSys 41.66 # Average system write bandwidth in MiByte/s 252system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 253system.physmem.busUtil 0.75 # Data bus utilization in percentage 254system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads 255system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes 256system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 257system.physmem.avgWrQLen 21.93 # Average write queue length when enqueuing 258system.physmem.readRowHits 317693 # Number of row buffer hits during reads 259system.physmem.writeRowHits 215552 # Number of row buffer hits during writes 260system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads 261system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes 262system.physmem.avgGap 663362.41 # Average gap between requests 263system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined 264system.physmem.memoryStateTime::IDLE 312439483250 # Time in different power states 265system.physmem.memoryStateTime::REF 15085200000 # Time in different power states 266system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 267system.physmem.memoryStateTime::ACT 124235187750 # Time in different power states 268system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 269system.membus.trans_dist::ReadReq 179971 # Transaction distribution 270system.membus.trans_dist::ReadResp 179970 # Transaction distribution 271system.membus.trans_dist::Writeback 294074 # Transaction distribution 272system.membus.trans_dist::UpgradeReq 179060 # Transaction distribution 273system.membus.trans_dist::UpgradeResp 179060 # Transaction distribution 274system.membus.trans_dist::ReadExReq 206977 # Transaction distribution 275system.membus.trans_dist::ReadExResp 206977 # Transaction distribution 276system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1426089 # Packet count per connected master and slave (bytes) 277system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1426089 # Packet count per connected master and slave (bytes) 278system.membus.pkt_count::total 1426089 # Packet count per connected master and slave (bytes) 279system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43585344 # Cumulative packet size per connected master and slave (bytes) 280system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43585344 # Cumulative packet size per connected master and slave (bytes) 281system.membus.pkt_size::total 43585344 # Cumulative packet size per connected master and slave (bytes) 282system.membus.snoops 0 # Total snoops (count) 283system.membus.snoop_fanout::samples 860082 # Request fanout histogram 284system.membus.snoop_fanout::mean 0 # Request fanout histogram 285system.membus.snoop_fanout::stdev 0 # Request fanout histogram 286system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 287system.membus.snoop_fanout::0 860082 100.00% 100.00% # Request fanout histogram 288system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 289system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 290system.membus.snoop_fanout::min_value 0 # Request fanout histogram 291system.membus.snoop_fanout::max_value 0 # Request fanout histogram 292system.membus.snoop_fanout::total 860082 # Request fanout histogram 293system.membus.reqLayer0.occupancy 3467694500 # Layer occupancy (ticks) 294system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 295system.membus.respLayer1.occupancy 3995364517 # Layer occupancy (ticks) 296system.membus.respLayer1.utilization 0.9 # Layer utilization (%) 297system.cpu_clk_domain.clock 500 # Clock period in ticks 298system.cpu.branchPred.lookups 231811700 # Number of BP lookups 299system.cpu.branchPred.condPredicted 231811700 # Number of conditional branches predicted 300system.cpu.branchPred.condIncorrect 9749774 # Number of conditional branches incorrect 301system.cpu.branchPred.BTBLookups 132043202 # Number of BTB lookups 302system.cpu.branchPred.BTBHits 129334985 # Number of BTB hits 303system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 304system.cpu.branchPred.BTBHitPct 97.948992 # BTB Hit Percentage 305system.cpu.branchPred.usedRAS 28034260 # Number of times the RAS was used to get a target. 306system.cpu.branchPred.RASInCorrect 1466603 # Number of incorrect RAS predictions. 307system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 308system.cpu.workload.num_syscalls 551 # Number of system calls 309system.cpu.numCycles 903528833 # number of cpu cycles simulated 310system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 311system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 312system.cpu.fetch.icacheStallCycles 186193866 # Number of cycles fetch is stalled on an Icache miss 313system.cpu.fetch.Insts 1278658073 # Number of instructions fetch has processed 314system.cpu.fetch.Branches 231811700 # Number of branches that fetch encountered 315system.cpu.fetch.predictedBranches 157369245 # Number of branches that fetch has predicted taken 316system.cpu.fetch.Cycles 706106364 # Number of cycles fetch has run and was not squashing or blocked 317system.cpu.fetch.SquashCycles 20239876 # Number of cycles fetch has spent squashing 318system.cpu.fetch.TlbCycles 1021 # Number of cycles fetch has spent waiting for tlb 319system.cpu.fetch.MiscStallCycles 98431 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 320system.cpu.fetch.PendingTrapStallCycles 825605 # Number of stall cycles due to pending traps 321system.cpu.fetch.PendingQuiesceStallCycles 1885 # Number of stall cycles due to pending quiesce instructions 322system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR 323system.cpu.fetch.CacheLines 180561661 # Number of cache lines fetched 324system.cpu.fetch.IcacheSquashes 2733230 # Number of outstanding Icache misses that were squashed 325system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed 326system.cpu.fetch.rateDist::samples 903347128 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::mean 2.632355 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::stdev 3.341099 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::0 492680103 54.54% 54.54% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::1 34123521 3.78% 58.32% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::2 33275891 3.68% 62.00% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::3 33627770 3.72% 65.72% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::4 27182272 3.01% 68.73% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::5 27855831 3.08% 71.82% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::6 37310737 4.13% 75.95% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::7 33828820 3.74% 79.69% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::8 183462183 20.31% 100.00% # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::total 903347128 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.branchRate 0.256563 # Number of branch fetches per cycle 344system.cpu.fetch.rate 1.415182 # Number of inst fetches per cycle 345system.cpu.decode.IdleCycles 127724228 # Number of cycles decode is idle 346system.cpu.decode.BlockedCycles 442644539 # Number of cycles decode is blocked 347system.cpu.decode.RunCycles 240143304 # Number of cycles decode is running 348system.cpu.decode.UnblockCycles 82715119 # Number of cycles decode is unblocking 349system.cpu.decode.SquashCycles 10119938 # Number of cycles decode is squashing 350system.cpu.decode.DecodedInsts 2233772257 # Number of instructions handled by decode 351system.cpu.rename.SquashCycles 10119938 # Number of cycles rename is squashing 352system.cpu.rename.IdleCycles 159908050 # Number of cycles rename is idle 353system.cpu.rename.BlockCycles 227395701 # Number of cycles rename is blocking 354system.cpu.rename.serializeStallCycles 31553 # count of cycles rename stalled for serializing inst 355system.cpu.rename.RunCycles 285948747 # Number of cycles rename is running 356system.cpu.rename.UnblockCycles 219943139 # Number of cycles rename is unblocking 357system.cpu.rename.RenamedInsts 2183809979 # Number of instructions processed by rename 358system.cpu.rename.ROBFullEvents 169165 # Number of times rename has blocked due to ROB full 359system.cpu.rename.IQFullEvents 140088736 # Number of times rename has blocked due to IQ full 360system.cpu.rename.LQFullEvents 23988102 # Number of times rename has blocked due to LQ full 361system.cpu.rename.SQFullEvents 45039827 # Number of times rename has blocked due to SQ full 362system.cpu.rename.RenamedOperands 2289176453 # Number of destination operands rename has renamed 363system.cpu.rename.RenameLookups 5526365527 # Number of register rename lookups that rename has made 364system.cpu.rename.int_rename_lookups 3514194402 # Number of integer rename lookups 365system.cpu.rename.fp_rename_lookups 52054 # Number of floating rename lookups 366system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed 367system.cpu.rename.UndoneMaps 675135599 # Number of HB maps that are undone due to squashing 368system.cpu.rename.serializingInsts 2312 # count of serializing insts renamed 369system.cpu.rename.tempSerializingInsts 2290 # count of temporary serializing insts renamed 370system.cpu.rename.skidInsts 426537147 # count of insts added to the skid buffer 371system.cpu.memDep0.insertedLoads 530783294 # Number of loads inserted to the mem dependence unit. 372system.cpu.memDep0.insertedStores 210410050 # Number of stores inserted to the mem dependence unit. 373system.cpu.memDep0.conflictingLoads 240827707 # Number of conflicting loads. 374system.cpu.memDep0.conflictingStores 72173678 # Number of conflicting stores. 375system.cpu.iq.iqInstsAdded 2112785390 # Number of instructions added to the IQ (excludes non-spec) 376system.cpu.iq.iqNonSpecInstsAdded 25204 # Number of non-speculative instructions added to the IQ 377system.cpu.iq.iqInstsIssued 1829110925 # Number of instructions issued 378system.cpu.iq.iqSquashedInstsIssued 437516 # Number of squashed instructions issued 379system.cpu.iq.iqSquashedInstsExamined 579120624 # Number of squashed instructions iterated over during squash; mainly for profiling 380system.cpu.iq.iqSquashedOperandsExamined 1007560279 # Number of squashed operands that are examined and possibly removed from graph 381system.cpu.iq.iqSquashedNonSpecRemoved 24652 # Number of squashed non-spec instructions that were removed 382system.cpu.iq.issued_per_cycle::samples 903347128 # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::mean 2.024815 # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::stdev 2.069613 # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::0 319005991 35.31% 35.31% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::1 130297139 14.42% 49.74% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::2 120325805 13.32% 63.06% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::3 111338872 12.33% 75.38% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::4 91295017 10.11% 85.49% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::5 61401299 6.80% 92.29% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::6 43188488 4.78% 97.07% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::7 19128067 2.12% 99.18% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::8 7366450 0.82% 100.00% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::total 903347128 # Number of insts issued each cycle 399system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 400system.cpu.iq.fu_full::IntAlu 11298417 42.44% 42.44% # attempts to use FU when none available 401system.cpu.iq.fu_full::IntMult 0 0.00% 42.44% # attempts to use FU when none available 402system.cpu.iq.fu_full::IntDiv 0 0.00% 42.44% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.44% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.44% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.44% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.44% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.44% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.44% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.44% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.44% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.44% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.44% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdMult 0 0.00% 42.44% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.44% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdShift 0 0.00% 42.44% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available 429system.cpu.iq.fu_full::MemRead 12271176 46.10% 88.54% # attempts to use FU when none available 430system.cpu.iq.fu_full::MemWrite 3050228 11.46% 100.00% # attempts to use FU when none available 431system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 432system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 433system.cpu.iq.FU_type_0::No_OpClass 2719541 0.15% 0.15% # Type of FU issued 434system.cpu.iq.FU_type_0::IntAlu 1212963557 66.31% 66.46% # Type of FU issued 435system.cpu.iq.FU_type_0::IntMult 389902 0.02% 66.48% # Type of FU issued 436system.cpu.iq.FU_type_0::IntDiv 3881002 0.21% 66.70% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 66.70% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued 440system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued 463system.cpu.iq.FU_type_0::MemRead 435438564 23.81% 90.50% # Type of FU issued 464system.cpu.iq.FU_type_0::MemWrite 173718237 9.50% 100.00% # Type of FU issued 465system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 466system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 467system.cpu.iq.FU_type_0::total 1829110925 # Type of FU issued 468system.cpu.iq.rate 2.024408 # Inst issue rate 469system.cpu.iq.fu_busy_cnt 26619821 # FU busy when requested 470system.cpu.iq.fu_busy_rate 0.014553 # FU busy rate (busy events/executed inst) 471system.cpu.iq.int_inst_queue_reads 4588595925 # Number of integer instruction queue reads 472system.cpu.iq.int_inst_queue_writes 2692200263 # Number of integer instruction queue writes 473system.cpu.iq.int_inst_queue_wakeup_accesses 1799476115 # Number of integer instruction queue wakeup accesses 474system.cpu.iq.fp_inst_queue_reads 30390 # Number of floating instruction queue reads 475system.cpu.iq.fp_inst_queue_writes 66120 # Number of floating instruction queue writes 476system.cpu.iq.fp_inst_queue_wakeup_accesses 6655 # Number of floating instruction queue wakeup accesses 477system.cpu.iq.int_alu_accesses 1852997149 # Number of integer alu accesses 478system.cpu.iq.fp_alu_accesses 14056 # Number of floating point alu accesses 479system.cpu.iew.lsq.thread0.forwLoads 185108157 # Number of loads that had data forwarded from stores 480system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 481system.cpu.iew.lsq.thread0.squashedLoads 146685050 # Number of loads squashed 482system.cpu.iew.lsq.thread0.ignoredResponses 212835 # Number of memory responses ignored because the instruction is squashed 483system.cpu.iew.lsq.thread0.memOrderViolation 388917 # Number of memory ordering violations 484system.cpu.iew.lsq.thread0.squashedStores 61249864 # Number of stores squashed 485system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 486system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 487system.cpu.iew.lsq.thread0.rescheduledLoads 18586 # Number of loads that were rescheduled 488system.cpu.iew.lsq.thread0.cacheBlocked 815 # Number of times an access to memory failed due to the cache being blocked 489system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 490system.cpu.iew.iewSquashCycles 10119938 # Number of cycles IEW is squashing 491system.cpu.iew.iewBlockCycles 166724787 # Number of cycles IEW is blocking 492system.cpu.iew.iewUnblockCycles 10164048 # Number of cycles IEW is unblocking 493system.cpu.iew.iewDispatchedInsts 2112810594 # Number of instructions dispatched to IQ 494system.cpu.iew.iewDispSquashedInsts 401170 # Number of squashed instructions skipped by dispatch 495system.cpu.iew.iewDispLoadInsts 530787207 # Number of dispatched load instructions 496system.cpu.iew.iewDispStoreInsts 210410050 # Number of dispatched store instructions 497system.cpu.iew.iewDispNonSpecInsts 7737 # Number of dispatched non-speculative instructions 498system.cpu.iew.iewIQFullEvents 4462758 # Number of times the IQ has become full, causing a stall 499system.cpu.iew.iewLSQFullEvents 3568650 # Number of times the LSQ has become full, causing a stall 500system.cpu.iew.memOrderViolationEvents 388917 # Number of memory order violations 501system.cpu.iew.predictedTakenIncorrect 5751622 # Number of branches that were predicted taken incorrectly 502system.cpu.iew.predictedNotTakenIncorrect 4609702 # Number of branches that were predicted not taken incorrectly 503system.cpu.iew.branchMispredicts 10361324 # Number of branch mispredicts detected at execute 504system.cpu.iew.iewExecutedInsts 1807989007 # Number of executed instructions 505system.cpu.iew.iewExecLoadInsts 429368726 # Number of load instructions executed 506system.cpu.iew.iewExecSquashedInsts 21121918 # Number of squashed instructions skipped in execute 507system.cpu.iew.exec_swp 0 # number of swp insts executed 508system.cpu.iew.exec_nop 0 # number of nop insts executed 509system.cpu.iew.exec_refs 599512830 # number of memory reference insts executed 510system.cpu.iew.exec_branches 171944433 # Number of branches executed 511system.cpu.iew.exec_stores 170144104 # Number of stores executed 512system.cpu.iew.exec_rate 2.001031 # Inst execution rate 513system.cpu.iew.wb_sent 1804759601 # cumulative count of insts sent to commit 514system.cpu.iew.wb_count 1799482770 # cumulative count of insts written-back 515system.cpu.iew.wb_producers 1369602342 # num instructions producing a value 516system.cpu.iew.wb_consumers 2093301343 # num instructions consuming a value 517system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 518system.cpu.iew.wb_rate 1.991616 # insts written-back per cycle 519system.cpu.iew.wb_fanout 0.654279 # average fanout of values written-back 520system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 521system.cpu.commit.commitSquashedInsts 584047933 # The number of squashed insts skipped by commit 522system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards 523system.cpu.commit.branchMispredicts 9837228 # The number of times a branch was mispredicted 524system.cpu.commit.committed_per_cycle::samples 824173639 # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::mean 1.855178 # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::stdev 2.504108 # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::0 355774645 43.17% 43.17% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::1 174944190 21.23% 64.39% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::2 57267566 6.95% 71.34% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::3 86311577 10.47% 81.82% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::4 27168668 3.30% 85.11% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::5 27065091 3.28% 88.40% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::6 9878369 1.20% 89.59% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::7 8803957 1.07% 90.66% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::8 76959576 9.34% 100.00% # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::total 824173639 # Number of insts commited each cycle 541system.cpu.commit.committedInsts 826877109 # Number of instructions committed 542system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 543system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 544system.cpu.commit.refs 533262343 # Number of memory references committed 545system.cpu.commit.loads 384102157 # Number of loads committed 546system.cpu.commit.membars 0 # Number of memory barriers committed 547system.cpu.commit.branches 149758583 # Number of branches committed 548system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 549system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. 550system.cpu.commit.function_calls 17673145 # Number of function calls committed. 551system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction 552system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction 553system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction 554system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction 555system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction 556system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction 557system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction 558system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction 559system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction 560system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction 561system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction 562system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction 563system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction 564system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction 567system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction 568system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction 569system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction 570system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction 571system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction 574system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction 576system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction 577system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction 578system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction 579system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction 580system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction 581system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction 582system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction 583system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 584system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 585system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction 586system.cpu.commit.bw_lim_events 76959576 # number cycles where commit BW limit reached 587system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 588system.cpu.rob.rob_reads 2860250697 # The number of ROB reads 589system.cpu.rob.rob_writes 4305432555 # The number of ROB writes 590system.cpu.timesIdled 2603 # Number of times that the entire CPU went into an idle state and unscheduled itself 591system.cpu.idleCycles 181705 # Total number of cycles that the CPU has spent unscheduled due to idling 592system.cpu.committedInsts 826877109 # Number of Instructions Simulated 593system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated 594system.cpu.cpi 1.092700 # CPI: Cycles Per Instruction 595system.cpu.cpi_total 1.092700 # CPI: Total CPI of All Threads 596system.cpu.ipc 0.915164 # IPC: Instructions Per Cycle 597system.cpu.ipc_total 0.915164 # IPC: Total IPC of All Threads 598system.cpu.int_regfile_reads 2763452160 # number of integer regfile reads 599system.cpu.int_regfile_writes 1467518123 # number of integer regfile writes 600system.cpu.fp_regfile_reads 6756 # number of floating regfile reads 601system.cpu.fp_regfile_writes 202 # number of floating regfile writes 602system.cpu.cc_regfile_reads 600952146 # number of cc regfile reads 603system.cpu.cc_regfile_writes 409697644 # number of cc regfile writes 604system.cpu.misc_regfile_reads 991728878 # number of misc regfile reads 605system.cpu.misc_regfile_writes 1 # number of misc regfile writes 606system.cpu.toL2Bus.trans_dist::ReadReq 1956687 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadResp 1956686 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::Writeback 2333034 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::UpgradeReq 180860 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::UpgradeResp 180860 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::ReadExReq 771518 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::ReadExResp 771518 # Transaction distribution 613system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 198212 # Packet count per connected master and slave (bytes) 614system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7771975 # Packet count per connected master and slave (bytes) 615system.cpu.toL2Bus.pkt_count::total 7970187 # Packet count per connected master and slave (bytes) 616system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551552 # Cumulative packet size per connected master and slave (bytes) 617system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311785216 # Cumulative packet size per connected master and slave (bytes) 618system.cpu.toL2Bus.pkt_size::total 312336768 # Cumulative packet size per connected master and slave (bytes) 619system.cpu.toL2Bus.snoops 180976 # Total snoops (count) 620system.cpu.toL2Bus.snoop_fanout::samples 5242099 # Request fanout histogram 621system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram 622system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 623system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 624system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 627system.cpu.toL2Bus.snoop_fanout::3 5242099 100.00% 100.00% # Request fanout histogram 628system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 629system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 630system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 631system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 632system.cpu.toL2Bus.snoop_fanout::total 5242099 # Request fanout histogram 633system.cpu.toL2Bus.reqLayer0.occupancy 4970549506 # Layer occupancy (ticks) 634system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 635system.cpu.toL2Bus.respLayer0.occupancy 284884490 # Layer occupancy (ticks) 636system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 637system.cpu.toL2Bus.respLayer1.occupancy 3981162622 # Layer occupancy (ticks) 638system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 639system.cpu.icache.tags.replacements 7001 # number of replacements 640system.cpu.icache.tags.tagsinuse 1081.953602 # Cycle average of tags in use 641system.cpu.icache.tags.total_refs 180366705 # Total number of references to valid blocks. 642system.cpu.icache.tags.sampled_refs 8614 # Sample count of references to valid blocks. 643system.cpu.icache.tags.avg_refs 20938.786278 # Average number of references to valid blocks. 644system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 645system.cpu.icache.tags.occ_blocks::cpu.inst 1081.953602 # Average occupied blocks per requestor 646system.cpu.icache.tags.occ_percent::cpu.inst 0.528298 # Average percentage of cache occupancy 647system.cpu.icache.tags.occ_percent::total 0.528298 # Average percentage of cache occupancy 648system.cpu.icache.tags.occ_task_id_blocks::1024 1613 # Occupied blocks per task id 649system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 650system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 651system.cpu.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id 652system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id 653system.cpu.icache.tags.age_task_id_blocks_1024::4 1172 # Occupied blocks per task id 654system.cpu.icache.tags.occ_task_id_percent::1024 0.787598 # Percentage of cache occupancy per task id 655system.cpu.icache.tags.tag_accesses 361312916 # Number of tag accesses 656system.cpu.icache.tags.data_accesses 361312916 # Number of data accesses 657system.cpu.icache.ReadReq_hits::cpu.inst 180369624 # number of ReadReq hits 658system.cpu.icache.ReadReq_hits::total 180369624 # number of ReadReq hits 659system.cpu.icache.demand_hits::cpu.inst 180369624 # number of demand (read+write) hits 660system.cpu.icache.demand_hits::total 180369624 # number of demand (read+write) hits 661system.cpu.icache.overall_hits::cpu.inst 180369624 # number of overall hits 662system.cpu.icache.overall_hits::total 180369624 # number of overall hits 663system.cpu.icache.ReadReq_misses::cpu.inst 192037 # number of ReadReq misses 664system.cpu.icache.ReadReq_misses::total 192037 # number of ReadReq misses 665system.cpu.icache.demand_misses::cpu.inst 192037 # number of demand (read+write) misses 666system.cpu.icache.demand_misses::total 192037 # number of demand (read+write) misses 667system.cpu.icache.overall_misses::cpu.inst 192037 # number of overall misses 668system.cpu.icache.overall_misses::total 192037 # number of overall misses 669system.cpu.icache.ReadReq_miss_latency::cpu.inst 1182728989 # number of ReadReq miss cycles 670system.cpu.icache.ReadReq_miss_latency::total 1182728989 # number of ReadReq miss cycles 671system.cpu.icache.demand_miss_latency::cpu.inst 1182728989 # number of demand (read+write) miss cycles 672system.cpu.icache.demand_miss_latency::total 1182728989 # number of demand (read+write) miss cycles 673system.cpu.icache.overall_miss_latency::cpu.inst 1182728989 # number of overall miss cycles 674system.cpu.icache.overall_miss_latency::total 1182728989 # number of overall miss cycles 675system.cpu.icache.ReadReq_accesses::cpu.inst 180561661 # number of ReadReq accesses(hits+misses) 676system.cpu.icache.ReadReq_accesses::total 180561661 # number of ReadReq accesses(hits+misses) 677system.cpu.icache.demand_accesses::cpu.inst 180561661 # number of demand (read+write) accesses 678system.cpu.icache.demand_accesses::total 180561661 # number of demand (read+write) accesses 679system.cpu.icache.overall_accesses::cpu.inst 180561661 # number of overall (read+write) accesses 680system.cpu.icache.overall_accesses::total 180561661 # number of overall (read+write) accesses 681system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001064 # miss rate for ReadReq accesses 682system.cpu.icache.ReadReq_miss_rate::total 0.001064 # miss rate for ReadReq accesses 683system.cpu.icache.demand_miss_rate::cpu.inst 0.001064 # miss rate for demand accesses 684system.cpu.icache.demand_miss_rate::total 0.001064 # miss rate for demand accesses 685system.cpu.icache.overall_miss_rate::cpu.inst 0.001064 # miss rate for overall accesses 686system.cpu.icache.overall_miss_rate::total 0.001064 # miss rate for overall accesses 687system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6158.859954 # average ReadReq miss latency 688system.cpu.icache.ReadReq_avg_miss_latency::total 6158.859954 # average ReadReq miss latency 689system.cpu.icache.demand_avg_miss_latency::cpu.inst 6158.859954 # average overall miss latency 690system.cpu.icache.demand_avg_miss_latency::total 6158.859954 # average overall miss latency 691system.cpu.icache.overall_avg_miss_latency::cpu.inst 6158.859954 # average overall miss latency 692system.cpu.icache.overall_avg_miss_latency::total 6158.859954 # average overall miss latency 693system.cpu.icache.blocked_cycles::no_mshrs 857 # number of cycles access was blocked 694system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 695system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked 696system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 697system.cpu.icache.avg_blocked_cycles::no_mshrs 57.133333 # average number of cycles each access was blocked 698system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 699system.cpu.icache.fast_writes 0 # number of fast writes performed 700system.cpu.icache.cache_copies 0 # number of cache copies performed 701system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2443 # number of ReadReq MSHR hits 702system.cpu.icache.ReadReq_mshr_hits::total 2443 # number of ReadReq MSHR hits 703system.cpu.icache.demand_mshr_hits::cpu.inst 2443 # number of demand (read+write) MSHR hits 704system.cpu.icache.demand_mshr_hits::total 2443 # number of demand (read+write) MSHR hits 705system.cpu.icache.overall_mshr_hits::cpu.inst 2443 # number of overall MSHR hits 706system.cpu.icache.overall_mshr_hits::total 2443 # number of overall MSHR hits 707system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189594 # number of ReadReq MSHR misses 708system.cpu.icache.ReadReq_mshr_misses::total 189594 # number of ReadReq MSHR misses 709system.cpu.icache.demand_mshr_misses::cpu.inst 189594 # number of demand (read+write) MSHR misses 710system.cpu.icache.demand_mshr_misses::total 189594 # number of demand (read+write) MSHR misses 711system.cpu.icache.overall_mshr_misses::cpu.inst 189594 # number of overall MSHR misses 712system.cpu.icache.overall_mshr_misses::total 189594 # number of overall MSHR misses 713system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 702034010 # number of ReadReq MSHR miss cycles 714system.cpu.icache.ReadReq_mshr_miss_latency::total 702034010 # number of ReadReq MSHR miss cycles 715system.cpu.icache.demand_mshr_miss_latency::cpu.inst 702034010 # number of demand (read+write) MSHR miss cycles 716system.cpu.icache.demand_mshr_miss_latency::total 702034010 # number of demand (read+write) MSHR miss cycles 717system.cpu.icache.overall_mshr_miss_latency::cpu.inst 702034010 # number of overall MSHR miss cycles 718system.cpu.icache.overall_mshr_miss_latency::total 702034010 # number of overall MSHR miss cycles 719system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001050 # mshr miss rate for ReadReq accesses 720system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001050 # mshr miss rate for ReadReq accesses 721system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001050 # mshr miss rate for demand accesses 722system.cpu.icache.demand_mshr_miss_rate::total 0.001050 # mshr miss rate for demand accesses 723system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001050 # mshr miss rate for overall accesses 724system.cpu.icache.overall_mshr_miss_rate::total 0.001050 # mshr miss rate for overall accesses 725system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3702.828201 # average ReadReq mshr miss latency 726system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3702.828201 # average ReadReq mshr miss latency 727system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3702.828201 # average overall mshr miss latency 728system.cpu.icache.demand_avg_mshr_miss_latency::total 3702.828201 # average overall mshr miss latency 729system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3702.828201 # average overall mshr miss latency 730system.cpu.icache.overall_avg_mshr_miss_latency::total 3702.828201 # average overall mshr miss latency 731system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 732system.cpu.l2cache.tags.replacements 354269 # number of replacements 733system.cpu.l2cache.tags.tagsinuse 29686.230679 # Cycle average of tags in use 734system.cpu.l2cache.tags.total_refs 3704231 # Total number of references to valid blocks. 735system.cpu.l2cache.tags.sampled_refs 386628 # Sample count of references to valid blocks. 736system.cpu.l2cache.tags.avg_refs 9.580866 # Average number of references to valid blocks. 737system.cpu.l2cache.tags.warmup_cycle 196903741500 # Cycle when the warmup percentage was hit. 738system.cpu.l2cache.tags.occ_blocks::writebacks 21108.649111 # Average occupied blocks per requestor 739system.cpu.l2cache.tags.occ_blocks::cpu.inst 250.939279 # Average occupied blocks per requestor 740system.cpu.l2cache.tags.occ_blocks::cpu.data 8326.642289 # Average occupied blocks per requestor 741system.cpu.l2cache.tags.occ_percent::writebacks 0.644185 # Average percentage of cache occupancy 742system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007658 # Average percentage of cache occupancy 743system.cpu.l2cache.tags.occ_percent::cpu.data 0.254109 # Average percentage of cache occupancy 744system.cpu.l2cache.tags.occ_percent::total 0.905952 # Average percentage of cache occupancy 745system.cpu.l2cache.tags.occ_task_id_blocks::1024 32359 # Occupied blocks per task id 746system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 747system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 748system.cpu.l2cache.tags.age_task_id_blocks_1024::2 247 # Occupied blocks per task id 749system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11757 # Occupied blocks per task id 750system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20273 # Occupied blocks per task id 751system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987518 # Percentage of cache occupancy per task id 752system.cpu.l2cache.tags.tag_accesses 41649377 # Number of tag accesses 753system.cpu.l2cache.tags.data_accesses 41649377 # Number of data accesses 754system.cpu.l2cache.ReadReq_hits::cpu.inst 5116 # number of ReadReq hits 755system.cpu.l2cache.ReadReq_hits::cpu.data 1590623 # number of ReadReq hits 756system.cpu.l2cache.ReadReq_hits::total 1595739 # number of ReadReq hits 757system.cpu.l2cache.Writeback_hits::writebacks 2333034 # number of Writeback hits 758system.cpu.l2cache.Writeback_hits::total 2333034 # number of Writeback hits 759system.cpu.l2cache.UpgradeReq_hits::cpu.data 1835 # number of UpgradeReq hits 760system.cpu.l2cache.UpgradeReq_hits::total 1835 # number of UpgradeReq hits 761system.cpu.l2cache.ReadExReq_hits::cpu.data 564506 # number of ReadExReq hits 762system.cpu.l2cache.ReadExReq_hits::total 564506 # number of ReadExReq hits 763system.cpu.l2cache.demand_hits::cpu.inst 5116 # number of demand (read+write) hits 764system.cpu.l2cache.demand_hits::cpu.data 2155129 # number of demand (read+write) hits 765system.cpu.l2cache.demand_hits::total 2160245 # number of demand (read+write) hits 766system.cpu.l2cache.overall_hits::cpu.inst 5116 # number of overall hits 767system.cpu.l2cache.overall_hits::cpu.data 2155129 # number of overall hits 768system.cpu.l2cache.overall_hits::total 2160245 # number of overall hits 769system.cpu.l2cache.ReadReq_misses::cpu.inst 3502 # number of ReadReq misses 770system.cpu.l2cache.ReadReq_misses::cpu.data 176470 # number of ReadReq misses 771system.cpu.l2cache.ReadReq_misses::total 179972 # number of ReadReq misses 772system.cpu.l2cache.UpgradeReq_misses::cpu.data 179025 # number of UpgradeReq misses 773system.cpu.l2cache.UpgradeReq_misses::total 179025 # number of UpgradeReq misses 774system.cpu.l2cache.ReadExReq_misses::cpu.data 207012 # number of ReadExReq misses 775system.cpu.l2cache.ReadExReq_misses::total 207012 # number of ReadExReq misses 776system.cpu.l2cache.demand_misses::cpu.inst 3502 # number of demand (read+write) misses 777system.cpu.l2cache.demand_misses::cpu.data 383482 # number of demand (read+write) misses 778system.cpu.l2cache.demand_misses::total 386984 # number of demand (read+write) misses 779system.cpu.l2cache.overall_misses::cpu.inst 3502 # number of overall misses 780system.cpu.l2cache.overall_misses::cpu.data 383482 # number of overall misses 781system.cpu.l2cache.overall_misses::total 386984 # number of overall misses 782system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 259185750 # number of ReadReq miss cycles 783system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12941216954 # number of ReadReq miss cycles 784system.cpu.l2cache.ReadReq_miss_latency::total 13200402704 # number of ReadReq miss cycles 785system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9580588 # number of UpgradeReq miss cycles 786system.cpu.l2cache.UpgradeReq_miss_latency::total 9580588 # number of UpgradeReq miss cycles 787system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14943351215 # number of ReadExReq miss cycles 788system.cpu.l2cache.ReadExReq_miss_latency::total 14943351215 # number of ReadExReq miss cycles 789system.cpu.l2cache.demand_miss_latency::cpu.inst 259185750 # number of demand (read+write) miss cycles 790system.cpu.l2cache.demand_miss_latency::cpu.data 27884568169 # number of demand (read+write) miss cycles 791system.cpu.l2cache.demand_miss_latency::total 28143753919 # number of demand (read+write) miss cycles 792system.cpu.l2cache.overall_miss_latency::cpu.inst 259185750 # number of overall miss cycles 793system.cpu.l2cache.overall_miss_latency::cpu.data 27884568169 # number of overall miss cycles 794system.cpu.l2cache.overall_miss_latency::total 28143753919 # number of overall miss cycles 795system.cpu.l2cache.ReadReq_accesses::cpu.inst 8618 # number of ReadReq accesses(hits+misses) 796system.cpu.l2cache.ReadReq_accesses::cpu.data 1767093 # number of ReadReq accesses(hits+misses) 797system.cpu.l2cache.ReadReq_accesses::total 1775711 # number of ReadReq accesses(hits+misses) 798system.cpu.l2cache.Writeback_accesses::writebacks 2333034 # number of Writeback accesses(hits+misses) 799system.cpu.l2cache.Writeback_accesses::total 2333034 # number of Writeback accesses(hits+misses) 800system.cpu.l2cache.UpgradeReq_accesses::cpu.data 180860 # number of UpgradeReq accesses(hits+misses) 801system.cpu.l2cache.UpgradeReq_accesses::total 180860 # number of UpgradeReq accesses(hits+misses) 802system.cpu.l2cache.ReadExReq_accesses::cpu.data 771518 # number of ReadExReq accesses(hits+misses) 803system.cpu.l2cache.ReadExReq_accesses::total 771518 # number of ReadExReq accesses(hits+misses) 804system.cpu.l2cache.demand_accesses::cpu.inst 8618 # number of demand (read+write) accesses 805system.cpu.l2cache.demand_accesses::cpu.data 2538611 # number of demand (read+write) accesses 806system.cpu.l2cache.demand_accesses::total 2547229 # number of demand (read+write) accesses 807system.cpu.l2cache.overall_accesses::cpu.inst 8618 # number of overall (read+write) accesses 808system.cpu.l2cache.overall_accesses::cpu.data 2538611 # number of overall (read+write) accesses 809system.cpu.l2cache.overall_accesses::total 2547229 # number of overall (read+write) accesses 810system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.406359 # miss rate for ReadReq accesses 811system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099865 # miss rate for ReadReq accesses 812system.cpu.l2cache.ReadReq_miss_rate::total 0.101352 # miss rate for ReadReq accesses 813system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989854 # miss rate for UpgradeReq accesses 814system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989854 # miss rate for UpgradeReq accesses 815system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268318 # miss rate for ReadExReq accesses 816system.cpu.l2cache.ReadExReq_miss_rate::total 0.268318 # miss rate for ReadExReq accesses 817system.cpu.l2cache.demand_miss_rate::cpu.inst 0.406359 # miss rate for demand accesses 818system.cpu.l2cache.demand_miss_rate::cpu.data 0.151060 # miss rate for demand accesses 819system.cpu.l2cache.demand_miss_rate::total 0.151924 # miss rate for demand accesses 820system.cpu.l2cache.overall_miss_rate::cpu.inst 0.406359 # miss rate for overall accesses 821system.cpu.l2cache.overall_miss_rate::cpu.data 0.151060 # miss rate for overall accesses 822system.cpu.l2cache.overall_miss_rate::total 0.151924 # miss rate for overall accesses 823system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74010.779555 # average ReadReq miss latency 824system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73333.807185 # average ReadReq miss latency 825system.cpu.l2cache.ReadReq_avg_miss_latency::total 73346.980108 # average ReadReq miss latency 826system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 53.515364 # average UpgradeReq miss latency 827system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 53.515364 # average UpgradeReq miss latency 828system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72185.917797 # average ReadExReq miss latency 829system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72185.917797 # average ReadExReq miss latency 830system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.779555 # average overall miss latency 831system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72714.151300 # average overall miss latency 832system.cpu.l2cache.demand_avg_miss_latency::total 72725.885099 # average overall miss latency 833system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.779555 # average overall miss latency 834system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72714.151300 # average overall miss latency 835system.cpu.l2cache.overall_avg_miss_latency::total 72725.885099 # average overall miss latency 836system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 837system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 838system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 839system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 840system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 841system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 842system.cpu.l2cache.fast_writes 0 # number of fast writes performed 843system.cpu.l2cache.cache_copies 0 # number of cache copies performed 844system.cpu.l2cache.writebacks::writebacks 294074 # number of writebacks 845system.cpu.l2cache.writebacks::total 294074 # number of writebacks 846system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 847system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 848system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 849system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 850system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 851system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 852system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3501 # number of ReadReq MSHR misses 853system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176470 # number of ReadReq MSHR misses 854system.cpu.l2cache.ReadReq_mshr_misses::total 179971 # number of ReadReq MSHR misses 855system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 179025 # number of UpgradeReq MSHR misses 856system.cpu.l2cache.UpgradeReq_mshr_misses::total 179025 # number of UpgradeReq MSHR misses 857system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207012 # number of ReadExReq MSHR misses 858system.cpu.l2cache.ReadExReq_mshr_misses::total 207012 # number of ReadExReq MSHR misses 859system.cpu.l2cache.demand_mshr_misses::cpu.inst 3501 # number of demand (read+write) MSHR misses 860system.cpu.l2cache.demand_mshr_misses::cpu.data 383482 # number of demand (read+write) MSHR misses 861system.cpu.l2cache.demand_mshr_misses::total 386983 # number of demand (read+write) MSHR misses 862system.cpu.l2cache.overall_mshr_misses::cpu.inst 3501 # number of overall MSHR misses 863system.cpu.l2cache.overall_mshr_misses::cpu.data 383482 # number of overall MSHR misses 864system.cpu.l2cache.overall_mshr_misses::total 386983 # number of overall MSHR misses 865system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215395750 # number of ReadReq MSHR miss cycles 866system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10692730954 # number of ReadReq MSHR miss cycles 867system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10908126704 # number of ReadReq MSHR miss cycles 868system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1807258037 # number of UpgradeReq MSHR miss cycles 869system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1807258037 # number of UpgradeReq MSHR miss cycles 870system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12309448785 # number of ReadExReq MSHR miss cycles 871system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12309448785 # number of ReadExReq MSHR miss cycles 872system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215395750 # number of demand (read+write) MSHR miss cycles 873system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23002179739 # number of demand (read+write) MSHR miss cycles 874system.cpu.l2cache.demand_mshr_miss_latency::total 23217575489 # number of demand (read+write) MSHR miss cycles 875system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215395750 # number of overall MSHR miss cycles 876system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23002179739 # number of overall MSHR miss cycles 877system.cpu.l2cache.overall_mshr_miss_latency::total 23217575489 # number of overall MSHR miss cycles 878system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.406243 # mshr miss rate for ReadReq accesses 879system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099865 # mshr miss rate for ReadReq accesses 880system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101352 # mshr miss rate for ReadReq accesses 881system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989854 # mshr miss rate for UpgradeReq accesses 882system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989854 # mshr miss rate for UpgradeReq accesses 883system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268318 # mshr miss rate for ReadExReq accesses 884system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268318 # mshr miss rate for ReadExReq accesses 885system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.406243 # mshr miss rate for demand accesses 886system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151060 # mshr miss rate for demand accesses 887system.cpu.l2cache.demand_mshr_miss_rate::total 0.151923 # mshr miss rate for demand accesses 888system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.406243 # mshr miss rate for overall accesses 889system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151060 # mshr miss rate for overall accesses 890system.cpu.l2cache.overall_mshr_miss_rate::total 0.151923 # mshr miss rate for overall accesses 891system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61524.064553 # average ReadReq mshr miss latency 892system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60592.344047 # average ReadReq mshr miss latency 893system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60610.468931 # average ReadReq mshr miss latency 894system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10095.003698 # average UpgradeReq mshr miss latency 895system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10095.003698 # average UpgradeReq mshr miss latency 896system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59462.489059 # average ReadExReq mshr miss latency 897system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59462.489059 # average ReadExReq mshr miss latency 898system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61524.064553 # average overall mshr miss latency 899system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59982.423527 # average overall mshr miss latency 900system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59996.370613 # average overall mshr miss latency 901system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61524.064553 # average overall mshr miss latency 902system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59982.423527 # average overall mshr miss latency 903system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59996.370613 # average overall mshr miss latency 904system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 905system.cpu.dcache.tags.replacements 2534514 # number of replacements 906system.cpu.dcache.tags.tagsinuse 4088.721227 # Cycle average of tags in use 907system.cpu.dcache.tags.total_refs 388791403 # Total number of references to valid blocks. 908system.cpu.dcache.tags.sampled_refs 2538610 # Sample count of references to valid blocks. 909system.cpu.dcache.tags.avg_refs 153.151293 # Average number of references to valid blocks. 910system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. 911system.cpu.dcache.tags.occ_blocks::cpu.data 4088.721227 # Average occupied blocks per requestor 912system.cpu.dcache.tags.occ_percent::cpu.data 0.998223 # Average percentage of cache occupancy 913system.cpu.dcache.tags.occ_percent::total 0.998223 # Average percentage of cache occupancy 914system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 915system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 916system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 917system.cpu.dcache.tags.age_task_id_blocks_1024::2 861 # Occupied blocks per task id 918system.cpu.dcache.tags.age_task_id_blocks_1024::3 3187 # Occupied blocks per task id 919system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 920system.cpu.dcache.tags.tag_accesses 786699916 # Number of tag accesses 921system.cpu.dcache.tags.data_accesses 786699916 # Number of data accesses 922system.cpu.dcache.ReadReq_hits::cpu.data 240205034 # number of ReadReq hits 923system.cpu.dcache.ReadReq_hits::total 240205034 # number of ReadReq hits 924system.cpu.dcache.WriteReq_hits::cpu.data 148189734 # number of WriteReq hits 925system.cpu.dcache.WriteReq_hits::total 148189734 # number of WriteReq hits 926system.cpu.dcache.demand_hits::cpu.data 388394768 # number of demand (read+write) hits 927system.cpu.dcache.demand_hits::total 388394768 # number of demand (read+write) hits 928system.cpu.dcache.overall_hits::cpu.data 388394768 # number of overall hits 929system.cpu.dcache.overall_hits::total 388394768 # number of overall hits 930system.cpu.dcache.ReadReq_misses::cpu.data 2715417 # number of ReadReq misses 931system.cpu.dcache.ReadReq_misses::total 2715417 # number of ReadReq misses 932system.cpu.dcache.WriteReq_misses::cpu.data 970468 # number of WriteReq misses 933system.cpu.dcache.WriteReq_misses::total 970468 # number of WriteReq misses 934system.cpu.dcache.demand_misses::cpu.data 3685885 # number of demand (read+write) misses 935system.cpu.dcache.demand_misses::total 3685885 # number of demand (read+write) misses 936system.cpu.dcache.overall_misses::cpu.data 3685885 # number of overall misses 937system.cpu.dcache.overall_misses::total 3685885 # number of overall misses 938system.cpu.dcache.ReadReq_miss_latency::cpu.data 55284847940 # number of ReadReq miss cycles 939system.cpu.dcache.ReadReq_miss_latency::total 55284847940 # number of ReadReq miss cycles 940system.cpu.dcache.WriteReq_miss_latency::cpu.data 27786671624 # number of WriteReq miss cycles 941system.cpu.dcache.WriteReq_miss_latency::total 27786671624 # number of WriteReq miss cycles 942system.cpu.dcache.demand_miss_latency::cpu.data 83071519564 # number of demand (read+write) miss cycles 943system.cpu.dcache.demand_miss_latency::total 83071519564 # number of demand (read+write) miss cycles 944system.cpu.dcache.overall_miss_latency::cpu.data 83071519564 # number of overall miss cycles 945system.cpu.dcache.overall_miss_latency::total 83071519564 # number of overall miss cycles 946system.cpu.dcache.ReadReq_accesses::cpu.data 242920451 # number of ReadReq accesses(hits+misses) 947system.cpu.dcache.ReadReq_accesses::total 242920451 # number of ReadReq accesses(hits+misses) 948system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 949system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) 950system.cpu.dcache.demand_accesses::cpu.data 392080653 # number of demand (read+write) accesses 951system.cpu.dcache.demand_accesses::total 392080653 # number of demand (read+write) accesses 952system.cpu.dcache.overall_accesses::cpu.data 392080653 # number of overall (read+write) accesses 953system.cpu.dcache.overall_accesses::total 392080653 # number of overall (read+write) accesses 954system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011178 # miss rate for ReadReq accesses 955system.cpu.dcache.ReadReq_miss_rate::total 0.011178 # miss rate for ReadReq accesses 956system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006506 # miss rate for WriteReq accesses 957system.cpu.dcache.WriteReq_miss_rate::total 0.006506 # miss rate for WriteReq accesses 958system.cpu.dcache.demand_miss_rate::cpu.data 0.009401 # miss rate for demand accesses 959system.cpu.dcache.demand_miss_rate::total 0.009401 # miss rate for demand accesses 960system.cpu.dcache.overall_miss_rate::cpu.data 0.009401 # miss rate for overall accesses 961system.cpu.dcache.overall_miss_rate::total 0.009401 # miss rate for overall accesses 962system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20359.616199 # average ReadReq miss latency 963system.cpu.dcache.ReadReq_avg_miss_latency::total 20359.616199 # average ReadReq miss latency 964system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28632.238903 # average WriteReq miss latency 965system.cpu.dcache.WriteReq_avg_miss_latency::total 28632.238903 # average WriteReq miss latency 966system.cpu.dcache.demand_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency 967system.cpu.dcache.demand_avg_miss_latency::total 22537.740479 # average overall miss latency 968system.cpu.dcache.overall_avg_miss_latency::cpu.data 22537.740479 # average overall miss latency 969system.cpu.dcache.overall_avg_miss_latency::total 22537.740479 # average overall miss latency 970system.cpu.dcache.blocked_cycles::no_mshrs 8578 # number of cycles access was blocked 971system.cpu.dcache.blocked_cycles::no_targets 67 # number of cycles access was blocked 972system.cpu.dcache.blocked::no_mshrs 914 # number of cycles access was blocked 973system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked 974system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.385120 # average number of cycles each access was blocked 975system.cpu.dcache.avg_blocked_cycles::no_targets 13.400000 # average number of cycles each access was blocked 976system.cpu.dcache.fast_writes 0 # number of fast writes performed 977system.cpu.dcache.cache_copies 0 # number of cache copies performed 978system.cpu.dcache.writebacks::writebacks 2333034 # number of writebacks 979system.cpu.dcache.writebacks::total 2333034 # number of writebacks 980system.cpu.dcache.ReadReq_mshr_hits::cpu.data 948123 # number of ReadReq MSHR hits 981system.cpu.dcache.ReadReq_mshr_hits::total 948123 # number of ReadReq MSHR hits 982system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18291 # number of WriteReq MSHR hits 983system.cpu.dcache.WriteReq_mshr_hits::total 18291 # number of WriteReq MSHR hits 984system.cpu.dcache.demand_mshr_hits::cpu.data 966414 # number of demand (read+write) MSHR hits 985system.cpu.dcache.demand_mshr_hits::total 966414 # number of demand (read+write) MSHR hits 986system.cpu.dcache.overall_mshr_hits::cpu.data 966414 # number of overall MSHR hits 987system.cpu.dcache.overall_mshr_hits::total 966414 # number of overall MSHR hits 988system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767294 # number of ReadReq MSHR misses 989system.cpu.dcache.ReadReq_mshr_misses::total 1767294 # number of ReadReq MSHR misses 990system.cpu.dcache.WriteReq_mshr_misses::cpu.data 952177 # number of WriteReq MSHR misses 991system.cpu.dcache.WriteReq_mshr_misses::total 952177 # number of WriteReq MSHR misses 992system.cpu.dcache.demand_mshr_misses::cpu.data 2719471 # number of demand (read+write) MSHR misses 993system.cpu.dcache.demand_mshr_misses::total 2719471 # number of demand (read+write) MSHR misses 994system.cpu.dcache.overall_mshr_misses::cpu.data 2719471 # number of overall MSHR misses 995system.cpu.dcache.overall_mshr_misses::total 2719471 # number of overall MSHR misses 996system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30652377753 # number of ReadReq MSHR miss cycles 997system.cpu.dcache.ReadReq_mshr_miss_latency::total 30652377753 # number of ReadReq MSHR miss cycles 998system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25560484625 # number of WriteReq MSHR miss cycles 999system.cpu.dcache.WriteReq_mshr_miss_latency::total 25560484625 # number of WriteReq MSHR miss cycles 1000system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56212862378 # number of demand (read+write) MSHR miss cycles 1001system.cpu.dcache.demand_mshr_miss_latency::total 56212862378 # number of demand (read+write) MSHR miss cycles 1002system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56212862378 # number of overall MSHR miss cycles 1003system.cpu.dcache.overall_mshr_miss_latency::total 56212862378 # number of overall MSHR miss cycles 1004system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007275 # mshr miss rate for ReadReq accesses 1005system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007275 # mshr miss rate for ReadReq accesses 1006system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006384 # mshr miss rate for WriteReq accesses 1007system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006384 # mshr miss rate for WriteReq accesses 1008system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for demand accesses 1009system.cpu.dcache.demand_mshr_miss_rate::total 0.006936 # mshr miss rate for demand accesses 1010system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006936 # mshr miss rate for overall accesses 1011system.cpu.dcache.overall_mshr_miss_rate::total 0.006936 # mshr miss rate for overall accesses 1012system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17344.243659 # average ReadReq mshr miss latency 1013system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17344.243659 # average ReadReq mshr miss latency 1014system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26844.257554 # average WriteReq mshr miss latency 1015system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26844.257554 # average WriteReq mshr miss latency 1016system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency 1017system.cpu.dcache.demand_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency 1018system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20670.513632 # average overall mshr miss latency 1019system.cpu.dcache.overall_avg_mshr_miss_latency::total 20670.513632 # average overall mshr miss latency 1020system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1021 1022---------- End Simulation Statistics ---------- 1023