config.ini revision 10645
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu.branchPred 58cachePorts=200 59checker=Null 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=1 69decodeWidth=8 70dispatchWidth=8 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dtb=system.cpu.dtb 75eventq_index=0 76fetchBufferSize=64 77fetchQueueSize=32 78fetchToDecodeDelay=1 79fetchTrapLatency=1 80fetchWidth=8 81forwardComSize=5 82fuPool=system.cpu.fuPool 83function_trace=false 84function_trace_start=0 85iewToCommitDelay=1 86iewToDecodeDelay=1 87iewToFetchDelay=1 88iewToRenameDelay=1 89interrupts=system.cpu.interrupts 90isa=system.cpu.isa 91issueToExecuteDelay=1 92issueWidth=8 93itb=system.cpu.itb 94max_insts_all_threads=0 95max_insts_any_thread=0 96max_loads_all_threads=0 97max_loads_any_thread=0 98needsTSO=true 99numIQEntries=64 100numPhysCCRegs=1280 101numPhysFloatRegs=256 102numPhysIntRegs=256 103numROBEntries=192 104numRobs=1 105numThreads=1 106profile=0 107progress_interval=0 108renameToDecodeDelay=1 109renameToFetchDelay=1 110renameToIEWDelay=2 111renameToROBDelay=1 112renameWidth=8 113simpoint_start_insts= 114smtCommitPolicy=RoundRobin 115smtFetchPolicy=SingleThread 116smtIQPolicy=Partitioned 117smtIQThreshold=100 118smtLSQPolicy=Partitioned 119smtLSQThreshold=100 120smtNumFetchingThreads=1 121smtROBPolicy=Partitioned 122smtROBThreshold=100 123socket_id=0 124squashWidth=8 125store_set_clear_period=250000 126switched_out=false 127system=system 128tracer=system.cpu.tracer 129trapLatency=13 130wbWidth=8 131workload=system.cpu.workload 132dcache_port=system.cpu.dcache.cpu_side 133icache_port=system.cpu.icache.cpu_side 134 135[system.cpu.apic_clk_domain] 136type=DerivedClockDomain 137clk_divider=16 138clk_domain=system.cpu_clk_domain 139eventq_index=0 140 141[system.cpu.branchPred] 142type=BranchPredictor 143BTBEntries=4096 144BTBTagSize=16 145RASSize=16 146choiceCtrBits=2 147choicePredictorSize=8192 148eventq_index=0 149globalCtrBits=2 150globalPredictorSize=8192 151instShiftAmt=2 152localCtrBits=2 153localHistoryTableSize=2048 154localPredictorSize=2048 155numThreads=1 156predType=tournament 157 158[system.cpu.dcache] 159type=BaseCache 160children=tags 161addr_ranges=0:18446744073709551615 162assoc=2 163clk_domain=system.cpu_clk_domain 164demand_mshr_reserve=1 165eventq_index=0 166forward_snoops=true 167hit_latency=2 168is_top_level=true 169max_miss_count=0 170mshrs=4 171prefetch_on_access=false 172prefetcher=Null 173response_latency=2 174sequential_access=false 175size=262144 176system=system 177tags=system.cpu.dcache.tags 178tgts_per_mshr=20 179two_queue=false 180write_buffers=8 181cpu_side=system.cpu.dcache_port 182mem_side=system.cpu.toL2Bus.slave[1] 183 184[system.cpu.dcache.tags] 185type=LRU 186assoc=2 187block_size=64 188clk_domain=system.cpu_clk_domain 189eventq_index=0 190hit_latency=2 191sequential_access=false 192size=262144 193 194[system.cpu.dtb] 195type=X86TLB 196children=walker 197eventq_index=0 198size=64 199walker=system.cpu.dtb.walker 200 201[system.cpu.dtb.walker] 202type=X86PagetableWalker 203clk_domain=system.cpu_clk_domain 204eventq_index=0 205num_squash_per_cycle=4 206system=system 207port=system.cpu.toL2Bus.slave[3] 208 209[system.cpu.fuPool] 210type=FUPool 211children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 212FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 213eventq_index=0 214 215[system.cpu.fuPool.FUList0] 216type=FUDesc 217children=opList 218count=6 219eventq_index=0 220opList=system.cpu.fuPool.FUList0.opList 221 222[system.cpu.fuPool.FUList0.opList] 223type=OpDesc 224eventq_index=0 225issueLat=1 226opClass=IntAlu 227opLat=1 228 229[system.cpu.fuPool.FUList1] 230type=FUDesc 231children=opList0 opList1 232count=2 233eventq_index=0 234opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 235 236[system.cpu.fuPool.FUList1.opList0] 237type=OpDesc 238eventq_index=0 239issueLat=1 240opClass=IntMult 241opLat=3 242 243[system.cpu.fuPool.FUList1.opList1] 244type=OpDesc 245eventq_index=0 246issueLat=19 247opClass=IntDiv 248opLat=20 249 250[system.cpu.fuPool.FUList2] 251type=FUDesc 252children=opList0 opList1 opList2 253count=4 254eventq_index=0 255opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 256 257[system.cpu.fuPool.FUList2.opList0] 258type=OpDesc 259eventq_index=0 260issueLat=1 261opClass=FloatAdd 262opLat=2 263 264[system.cpu.fuPool.FUList2.opList1] 265type=OpDesc 266eventq_index=0 267issueLat=1 268opClass=FloatCmp 269opLat=2 270 271[system.cpu.fuPool.FUList2.opList2] 272type=OpDesc 273eventq_index=0 274issueLat=1 275opClass=FloatCvt 276opLat=2 277 278[system.cpu.fuPool.FUList3] 279type=FUDesc 280children=opList0 opList1 opList2 281count=2 282eventq_index=0 283opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 284 285[system.cpu.fuPool.FUList3.opList0] 286type=OpDesc 287eventq_index=0 288issueLat=1 289opClass=FloatMult 290opLat=4 291 292[system.cpu.fuPool.FUList3.opList1] 293type=OpDesc 294eventq_index=0 295issueLat=12 296opClass=FloatDiv 297opLat=12 298 299[system.cpu.fuPool.FUList3.opList2] 300type=OpDesc 301eventq_index=0 302issueLat=24 303opClass=FloatSqrt 304opLat=24 305 306[system.cpu.fuPool.FUList4] 307type=FUDesc 308children=opList 309count=0 310eventq_index=0 311opList=system.cpu.fuPool.FUList4.opList 312 313[system.cpu.fuPool.FUList4.opList] 314type=OpDesc 315eventq_index=0 316issueLat=1 317opClass=MemRead 318opLat=1 319 320[system.cpu.fuPool.FUList5] 321type=FUDesc 322children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 323count=4 324eventq_index=0 325opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 326 327[system.cpu.fuPool.FUList5.opList00] 328type=OpDesc 329eventq_index=0 330issueLat=1 331opClass=SimdAdd 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList01] 335type=OpDesc 336eventq_index=0 337issueLat=1 338opClass=SimdAddAcc 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList02] 342type=OpDesc 343eventq_index=0 344issueLat=1 345opClass=SimdAlu 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList03] 349type=OpDesc 350eventq_index=0 351issueLat=1 352opClass=SimdCmp 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList04] 356type=OpDesc 357eventq_index=0 358issueLat=1 359opClass=SimdCvt 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList05] 363type=OpDesc 364eventq_index=0 365issueLat=1 366opClass=SimdMisc 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList06] 370type=OpDesc 371eventq_index=0 372issueLat=1 373opClass=SimdMult 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList07] 377type=OpDesc 378eventq_index=0 379issueLat=1 380opClass=SimdMultAcc 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList08] 384type=OpDesc 385eventq_index=0 386issueLat=1 387opClass=SimdShift 388opLat=1 389 390[system.cpu.fuPool.FUList5.opList09] 391type=OpDesc 392eventq_index=0 393issueLat=1 394opClass=SimdShiftAcc 395opLat=1 396 397[system.cpu.fuPool.FUList5.opList10] 398type=OpDesc 399eventq_index=0 400issueLat=1 401opClass=SimdSqrt 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList11] 405type=OpDesc 406eventq_index=0 407issueLat=1 408opClass=SimdFloatAdd 409opLat=1 410 411[system.cpu.fuPool.FUList5.opList12] 412type=OpDesc 413eventq_index=0 414issueLat=1 415opClass=SimdFloatAlu 416opLat=1 417 418[system.cpu.fuPool.FUList5.opList13] 419type=OpDesc 420eventq_index=0 421issueLat=1 422opClass=SimdFloatCmp 423opLat=1 424 425[system.cpu.fuPool.FUList5.opList14] 426type=OpDesc 427eventq_index=0 428issueLat=1 429opClass=SimdFloatCvt 430opLat=1 431 432[system.cpu.fuPool.FUList5.opList15] 433type=OpDesc 434eventq_index=0 435issueLat=1 436opClass=SimdFloatDiv 437opLat=1 438 439[system.cpu.fuPool.FUList5.opList16] 440type=OpDesc 441eventq_index=0 442issueLat=1 443opClass=SimdFloatMisc 444opLat=1 445 446[system.cpu.fuPool.FUList5.opList17] 447type=OpDesc 448eventq_index=0 449issueLat=1 450opClass=SimdFloatMult 451opLat=1 452 453[system.cpu.fuPool.FUList5.opList18] 454type=OpDesc 455eventq_index=0 456issueLat=1 457opClass=SimdFloatMultAcc 458opLat=1 459 460[system.cpu.fuPool.FUList5.opList19] 461type=OpDesc 462eventq_index=0 463issueLat=1 464opClass=SimdFloatSqrt 465opLat=1 466 467[system.cpu.fuPool.FUList6] 468type=FUDesc 469children=opList 470count=0 471eventq_index=0 472opList=system.cpu.fuPool.FUList6.opList 473 474[system.cpu.fuPool.FUList6.opList] 475type=OpDesc 476eventq_index=0 477issueLat=1 478opClass=MemWrite 479opLat=1 480 481[system.cpu.fuPool.FUList7] 482type=FUDesc 483children=opList0 opList1 484count=4 485eventq_index=0 486opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 487 488[system.cpu.fuPool.FUList7.opList0] 489type=OpDesc 490eventq_index=0 491issueLat=1 492opClass=MemRead 493opLat=1 494 495[system.cpu.fuPool.FUList7.opList1] 496type=OpDesc 497eventq_index=0 498issueLat=1 499opClass=MemWrite 500opLat=1 501 502[system.cpu.fuPool.FUList8] 503type=FUDesc 504children=opList 505count=1 506eventq_index=0 507opList=system.cpu.fuPool.FUList8.opList 508 509[system.cpu.fuPool.FUList8.opList] 510type=OpDesc 511eventq_index=0 512issueLat=3 513opClass=IprAccess 514opLat=3 515 516[system.cpu.icache] 517type=BaseCache 518children=tags 519addr_ranges=0:18446744073709551615 520assoc=2 521clk_domain=system.cpu_clk_domain 522demand_mshr_reserve=1 523eventq_index=0 524forward_snoops=true 525hit_latency=2 526is_top_level=true 527max_miss_count=0 528mshrs=4 529prefetch_on_access=false 530prefetcher=Null 531response_latency=2 532sequential_access=false 533size=131072 534system=system 535tags=system.cpu.icache.tags 536tgts_per_mshr=20 537two_queue=false 538write_buffers=8 539cpu_side=system.cpu.icache_port 540mem_side=system.cpu.toL2Bus.slave[0] 541 542[system.cpu.icache.tags] 543type=LRU 544assoc=2 545block_size=64 546clk_domain=system.cpu_clk_domain 547eventq_index=0 548hit_latency=2 549sequential_access=false 550size=131072 551 552[system.cpu.interrupts] 553type=X86LocalApic 554clk_domain=system.cpu.apic_clk_domain 555eventq_index=0 556int_latency=1000 557pio_addr=2305843009213693952 558pio_latency=100000 559system=system 560int_master=system.membus.slave[2] 561int_slave=system.membus.master[2] 562pio=system.membus.master[1] 563 564[system.cpu.isa] 565type=X86ISA 566eventq_index=0 567 568[system.cpu.itb] 569type=X86TLB 570children=walker 571eventq_index=0 572size=64 573walker=system.cpu.itb.walker 574 575[system.cpu.itb.walker] 576type=X86PagetableWalker 577clk_domain=system.cpu_clk_domain 578eventq_index=0 579num_squash_per_cycle=4 580system=system 581port=system.cpu.toL2Bus.slave[2] 582 583[system.cpu.l2cache] 584type=BaseCache 585children=tags 586addr_ranges=0:18446744073709551615 587assoc=8 588clk_domain=system.cpu_clk_domain 589demand_mshr_reserve=1 590eventq_index=0 591forward_snoops=true 592hit_latency=20 593is_top_level=false 594max_miss_count=0 595mshrs=20 596prefetch_on_access=false 597prefetcher=Null 598response_latency=20 599sequential_access=false 600size=2097152 601system=system 602tags=system.cpu.l2cache.tags 603tgts_per_mshr=12 604two_queue=false 605write_buffers=8 606cpu_side=system.cpu.toL2Bus.master[0] 607mem_side=system.membus.slave[1] 608 609[system.cpu.l2cache.tags] 610type=LRU 611assoc=8 612block_size=64 613clk_domain=system.cpu_clk_domain 614eventq_index=0 615hit_latency=20 616sequential_access=false 617size=2097152 618 619[system.cpu.toL2Bus] 620type=CoherentXBar 621clk_domain=system.cpu_clk_domain 622eventq_index=0 623header_cycles=1 624snoop_filter=Null 625system=system 626use_default_range=false 627width=32 628master=system.cpu.l2cache.cpu_side 629slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 630 631[system.cpu.tracer] 632type=ExeTracer 633eventq_index=0 634 635[system.cpu.workload] 636type=LiveProcess 637cmd=parser 2.1.dict -batch 638cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing 639drivers= 640egid=100 641env= 642errout=cerr 643euid=100 644eventq_index=0 645executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser 646gid=100 647input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in 648kvmInSE=false 649max_stack_size=67108864 650output=cout 651pid=100 652ppid=99 653simpoint=114600000000 654system=system 655uid=100 656useArchPT=false 657 658[system.cpu_clk_domain] 659type=SrcClockDomain 660clock=500 661domain_id=-1 662eventq_index=0 663init_perf_level=0 664voltage_domain=system.voltage_domain 665 666[system.dvfs_handler] 667type=DVFSHandler 668domains= 669enable=false 670eventq_index=0 671sys_clk_domain=system.clk_domain 672transition_latency=100000000 673 674[system.membus] 675type=CoherentXBar 676clk_domain=system.clk_domain 677eventq_index=0 678header_cycles=1 679snoop_filter=Null 680system=system 681use_default_range=false 682width=8 683master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 684slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 685 686[system.physmem] 687type=DRAMCtrl 688IDD0=0.075000 689IDD02=0.000000 690IDD2N=0.050000 691IDD2N2=0.000000 692IDD2P0=0.000000 693IDD2P02=0.000000 694IDD2P1=0.000000 695IDD2P12=0.000000 696IDD3N=0.057000 697IDD3N2=0.000000 698IDD3P0=0.000000 699IDD3P02=0.000000 700IDD3P1=0.000000 701IDD3P12=0.000000 702IDD4R=0.187000 703IDD4R2=0.000000 704IDD4W=0.165000 705IDD4W2=0.000000 706IDD5=0.220000 707IDD52=0.000000 708IDD6=0.000000 709IDD62=0.000000 710VDD=1.500000 711VDD2=0.000000 712activation_limit=4 713addr_mapping=RoRaBaChCo 714bank_groups_per_rank=0 715banks_per_rank=8 716burst_length=8 717channels=1 718clk_domain=system.clk_domain 719conf_table_reported=true 720device_bus_width=8 721device_rowbuffer_size=1024 722device_size=536870912 723devices_per_rank=8 724dll=true 725eventq_index=0 726in_addr_map=true 727max_accesses_per_row=16 728mem_sched_policy=frfcfs 729min_writes_per_switch=16 730null=false 731page_policy=open_adaptive 732range=0:134217727 733ranks_per_channel=2 734read_buffer_size=32 735static_backend_latency=10000 736static_frontend_latency=10000 737tBURST=5000 738tCCD_L=0 739tCK=1250 740tCL=13750 741tCS=2500 742tRAS=35000 743tRCD=13750 744tREFI=7800000 745tRFC=260000 746tRP=13750 747tRRD=6000 748tRRD_L=0 749tRTP=7500 750tRTW=2500 751tWR=15000 752tWTR=7500 753tXAW=30000 754tXP=0 755tXPDLL=0 756tXS=0 757tXSDLL=0 758write_buffer_size=64 759write_high_thresh_perc=85 760write_low_thresh_perc=50 761port=system.membus.master[0] 762 763[system.voltage_domain] 764type=VoltageDomain 765eventq_index=0 766voltage=1.000000 767 768