config.ini revision 8825
17893SN/A[root]
27893SN/Atype=Root
37893SN/Achildren=system
48825Snilay@cs.wisc.edufull_system=false
57893SN/Atime_sync_enable=false
67893SN/Atime_sync_period=100000000000
77893SN/Atime_sync_spin_threshold=100000000
87893SN/A
97893SN/A[system]
107893SN/Atype=System
117893SN/Achildren=cpu membus physmem
128825Snilay@cs.wisc.eduboot_osflags=a
138825Snilay@cs.wisc.eduinit_param=0
148825Snilay@cs.wisc.edukernel=
158825Snilay@cs.wisc.eduload_addr_mask=1099511627775
167893SN/Amem_mode=atomic
178464SN/Amemories=system.physmem
188721SN/Anum_work_ids=16
197893SN/Aphysmem=system.physmem
208825Snilay@cs.wisc.edureadfile=
218825Snilay@cs.wisc.edusymbolfile=
227935SN/Awork_begin_ckpt_count=0
237935SN/Awork_begin_cpu_id_exit=-1
247935SN/Awork_begin_exit_count=0
257935SN/Awork_cpus_ckpt_count=0
267935SN/Awork_end_ckpt_count=0
277935SN/Awork_end_exit_count=0
287935SN/Awork_item_id=-1
298721SN/Asystem_port=system.membus.port[0]
307893SN/A
317893SN/A[system.cpu]
327893SN/Atype=DerivO3CPU
338825Snilay@cs.wisc.educhildren=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
347893SN/ABTBEntries=4096
357893SN/ABTBTagSize=16
367893SN/ALFSTSize=1024
377893SN/ALQEntries=32
388241SN/ALSQCheckLoads=true
398241SN/ALSQDepCheckShift=4
407893SN/ARASSize=16
417893SN/ASQEntries=32
427893SN/ASSITSize=1024
437893SN/Aactivity=0
447893SN/AbackComSize=5
457893SN/AcachePorts=200
467893SN/Achecker=Null
477893SN/AchoiceCtrBits=2
487893SN/AchoicePredictorSize=8192
497893SN/Aclock=500
507893SN/AcommitToDecodeDelay=1
517893SN/AcommitToFetchDelay=1
527893SN/AcommitToIEWDelay=1
537893SN/AcommitToRenameDelay=1
547893SN/AcommitWidth=8
557893SN/Acpu_id=0
567893SN/AdecodeToFetchDelay=1
577893SN/AdecodeToRenameDelay=1
587893SN/AdecodeWidth=8
597893SN/Adefer_registration=false
607893SN/AdispatchWidth=8
617893SN/Ado_checkpoint_insts=true
628825Snilay@cs.wisc.edudo_quiesce=true
637893SN/Ado_statistics_insts=true
647893SN/Adtb=system.cpu.dtb
657893SN/AfetchToDecodeDelay=1
667893SN/AfetchTrapLatency=1
677893SN/AfetchWidth=8
687893SN/AforwardComSize=5
697893SN/AfuPool=system.cpu.fuPool
707893SN/Afunction_trace=false
717893SN/Afunction_trace_start=0
727893SN/AglobalCtrBits=2
737893SN/AglobalHistoryBits=13
747893SN/AglobalPredictorSize=8192
757893SN/AiewToCommitDelay=1
767893SN/AiewToDecodeDelay=1
777893SN/AiewToFetchDelay=1
787893SN/AiewToRenameDelay=1
797893SN/AinstShiftAmt=2
808825Snilay@cs.wisc.eduinterrupts=system.cpu.interrupts
817893SN/AissueToExecuteDelay=1
827893SN/AissueWidth=8
837893SN/Aitb=system.cpu.itb
847893SN/AlocalCtrBits=2
857893SN/AlocalHistoryBits=11
867893SN/AlocalHistoryTableSize=2048
877893SN/AlocalPredictorSize=2048
887893SN/Amax_insts_all_threads=0
897893SN/Amax_insts_any_thread=0
907893SN/Amax_loads_all_threads=0
917893SN/Amax_loads_any_thread=0
928728SN/AneedsTSO=true
937893SN/AnumIQEntries=64
947893SN/AnumPhysFloatRegs=256
957893SN/AnumPhysIntRegs=256
967893SN/AnumROBEntries=192
977893SN/AnumRobs=1
987893SN/AnumThreads=1
997893SN/Aphase=0
1007893SN/ApredType=tournament
1018825Snilay@cs.wisc.eduprofile=0
1027893SN/Aprogress_interval=0
1037893SN/ArenameToDecodeDelay=1
1047893SN/ArenameToFetchDelay=1
1057893SN/ArenameToIEWDelay=2
1067893SN/ArenameToROBDelay=1
1077893SN/ArenameWidth=8
1087893SN/AsmtCommitPolicy=RoundRobin
1097893SN/AsmtFetchPolicy=SingleThread
1107893SN/AsmtIQPolicy=Partitioned
1117893SN/AsmtIQThreshold=100
1127893SN/AsmtLSQPolicy=Partitioned
1137893SN/AsmtLSQThreshold=100
1147893SN/AsmtNumFetchingThreads=1
1157893SN/AsmtROBPolicy=Partitioned
1167893SN/AsmtROBThreshold=100
1177893SN/AsquashWidth=8
1188521SN/Astore_set_clear_period=250000
1197893SN/Asystem=system
1207893SN/Atracer=system.cpu.tracer
1217893SN/AtrapLatency=13
1227893SN/AwbDepth=1
1237893SN/AwbWidth=8
1247893SN/Aworkload=system.cpu.workload
1257893SN/Adcache_port=system.cpu.dcache.cpu_side
1267893SN/Aicache_port=system.cpu.icache.cpu_side
1277893SN/A
1287893SN/A[system.cpu.dcache]
1297893SN/Atype=BaseCache
1307893SN/Aaddr_range=0:18446744073709551615
1317893SN/Aassoc=2
1327893SN/Ablock_size=64
1337893SN/Aforward_snoops=true
1347893SN/Ahash_delay=1
1358200SN/Ais_top_level=true
1367893SN/Alatency=1000
1377893SN/Amax_miss_count=0
1387893SN/Amshrs=10
1397893SN/Anum_cpus=1
1407893SN/Aprefetch_data_accesses_only=false
1417893SN/Aprefetch_degree=1
1427893SN/Aprefetch_latency=10000
1437893SN/Aprefetch_on_access=false
1447893SN/Aprefetch_past_page=false
1457893SN/Aprefetch_policy=none
1467893SN/Aprefetch_serial_squash=false
1477893SN/Aprefetch_use_cpu_id=true
1487893SN/Aprefetcher_size=100
1497893SN/AprioritizeRequests=false
1507893SN/Arepl=Null
1517893SN/Asize=262144
1527893SN/Asubblock_size=0
1537893SN/Atgts_per_mshr=20
1547893SN/Atrace_addr=0
1557893SN/Atwo_queue=false
1567893SN/Awrite_buffers=8
1577893SN/Acpu_side=system.cpu.dcache_port
1587893SN/Amem_side=system.cpu.toL2Bus.port[1]
1597893SN/A
1607893SN/A[system.cpu.dtb]
1617893SN/Atype=X86TLB
1628825Snilay@cs.wisc.educhildren=walker
1637893SN/Asize=64
1648825Snilay@cs.wisc.eduwalker=system.cpu.dtb.walker
1658825Snilay@cs.wisc.edu
1668825Snilay@cs.wisc.edu[system.cpu.dtb.walker]
1678825Snilay@cs.wisc.edutype=X86PagetableWalker
1688825Snilay@cs.wisc.edusystem=system
1698825Snilay@cs.wisc.eduport=system.cpu.toL2Bus.port[3]
1707893SN/A
1717893SN/A[system.cpu.fuPool]
1727893SN/Atype=FUPool
1737893SN/Achildren=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1747893SN/AFUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
1757893SN/A
1767893SN/A[system.cpu.fuPool.FUList0]
1777893SN/Atype=FUDesc
1787893SN/Achildren=opList
1797893SN/Acount=6
1807893SN/AopList=system.cpu.fuPool.FUList0.opList
1817893SN/A
1827893SN/A[system.cpu.fuPool.FUList0.opList]
1837893SN/Atype=OpDesc
1847893SN/AissueLat=1
1857893SN/AopClass=IntAlu
1867893SN/AopLat=1
1877893SN/A
1887893SN/A[system.cpu.fuPool.FUList1]
1897893SN/Atype=FUDesc
1907893SN/Achildren=opList0 opList1
1917893SN/Acount=2
1927893SN/AopList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
1937893SN/A
1947893SN/A[system.cpu.fuPool.FUList1.opList0]
1957893SN/Atype=OpDesc
1967893SN/AissueLat=1
1977893SN/AopClass=IntMult
1987893SN/AopLat=3
1997893SN/A
2007893SN/A[system.cpu.fuPool.FUList1.opList1]
2017893SN/Atype=OpDesc
2027893SN/AissueLat=19
2037893SN/AopClass=IntDiv
2047893SN/AopLat=20
2057893SN/A
2067893SN/A[system.cpu.fuPool.FUList2]
2077893SN/Atype=FUDesc
2087893SN/Achildren=opList0 opList1 opList2
2097893SN/Acount=4
2107893SN/AopList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
2117893SN/A
2127893SN/A[system.cpu.fuPool.FUList2.opList0]
2137893SN/Atype=OpDesc
2147893SN/AissueLat=1
2157893SN/AopClass=FloatAdd
2167893SN/AopLat=2
2177893SN/A
2187893SN/A[system.cpu.fuPool.FUList2.opList1]
2197893SN/Atype=OpDesc
2207893SN/AissueLat=1
2217893SN/AopClass=FloatCmp
2227893SN/AopLat=2
2237893SN/A
2247893SN/A[system.cpu.fuPool.FUList2.opList2]
2257893SN/Atype=OpDesc
2267893SN/AissueLat=1
2277893SN/AopClass=FloatCvt
2287893SN/AopLat=2
2297893SN/A
2307893SN/A[system.cpu.fuPool.FUList3]
2317893SN/Atype=FUDesc
2327893SN/Achildren=opList0 opList1 opList2
2337893SN/Acount=2
2347893SN/AopList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
2357893SN/A
2367893SN/A[system.cpu.fuPool.FUList3.opList0]
2377893SN/Atype=OpDesc
2387893SN/AissueLat=1
2397893SN/AopClass=FloatMult
2407893SN/AopLat=4
2417893SN/A
2427893SN/A[system.cpu.fuPool.FUList3.opList1]
2437893SN/Atype=OpDesc
2447893SN/AissueLat=12
2457893SN/AopClass=FloatDiv
2467893SN/AopLat=12
2477893SN/A
2487893SN/A[system.cpu.fuPool.FUList3.opList2]
2497893SN/Atype=OpDesc
2507893SN/AissueLat=24
2517893SN/AopClass=FloatSqrt
2527893SN/AopLat=24
2537893SN/A
2547893SN/A[system.cpu.fuPool.FUList4]
2557893SN/Atype=FUDesc
2567893SN/Achildren=opList
2577893SN/Acount=0
2587893SN/AopList=system.cpu.fuPool.FUList4.opList
2597893SN/A
2607893SN/A[system.cpu.fuPool.FUList4.opList]
2617893SN/Atype=OpDesc
2627893SN/AissueLat=1
2637893SN/AopClass=MemRead
2647893SN/AopLat=1
2657893SN/A
2667893SN/A[system.cpu.fuPool.FUList5]
2677893SN/Atype=FUDesc
2687893SN/Achildren=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
2697893SN/Acount=4
2707893SN/AopList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
2717893SN/A
2727893SN/A[system.cpu.fuPool.FUList5.opList00]
2737893SN/Atype=OpDesc
2747893SN/AissueLat=1
2757893SN/AopClass=SimdAdd
2767893SN/AopLat=1
2777893SN/A
2787893SN/A[system.cpu.fuPool.FUList5.opList01]
2797893SN/Atype=OpDesc
2807893SN/AissueLat=1
2817893SN/AopClass=SimdAddAcc
2827893SN/AopLat=1
2837893SN/A
2847893SN/A[system.cpu.fuPool.FUList5.opList02]
2857893SN/Atype=OpDesc
2867893SN/AissueLat=1
2877893SN/AopClass=SimdAlu
2887893SN/AopLat=1
2897893SN/A
2907893SN/A[system.cpu.fuPool.FUList5.opList03]
2917893SN/Atype=OpDesc
2927893SN/AissueLat=1
2937893SN/AopClass=SimdCmp
2947893SN/AopLat=1
2957893SN/A
2967893SN/A[system.cpu.fuPool.FUList5.opList04]
2977893SN/Atype=OpDesc
2987893SN/AissueLat=1
2997893SN/AopClass=SimdCvt
3007893SN/AopLat=1
3017893SN/A
3027893SN/A[system.cpu.fuPool.FUList5.opList05]
3037893SN/Atype=OpDesc
3047893SN/AissueLat=1
3057893SN/AopClass=SimdMisc
3067893SN/AopLat=1
3077893SN/A
3087893SN/A[system.cpu.fuPool.FUList5.opList06]
3097893SN/Atype=OpDesc
3107893SN/AissueLat=1
3117893SN/AopClass=SimdMult
3127893SN/AopLat=1
3137893SN/A
3147893SN/A[system.cpu.fuPool.FUList5.opList07]
3157893SN/Atype=OpDesc
3167893SN/AissueLat=1
3177893SN/AopClass=SimdMultAcc
3187893SN/AopLat=1
3197893SN/A
3207893SN/A[system.cpu.fuPool.FUList5.opList08]
3217893SN/Atype=OpDesc
3227893SN/AissueLat=1
3237893SN/AopClass=SimdShift
3247893SN/AopLat=1
3257893SN/A
3267893SN/A[system.cpu.fuPool.FUList5.opList09]
3277893SN/Atype=OpDesc
3287893SN/AissueLat=1
3297893SN/AopClass=SimdShiftAcc
3307893SN/AopLat=1
3317893SN/A
3327893SN/A[system.cpu.fuPool.FUList5.opList10]
3337893SN/Atype=OpDesc
3347893SN/AissueLat=1
3357893SN/AopClass=SimdSqrt
3367893SN/AopLat=1
3377893SN/A
3387893SN/A[system.cpu.fuPool.FUList5.opList11]
3397893SN/Atype=OpDesc
3407893SN/AissueLat=1
3417893SN/AopClass=SimdFloatAdd
3427893SN/AopLat=1
3437893SN/A
3447893SN/A[system.cpu.fuPool.FUList5.opList12]
3457893SN/Atype=OpDesc
3467893SN/AissueLat=1
3477893SN/AopClass=SimdFloatAlu
3487893SN/AopLat=1
3497893SN/A
3507893SN/A[system.cpu.fuPool.FUList5.opList13]
3517893SN/Atype=OpDesc
3527893SN/AissueLat=1
3537893SN/AopClass=SimdFloatCmp
3547893SN/AopLat=1
3557893SN/A
3567893SN/A[system.cpu.fuPool.FUList5.opList14]
3577893SN/Atype=OpDesc
3587893SN/AissueLat=1
3597893SN/AopClass=SimdFloatCvt
3607893SN/AopLat=1
3617893SN/A
3627893SN/A[system.cpu.fuPool.FUList5.opList15]
3637893SN/Atype=OpDesc
3647893SN/AissueLat=1
3657893SN/AopClass=SimdFloatDiv
3667893SN/AopLat=1
3677893SN/A
3687893SN/A[system.cpu.fuPool.FUList5.opList16]
3697893SN/Atype=OpDesc
3707893SN/AissueLat=1
3717893SN/AopClass=SimdFloatMisc
3727893SN/AopLat=1
3737893SN/A
3747893SN/A[system.cpu.fuPool.FUList5.opList17]
3757893SN/Atype=OpDesc
3767893SN/AissueLat=1
3777893SN/AopClass=SimdFloatMult
3787893SN/AopLat=1
3797893SN/A
3807893SN/A[system.cpu.fuPool.FUList5.opList18]
3817893SN/Atype=OpDesc
3827893SN/AissueLat=1
3837893SN/AopClass=SimdFloatMultAcc
3847893SN/AopLat=1
3857893SN/A
3867893SN/A[system.cpu.fuPool.FUList5.opList19]
3877893SN/Atype=OpDesc
3887893SN/AissueLat=1
3897893SN/AopClass=SimdFloatSqrt
3907893SN/AopLat=1
3917893SN/A
3927893SN/A[system.cpu.fuPool.FUList6]
3937893SN/Atype=FUDesc
3947893SN/Achildren=opList
3957893SN/Acount=0
3967893SN/AopList=system.cpu.fuPool.FUList6.opList
3977893SN/A
3987893SN/A[system.cpu.fuPool.FUList6.opList]
3997893SN/Atype=OpDesc
4007893SN/AissueLat=1
4017893SN/AopClass=MemWrite
4027893SN/AopLat=1
4037893SN/A
4047893SN/A[system.cpu.fuPool.FUList7]
4057893SN/Atype=FUDesc
4067893SN/Achildren=opList0 opList1
4077893SN/Acount=4
4087893SN/AopList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
4097893SN/A
4107893SN/A[system.cpu.fuPool.FUList7.opList0]
4117893SN/Atype=OpDesc
4127893SN/AissueLat=1
4137893SN/AopClass=MemRead
4147893SN/AopLat=1
4157893SN/A
4167893SN/A[system.cpu.fuPool.FUList7.opList1]
4177893SN/Atype=OpDesc
4187893SN/AissueLat=1
4197893SN/AopClass=MemWrite
4207893SN/AopLat=1
4217893SN/A
4227893SN/A[system.cpu.fuPool.FUList8]
4237893SN/Atype=FUDesc
4247893SN/Achildren=opList
4257893SN/Acount=1
4267893SN/AopList=system.cpu.fuPool.FUList8.opList
4277893SN/A
4287893SN/A[system.cpu.fuPool.FUList8.opList]
4297893SN/Atype=OpDesc
4307893SN/AissueLat=3
4317893SN/AopClass=IprAccess
4327893SN/AopLat=3
4337893SN/A
4347893SN/A[system.cpu.icache]
4357893SN/Atype=BaseCache
4367893SN/Aaddr_range=0:18446744073709551615
4377893SN/Aassoc=2
4387893SN/Ablock_size=64
4397893SN/Aforward_snoops=true
4407893SN/Ahash_delay=1
4418200SN/Ais_top_level=true
4427893SN/Alatency=1000
4437893SN/Amax_miss_count=0
4447893SN/Amshrs=10
4457893SN/Anum_cpus=1
4467893SN/Aprefetch_data_accesses_only=false
4477893SN/Aprefetch_degree=1
4487893SN/Aprefetch_latency=10000
4497893SN/Aprefetch_on_access=false
4507893SN/Aprefetch_past_page=false
4517893SN/Aprefetch_policy=none
4527893SN/Aprefetch_serial_squash=false
4537893SN/Aprefetch_use_cpu_id=true
4547893SN/Aprefetcher_size=100
4557893SN/AprioritizeRequests=false
4567893SN/Arepl=Null
4577893SN/Asize=131072
4587893SN/Asubblock_size=0
4597893SN/Atgts_per_mshr=20
4607893SN/Atrace_addr=0
4617893SN/Atwo_queue=false
4627893SN/Awrite_buffers=8
4637893SN/Acpu_side=system.cpu.icache_port
4647893SN/Amem_side=system.cpu.toL2Bus.port[0]
4657893SN/A
4668825Snilay@cs.wisc.edu[system.cpu.interrupts]
4678825Snilay@cs.wisc.edutype=X86LocalApic
4688825Snilay@cs.wisc.eduint_latency=1000
4698825Snilay@cs.wisc.edupio_addr=2305843009213693952
4708825Snilay@cs.wisc.edupio_latency=1000
4718825Snilay@cs.wisc.edusystem=system
4728825Snilay@cs.wisc.eduint_port=system.membus.port[4]
4738825Snilay@cs.wisc.edupio=system.membus.port[3]
4748825Snilay@cs.wisc.edu
4757893SN/A[system.cpu.itb]
4767893SN/Atype=X86TLB
4778825Snilay@cs.wisc.educhildren=walker
4787893SN/Asize=64
4798825Snilay@cs.wisc.eduwalker=system.cpu.itb.walker
4808825Snilay@cs.wisc.edu
4818825Snilay@cs.wisc.edu[system.cpu.itb.walker]
4828825Snilay@cs.wisc.edutype=X86PagetableWalker
4838825Snilay@cs.wisc.edusystem=system
4848825Snilay@cs.wisc.eduport=system.cpu.toL2Bus.port[2]
4857893SN/A
4867893SN/A[system.cpu.l2cache]
4877893SN/Atype=BaseCache
4887893SN/Aaddr_range=0:18446744073709551615
4897893SN/Aassoc=2
4907893SN/Ablock_size=64
4917893SN/Aforward_snoops=true
4927893SN/Ahash_delay=1
4938200SN/Ais_top_level=false
4947893SN/Alatency=1000
4957893SN/Amax_miss_count=0
4967893SN/Amshrs=10
4977893SN/Anum_cpus=1
4987893SN/Aprefetch_data_accesses_only=false
4997893SN/Aprefetch_degree=1
5007893SN/Aprefetch_latency=10000
5017893SN/Aprefetch_on_access=false
5027893SN/Aprefetch_past_page=false
5037893SN/Aprefetch_policy=none
5047893SN/Aprefetch_serial_squash=false
5057893SN/Aprefetch_use_cpu_id=true
5067893SN/Aprefetcher_size=100
5077893SN/AprioritizeRequests=false
5087893SN/Arepl=Null
5097893SN/Asize=2097152
5107893SN/Asubblock_size=0
5117893SN/Atgts_per_mshr=5
5127893SN/Atrace_addr=0
5137893SN/Atwo_queue=false
5147893SN/Awrite_buffers=8
5158825Snilay@cs.wisc.educpu_side=system.cpu.toL2Bus.port[4]
5168721SN/Amem_side=system.membus.port[2]
5177893SN/A
5187893SN/A[system.cpu.toL2Bus]
5197893SN/Atype=Bus
5207893SN/Ablock_size=64
5217893SN/Abus_id=0
5227893SN/Aclock=1000
5237893SN/Aheader_cycles=1
5247893SN/Ause_default_range=false
5257893SN/Awidth=64
5268825Snilay@cs.wisc.eduport=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
5277893SN/A
5287893SN/A[system.cpu.tracer]
5297893SN/Atype=ExeTracer
5307893SN/A
5317893SN/A[system.cpu.workload]
5327893SN/Atype=LiveProcess
5337893SN/Acmd=parser 2.1.dict -batch
5348825Snilay@cs.wisc.educwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
5357893SN/Aegid=100
5367893SN/Aenv=
5377893SN/Aerrout=cerr
5387893SN/Aeuid=100
5398728SN/Aexecutable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
5407893SN/Agid=100
5418728SN/Ainput=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
5427893SN/Amax_stack_size=67108864
5437893SN/Aoutput=cout
5447893SN/Apid=100
5457893SN/Appid=99
5467893SN/Asimpoint=114600000000
5477893SN/Asystem=system
5487893SN/Auid=100
5497893SN/A
5507893SN/A[system.membus]
5517893SN/Atype=Bus
5527893SN/Ablock_size=64
5537893SN/Abus_id=0
5547893SN/Aclock=1000
5557893SN/Aheader_cycles=1
5567893SN/Ause_default_range=false
5577893SN/Awidth=64
5588825Snilay@cs.wisc.eduport=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
5597893SN/A
5607893SN/A[system.physmem]
5617893SN/Atype=PhysicalMemory
5627893SN/Afile=
5637893SN/Alatency=30000
5647893SN/Alatency_var=0
5657893SN/Anull=false
5667893SN/Arange=0:134217727
5677893SN/Azero=false
5688721SN/Aport=system.membus.port[1]
5697893SN/A
570