stats.txt revision 9285:9901180cd573
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 0.717833 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 717832876000 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 717832876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 1074460 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 1210735 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 1527332222 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 237040 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 469.99 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 504986853 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 569034839 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory 1511507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 9663872 # Number of bytes read from this memory 1611860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 9842240 # Number of bytes read from this memory 1711606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu.inst 178368 # Number of instructions bytes read from this memory 1811860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 178368 # Number of instructions bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 6574720 # Number of bytes written to this memory 2011606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 6574720 # Number of bytes written to this memory 2111606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu.inst 2787 # Number of read requests responded to by this memory 2211860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 150998 # Number of read requests responded to by this memory 2311860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 153785 # Number of read requests responded to by this memory 2411606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory 2511860Sandreas.hansson@arm.comsystem.physmem.num_writes::total 102730 # Number of write requests responded to by this memory 2611860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 248481 # Total read bandwidth from this memory (bytes/s) 2711860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13462565 # Total read bandwidth from this memory (bytes/s) 2811860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 13711047 # Total read bandwidth from this memory (bytes/s) 2911860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 248481 # Instruction read bandwidth from this memory (bytes/s) 3011860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 248481 # Instruction read bandwidth from this memory (bytes/s) 3111860Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 9159124 # Write bandwidth from this memory (bytes/s) 3211860Sandreas.hansson@arm.comsystem.physmem.bw_write::total 9159124 # Write bandwidth from this memory (bytes/s) 3311860Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 9159124 # Total bandwidth to/from this memory (bytes/s) 3411860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 248481 # Total bandwidth to/from this memory (bytes/s) 3511860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13462565 # Total bandwidth to/from this memory (bytes/s) 3611860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 22870170 # Total bandwidth to/from this memory (bytes/s) 3711860Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 3811860Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 3911860Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 4011860Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 4111860Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 4211860Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 4311860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 4411860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4511860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4611860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4711860Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 4811860Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 4911860Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 5011507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 5111507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 5211860Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 5311860Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 5411860Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 5511860Sandreas.hansson@arm.comsystem.cpu.dtb.hits 0 # DTB hits 5611860Sandreas.hansson@arm.comsystem.cpu.dtb.misses 0 # DTB misses 5711860Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 5811860Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 5911680SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 6011860Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 6111860Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 6211860Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 6311680SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 6411860Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 6511860Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 6611860Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 6711860Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 6811860Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 6911860Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 7011860Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 7111860Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 7211860Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 7311860Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 7411860Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 7511860Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 7611860Sandreas.hansson@arm.comsystem.cpu.itb.hits 0 # DTB hits 7711860Sandreas.hansson@arm.comsystem.cpu.itb.misses 0 # DTB misses 7811860Sandreas.hansson@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 7911860Sandreas.hansson@arm.comsystem.cpu.workload.num_syscalls 548 # Number of system calls 8011860Sandreas.hansson@arm.comsystem.cpu.numCycles 1435665752 # number of cpu cycles simulated 8111860Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 8211860Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 8311606Sandreas.sandberg@arm.comsystem.cpu.committedInsts 504986853 # Number of instructions committed 8411507SCurtis.Dunham@arm.comsystem.cpu.committedOps 569034839 # Number of ops (including micro ops) committed 8511507SCurtis.Dunham@arm.comsystem.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses 8611860Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 8711507SCurtis.Dunham@arm.comsystem.cpu.num_func_calls 19311615 # number of times a function call or return occured 8811507SCurtis.Dunham@arm.comsystem.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls 8911507SCurtis.Dunham@arm.comsystem.cpu.num_int_insts 470727695 # number of integer instructions 9011507SCurtis.Dunham@arm.comsystem.cpu.num_fp_insts 16 # number of float instructions 9111507SCurtis.Dunham@arm.comsystem.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read 9211507SCurtis.Dunham@arm.comsystem.cpu.num_int_register_writes 646169352 # number of times the integer registers were written 9311860Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads 16 # number of times the floating registers were read 9411507SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 9511507SCurtis.Dunham@arm.comsystem.cpu.num_mem_refs 182890034 # number of memory refs 9611507SCurtis.Dunham@arm.comsystem.cpu.num_load_insts 126029555 # Number of load instructions 9711507SCurtis.Dunham@arm.comsystem.cpu.num_store_insts 56860479 # Number of store instructions 9811507SCurtis.Dunham@arm.comsystem.cpu.num_idle_cycles 0 # Number of idle cycles 9911507SCurtis.Dunham@arm.comsystem.cpu.num_busy_cycles 1435665752 # Number of busy cycles 10011860Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 10111860Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0 # Percentage of idle cycles 10211860Sandreas.hansson@arm.comsystem.cpu.icache.replacements 9788 # number of replacements 10311570SCurtis.Dunham@arm.comsystem.cpu.icache.tagsinuse 982.776891 # Cycle average of tags in use 10411507SCurtis.Dunham@arm.comsystem.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. 10511507SCurtis.Dunham@arm.comsystem.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. 10611507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. 10711507SCurtis.Dunham@arm.comsystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 10811507SCurtis.Dunham@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 982.776891 # Average occupied blocks per requestor 10911507SCurtis.Dunham@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.479872 # Average percentage of cache occupancy 11011507SCurtis.Dunham@arm.comsystem.cpu.icache.occ_percent::total 0.479872 # Average percentage of cache occupancy 11111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits 11211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits 11311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits 11411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits 11511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits 11611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 516599855 # number of overall hits 11711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 11811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 11911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 12011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 12111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 12211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 11521 # number of overall misses 12311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 266834000 # number of ReadReq miss cycles 12411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 266834000 # number of ReadReq miss cycles 12511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 266834000 # number of demand (read+write) miss cycles 12611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 266834000 # number of demand (read+write) miss cycles 12711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 266834000 # number of overall miss cycles 12811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 266834000 # number of overall miss cycles 12911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) 13011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) 13111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses 13211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses 13311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses 13411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses 13511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 13611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 13711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 13811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses 13911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 14011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses 14111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23160.663137 # average ReadReq miss latency 14211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 23160.663137 # average ReadReq miss latency 14311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency 14411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 23160.663137 # average overall miss latency 14511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 23160.663137 # average overall miss latency 14611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 23160.663137 # average overall miss latency 14711507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 14811860Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 14911860Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 15011860Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 15111860Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 15211860Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 15311860Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 15411860Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 15511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 15611754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 15711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 15811860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 15911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 16011860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses 16111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243792000 # number of ReadReq MSHR miss cycles 16211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 243792000 # number of ReadReq MSHR miss cycles 16311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 243792000 # number of demand (read+write) MSHR miss cycles 16411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 243792000 # number of demand (read+write) MSHR miss cycles 16511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 243792000 # number of overall MSHR miss cycles 16611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 243792000 # number of overall MSHR miss cycles 16711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 16811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 16911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 17011570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses 17111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 17211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses 17311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.663137 # average ReadReq mshr miss latency 17411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.663137 # average ReadReq mshr miss latency 17511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency 17611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency 17711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.663137 # average overall mshr miss latency 17811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 21160.663137 # average overall mshr miss latency 17911507SCurtis.Dunham@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 18011507SCurtis.Dunham@arm.comsystem.cpu.dcache.replacements 1134822 # number of replacements 18111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tagsinuse 4065.317414 # Cycle average of tags in use 18211507SCurtis.Dunham@arm.comsystem.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. 18311507SCurtis.Dunham@arm.comsystem.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. 18411507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. 18511507SCurtis.Dunham@arm.comsystem.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. 18611507SCurtis.Dunham@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 4065.317414 # Average occupied blocks per requestor 18711507SCurtis.Dunham@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy 18811507SCurtis.Dunham@arm.comsystem.cpu.dcache.occ_percent::total 0.992509 # Average percentage of cache occupancy 18911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits 19011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits 19111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits 19211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits 19311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 19411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 19511507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 19611507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 19711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits 19811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits 19911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits 20011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 176840704 # number of overall hits 20111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses 20211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses 20311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses 20411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses 20511754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses 20611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses 20711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses 20811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 1138918 # number of overall misses 20911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 12178377000 # number of ReadReq miss cycles 21011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 12178377000 # number of ReadReq miss cycles 21111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 8970025000 # number of WriteReq miss cycles 21211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 8970025000 # number of WriteReq miss cycles 21311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 21148402000 # number of demand (read+write) miss cycles 21411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 21148402000 # number of demand (read+write) miss cycles 21511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 21148402000 # number of overall miss cycles 21611680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 21148402000 # number of overall miss cycles 21711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) 21811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) 21911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 22011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 22111680SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 22211860Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 22311507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 22411680SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 22511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses 22611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses 22711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses 22811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses 22911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses 23011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses 23111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 23211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses 23311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses 23411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses 23511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses 23611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses 23711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.279202 # average ReadReq miss latency 23811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 15560.279202 # average ReadReq miss latency 23911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25178.310784 # average WriteReq miss latency 24011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 25178.310784 # average WriteReq miss latency 24111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency 24211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 18568.853947 # average overall miss latency 24311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 18568.853947 # average overall miss latency 24411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 18568.853947 # average overall miss latency 24511860Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 24611860Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 24711507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 24811680SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 24911680SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 25011680SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 25111507SCurtis.Dunham@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 25211860Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 25311860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 1061444 # number of writebacks 25411860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 1061444 # number of writebacks 25511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses 25611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses 25711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses 25811680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses 25911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses 26011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses 26111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses 26211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses 26311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10613061000 # number of ReadReq MSHR miss cycles 26411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 10613061000 # number of ReadReq MSHR miss cycles 26511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257505000 # number of WriteReq MSHR miss cycles 26611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 8257505000 # number of WriteReq MSHR miss cycles 26711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870566000 # number of demand (read+write) MSHR miss cycles 26811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 18870566000 # number of demand (read+write) MSHR miss cycles 26911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870566000 # number of overall MSHR miss cycles 27011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 18870566000 # number of overall MSHR miss cycles 27111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses 27211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses 27311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses 27411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses 27511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses 27611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses 27711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses 27811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses 27911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13560.279202 # average ReadReq mshr miss latency 28011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13560.279202 # average ReadReq mshr miss latency 28111680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.310784 # average WriteReq mshr miss latency 28211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.310784 # average WriteReq mshr miss latency 28311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency 28411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency 28511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.853947 # average overall mshr miss latency 28611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.853947 # average overall mshr miss latency 28711860Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 28811860Sandreas.hansson@arm.comsystem.cpu.l2cache.replacements 122482 # number of replacements 28911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 26931.505779 # Cycle average of tags in use 29011860Sandreas.hansson@arm.comsystem.cpu.l2cache.total_refs 1623186 # Total number of references to valid blocks. 29111860Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 153644 # Sample count of references to valid blocks. 29211860Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 10.564591 # Average number of references to valid blocks. 29311860Sandreas.hansson@arm.comsystem.cpu.l2cache.warmup_cycle 343812481000 # Cycle when the warmup percentage was hit. 29411860Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::writebacks 23220.335885 # Average occupied blocks per requestor 29511860Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 246.652044 # Average occupied blocks per requestor 29611860Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 3464.517849 # Average occupied blocks per requestor 29711860Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::writebacks 0.708628 # Average percentage of cache occupancy 29811860Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.007527 # Average percentage of cache occupancy 29911860Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.105729 # Average percentage of cache occupancy 30011860Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.821884 # Average percentage of cache occupancy 30111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits 30211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits 30311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits 30411860Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 1061444 # number of Writeback hits 30511860Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 1061444 # number of Writeback hits 30611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 252959 # number of ReadExReq hits 30711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 252959 # number of ReadExReq hits 30811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 8734 # number of demand (read+write) hits 30911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 987920 # number of demand (read+write) hits 31011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 996654 # number of demand (read+write) hits 31111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 8734 # number of overall hits 31211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 987920 # number of overall hits 31311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 996654 # number of overall hits 31411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 2787 # number of ReadReq misses 31511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 47697 # number of ReadReq misses 31611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_misses::total 50484 # number of ReadReq misses 31711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 103301 # number of ReadExReq misses 31811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 103301 # number of ReadExReq misses 31911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2787 # number of demand (read+write) misses 32011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 150998 # number of demand (read+write) misses 32111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 153785 # number of demand (read+write) misses 32211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2787 # number of overall misses 32311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 150998 # number of overall misses 32411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 153785 # number of overall misses 32511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144931000 # number of ReadReq miss cycles 32611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 2480793000 # number of ReadReq miss cycles 32711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 2625724000 # number of ReadReq miss cycles 32811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371655000 # number of ReadExReq miss cycles 32911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 5371655000 # number of ReadExReq miss cycles 33011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 144931000 # number of demand (read+write) miss cycles 33111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 7852448000 # number of demand (read+write) miss cycles 33211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 7997379000 # number of demand (read+write) miss cycles 33311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 144931000 # number of overall miss cycles 33411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 7852448000 # number of overall miss cycles 33511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 7997379000 # number of overall miss cycles 33611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) 33711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) 33811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) 33911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 1061444 # number of Writeback accesses(hits+misses) 34011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.Writeback_accesses::total 1061444 # number of Writeback accesses(hits+misses) 34111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) 34211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) 34311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses 34411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses 34511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses 34611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses 34711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses 34811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses 34911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.241906 # miss rate for ReadReq accesses 35011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses 35111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.063568 # miss rate for ReadReq accesses 35211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.289960 # miss rate for ReadExReq accesses 35311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.289960 # miss rate for ReadExReq accesses 35411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.241906 # miss rate for demand accesses 35511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.132580 # miss rate for demand accesses 35611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.133675 # miss rate for demand accesses 35711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.241906 # miss rate for overall accesses 35811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.132580 # miss rate for overall accesses 35911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.133675 # miss rate for overall accesses 36011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.511661 # average ReadReq miss latency 36111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52011.510158 # average ReadReq miss latency 36211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.013390 # average ReadReq miss latency 36311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.029041 # average ReadExReq miss latency 36411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.029041 # average ReadExReq miss latency 36511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency 36611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency 36711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 52003.634945 # average overall miss latency 36811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.511661 # average overall miss latency 36911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.655678 # average overall miss latency 37011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 52003.634945 # average overall miss latency 37111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 37211860Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 37311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 37411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 37511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 37611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 37711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 37811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 37911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 102730 # number of writebacks 38011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 102730 # number of writebacks 38111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2787 # number of ReadReq MSHR misses 38211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 47697 # number of ReadReq MSHR misses 38311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 50484 # number of ReadReq MSHR misses 38411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103301 # number of ReadExReq MSHR misses 38511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 103301 # number of ReadExReq MSHR misses 38611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2787 # number of demand (read+write) MSHR misses 38711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 150998 # number of demand (read+write) MSHR misses 38811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 153785 # number of demand (read+write) MSHR misses 38911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2787 # number of overall MSHR misses 39011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 150998 # number of overall MSHR misses 39111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 153785 # number of overall MSHR misses 39211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111487000 # number of ReadReq MSHR miss cycles 39311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1908429000 # number of ReadReq MSHR miss cycles 39411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 2019916000 # number of ReadReq MSHR miss cycles 39511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4132043000 # number of ReadExReq MSHR miss cycles 39611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4132043000 # number of ReadExReq MSHR miss cycles 39711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111487000 # number of demand (read+write) MSHR miss cycles 39811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6040472000 # number of demand (read+write) MSHR miss cycles 39911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 6151959000 # number of demand (read+write) MSHR miss cycles 40011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111487000 # number of overall MSHR miss cycles 40111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6040472000 # number of overall MSHR miss cycles 40211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 6151959000 # number of overall MSHR miss cycles 40311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for ReadReq accesses 40411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060942 # mshr miss rate for ReadReq accesses 40511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063568 # mshr miss rate for ReadReq accesses 40611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.289960 # mshr miss rate for ReadExReq accesses 40711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.289960 # mshr miss rate for ReadExReq accesses 40811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for demand accesses 40911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for demand accesses 41011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.133675 # mshr miss rate for demand accesses 41111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for overall accesses 41211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for overall accesses 41311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.133675 # mshr miss rate for overall accesses 41411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.511661 # average ReadReq mshr miss latency 41511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40011.510158 # average ReadReq mshr miss latency 41611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.013390 # average ReadReq mshr miss latency 41711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.029041 # average ReadExReq mshr miss latency 41811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.029041 # average ReadExReq mshr miss latency 41911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency 42011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency 42111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency 42211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40002.511661 # average overall mshr miss latency 42311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.655678 # average overall mshr miss latency 42411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40003.634945 # average overall mshr miss latency 42511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 42611507SCurtis.Dunham@arm.com 42711507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 42811507SCurtis.Dunham@arm.com