stats.txt revision 10488:7c27480a5031
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.707539 # Number of seconds simulated 4sim_ticks 707539023000 # Number of ticks simulated 5final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1199909 # Simulator instruction rate (inst/s) 8host_op_rate 1299448 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1681197618 # Simulator tick rate (ticks/s) 10host_mem_usage 309428 # Number of bytes of host memory used 11host_seconds 420.85 # Real time elapsed on the host 12sim_insts 504986853 # Number of instructions simulated 13sim_ops 546878104 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 139879 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) 39system.membus.trans_dist::ReadReq 41855 # Transaction distribution 40system.membus.trans_dist::ReadResp 41855 # Transaction distribution 41system.membus.trans_dist::Writeback 95953 # Transaction distribution 42system.membus.trans_dist::ReadExReq 100794 # Transaction distribution 43system.membus.trans_dist::ReadExResp 100794 # Transaction distribution 44system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) 45system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) 46system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) 47system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) 48system.membus.snoops 0 # Total snoops (count) 49system.membus.snoop_fanout::samples 238603 # Request fanout histogram 50system.membus.snoop_fanout::mean 0 # Request fanout histogram 51system.membus.snoop_fanout::stdev 0 # Request fanout histogram 52system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 53system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram 54system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 55system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 56system.membus.snoop_fanout::min_value 0 # Request fanout histogram 57system.membus.snoop_fanout::max_value 0 # Request fanout histogram 58system.membus.snoop_fanout::total 238603 # Request fanout histogram 59system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) 60system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 61system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) 62system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 63system.cpu_clk_domain.clock 500 # Clock period in ticks 64system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 65system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 66system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 67system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 68system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 69system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 70system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 71system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 72system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 73system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 74system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 75system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 76system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 77system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 78system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 79system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 80system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 81system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 82system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 83system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 84system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 85system.cpu.dtb.inst_hits 0 # ITB inst hits 86system.cpu.dtb.inst_misses 0 # ITB inst misses 87system.cpu.dtb.read_hits 0 # DTB read hits 88system.cpu.dtb.read_misses 0 # DTB read misses 89system.cpu.dtb.write_hits 0 # DTB write hits 90system.cpu.dtb.write_misses 0 # DTB write misses 91system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 92system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 93system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 94system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 95system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 96system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 97system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 98system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 99system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 100system.cpu.dtb.read_accesses 0 # DTB read accesses 101system.cpu.dtb.write_accesses 0 # DTB write accesses 102system.cpu.dtb.inst_accesses 0 # ITB inst accesses 103system.cpu.dtb.hits 0 # DTB hits 104system.cpu.dtb.misses 0 # DTB misses 105system.cpu.dtb.accesses 0 # DTB accesses 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu.itb.inst_hits 0 # ITB inst hits 128system.cpu.itb.inst_misses 0 # ITB inst misses 129system.cpu.itb.read_hits 0 # DTB read hits 130system.cpu.itb.read_misses 0 # DTB read misses 131system.cpu.itb.write_hits 0 # DTB write hits 132system.cpu.itb.write_misses 0 # DTB write misses 133system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 134system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 135system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 136system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 137system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 138system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 139system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 140system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 141system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 142system.cpu.itb.read_accesses 0 # DTB read accesses 143system.cpu.itb.write_accesses 0 # DTB write accesses 144system.cpu.itb.inst_accesses 0 # ITB inst accesses 145system.cpu.itb.hits 0 # DTB hits 146system.cpu.itb.misses 0 # DTB misses 147system.cpu.itb.accesses 0 # DTB accesses 148system.cpu.workload.num_syscalls 548 # Number of system calls 149system.cpu.numCycles 1415078046 # number of cpu cycles simulated 150system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 151system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 152system.cpu.committedInsts 504986853 # Number of instructions committed 153system.cpu.committedOps 546878104 # Number of ops (including micro ops) committed 154system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses 155system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 156system.cpu.num_func_calls 19311615 # number of times a function call or return occured 157system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls 158system.cpu.num_int_insts 448454356 # number of integer instructions 159system.cpu.num_fp_insts 16 # number of float instructions 160system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read 161system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written 162system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 163system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 164system.cpu.num_cc_register_reads 1984297856 # number of times the CC registers were read 165system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written 166system.cpu.num_mem_refs 172745235 # number of memory refs 167system.cpu.num_load_insts 115884756 # Number of load instructions 168system.cpu.num_store_insts 56860479 # Number of store instructions 169system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 170system.cpu.num_busy_cycles 1415078045.998000 # Number of busy cycles 171system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 172system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 173system.cpu.Branches 121548301 # Number of branches fetched 174system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 175system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction 176system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction 177system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction 178system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction 179system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction 180system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction 181system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction 182system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction 183system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction 184system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction 185system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction 186system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction 187system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction 188system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction 189system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction 190system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction 191system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction 192system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction 193system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction 194system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction 195system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction 196system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction 197system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction 198system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction 199system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction 200system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction 201system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction 202system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction 203system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction 204system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction 205system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction 206system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 207system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::total 548695378 # Class of executed instruction 209system.cpu.icache.tags.replacements 9788 # number of replacements 210system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use 211system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. 212system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. 213system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. 214system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 215system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor 216system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy 217system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy 218system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id 219system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 220system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id 223system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id 224system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id 225system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses 226system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses 227system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits 228system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits 229system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits 230system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits 231system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits 232system.cpu.icache.overall_hits::total 516599855 # number of overall hits 233system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses 234system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses 235system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses 236system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses 237system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses 238system.cpu.icache.overall_misses::total 11521 # number of overall misses 239system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles 240system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles 241system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles 242system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles 243system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles 244system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles 245system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) 246system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) 247system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses 248system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses 249system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses 250system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses 251system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses 252system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses 253system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses 254system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses 255system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses 256system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses 257system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency 258system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency 259system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency 260system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency 261system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency 262system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency 263system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 264system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 265system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 266system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 267system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 268system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 269system.cpu.icache.fast_writes 0 # number of fast writes performed 270system.cpu.icache.cache_copies 0 # number of cache copies performed 271system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses 272system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses 273system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses 274system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses 275system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses 276system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses 277system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles 278system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles 279system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles 280system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles 281system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles 282system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles 283system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses 284system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses 285system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses 286system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses 287system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses 288system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses 289system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency 290system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency 292system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency 293system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency 294system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency 295system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 296system.cpu.l2cache.tags.replacements 109895 # number of replacements 297system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use 298system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. 299system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. 300system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. 301system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit. 302system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor 303system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor 304system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor 305system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy 306system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008786 # Average percentage of cache occupancy 307system.cpu.l2cache.tags.occ_percent::cpu.data 0.109085 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy 309system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 312system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3656 # Occupied blocks per task id 313system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27181 # Occupied blocks per task id 314system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id 315system.cpu.l2cache.tags.tag_accesses 18220084 # Number of tag accesses 316system.cpu.l2cache.tags.data_accesses 18220084 # Number of data accesses 317system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits 318system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits 319system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits 320system.cpu.l2cache.Writeback_hits::writebacks 1064905 # number of Writeback hits 321system.cpu.l2cache.Writeback_hits::total 1064905 # number of Writeback hits 322system.cpu.l2cache.ReadExReq_hits::cpu.data 255466 # number of ReadExReq hits 323system.cpu.l2cache.ReadExReq_hits::total 255466 # number of ReadExReq hits 324system.cpu.l2cache.demand_hits::cpu.inst 8751 # number of demand (read+write) hits 325system.cpu.l2cache.demand_hits::cpu.data 999039 # number of demand (read+write) hits 326system.cpu.l2cache.demand_hits::total 1007790 # number of demand (read+write) hits 327system.cpu.l2cache.overall_hits::cpu.inst 8751 # number of overall hits 328system.cpu.l2cache.overall_hits::cpu.data 999039 # number of overall hits 329system.cpu.l2cache.overall_hits::total 1007790 # number of overall hits 330system.cpu.l2cache.ReadReq_misses::cpu.inst 2770 # number of ReadReq misses 331system.cpu.l2cache.ReadReq_misses::cpu.data 39085 # number of ReadReq misses 332system.cpu.l2cache.ReadReq_misses::total 41855 # number of ReadReq misses 333system.cpu.l2cache.ReadExReq_misses::cpu.data 100794 # number of ReadExReq misses 334system.cpu.l2cache.ReadExReq_misses::total 100794 # number of ReadExReq misses 335system.cpu.l2cache.demand_misses::cpu.inst 2770 # number of demand (read+write) misses 336system.cpu.l2cache.demand_misses::cpu.data 139879 # number of demand (read+write) misses 337system.cpu.l2cache.demand_misses::total 142649 # number of demand (read+write) misses 338system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses 339system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses 340system.cpu.l2cache.overall_misses::total 142649 # number of overall misses 341system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles 342system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles 343system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles 344system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles 345system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles 346system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles 347system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles 348system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles 349system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles 350system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles 351system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles 352system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) 353system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) 354system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) 355system.cpu.l2cache.Writeback_accesses::writebacks 1064905 # number of Writeback accesses(hits+misses) 356system.cpu.l2cache.Writeback_accesses::total 1064905 # number of Writeback accesses(hits+misses) 357system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) 358system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) 359system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses 360system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses 361system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses 362system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses 363system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses 364system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses 365system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.240431 # miss rate for ReadReq accesses 366system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.049939 # miss rate for ReadReq accesses 367system.cpu.l2cache.ReadReq_miss_rate::total 0.052702 # miss rate for ReadReq accesses 368system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282923 # miss rate for ReadExReq accesses 369system.cpu.l2cache.ReadExReq_miss_rate::total 0.282923 # miss rate for ReadExReq accesses 370system.cpu.l2cache.demand_miss_rate::cpu.inst 0.240431 # miss rate for demand accesses 371system.cpu.l2cache.demand_miss_rate::cpu.data 0.122817 # miss rate for demand accesses 372system.cpu.l2cache.demand_miss_rate::total 0.123995 # miss rate for demand accesses 373system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses 374system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses 375system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses 376system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency 377system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency 378system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency 379system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency 380system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency 381system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency 382system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency 383system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency 384system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency 385system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency 386system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency 387system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 388system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 389system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 390system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 391system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 392system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 393system.cpu.l2cache.fast_writes 0 # number of fast writes performed 394system.cpu.l2cache.cache_copies 0 # number of cache copies performed 395system.cpu.l2cache.writebacks::writebacks 95953 # number of writebacks 396system.cpu.l2cache.writebacks::total 95953 # number of writebacks 397system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2770 # number of ReadReq MSHR misses 398system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39085 # number of ReadReq MSHR misses 399system.cpu.l2cache.ReadReq_mshr_misses::total 41855 # number of ReadReq MSHR misses 400system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100794 # number of ReadExReq MSHR misses 401system.cpu.l2cache.ReadExReq_mshr_misses::total 100794 # number of ReadExReq MSHR misses 402system.cpu.l2cache.demand_mshr_misses::cpu.inst 2770 # number of demand (read+write) MSHR misses 403system.cpu.l2cache.demand_mshr_misses::cpu.data 139879 # number of demand (read+write) MSHR misses 404system.cpu.l2cache.demand_mshr_misses::total 142649 # number of demand (read+write) MSHR misses 405system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses 406system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses 407system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses 408system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles 409system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles 410system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles 411system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles 412system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles 413system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles 414system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles 415system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles 416system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles 418system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles 419system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses 420system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses 421system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses 422system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses 423system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses 424system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for demand accesses 425system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for demand accesses 426system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses 427system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses 428system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses 429system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses 430system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency 431system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency 432system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency 433system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency 434system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency 435system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency 436system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency 437system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency 438system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency 439system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency 440system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency 441system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.cpu.dcache.tags.replacements 1134822 # number of replacements 443system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use 444system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. 445system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. 446system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. 447system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. 448system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor 449system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy 450system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy 451system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 452system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 453system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 454system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id 455system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id 456system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id 457system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 458system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses 459system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses 460system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits 461system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits 462system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits 463system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits 464system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits 465system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits 466system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 467system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 468system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 469system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 470system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits 471system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits 472system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits 473system.cpu.dcache.overall_hits::total 167203374 # number of overall hits 474system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses 475system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses 476system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses 477system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses 478system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 479system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 480system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses 481system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses 482system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses 483system.cpu.dcache.overall_misses::total 1138918 # number of overall misses 484system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles 485system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles 486system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles 487system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles 488system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles 489system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles 490system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles 491system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles 492system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) 493system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) 494system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 495system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 496system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) 497system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) 498system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 499system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 500system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 501system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 502system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses 503system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses 504system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses 505system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses 506system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses 507system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses 508system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses 509system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses 510system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses 511system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses 512system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses 513system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses 514system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses 515system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses 516system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency 517system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency 518system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency 519system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency 520system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency 521system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency 522system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency 523system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency 524system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 525system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 526system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 527system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 528system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 529system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 530system.cpu.dcache.fast_writes 0 # number of fast writes performed 531system.cpu.dcache.cache_copies 0 # number of cache copies performed 532system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks 533system.cpu.dcache.writebacks::total 1064905 # number of writebacks 534system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses 535system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses 536system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses 537system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses 538system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 539system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 540system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses 541system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses 542system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses 543system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses 544system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles 545system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles 546system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles 547system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles 548system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles 549system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles 550system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles 551system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles 552system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles 553system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles 554system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses 555system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses 556system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses 557system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses 558system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses 559system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses 560system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses 561system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses 562system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses 563system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses 564system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency 565system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency 566system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency 567system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency 568system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency 569system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency 570system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency 571system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency 572system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency 573system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency 574system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 575system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution 578system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution 580system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes) 581system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes) 582system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes) 583system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) 584system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) 585system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) 586system.cpu.toL2Bus.snoops 0 # Total snoops (count) 587system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram 588system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 589system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 590system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 591system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 592system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 593system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 594system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 595system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 596system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram 597system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 599system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 600system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram 602system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) 603system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 604system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) 605system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 606system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) 607system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 608 609---------- End Simulation Statistics ---------- 610