stats.txt revision 9378:36ed6d4654bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.206025 # Number of seconds simulated 4sim_ticks 206024606500 # Number of ticks simulated 5final_tick 206024606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 152686 # Simulator instruction rate (inst/s) 8host_op_rate 172002 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 61807337 # Simulator tick rate (ticks/s) 10host_mem_usage 303988 # Number of bytes of host memory used 11host_seconds 3333.34 # Real time elapsed on the host 12sim_insts 508955238 # Number of instructions simulated 13sim_ops 573341798 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9266560 # Number of bytes read from this memory 16system.physmem.bytes_read::total 9483840 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6249216 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6249216 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 144790 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 148185 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 97644 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 97644 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1054631 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 44977928 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 46032560 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1054631 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1054631 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 30332377 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 30332377 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 30332377 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1054631 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 44977928 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 76364937 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 148186 # Total number of read requests seen 38system.physmem.writeReqs 97644 # Total number of write requests seen 39system.physmem.cpureqs 245841 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 9483840 # Total number of bytes read from memory 41system.physmem.bytesWritten 6249216 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 9483840 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 6249216 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 83 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 9219 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 9199 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 9344 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 8811 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 9228 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 8973 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 9239 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 9440 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 9127 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 10272 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 9693 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 9714 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 9129 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 8954 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 8756 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 5972 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 6125 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 5945 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 6129 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 5951 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 6023 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 6373 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 5964 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 6647 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 6322 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 6045 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 6065 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 5899 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 5778 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 80system.physmem.totGap 206024585500 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 148186 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes 96system.physmem.writePktSize::6 97644 # categorize write packet sizes 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 11 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 108system.physmem.rdQLenPdf::0 138148 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 9303 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 576 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 4240 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 4246 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 4246 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 4246 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 4246 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 4246 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 4246 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 4246 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 4246 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 174system.physmem.totQLat 1634901672 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 4710633672 # Sum of mem lat for all requests 176system.physmem.totBusLat 592412000 # Total cycles spent in databus access 177system.physmem.totBankLat 2483320000 # Total cycles spent in bank access 178system.physmem.avgQLat 11038.95 # Average queueing delay per request 179system.physmem.avgBankLat 16767.52 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request 181system.physmem.avgMemAccLat 31806.47 # Average memory access latency 182system.physmem.avgRdBW 46.03 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 30.33 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 46.03 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 30.33 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.48 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.02 # Average read queue length over time 189system.physmem.avgWrQLen 8.63 # Average write queue length over time 190system.physmem.readRowHits 128528 # Number of row buffer hits during reads 191system.physmem.writeRowHits 35061 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 86.78 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 35.91 # Row buffer hit rate for writes 194system.physmem.avgGap 838077.47 # Average gap between requests 195system.cpu.dtb.inst_hits 0 # ITB inst hits 196system.cpu.dtb.inst_misses 0 # ITB inst misses 197system.cpu.dtb.read_hits 0 # DTB read hits 198system.cpu.dtb.read_misses 0 # DTB read misses 199system.cpu.dtb.write_hits 0 # DTB write hits 200system.cpu.dtb.write_misses 0 # DTB write misses 201system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 202system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 203system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 204system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 205system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 206system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 207system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 208system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 209system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 210system.cpu.dtb.read_accesses 0 # DTB read accesses 211system.cpu.dtb.write_accesses 0 # DTB write accesses 212system.cpu.dtb.inst_accesses 0 # ITB inst accesses 213system.cpu.dtb.hits 0 # DTB hits 214system.cpu.dtb.misses 0 # DTB misses 215system.cpu.dtb.accesses 0 # DTB accesses 216system.cpu.itb.inst_hits 0 # ITB inst hits 217system.cpu.itb.inst_misses 0 # ITB inst misses 218system.cpu.itb.read_hits 0 # DTB read hits 219system.cpu.itb.read_misses 0 # DTB read misses 220system.cpu.itb.write_hits 0 # DTB write hits 221system.cpu.itb.write_misses 0 # DTB write misses 222system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 223system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 224system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 225system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 226system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 227system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 228system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 229system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 230system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu.itb.read_accesses 0 # DTB read accesses 232system.cpu.itb.write_accesses 0 # DTB write accesses 233system.cpu.itb.inst_accesses 0 # ITB inst accesses 234system.cpu.itb.hits 0 # DTB hits 235system.cpu.itb.misses 0 # DTB misses 236system.cpu.itb.accesses 0 # DTB accesses 237system.cpu.workload.num_syscalls 548 # Number of system calls 238system.cpu.numCycles 412049214 # number of cpu cycles simulated 239system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 240system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 241system.cpu.BPredUnit.lookups 182068030 # Number of BP lookups 242system.cpu.BPredUnit.condPredicted 142371650 # Number of conditional branches predicted 243system.cpu.BPredUnit.condIncorrect 7270692 # Number of conditional branches incorrect 244system.cpu.BPredUnit.BTBLookups 93491623 # Number of BTB lookups 245system.cpu.BPredUnit.BTBHits 88706856 # Number of BTB hits 246system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 247system.cpu.BPredUnit.usedRAS 12684721 # Number of times the RAS was used to get a target. 248system.cpu.BPredUnit.RASInCorrect 116337 # Number of incorrect RAS predictions. 249system.cpu.fetch.icacheStallCycles 117167260 # Number of cycles fetch is stalled on an Icache miss 250system.cpu.fetch.Insts 763059580 # Number of instructions fetch has processed 251system.cpu.fetch.Branches 182068030 # Number of branches that fetch encountered 252system.cpu.fetch.predictedBranches 101391577 # Number of branches that fetch has predicted taken 253system.cpu.fetch.Cycles 170902348 # Number of cycles fetch has run and was not squashing or blocked 254system.cpu.fetch.SquashCycles 35691223 # Number of cycles fetch has spent squashing 255system.cpu.fetch.BlockedCycles 89206735 # Number of cycles fetch has spent blocked 256system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 257system.cpu.fetch.PendingTrapStallCycles 447 # Number of stall cycles due to pending traps 258system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR 259system.cpu.fetch.CacheLines 113060023 # Number of cache lines fetched 260system.cpu.fetch.IcacheSquashes 2443326 # Number of outstanding Icache misses that were squashed 261system.cpu.fetch.rateDist::samples 404896941 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::mean 2.113484 # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::stdev 2.961332 # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::0 234007224 57.79% 57.79% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::1 14183787 3.50% 61.30% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::2 22898202 5.66% 66.95% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::3 22746913 5.62% 72.57% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::4 20897614 5.16% 77.73% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::5 13086335 3.23% 80.96% # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::6 13059349 3.23% 84.19% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::7 11995905 2.96% 87.15% # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::8 52021612 12.85% 100.00% # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::total 404896941 # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.branchRate 0.441860 # Number of branch fetches per cycle 279system.cpu.fetch.rate 1.851865 # Number of inst fetches per cycle 280system.cpu.decode.IdleCycles 127568061 # Number of cycles decode is idle 281system.cpu.decode.BlockedCycles 83247236 # Number of cycles decode is blocked 282system.cpu.decode.RunCycles 161078099 # Number of cycles decode is running 283system.cpu.decode.UnblockCycles 5457696 # Number of cycles decode is unblocking 284system.cpu.decode.SquashCycles 27545849 # Number of cycles decode is squashing 285system.cpu.decode.BranchResolved 26128375 # Number of times decode resolved a branch 286system.cpu.decode.BranchMispred 76880 # Number of times decode detected a branch misprediction 287system.cpu.decode.DecodedInsts 833033782 # Number of instructions handled by decode 288system.cpu.decode.SquashedInsts 297363 # Number of squashed instructions handled by decode 289system.cpu.rename.SquashCycles 27545849 # Number of cycles rename is squashing 290system.cpu.rename.IdleCycles 135637511 # Number of cycles rename is idle 291system.cpu.rename.BlockCycles 9603466 # Number of cycles rename is blocking 292system.cpu.rename.serializeStallCycles 58001862 # count of cycles rename stalled for serializing inst 293system.cpu.rename.RunCycles 158291644 # Number of cycles rename is running 294system.cpu.rename.UnblockCycles 15816609 # Number of cycles rename is unblocking 295system.cpu.rename.RenamedInsts 804360707 # Number of instructions processed by rename 296system.cpu.rename.ROBFullEvents 1150 # Number of times rename has blocked due to ROB full 297system.cpu.rename.IQFullEvents 3056892 # Number of times rename has blocked due to IQ full 298system.cpu.rename.LSQFullEvents 8825253 # Number of times rename has blocked due to LSQ full 299system.cpu.rename.FullRegisterEvents 274 # Number of times there has been no free registers 300system.cpu.rename.RenamedOperands 960209661 # Number of destination operands rename has renamed 301system.cpu.rename.RenameLookups 3520079656 # Number of register rename lookups that rename has made 302system.cpu.rename.int_rename_lookups 3520077996 # Number of integer rename lookups 303system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups 304system.cpu.rename.CommittedMaps 672200315 # Number of HB maps that are committed 305system.cpu.rename.UndoneMaps 288009346 # Number of HB maps that are undone due to squashing 306system.cpu.rename.serializingInsts 3037560 # count of serializing insts renamed 307system.cpu.rename.tempSerializingInsts 3037556 # count of temporary serializing insts renamed 308system.cpu.rename.skidInsts 48985402 # count of insts added to the skid buffer 309system.cpu.memDep0.insertedLoads 170961044 # Number of loads inserted to the mem dependence unit. 310system.cpu.memDep0.insertedStores 74192431 # Number of stores inserted to the mem dependence unit. 311system.cpu.memDep0.conflictingLoads 27929541 # Number of conflicting loads. 312system.cpu.memDep0.conflictingStores 15655992 # Number of conflicting stores. 313system.cpu.iq.iqInstsAdded 757955551 # Number of instructions added to the IQ (excludes non-spec) 314system.cpu.iq.iqNonSpecInstsAdded 4467760 # Number of non-speculative instructions added to the IQ 315system.cpu.iq.iqInstsIssued 669035735 # Number of instructions issued 316system.cpu.iq.iqSquashedInstsIssued 1391656 # Number of squashed instructions issued 317system.cpu.iq.iqSquashedInstsExamined 187243555 # Number of squashed instructions iterated over during squash; mainly for profiling 318system.cpu.iq.iqSquashedOperandsExamined 479554620 # Number of squashed operands that are examined and possibly removed from graph 319system.cpu.iq.iqSquashedNonSpecRemoved 746625 # Number of squashed non-spec instructions that were removed 320system.cpu.iq.issued_per_cycle::samples 404896941 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::mean 1.652361 # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::stdev 1.728633 # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::0 145342748 35.90% 35.90% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::1 75751868 18.71% 54.61% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::2 69103679 17.07% 71.67% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::3 53697004 13.26% 84.93% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::4 30880919 7.63% 92.56% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::5 16180758 4.00% 96.56% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::6 9302044 2.30% 98.85% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::7 3357601 0.83% 99.68% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::8 1280320 0.32% 100.00% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::total 404896941 # Number of insts issued each cycle 337system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 338system.cpu.iq.fu_full::IntAlu 478504 4.99% 4.99% # attempts to use FU when none available 339system.cpu.iq.fu_full::IntMult 0 0.00% 4.99% # attempts to use FU when none available 340system.cpu.iq.fu_full::IntDiv 0 0.00% 4.99% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.99% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.99% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.99% # attempts to use FU when none available 344system.cpu.iq.fu_full::FloatMult 0 0.00% 4.99% # attempts to use FU when none available 345system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.99% # attempts to use FU when none available 346system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.99% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.99% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.99% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.99% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.99% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.99% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.99% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdMult 0 0.00% 4.99% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.99% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdShift 0 0.00% 4.99% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.99% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.99% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.99% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.99% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.99% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.99% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.99% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.99% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.99% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.99% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.99% # attempts to use FU when none available 367system.cpu.iq.fu_full::MemRead 6546722 68.33% 73.32% # attempts to use FU when none available 368system.cpu.iq.fu_full::MemWrite 2556023 26.68% 100.00% # attempts to use FU when none available 369system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 370system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 371system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 372system.cpu.iq.FU_type_0::IntAlu 449967918 67.26% 67.26% # Type of FU issued 373system.cpu.iq.FU_type_0::IntMult 383484 0.06% 67.31% # Type of FU issued 374system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.31% # Type of FU issued 375system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.31% # Type of FU issued 376system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.31% # Type of FU issued 377system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.31% # Type of FU issued 378system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.31% # Type of FU issued 379system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.31% # Type of FU issued 380system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.31% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.31% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.31% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.31% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.31% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.31% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.31% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.31% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.31% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.31% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.31% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.31% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.31% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.31% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.31% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.31% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.31% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.31% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.31% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.31% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.31% # Type of FU issued 401system.cpu.iq.FU_type_0::MemRead 154140670 23.04% 90.35% # Type of FU issued 402system.cpu.iq.FU_type_0::MemWrite 64543544 9.65% 100.00% # Type of FU issued 403system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 404system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 405system.cpu.iq.FU_type_0::total 669035735 # Type of FU issued 406system.cpu.iq.rate 1.623679 # Inst issue rate 407system.cpu.iq.fu_busy_cnt 9581249 # FU busy when requested 408system.cpu.iq.fu_busy_rate 0.014321 # FU busy rate (busy events/executed inst) 409system.cpu.iq.int_inst_queue_reads 1753941049 # Number of integer instruction queue reads 410system.cpu.iq.int_inst_queue_writes 950473417 # Number of integer instruction queue writes 411system.cpu.iq.int_inst_queue_wakeup_accesses 649676758 # Number of integer instruction queue wakeup accesses 412system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads 413system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes 414system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 415system.cpu.iq.int_alu_accesses 678616849 # Number of integer alu accesses 416system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses 417system.cpu.iew.lsq.thread0.forwLoads 8574736 # Number of loads that had data forwarded from stores 418system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 419system.cpu.iew.lsq.thread0.squashedLoads 44187986 # Number of loads squashed 420system.cpu.iew.lsq.thread0.ignoredResponses 40720 # Number of memory responses ignored because the instruction is squashed 421system.cpu.iew.lsq.thread0.memOrderViolation 810577 # Number of memory ordering violations 422system.cpu.iew.lsq.thread0.squashedStores 16588451 # Number of stores squashed 423system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 424system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 425system.cpu.iew.lsq.thread0.rescheduledLoads 19568 # Number of loads that were rescheduled 426system.cpu.iew.lsq.thread0.cacheBlocked 4004 # Number of times an access to memory failed due to the cache being blocked 427system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 428system.cpu.iew.iewSquashCycles 27545849 # Number of cycles IEW is squashing 429system.cpu.iew.iewBlockCycles 4988149 # Number of cycles IEW is blocking 430system.cpu.iew.iewUnblockCycles 372803 # Number of cycles IEW is unblocking 431system.cpu.iew.iewDispatchedInsts 763982304 # Number of instructions dispatched to IQ 432system.cpu.iew.iewDispSquashedInsts 1114436 # Number of squashed instructions skipped by dispatch 433system.cpu.iew.iewDispLoadInsts 170961044 # Number of dispatched load instructions 434system.cpu.iew.iewDispStoreInsts 74192431 # Number of dispatched store instructions 435system.cpu.iew.iewDispNonSpecInsts 2979014 # Number of dispatched non-speculative instructions 436system.cpu.iew.iewIQFullEvents 218503 # Number of times the IQ has become full, causing a stall 437system.cpu.iew.iewLSQFullEvents 11510 # Number of times the LSQ has become full, causing a stall 438system.cpu.iew.memOrderViolationEvents 810577 # Number of memory order violations 439system.cpu.iew.predictedTakenIncorrect 4341639 # Number of branches that were predicted taken incorrectly 440system.cpu.iew.predictedNotTakenIncorrect 4005453 # Number of branches that were predicted not taken incorrectly 441system.cpu.iew.branchMispredicts 8347092 # Number of branch mispredicts detected at execute 442system.cpu.iew.iewExecutedInsts 659537182 # Number of executed instructions 443system.cpu.iew.iewExecLoadInsts 150855099 # Number of load instructions executed 444system.cpu.iew.iewExecSquashedInsts 9498553 # Number of squashed instructions skipped in execute 445system.cpu.iew.exec_swp 0 # number of swp insts executed 446system.cpu.iew.exec_nop 1558993 # number of nop insts executed 447system.cpu.iew.exec_refs 214102413 # number of memory reference insts executed 448system.cpu.iew.exec_branches 139198797 # Number of branches executed 449system.cpu.iew.exec_stores 63247314 # Number of stores executed 450system.cpu.iew.exec_rate 1.600627 # Inst execution rate 451system.cpu.iew.wb_sent 654653382 # cumulative count of insts sent to commit 452system.cpu.iew.wb_count 649676774 # cumulative count of insts written-back 453system.cpu.iew.wb_producers 375457821 # num instructions producing a value 454system.cpu.iew.wb_consumers 646369335 # num instructions consuming a value 455system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 456system.cpu.iew.wb_rate 1.576697 # insts written-back per cycle 457system.cpu.iew.wb_fanout 0.580872 # average fanout of values written-back 458system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 459system.cpu.commit.commitSquashedInsts 189322511 # The number of squashed insts skipped by commit 460system.cpu.commit.commitNonSpecStalls 3721135 # The number of times commit has been forced to stall to communicate backwards 461system.cpu.commit.branchMispredicts 7196542 # The number of times a branch was mispredicted 462system.cpu.commit.committed_per_cycle::samples 377351093 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::mean 1.522947 # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::stdev 2.207142 # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::0 165639440 43.90% 43.90% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::1 102355544 27.12% 71.02% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::2 34004026 9.01% 80.03% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::3 18854456 5.00% 85.03% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::4 16118319 4.27% 89.30% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::5 7599031 2.01% 91.31% # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::6 6941679 1.84% 93.15% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::7 3068571 0.81% 93.97% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::8 22770027 6.03% 100.00% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::total 377351093 # Number of insts commited each cycle 479system.cpu.commit.committedInsts 510299122 # Number of instructions committed 480system.cpu.commit.committedOps 574685682 # Number of ops (including micro ops) committed 481system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 482system.cpu.commit.refs 184377038 # Number of memory references committed 483system.cpu.commit.loads 126773058 # Number of loads committed 484system.cpu.commit.membars 1488542 # Number of memory barriers committed 485system.cpu.commit.branches 122291804 # Number of branches committed 486system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 487system.cpu.commit.int_insts 473701705 # Number of committed integer instructions. 488system.cpu.commit.function_calls 9757362 # Number of function calls committed. 489system.cpu.commit.bw_lim_events 22770027 # number cycles where commit BW limit reached 490system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 491system.cpu.rob.rob_reads 1118582121 # The number of ROB reads 492system.cpu.rob.rob_writes 1555682986 # The number of ROB writes 493system.cpu.timesIdled 306922 # Number of times that the entire CPU went into an idle state and unscheduled itself 494system.cpu.idleCycles 7152273 # Total number of cycles that the CPU has spent unscheduled due to idling 495system.cpu.committedInsts 508955238 # Number of Instructions Simulated 496system.cpu.committedOps 573341798 # Number of Ops (including micro ops) Simulated 497system.cpu.committedInsts_total 508955238 # Number of Instructions Simulated 498system.cpu.cpi 0.809598 # CPI: Cycles Per Instruction 499system.cpu.cpi_total 0.809598 # CPI: Total CPI of All Threads 500system.cpu.ipc 1.235181 # IPC: Instructions Per Cycle 501system.cpu.ipc_total 1.235181 # IPC: Total IPC of All Threads 502system.cpu.int_regfile_reads 3078487600 # number of integer regfile reads 503system.cpu.int_regfile_writes 757812476 # number of integer regfile writes 504system.cpu.fp_regfile_reads 16 # number of floating regfile reads 505system.cpu.misc_regfile_reads 213834943 # number of misc regfile reads 506system.cpu.misc_regfile_writes 4464090 # number of misc regfile writes 507system.cpu.icache.replacements 14939 # number of replacements 508system.cpu.icache.tagsinuse 1085.691077 # Cycle average of tags in use 509system.cpu.icache.total_refs 113039002 # Total number of references to valid blocks. 510system.cpu.icache.sampled_refs 16794 # Sample count of references to valid blocks. 511system.cpu.icache.avg_refs 6730.915922 # Average number of references to valid blocks. 512system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 513system.cpu.icache.occ_blocks::cpu.inst 1085.691077 # Average occupied blocks per requestor 514system.cpu.icache.occ_percent::cpu.inst 0.530123 # Average percentage of cache occupancy 515system.cpu.icache.occ_percent::total 0.530123 # Average percentage of cache occupancy 516system.cpu.icache.ReadReq_hits::cpu.inst 113039002 # number of ReadReq hits 517system.cpu.icache.ReadReq_hits::total 113039002 # number of ReadReq hits 518system.cpu.icache.demand_hits::cpu.inst 113039002 # number of demand (read+write) hits 519system.cpu.icache.demand_hits::total 113039002 # number of demand (read+write) hits 520system.cpu.icache.overall_hits::cpu.inst 113039002 # number of overall hits 521system.cpu.icache.overall_hits::total 113039002 # number of overall hits 522system.cpu.icache.ReadReq_misses::cpu.inst 21020 # number of ReadReq misses 523system.cpu.icache.ReadReq_misses::total 21020 # number of ReadReq misses 524system.cpu.icache.demand_misses::cpu.inst 21020 # number of demand (read+write) misses 525system.cpu.icache.demand_misses::total 21020 # number of demand (read+write) misses 526system.cpu.icache.overall_misses::cpu.inst 21020 # number of overall misses 527system.cpu.icache.overall_misses::total 21020 # number of overall misses 528system.cpu.icache.ReadReq_miss_latency::cpu.inst 467898499 # number of ReadReq miss cycles 529system.cpu.icache.ReadReq_miss_latency::total 467898499 # number of ReadReq miss cycles 530system.cpu.icache.demand_miss_latency::cpu.inst 467898499 # number of demand (read+write) miss cycles 531system.cpu.icache.demand_miss_latency::total 467898499 # number of demand (read+write) miss cycles 532system.cpu.icache.overall_miss_latency::cpu.inst 467898499 # number of overall miss cycles 533system.cpu.icache.overall_miss_latency::total 467898499 # number of overall miss cycles 534system.cpu.icache.ReadReq_accesses::cpu.inst 113060022 # number of ReadReq accesses(hits+misses) 535system.cpu.icache.ReadReq_accesses::total 113060022 # number of ReadReq accesses(hits+misses) 536system.cpu.icache.demand_accesses::cpu.inst 113060022 # number of demand (read+write) accesses 537system.cpu.icache.demand_accesses::total 113060022 # number of demand (read+write) accesses 538system.cpu.icache.overall_accesses::cpu.inst 113060022 # number of overall (read+write) accesses 539system.cpu.icache.overall_accesses::total 113060022 # number of overall (read+write) accesses 540system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses 541system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses 542system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses 543system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses 544system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses 545system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses 546system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22259.681208 # average ReadReq miss latency 547system.cpu.icache.ReadReq_avg_miss_latency::total 22259.681208 # average ReadReq miss latency 548system.cpu.icache.demand_avg_miss_latency::cpu.inst 22259.681208 # average overall miss latency 549system.cpu.icache.demand_avg_miss_latency::total 22259.681208 # average overall miss latency 550system.cpu.icache.overall_avg_miss_latency::cpu.inst 22259.681208 # average overall miss latency 551system.cpu.icache.overall_avg_miss_latency::total 22259.681208 # average overall miss latency 552system.cpu.icache.blocked_cycles::no_mshrs 617 # number of cycles access was blocked 553system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked 555system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu.icache.avg_blocked_cycles::no_mshrs 44.071429 # average number of cycles each access was blocked 557system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.cpu.icache.fast_writes 0 # number of fast writes performed 559system.cpu.icache.cache_copies 0 # number of cache copies performed 560system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4142 # number of ReadReq MSHR hits 561system.cpu.icache.ReadReq_mshr_hits::total 4142 # number of ReadReq MSHR hits 562system.cpu.icache.demand_mshr_hits::cpu.inst 4142 # number of demand (read+write) MSHR hits 563system.cpu.icache.demand_mshr_hits::total 4142 # number of demand (read+write) MSHR hits 564system.cpu.icache.overall_mshr_hits::cpu.inst 4142 # number of overall MSHR hits 565system.cpu.icache.overall_mshr_hits::total 4142 # number of overall MSHR hits 566system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16878 # number of ReadReq MSHR misses 567system.cpu.icache.ReadReq_mshr_misses::total 16878 # number of ReadReq MSHR misses 568system.cpu.icache.demand_mshr_misses::cpu.inst 16878 # number of demand (read+write) MSHR misses 569system.cpu.icache.demand_mshr_misses::total 16878 # number of demand (read+write) MSHR misses 570system.cpu.icache.overall_mshr_misses::cpu.inst 16878 # number of overall MSHR misses 571system.cpu.icache.overall_mshr_misses::total 16878 # number of overall MSHR misses 572system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 345467499 # number of ReadReq MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_latency::total 345467499 # number of ReadReq MSHR miss cycles 574system.cpu.icache.demand_mshr_miss_latency::cpu.inst 345467499 # number of demand (read+write) MSHR miss cycles 575system.cpu.icache.demand_mshr_miss_latency::total 345467499 # number of demand (read+write) MSHR miss cycles 576system.cpu.icache.overall_mshr_miss_latency::cpu.inst 345467499 # number of overall MSHR miss cycles 577system.cpu.icache.overall_mshr_miss_latency::total 345467499 # number of overall MSHR miss cycles 578system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses 579system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses 580system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses 581system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses 582system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses 583system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses 584system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20468.509243 # average ReadReq mshr miss latency 585system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20468.509243 # average ReadReq mshr miss latency 586system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20468.509243 # average overall mshr miss latency 587system.cpu.icache.demand_avg_mshr_miss_latency::total 20468.509243 # average overall mshr miss latency 588system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20468.509243 # average overall mshr miss latency 589system.cpu.icache.overall_avg_mshr_miss_latency::total 20468.509243 # average overall mshr miss latency 590system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 591system.cpu.dcache.replacements 1192636 # number of replacements 592system.cpu.dcache.tagsinuse 4054.758730 # Cycle average of tags in use 593system.cpu.dcache.total_refs 191679858 # Total number of references to valid blocks. 594system.cpu.dcache.sampled_refs 1196732 # Sample count of references to valid blocks. 595system.cpu.dcache.avg_refs 160.169410 # Average number of references to valid blocks. 596system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit. 597system.cpu.dcache.occ_blocks::cpu.data 4054.758730 # Average occupied blocks per requestor 598system.cpu.dcache.occ_percent::cpu.data 0.989931 # Average percentage of cache occupancy 599system.cpu.dcache.occ_percent::total 0.989931 # Average percentage of cache occupancy 600system.cpu.dcache.ReadReq_hits::cpu.data 136223332 # number of ReadReq hits 601system.cpu.dcache.ReadReq_hits::total 136223332 # number of ReadReq hits 602system.cpu.dcache.WriteReq_hits::cpu.data 50991136 # number of WriteReq hits 603system.cpu.dcache.WriteReq_hits::total 50991136 # number of WriteReq hits 604system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233077 # number of LoadLockedReq hits 605system.cpu.dcache.LoadLockedReq_hits::total 2233077 # number of LoadLockedReq hits 606system.cpu.dcache.StoreCondReq_hits::cpu.data 2232044 # number of StoreCondReq hits 607system.cpu.dcache.StoreCondReq_hits::total 2232044 # number of StoreCondReq hits 608system.cpu.dcache.demand_hits::cpu.data 187214468 # number of demand (read+write) hits 609system.cpu.dcache.demand_hits::total 187214468 # number of demand (read+write) hits 610system.cpu.dcache.overall_hits::cpu.data 187214468 # number of overall hits 611system.cpu.dcache.overall_hits::total 187214468 # number of overall hits 612system.cpu.dcache.ReadReq_misses::cpu.data 1695528 # number of ReadReq misses 613system.cpu.dcache.ReadReq_misses::total 1695528 # number of ReadReq misses 614system.cpu.dcache.WriteReq_misses::cpu.data 3248170 # number of WriteReq misses 615system.cpu.dcache.WriteReq_misses::total 3248170 # number of WriteReq misses 616system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses 617system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses 618system.cpu.dcache.demand_misses::cpu.data 4943698 # number of demand (read+write) misses 619system.cpu.dcache.demand_misses::total 4943698 # number of demand (read+write) misses 620system.cpu.dcache.overall_misses::cpu.data 4943698 # number of overall misses 621system.cpu.dcache.overall_misses::total 4943698 # number of overall misses 622system.cpu.dcache.ReadReq_miss_latency::cpu.data 25996744000 # number of ReadReq miss cycles 623system.cpu.dcache.ReadReq_miss_latency::total 25996744000 # number of ReadReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::cpu.data 58872632949 # number of WriteReq miss cycles 625system.cpu.dcache.WriteReq_miss_latency::total 58872632949 # number of WriteReq miss cycles 626system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 602000 # number of LoadLockedReq miss cycles 627system.cpu.dcache.LoadLockedReq_miss_latency::total 602000 # number of LoadLockedReq miss cycles 628system.cpu.dcache.demand_miss_latency::cpu.data 84869376949 # number of demand (read+write) miss cycles 629system.cpu.dcache.demand_miss_latency::total 84869376949 # number of demand (read+write) miss cycles 630system.cpu.dcache.overall_miss_latency::cpu.data 84869376949 # number of overall miss cycles 631system.cpu.dcache.overall_miss_latency::total 84869376949 # number of overall miss cycles 632system.cpu.dcache.ReadReq_accesses::cpu.data 137918860 # number of ReadReq accesses(hits+misses) 633system.cpu.dcache.ReadReq_accesses::total 137918860 # number of ReadReq accesses(hits+misses) 634system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 635system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 636system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233117 # number of LoadLockedReq accesses(hits+misses) 637system.cpu.dcache.LoadLockedReq_accesses::total 2233117 # number of LoadLockedReq accesses(hits+misses) 638system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232044 # number of StoreCondReq accesses(hits+misses) 639system.cpu.dcache.StoreCondReq_accesses::total 2232044 # number of StoreCondReq accesses(hits+misses) 640system.cpu.dcache.demand_accesses::cpu.data 192158166 # number of demand (read+write) accesses 641system.cpu.dcache.demand_accesses::total 192158166 # number of demand (read+write) accesses 642system.cpu.dcache.overall_accesses::cpu.data 192158166 # number of overall (read+write) accesses 643system.cpu.dcache.overall_accesses::total 192158166 # number of overall (read+write) accesses 644system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012294 # miss rate for ReadReq accesses 645system.cpu.dcache.ReadReq_miss_rate::total 0.012294 # miss rate for ReadReq accesses 646system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059886 # miss rate for WriteReq accesses 647system.cpu.dcache.WriteReq_miss_rate::total 0.059886 # miss rate for WriteReq accesses 648system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000018 # miss rate for LoadLockedReq accesses 649system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000018 # miss rate for LoadLockedReq accesses 650system.cpu.dcache.demand_miss_rate::cpu.data 0.025727 # miss rate for demand accesses 651system.cpu.dcache.demand_miss_rate::total 0.025727 # miss rate for demand accesses 652system.cpu.dcache.overall_miss_rate::cpu.data 0.025727 # miss rate for overall accesses 653system.cpu.dcache.overall_miss_rate::total 0.025727 # miss rate for overall accesses 654system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15332.535942 # average ReadReq miss latency 655system.cpu.dcache.ReadReq_avg_miss_latency::total 15332.535942 # average ReadReq miss latency 656system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18124.861984 # average WriteReq miss latency 657system.cpu.dcache.WriteReq_avg_miss_latency::total 18124.861984 # average WriteReq miss latency 658system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15050 # average LoadLockedReq miss latency 659system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15050 # average LoadLockedReq miss latency 660system.cpu.dcache.demand_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency 661system.cpu.dcache.demand_avg_miss_latency::total 17167.184757 # average overall miss latency 662system.cpu.dcache.overall_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::total 17167.184757 # average overall miss latency 664system.cpu.dcache.blocked_cycles::no_mshrs 14786 # number of cycles access was blocked 665system.cpu.dcache.blocked_cycles::no_targets 14311 # number of cycles access was blocked 666system.cpu.dcache.blocked::no_mshrs 1668 # number of cycles access was blocked 667system.cpu.dcache.blocked::no_targets 602 # number of cycles access was blocked 668system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.864508 # average number of cycles each access was blocked 669system.cpu.dcache.avg_blocked_cycles::no_targets 23.772425 # average number of cycles each access was blocked 670system.cpu.dcache.fast_writes 0 # number of fast writes performed 671system.cpu.dcache.cache_copies 0 # number of cache copies performed 672system.cpu.dcache.writebacks::writebacks 1110847 # number of writebacks 673system.cpu.dcache.writebacks::total 1110847 # number of writebacks 674system.cpu.dcache.ReadReq_mshr_hits::cpu.data 847136 # number of ReadReq MSHR hits 675system.cpu.dcache.ReadReq_mshr_hits::total 847136 # number of ReadReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899743 # number of WriteReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::total 2899743 # number of WriteReq MSHR hits 678system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits 679system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits 680system.cpu.dcache.demand_mshr_hits::cpu.data 3746879 # number of demand (read+write) MSHR hits 681system.cpu.dcache.demand_mshr_hits::total 3746879 # number of demand (read+write) MSHR hits 682system.cpu.dcache.overall_mshr_hits::cpu.data 3746879 # number of overall MSHR hits 683system.cpu.dcache.overall_mshr_hits::total 3746879 # number of overall MSHR hits 684system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848392 # number of ReadReq MSHR misses 685system.cpu.dcache.ReadReq_mshr_misses::total 848392 # number of ReadReq MSHR misses 686system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348427 # number of WriteReq MSHR misses 687system.cpu.dcache.WriteReq_mshr_misses::total 348427 # number of WriteReq MSHR misses 688system.cpu.dcache.demand_mshr_misses::cpu.data 1196819 # number of demand (read+write) MSHR misses 689system.cpu.dcache.demand_mshr_misses::total 1196819 # number of demand (read+write) MSHR misses 690system.cpu.dcache.overall_mshr_misses::cpu.data 1196819 # number of overall MSHR misses 691system.cpu.dcache.overall_mshr_misses::total 1196819 # number of overall MSHR misses 692system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11475027500 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.ReadReq_mshr_miss_latency::total 11475027500 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8270144996 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::total 8270144996 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19745172496 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.demand_mshr_miss_latency::total 19745172496 # number of demand (read+write) MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19745172496 # number of overall MSHR miss cycles 699system.cpu.dcache.overall_mshr_miss_latency::total 19745172496 # number of overall MSHR miss cycles 700system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses 701system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses 702system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses 703system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses 704system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses 705system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses 706system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses 707system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses 708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13525.619643 # average ReadReq mshr miss latency 709system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13525.619643 # average ReadReq mshr miss latency 710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23735.660543 # average WriteReq mshr miss latency 711system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23735.660543 # average WriteReq mshr miss latency 712system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16498.043978 # average overall mshr miss latency 713system.cpu.dcache.demand_avg_mshr_miss_latency::total 16498.043978 # average overall mshr miss latency 714system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16498.043978 # average overall mshr miss latency 715system.cpu.dcache.overall_avg_mshr_miss_latency::total 16498.043978 # average overall mshr miss latency 716system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 717system.cpu.l2cache.replacements 115436 # number of replacements 718system.cpu.l2cache.tagsinuse 26914.677594 # Cycle average of tags in use 719system.cpu.l2cache.total_refs 1781438 # Total number of references to valid blocks. 720system.cpu.l2cache.sampled_refs 146695 # Sample count of references to valid blocks. 721system.cpu.l2cache.avg_refs 12.143822 # Average number of references to valid blocks. 722system.cpu.l2cache.warmup_cycle 106786835500 # Cycle when the warmup percentage was hit. 723system.cpu.l2cache.occ_blocks::writebacks 22885.911087 # Average occupied blocks per requestor 724system.cpu.l2cache.occ_blocks::cpu.inst 362.909713 # Average occupied blocks per requestor 725system.cpu.l2cache.occ_blocks::cpu.data 3665.856794 # Average occupied blocks per requestor 726system.cpu.l2cache.occ_percent::writebacks 0.698423 # Average percentage of cache occupancy 727system.cpu.l2cache.occ_percent::cpu.inst 0.011075 # Average percentage of cache occupancy 728system.cpu.l2cache.occ_percent::cpu.data 0.111873 # Average percentage of cache occupancy 729system.cpu.l2cache.occ_percent::total 0.821371 # Average percentage of cache occupancy 730system.cpu.l2cache.ReadReq_hits::cpu.inst 13377 # number of ReadReq hits 731system.cpu.l2cache.ReadReq_hits::cpu.data 804311 # number of ReadReq hits 732system.cpu.l2cache.ReadReq_hits::total 817688 # number of ReadReq hits 733system.cpu.l2cache.Writeback_hits::writebacks 1110847 # number of Writeback hits 734system.cpu.l2cache.Writeback_hits::total 1110847 # number of Writeback hits 735system.cpu.l2cache.UpgradeReq_hits::cpu.data 76 # number of UpgradeReq hits 736system.cpu.l2cache.UpgradeReq_hits::total 76 # number of UpgradeReq hits 737system.cpu.l2cache.ReadExReq_hits::cpu.data 247608 # number of ReadExReq hits 738system.cpu.l2cache.ReadExReq_hits::total 247608 # number of ReadExReq hits 739system.cpu.l2cache.demand_hits::cpu.inst 13377 # number of demand (read+write) hits 740system.cpu.l2cache.demand_hits::cpu.data 1051919 # number of demand (read+write) hits 741system.cpu.l2cache.demand_hits::total 1065296 # number of demand (read+write) hits 742system.cpu.l2cache.overall_hits::cpu.inst 13377 # number of overall hits 743system.cpu.l2cache.overall_hits::cpu.data 1051919 # number of overall hits 744system.cpu.l2cache.overall_hits::total 1065296 # number of overall hits 745system.cpu.l2cache.ReadReq_misses::cpu.inst 3401 # number of ReadReq misses 746system.cpu.l2cache.ReadReq_misses::cpu.data 43520 # number of ReadReq misses 747system.cpu.l2cache.ReadReq_misses::total 46921 # number of ReadReq misses 748system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses 749system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses 750system.cpu.l2cache.ReadExReq_misses::cpu.data 101293 # number of ReadExReq misses 751system.cpu.l2cache.ReadExReq_misses::total 101293 # number of ReadExReq misses 752system.cpu.l2cache.demand_misses::cpu.inst 3401 # number of demand (read+write) misses 753system.cpu.l2cache.demand_misses::cpu.data 144813 # number of demand (read+write) misses 754system.cpu.l2cache.demand_misses::total 148214 # number of demand (read+write) misses 755system.cpu.l2cache.overall_misses::cpu.inst 3401 # number of overall misses 756system.cpu.l2cache.overall_misses::cpu.data 144813 # number of overall misses 757system.cpu.l2cache.overall_misses::total 148214 # number of overall misses 758system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 194270000 # number of ReadReq miss cycles 759system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2545313000 # number of ReadReq miss cycles 760system.cpu.l2cache.ReadReq_miss_latency::total 2739583000 # number of ReadReq miss cycles 761system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5395902500 # number of ReadExReq miss cycles 762system.cpu.l2cache.ReadExReq_miss_latency::total 5395902500 # number of ReadExReq miss cycles 763system.cpu.l2cache.demand_miss_latency::cpu.inst 194270000 # number of demand (read+write) miss cycles 764system.cpu.l2cache.demand_miss_latency::cpu.data 7941215500 # number of demand (read+write) miss cycles 765system.cpu.l2cache.demand_miss_latency::total 8135485500 # number of demand (read+write) miss cycles 766system.cpu.l2cache.overall_miss_latency::cpu.inst 194270000 # number of overall miss cycles 767system.cpu.l2cache.overall_miss_latency::cpu.data 7941215500 # number of overall miss cycles 768system.cpu.l2cache.overall_miss_latency::total 8135485500 # number of overall miss cycles 769system.cpu.l2cache.ReadReq_accesses::cpu.inst 16778 # number of ReadReq accesses(hits+misses) 770system.cpu.l2cache.ReadReq_accesses::cpu.data 847831 # number of ReadReq accesses(hits+misses) 771system.cpu.l2cache.ReadReq_accesses::total 864609 # number of ReadReq accesses(hits+misses) 772system.cpu.l2cache.Writeback_accesses::writebacks 1110847 # number of Writeback accesses(hits+misses) 773system.cpu.l2cache.Writeback_accesses::total 1110847 # number of Writeback accesses(hits+misses) 774system.cpu.l2cache.UpgradeReq_accesses::cpu.data 87 # number of UpgradeReq accesses(hits+misses) 775system.cpu.l2cache.UpgradeReq_accesses::total 87 # number of UpgradeReq accesses(hits+misses) 776system.cpu.l2cache.ReadExReq_accesses::cpu.data 348901 # number of ReadExReq accesses(hits+misses) 777system.cpu.l2cache.ReadExReq_accesses::total 348901 # number of ReadExReq accesses(hits+misses) 778system.cpu.l2cache.demand_accesses::cpu.inst 16778 # number of demand (read+write) accesses 779system.cpu.l2cache.demand_accesses::cpu.data 1196732 # number of demand (read+write) accesses 780system.cpu.l2cache.demand_accesses::total 1213510 # number of demand (read+write) accesses 781system.cpu.l2cache.overall_accesses::cpu.inst 16778 # number of overall (read+write) accesses 782system.cpu.l2cache.overall_accesses::cpu.data 1196732 # number of overall (read+write) accesses 783system.cpu.l2cache.overall_accesses::total 1213510 # number of overall (read+write) accesses 784system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.202706 # miss rate for ReadReq accesses 785system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051331 # miss rate for ReadReq accesses 786system.cpu.l2cache.ReadReq_miss_rate::total 0.054268 # miss rate for ReadReq accesses 787system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.126437 # miss rate for UpgradeReq accesses 788system.cpu.l2cache.UpgradeReq_miss_rate::total 0.126437 # miss rate for UpgradeReq accesses 789system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290320 # miss rate for ReadExReq accesses 790system.cpu.l2cache.ReadExReq_miss_rate::total 0.290320 # miss rate for ReadExReq accesses 791system.cpu.l2cache.demand_miss_rate::cpu.inst 0.202706 # miss rate for demand accesses 792system.cpu.l2cache.demand_miss_rate::cpu.data 0.121007 # miss rate for demand accesses 793system.cpu.l2cache.demand_miss_rate::total 0.122137 # miss rate for demand accesses 794system.cpu.l2cache.overall_miss_rate::cpu.inst 0.202706 # miss rate for overall accesses 795system.cpu.l2cache.overall_miss_rate::cpu.data 0.121007 # miss rate for overall accesses 796system.cpu.l2cache.overall_miss_rate::total 0.122137 # miss rate for overall accesses 797system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57121.434872 # average ReadReq miss latency 798system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58486.052390 # average ReadReq miss latency 799system.cpu.l2cache.ReadReq_avg_miss_latency::total 58387.140087 # average ReadReq miss latency 800system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53270.240787 # average ReadExReq miss latency 801system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53270.240787 # average ReadExReq miss latency 802system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57121.434872 # average overall miss latency 803system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54837.725204 # average overall miss latency 804system.cpu.l2cache.demand_avg_miss_latency::total 54890.128463 # average overall miss latency 805system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57121.434872 # average overall miss latency 806system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54837.725204 # average overall miss latency 807system.cpu.l2cache.overall_avg_miss_latency::total 54890.128463 # average overall miss latency 808system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 809system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 810system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 811system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 812system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 813system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 814system.cpu.l2cache.fast_writes 0 # number of fast writes performed 815system.cpu.l2cache.cache_copies 0 # number of cache copies performed 816system.cpu.l2cache.writebacks::writebacks 97644 # number of writebacks 817system.cpu.l2cache.writebacks::total 97644 # number of writebacks 818system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 819system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits 820system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits 821system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 822system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits 823system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits 824system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 825system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits 826system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits 827system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3396 # number of ReadReq MSHR misses 828system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43497 # number of ReadReq MSHR misses 829system.cpu.l2cache.ReadReq_mshr_misses::total 46893 # number of ReadReq MSHR misses 830system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses 831system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses 832system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses 833system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses 834system.cpu.l2cache.demand_mshr_misses::cpu.inst 3396 # number of demand (read+write) MSHR misses 835system.cpu.l2cache.demand_mshr_misses::cpu.data 144790 # number of demand (read+write) MSHR misses 836system.cpu.l2cache.demand_mshr_misses::total 148186 # number of demand (read+write) MSHR misses 837system.cpu.l2cache.overall_mshr_misses::cpu.inst 3396 # number of overall MSHR misses 838system.cpu.l2cache.overall_mshr_misses::cpu.data 144790 # number of overall MSHR misses 839system.cpu.l2cache.overall_mshr_misses::total 148186 # number of overall MSHR misses 840system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 150961260 # number of ReadReq MSHR miss cycles 841system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1989439233 # number of ReadReq MSHR miss cycles 842system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2140400493 # number of ReadReq MSHR miss cycles 843system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 110011 # number of UpgradeReq MSHR miss cycles 844system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 110011 # number of UpgradeReq MSHR miss cycles 845system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4107848419 # number of ReadExReq MSHR miss cycles 846system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4107848419 # number of ReadExReq MSHR miss cycles 847system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 150961260 # number of demand (read+write) MSHR miss cycles 848system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6097287652 # number of demand (read+write) MSHR miss cycles 849system.cpu.l2cache.demand_mshr_miss_latency::total 6248248912 # number of demand (read+write) MSHR miss cycles 850system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 150961260 # number of overall MSHR miss cycles 851system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6097287652 # number of overall MSHR miss cycles 852system.cpu.l2cache.overall_mshr_miss_latency::total 6248248912 # number of overall MSHR miss cycles 853system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for ReadReq accesses 854system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051304 # mshr miss rate for ReadReq accesses 855system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses 856system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.126437 # mshr miss rate for UpgradeReq accesses 857system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.126437 # mshr miss rate for UpgradeReq accesses 858system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290320 # mshr miss rate for ReadExReq accesses 859system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290320 # mshr miss rate for ReadExReq accesses 860system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for demand accesses 861system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120988 # mshr miss rate for demand accesses 862system.cpu.l2cache.demand_mshr_miss_rate::total 0.122114 # mshr miss rate for demand accesses 863system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for overall accesses 864system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120988 # mshr miss rate for overall accesses 865system.cpu.l2cache.overall_mshr_miss_rate::total 0.122114 # mshr miss rate for overall accesses 866system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44452.667845 # average ReadReq mshr miss latency 867system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45737.389544 # average ReadReq mshr miss latency 868system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45644.349754 # average ReadReq mshr miss latency 869system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 870system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 871system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40554.119426 # average ReadExReq mshr miss latency 872system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40554.119426 # average ReadExReq mshr miss latency 873system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44452.667845 # average overall mshr miss latency 874system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42111.248374 # average overall mshr miss latency 875system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42164.907022 # average overall mshr miss latency 876system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44452.667845 # average overall mshr miss latency 877system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42111.248374 # average overall mshr miss latency 878system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42164.907022 # average overall mshr miss latency 879system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 880 881---------- End Simulation Statistics ---------- 882