stats.txt revision 9312:e05e1b69ebf2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.201821 # Number of seconds simulated 4sim_ticks 201820850500 # Number of ticks simulated 5final_tick 201820850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 158073 # Simulator instruction rate (inst/s) 8host_op_rate 178071 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 62682331 # Simulator tick rate (ticks/s) 10host_mem_usage 261124 # Number of bytes of host memory used 11host_seconds 3219.74 # Real time elapsed on the host 12sim_insts 508955148 # Number of instructions simulated 13sim_ops 573341708 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 219776 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 10015744 # Number of bytes read from this memory 16system.physmem.bytes_read::total 10235520 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 219776 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 219776 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6680640 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6680640 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3434 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 156496 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 159930 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 104385 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 104385 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1088966 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 49626904 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 50715870 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 1088966 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 1088966 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 33101833 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 33101833 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 33101833 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 1088966 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 49626904 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 83817702 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 159931 # Total number of read requests seen 38system.physmem.writeReqs 104385 # Total number of write requests seen 39system.physmem.cpureqs 264320 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 10235520 # Total number of bytes read from memory 41system.physmem.bytesWritten 6680640 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 10235520 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 6680640 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 186 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 4 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 9715 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 10028 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 9563 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 9185 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 9586 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 9626 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 9845 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 10204 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 9902 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 11404 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 10776 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 10740 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 9984 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 9763 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 9956 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 9468 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 6164 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 6588 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 6206 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 6224 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 6375 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 6383 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 6446 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 6854 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 6435 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 7038 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 6926 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 6925 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 6680 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 6603 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 6451 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 6087 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 80system.physmem.totGap 201820829500 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 159931 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes 96system.physmem.writePktSize::6 104385 # categorize write packet sizes 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 4 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 108system.physmem.rdQLenPdf::0 148144 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 10717 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 754 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 102 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 4524 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 4539 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 4539 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 4539 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 4539 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 4539 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 4539 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 4539 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 4539 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 4539 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 4539 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 4538 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 4538 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 4538 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 4538 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 4538 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 4538 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 4538 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 4538 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 4538 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 4538 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 4538 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 4538 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 174system.physmem.totQLat 1228593768 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 4610173768 # Sum of mem lat for all requests 176system.physmem.totBusLat 638980000 # Total cycles spent in databus access 177system.physmem.totBankLat 2742600000 # Total cycles spent in bank access 178system.physmem.avgQLat 7690.97 # Average queueing delay per request 179system.physmem.avgBankLat 17168.61 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request 181system.physmem.avgMemAccLat 28859.58 # Average memory access latency 182system.physmem.avgRdBW 50.72 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 33.10 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 50.72 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 33.10 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.52 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.02 # Average read queue length over time 189system.physmem.avgWrQLen 8.69 # Average write queue length over time 190system.physmem.readRowHits 136302 # Number of row buffer hits during reads 191system.physmem.writeRowHits 64360 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 85.32 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 61.66 # Row buffer hit rate for writes 194system.physmem.avgGap 763558.88 # Average gap between requests 195system.cpu.dtb.inst_hits 0 # ITB inst hits 196system.cpu.dtb.inst_misses 0 # ITB inst misses 197system.cpu.dtb.read_hits 0 # DTB read hits 198system.cpu.dtb.read_misses 0 # DTB read misses 199system.cpu.dtb.write_hits 0 # DTB write hits 200system.cpu.dtb.write_misses 0 # DTB write misses 201system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 202system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 203system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 204system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 205system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 206system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 207system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 208system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 209system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 210system.cpu.dtb.read_accesses 0 # DTB read accesses 211system.cpu.dtb.write_accesses 0 # DTB write accesses 212system.cpu.dtb.inst_accesses 0 # ITB inst accesses 213system.cpu.dtb.hits 0 # DTB hits 214system.cpu.dtb.misses 0 # DTB misses 215system.cpu.dtb.accesses 0 # DTB accesses 216system.cpu.itb.inst_hits 0 # ITB inst hits 217system.cpu.itb.inst_misses 0 # ITB inst misses 218system.cpu.itb.read_hits 0 # DTB read hits 219system.cpu.itb.read_misses 0 # DTB read misses 220system.cpu.itb.write_hits 0 # DTB write hits 221system.cpu.itb.write_misses 0 # DTB write misses 222system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 223system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 224system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 225system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 226system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 227system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 228system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 229system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 230system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu.itb.read_accesses 0 # DTB read accesses 232system.cpu.itb.write_accesses 0 # DTB write accesses 233system.cpu.itb.inst_accesses 0 # ITB inst accesses 234system.cpu.itb.hits 0 # DTB hits 235system.cpu.itb.misses 0 # DTB misses 236system.cpu.itb.accesses 0 # DTB accesses 237system.cpu.workload.num_syscalls 548 # Number of system calls 238system.cpu.numCycles 403641702 # number of cpu cycles simulated 239system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 240system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 241system.cpu.BPredUnit.lookups 183652385 # Number of BP lookups 242system.cpu.BPredUnit.condPredicted 143319168 # Number of conditional branches predicted 243system.cpu.BPredUnit.condIncorrect 7791559 # Number of conditional branches incorrect 244system.cpu.BPredUnit.BTBLookups 98117243 # Number of BTB lookups 245system.cpu.BPredUnit.BTBHits 90149856 # Number of BTB hits 246system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 247system.cpu.BPredUnit.usedRAS 12789076 # Number of times the RAS was used to get a target. 248system.cpu.BPredUnit.RASInCorrect 115438 # Number of incorrect RAS predictions. 249system.cpu.fetch.icacheStallCycles 119026376 # Number of cycles fetch is stalled on an Icache miss 250system.cpu.fetch.Insts 771196614 # Number of instructions fetch has processed 251system.cpu.fetch.Branches 183652385 # Number of branches that fetch encountered 252system.cpu.fetch.predictedBranches 102938932 # Number of branches that fetch has predicted taken 253system.cpu.fetch.Cycles 173108927 # Number of cycles fetch has run and was not squashing or blocked 254system.cpu.fetch.SquashCycles 37044032 # Number of cycles fetch has spent squashing 255system.cpu.fetch.BlockedCycles 80186575 # Number of cycles fetch has spent blocked 256system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 257system.cpu.fetch.PendingTrapStallCycles 394 # Number of stall cycles due to pending traps 258system.cpu.fetch.CacheLines 114778688 # Number of cache lines fetched 259system.cpu.fetch.IcacheSquashes 2637185 # Number of outstanding Icache misses that were squashed 260system.cpu.fetch.rateDist::samples 400780006 # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::mean 2.162952 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::stdev 2.978630 # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::0 227683870 56.81% 56.81% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::1 14342886 3.58% 60.39% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::2 23399081 5.84% 66.23% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::3 22963566 5.73% 71.96% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::4 20939416 5.22% 77.18% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::5 13281175 3.31% 80.50% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::6 13284797 3.31% 83.81% # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::7 12117870 3.02% 86.83% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::8 52767345 13.17% 100.00% # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::total 400780006 # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.branchRate 0.454989 # Number of branch fetches per cycle 278system.cpu.fetch.rate 1.910597 # Number of inst fetches per cycle 279system.cpu.decode.IdleCycles 129077693 # Number of cycles decode is idle 280system.cpu.decode.BlockedCycles 74884830 # Number of cycles decode is blocked 281system.cpu.decode.RunCycles 163721203 # Number of cycles decode is running 282system.cpu.decode.UnblockCycles 4713887 # Number of cycles decode is unblocking 283system.cpu.decode.SquashCycles 28382393 # Number of cycles decode is squashing 284system.cpu.decode.BranchResolved 26602700 # Number of times decode resolved a branch 285system.cpu.decode.BranchMispred 78428 # Number of times decode detected a branch misprediction 286system.cpu.decode.DecodedInsts 842461319 # Number of instructions handled by decode 287system.cpu.decode.SquashedInsts 313133 # Number of squashed instructions handled by decode 288system.cpu.rename.SquashCycles 28382393 # Number of cycles rename is squashing 289system.cpu.rename.IdleCycles 136940970 # Number of cycles rename is idle 290system.cpu.rename.BlockCycles 4647966 # Number of cycles rename is blocking 291system.cpu.rename.serializeStallCycles 57066662 # count of cycles rename stalled for serializing inst 292system.cpu.rename.RunCycles 160444938 # Number of cycles rename is running 293system.cpu.rename.UnblockCycles 13297077 # Number of cycles rename is unblocking 294system.cpu.rename.RenamedInsts 812260436 # Number of instructions processed by rename 295system.cpu.rename.ROBFullEvents 946 # Number of times rename has blocked due to ROB full 296system.cpu.rename.IQFullEvents 2860927 # Number of times rename has blocked due to IQ full 297system.cpu.rename.LSQFullEvents 6878465 # Number of times rename has blocked due to LSQ full 298system.cpu.rename.FullRegisterEvents 58 # Number of times there has been no free registers 299system.cpu.rename.RenamedOperands 967590618 # Number of destination operands rename has renamed 300system.cpu.rename.RenameLookups 3556107711 # Number of register rename lookups that rename has made 301system.cpu.rename.int_rename_lookups 3556106126 # Number of integer rename lookups 302system.cpu.rename.fp_rename_lookups 1585 # Number of floating rename lookups 303system.cpu.rename.CommittedMaps 672200171 # Number of HB maps that are committed 304system.cpu.rename.UndoneMaps 295390447 # Number of HB maps that are undone due to squashing 305system.cpu.rename.serializingInsts 3042631 # count of serializing insts renamed 306system.cpu.rename.tempSerializingInsts 3042626 # count of temporary serializing insts renamed 307system.cpu.rename.skidInsts 43966533 # count of insts added to the skid buffer 308system.cpu.memDep0.insertedLoads 172435046 # Number of loads inserted to the mem dependence unit. 309system.cpu.memDep0.insertedStores 75040987 # Number of stores inserted to the mem dependence unit. 310system.cpu.memDep0.conflictingLoads 27084528 # Number of conflicting loads. 311system.cpu.memDep0.conflictingStores 14183257 # Number of conflicting stores. 312system.cpu.iq.iqInstsAdded 762885569 # Number of instructions added to the IQ (excludes non-spec) 313system.cpu.iq.iqNonSpecInstsAdded 4467405 # Number of non-speculative instructions added to the IQ 314system.cpu.iq.iqInstsIssued 672287055 # Number of instructions issued 315system.cpu.iq.iqSquashedInstsIssued 1597234 # Number of squashed instructions issued 316system.cpu.iq.iqSquashedInstsExamined 191943939 # Number of squashed instructions iterated over during squash; mainly for profiling 317system.cpu.iq.iqSquashedOperandsExamined 493452075 # Number of squashed operands that are examined and possibly removed from graph 318system.cpu.iq.iqSquashedNonSpecRemoved 746288 # Number of squashed non-spec instructions that were removed 319system.cpu.iq.issued_per_cycle::samples 400780006 # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::mean 1.677447 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::stdev 1.741326 # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::0 142470034 35.55% 35.55% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::1 73884527 18.44% 53.98% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::2 68392945 17.06% 71.05% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::3 53248174 13.29% 84.33% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::4 32249720 8.05% 92.38% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::5 16393621 4.09% 96.47% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::6 9384825 2.34% 98.81% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::7 3453099 0.86% 99.67% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::8 1303061 0.33% 100.00% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::total 400780006 # Number of insts issued each cycle 336system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 337system.cpu.iq.fu_full::IntAlu 434732 4.35% 4.35% # attempts to use FU when none available 338system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available 339system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available 344system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available 345system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available 366system.cpu.iq.fu_full::MemRead 6807090 68.10% 72.45% # attempts to use FU when none available 367system.cpu.iq.fu_full::MemWrite 2754377 27.55% 100.00% # attempts to use FU when none available 368system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 369system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 370system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 371system.cpu.iq.FU_type_0::IntAlu 451597333 67.17% 67.17% # Type of FU issued 372system.cpu.iq.FU_type_0::IntMult 385890 0.06% 67.23% # Type of FU issued 373system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued 374system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.23% # Type of FU issued 375system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued 376system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued 377system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued 378system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued 379system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued 400system.cpu.iq.FU_type_0::MemRead 155180120 23.08% 90.31% # Type of FU issued 401system.cpu.iq.FU_type_0::MemWrite 65123593 9.69% 100.00% # Type of FU issued 402system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 403system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 404system.cpu.iq.FU_type_0::total 672287055 # Type of FU issued 405system.cpu.iq.rate 1.665554 # Inst issue rate 406system.cpu.iq.fu_busy_cnt 9996199 # FU busy when requested 407system.cpu.iq.fu_busy_rate 0.014869 # FU busy rate (busy events/executed inst) 408system.cpu.iq.int_inst_queue_reads 1756947282 # Number of integer instruction queue reads 409system.cpu.iq.int_inst_queue_writes 960099456 # Number of integer instruction queue writes 410system.cpu.iq.int_inst_queue_wakeup_accesses 651370563 # Number of integer instruction queue wakeup accesses 411system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads 412system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes 413system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 414system.cpu.iq.int_alu_accesses 682283119 # Number of integer alu accesses 415system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses 416system.cpu.iew.lsq.thread0.forwLoads 8423591 # Number of loads that had data forwarded from stores 417system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 418system.cpu.iew.lsq.thread0.squashedLoads 45662006 # Number of loads squashed 419system.cpu.iew.lsq.thread0.ignoredResponses 43583 # Number of memory responses ignored because the instruction is squashed 420system.cpu.iew.lsq.thread0.memOrderViolation 806705 # Number of memory ordering violations 421system.cpu.iew.lsq.thread0.squashedStores 17437025 # Number of stores squashed 422system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 423system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 424system.cpu.iew.lsq.thread0.rescheduledLoads 19460 # Number of loads that were rescheduled 425system.cpu.iew.lsq.thread0.cacheBlocked 290 # Number of times an access to memory failed due to the cache being blocked 426system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 427system.cpu.iew.iewSquashCycles 28382393 # Number of cycles IEW is squashing 428system.cpu.iew.iewBlockCycles 1656439 # Number of cycles IEW is blocking 429system.cpu.iew.iewUnblockCycles 73515 # Number of cycles IEW is unblocking 430system.cpu.iew.iewDispatchedInsts 768921673 # Number of instructions dispatched to IQ 431system.cpu.iew.iewDispSquashedInsts 1234448 # Number of squashed instructions skipped by dispatch 432system.cpu.iew.iewDispLoadInsts 172435046 # Number of dispatched load instructions 433system.cpu.iew.iewDispStoreInsts 75040987 # Number of dispatched store instructions 434system.cpu.iew.iewDispNonSpecInsts 2978685 # Number of dispatched non-speculative instructions 435system.cpu.iew.iewIQFullEvents 37777 # Number of times the IQ has become full, causing a stall 436system.cpu.iew.iewLSQFullEvents 4191 # Number of times the LSQ has become full, causing a stall 437system.cpu.iew.memOrderViolationEvents 806705 # Number of memory order violations 438system.cpu.iew.predictedTakenIncorrect 4752820 # Number of branches that were predicted taken incorrectly 439system.cpu.iew.predictedNotTakenIncorrect 4170938 # Number of branches that were predicted not taken incorrectly 440system.cpu.iew.branchMispredicts 8923758 # Number of branch mispredicts detected at execute 441system.cpu.iew.iewExecutedInsts 661908420 # Number of executed instructions 442system.cpu.iew.iewExecLoadInsts 151549628 # Number of load instructions executed 443system.cpu.iew.iewExecSquashedInsts 10378635 # Number of squashed instructions skipped in execute 444system.cpu.iew.exec_swp 0 # number of swp insts executed 445system.cpu.iew.exec_nop 1568699 # number of nop insts executed 446system.cpu.iew.exec_refs 215209256 # number of memory reference insts executed 447system.cpu.iew.exec_branches 139387977 # Number of branches executed 448system.cpu.iew.exec_stores 63659628 # Number of stores executed 449system.cpu.iew.exec_rate 1.639842 # Inst execution rate 450system.cpu.iew.wb_sent 656622179 # cumulative count of insts sent to commit 451system.cpu.iew.wb_count 651370579 # cumulative count of insts written-back 452system.cpu.iew.wb_producers 376034680 # num instructions producing a value 453system.cpu.iew.wb_consumers 649424114 # num instructions consuming a value 454system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 455system.cpu.iew.wb_rate 1.613735 # insts written-back per cycle 456system.cpu.iew.wb_fanout 0.579028 # average fanout of values written-back 457system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 458system.cpu.commit.commitSquashedInsts 194250034 # The number of squashed insts skipped by commit 459system.cpu.commit.commitNonSpecStalls 3721117 # The number of times commit has been forced to stall to communicate backwards 460system.cpu.commit.branchMispredicts 7716233 # The number of times a branch was mispredicted 461system.cpu.commit.committed_per_cycle::samples 372397614 # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::mean 1.543204 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::stdev 2.198347 # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::0 159514435 42.83% 42.83% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::1 102731237 27.59% 70.42% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::2 34442629 9.25% 79.67% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::3 18453291 4.96% 84.63% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::4 17522832 4.71% 89.33% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::5 7762690 2.08% 91.41% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::6 6910466 1.86% 93.27% # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::7 3138622 0.84% 94.11% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::8 21921412 5.89% 100.00% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::total 372397614 # Number of insts commited each cycle 478system.cpu.commit.committedInsts 510299032 # Number of instructions committed 479system.cpu.commit.committedOps 574685592 # Number of ops (including micro ops) committed 480system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 481system.cpu.commit.refs 184377002 # Number of memory references committed 482system.cpu.commit.loads 126773040 # Number of loads committed 483system.cpu.commit.membars 1488542 # Number of memory barriers committed 484system.cpu.commit.branches 122291786 # Number of branches committed 485system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 486system.cpu.commit.int_insts 473701633 # Number of committed integer instructions. 487system.cpu.commit.function_calls 9757362 # Number of function calls committed. 488system.cpu.commit.bw_lim_events 21921412 # number cycles where commit BW limit reached 489system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 490system.cpu.rob.rob_reads 1119404690 # The number of ROB reads 491system.cpu.rob.rob_writes 1566395163 # The number of ROB writes 492system.cpu.timesIdled 33245 # Number of times that the entire CPU went into an idle state and unscheduled itself 493system.cpu.idleCycles 2861696 # Total number of cycles that the CPU has spent unscheduled due to idling 494system.cpu.committedInsts 508955148 # Number of Instructions Simulated 495system.cpu.committedOps 573341708 # Number of Ops (including micro ops) Simulated 496system.cpu.committedInsts_total 508955148 # Number of Instructions Simulated 497system.cpu.cpi 0.793079 # CPI: Cycles Per Instruction 498system.cpu.cpi_total 0.793079 # CPI: Total CPI of All Threads 499system.cpu.ipc 1.260908 # IPC: Instructions Per Cycle 500system.cpu.ipc_total 1.260908 # IPC: Total IPC of All Threads 501system.cpu.int_regfile_reads 3088491950 # number of integer regfile reads 502system.cpu.int_regfile_writes 759517885 # number of integer regfile writes 503system.cpu.fp_regfile_reads 16 # number of floating regfile reads 504system.cpu.misc_regfile_reads 999182003 # number of misc regfile reads 505system.cpu.misc_regfile_writes 4464054 # number of misc regfile writes 506system.cpu.icache.replacements 15774 # number of replacements 507system.cpu.icache.tagsinuse 1094.155149 # Cycle average of tags in use 508system.cpu.icache.total_refs 114759358 # Total number of references to valid blocks. 509system.cpu.icache.sampled_refs 17633 # Sample count of references to valid blocks. 510system.cpu.icache.avg_refs 6508.215165 # Average number of references to valid blocks. 511system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 512system.cpu.icache.occ_blocks::cpu.inst 1094.155149 # Average occupied blocks per requestor 513system.cpu.icache.occ_percent::cpu.inst 0.534255 # Average percentage of cache occupancy 514system.cpu.icache.occ_percent::total 0.534255 # Average percentage of cache occupancy 515system.cpu.icache.ReadReq_hits::cpu.inst 114759358 # number of ReadReq hits 516system.cpu.icache.ReadReq_hits::total 114759358 # number of ReadReq hits 517system.cpu.icache.demand_hits::cpu.inst 114759358 # number of demand (read+write) hits 518system.cpu.icache.demand_hits::total 114759358 # number of demand (read+write) hits 519system.cpu.icache.overall_hits::cpu.inst 114759358 # number of overall hits 520system.cpu.icache.overall_hits::total 114759358 # number of overall hits 521system.cpu.icache.ReadReq_misses::cpu.inst 19330 # number of ReadReq misses 522system.cpu.icache.ReadReq_misses::total 19330 # number of ReadReq misses 523system.cpu.icache.demand_misses::cpu.inst 19330 # number of demand (read+write) misses 524system.cpu.icache.demand_misses::total 19330 # number of demand (read+write) misses 525system.cpu.icache.overall_misses::cpu.inst 19330 # number of overall misses 526system.cpu.icache.overall_misses::total 19330 # number of overall misses 527system.cpu.icache.ReadReq_miss_latency::cpu.inst 255186500 # number of ReadReq miss cycles 528system.cpu.icache.ReadReq_miss_latency::total 255186500 # number of ReadReq miss cycles 529system.cpu.icache.demand_miss_latency::cpu.inst 255186500 # number of demand (read+write) miss cycles 530system.cpu.icache.demand_miss_latency::total 255186500 # number of demand (read+write) miss cycles 531system.cpu.icache.overall_miss_latency::cpu.inst 255186500 # number of overall miss cycles 532system.cpu.icache.overall_miss_latency::total 255186500 # number of overall miss cycles 533system.cpu.icache.ReadReq_accesses::cpu.inst 114778688 # number of ReadReq accesses(hits+misses) 534system.cpu.icache.ReadReq_accesses::total 114778688 # number of ReadReq accesses(hits+misses) 535system.cpu.icache.demand_accesses::cpu.inst 114778688 # number of demand (read+write) accesses 536system.cpu.icache.demand_accesses::total 114778688 # number of demand (read+write) accesses 537system.cpu.icache.overall_accesses::cpu.inst 114778688 # number of overall (read+write) accesses 538system.cpu.icache.overall_accesses::total 114778688 # number of overall (read+write) accesses 539system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000168 # miss rate for ReadReq accesses 540system.cpu.icache.ReadReq_miss_rate::total 0.000168 # miss rate for ReadReq accesses 541system.cpu.icache.demand_miss_rate::cpu.inst 0.000168 # miss rate for demand accesses 542system.cpu.icache.demand_miss_rate::total 0.000168 # miss rate for demand accesses 543system.cpu.icache.overall_miss_rate::cpu.inst 0.000168 # miss rate for overall accesses 544system.cpu.icache.overall_miss_rate::total 0.000168 # miss rate for overall accesses 545system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13201.577858 # average ReadReq miss latency 546system.cpu.icache.ReadReq_avg_miss_latency::total 13201.577858 # average ReadReq miss latency 547system.cpu.icache.demand_avg_miss_latency::cpu.inst 13201.577858 # average overall miss latency 548system.cpu.icache.demand_avg_miss_latency::total 13201.577858 # average overall miss latency 549system.cpu.icache.overall_avg_miss_latency::cpu.inst 13201.577858 # average overall miss latency 550system.cpu.icache.overall_avg_miss_latency::total 13201.577858 # average overall miss latency 551system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 552system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 553system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 554system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 555system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 556system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 557system.cpu.icache.fast_writes 0 # number of fast writes performed 558system.cpu.icache.cache_copies 0 # number of cache copies performed 559system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1645 # number of ReadReq MSHR hits 560system.cpu.icache.ReadReq_mshr_hits::total 1645 # number of ReadReq MSHR hits 561system.cpu.icache.demand_mshr_hits::cpu.inst 1645 # number of demand (read+write) MSHR hits 562system.cpu.icache.demand_mshr_hits::total 1645 # number of demand (read+write) MSHR hits 563system.cpu.icache.overall_mshr_hits::cpu.inst 1645 # number of overall MSHR hits 564system.cpu.icache.overall_mshr_hits::total 1645 # number of overall MSHR hits 565system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17685 # number of ReadReq MSHR misses 566system.cpu.icache.ReadReq_mshr_misses::total 17685 # number of ReadReq MSHR misses 567system.cpu.icache.demand_mshr_misses::cpu.inst 17685 # number of demand (read+write) MSHR misses 568system.cpu.icache.demand_mshr_misses::total 17685 # number of demand (read+write) MSHR misses 569system.cpu.icache.overall_mshr_misses::cpu.inst 17685 # number of overall MSHR misses 570system.cpu.icache.overall_mshr_misses::total 17685 # number of overall MSHR misses 571system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170616000 # number of ReadReq MSHR miss cycles 572system.cpu.icache.ReadReq_mshr_miss_latency::total 170616000 # number of ReadReq MSHR miss cycles 573system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170616000 # number of demand (read+write) MSHR miss cycles 574system.cpu.icache.demand_mshr_miss_latency::total 170616000 # number of demand (read+write) MSHR miss cycles 575system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170616000 # number of overall MSHR miss cycles 576system.cpu.icache.overall_mshr_miss_latency::total 170616000 # number of overall MSHR miss cycles 577system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000154 # mshr miss rate for ReadReq accesses 578system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000154 # mshr miss rate for ReadReq accesses 579system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000154 # mshr miss rate for demand accesses 580system.cpu.icache.demand_mshr_miss_rate::total 0.000154 # mshr miss rate for demand accesses 581system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000154 # mshr miss rate for overall accesses 582system.cpu.icache.overall_mshr_miss_rate::total 0.000154 # mshr miss rate for overall accesses 583system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9647.497880 # average ReadReq mshr miss latency 584system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9647.497880 # average ReadReq mshr miss latency 585system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9647.497880 # average overall mshr miss latency 586system.cpu.icache.demand_avg_mshr_miss_latency::total 9647.497880 # average overall mshr miss latency 587system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9647.497880 # average overall mshr miss latency 588system.cpu.icache.overall_avg_mshr_miss_latency::total 9647.497880 # average overall mshr miss latency 589system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 590system.cpu.dcache.replacements 1187152 # number of replacements 591system.cpu.dcache.tagsinuse 4054.331998 # Cycle average of tags in use 592system.cpu.dcache.total_refs 194883287 # Total number of references to valid blocks. 593system.cpu.dcache.sampled_refs 1191248 # Sample count of references to valid blocks. 594system.cpu.dcache.avg_refs 163.595899 # Average number of references to valid blocks. 595system.cpu.dcache.warmup_cycle 4629867000 # Cycle when the warmup percentage was hit. 596system.cpu.dcache.occ_blocks::cpu.data 4054.331998 # Average occupied blocks per requestor 597system.cpu.dcache.occ_percent::cpu.data 0.989827 # Average percentage of cache occupancy 598system.cpu.dcache.occ_percent::total 0.989827 # Average percentage of cache occupancy 599system.cpu.dcache.ReadReq_hits::cpu.data 137481946 # number of ReadReq hits 600system.cpu.dcache.ReadReq_hits::total 137481946 # number of ReadReq hits 601system.cpu.dcache.WriteReq_hits::cpu.data 52936216 # number of WriteReq hits 602system.cpu.dcache.WriteReq_hits::total 52936216 # number of WriteReq hits 603system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233002 # number of LoadLockedReq hits 604system.cpu.dcache.LoadLockedReq_hits::total 2233002 # number of LoadLockedReq hits 605system.cpu.dcache.StoreCondReq_hits::cpu.data 2232026 # number of StoreCondReq hits 606system.cpu.dcache.StoreCondReq_hits::total 2232026 # number of StoreCondReq hits 607system.cpu.dcache.demand_hits::cpu.data 190418162 # number of demand (read+write) hits 608system.cpu.dcache.demand_hits::total 190418162 # number of demand (read+write) hits 609system.cpu.dcache.overall_hits::cpu.data 190418162 # number of overall hits 610system.cpu.dcache.overall_hits::total 190418162 # number of overall hits 611system.cpu.dcache.ReadReq_misses::cpu.data 1200073 # number of ReadReq misses 612system.cpu.dcache.ReadReq_misses::total 1200073 # number of ReadReq misses 613system.cpu.dcache.WriteReq_misses::cpu.data 1303090 # number of WriteReq misses 614system.cpu.dcache.WriteReq_misses::total 1303090 # number of WriteReq misses 615system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses 616system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses 617system.cpu.dcache.demand_misses::cpu.data 2503163 # number of demand (read+write) misses 618system.cpu.dcache.demand_misses::total 2503163 # number of demand (read+write) misses 619system.cpu.dcache.overall_misses::cpu.data 2503163 # number of overall misses 620system.cpu.dcache.overall_misses::total 2503163 # number of overall misses 621system.cpu.dcache.ReadReq_miss_latency::cpu.data 10102287000 # number of ReadReq miss cycles 622system.cpu.dcache.ReadReq_miss_latency::total 10102287000 # number of ReadReq miss cycles 623system.cpu.dcache.WriteReq_miss_latency::cpu.data 23193721000 # number of WriteReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::total 23193721000 # number of WriteReq miss cycles 625system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 570000 # number of LoadLockedReq miss cycles 626system.cpu.dcache.LoadLockedReq_miss_latency::total 570000 # number of LoadLockedReq miss cycles 627system.cpu.dcache.demand_miss_latency::cpu.data 33296008000 # number of demand (read+write) miss cycles 628system.cpu.dcache.demand_miss_latency::total 33296008000 # number of demand (read+write) miss cycles 629system.cpu.dcache.overall_miss_latency::cpu.data 33296008000 # number of overall miss cycles 630system.cpu.dcache.overall_miss_latency::total 33296008000 # number of overall miss cycles 631system.cpu.dcache.ReadReq_accesses::cpu.data 138682019 # number of ReadReq accesses(hits+misses) 632system.cpu.dcache.ReadReq_accesses::total 138682019 # number of ReadReq accesses(hits+misses) 633system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 634system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 635system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233044 # number of LoadLockedReq accesses(hits+misses) 636system.cpu.dcache.LoadLockedReq_accesses::total 2233044 # number of LoadLockedReq accesses(hits+misses) 637system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232026 # number of StoreCondReq accesses(hits+misses) 638system.cpu.dcache.StoreCondReq_accesses::total 2232026 # number of StoreCondReq accesses(hits+misses) 639system.cpu.dcache.demand_accesses::cpu.data 192921325 # number of demand (read+write) accesses 640system.cpu.dcache.demand_accesses::total 192921325 # number of demand (read+write) accesses 641system.cpu.dcache.overall_accesses::cpu.data 192921325 # number of overall (read+write) accesses 642system.cpu.dcache.overall_accesses::total 192921325 # number of overall (read+write) accesses 643system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008653 # miss rate for ReadReq accesses 644system.cpu.dcache.ReadReq_miss_rate::total 0.008653 # miss rate for ReadReq accesses 645system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024025 # miss rate for WriteReq accesses 646system.cpu.dcache.WriteReq_miss_rate::total 0.024025 # miss rate for WriteReq accesses 647system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000019 # miss rate for LoadLockedReq accesses 648system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000019 # miss rate for LoadLockedReq accesses 649system.cpu.dcache.demand_miss_rate::cpu.data 0.012975 # miss rate for demand accesses 650system.cpu.dcache.demand_miss_rate::total 0.012975 # miss rate for demand accesses 651system.cpu.dcache.overall_miss_rate::cpu.data 0.012975 # miss rate for overall accesses 652system.cpu.dcache.overall_miss_rate::total 0.012975 # miss rate for overall accesses 653system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8418.060401 # average ReadReq miss latency 654system.cpu.dcache.ReadReq_avg_miss_latency::total 8418.060401 # average ReadReq miss latency 655system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17799.016952 # average WriteReq miss latency 656system.cpu.dcache.WriteReq_avg_miss_latency::total 17799.016952 # average WriteReq miss latency 657system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13571.428571 # average LoadLockedReq miss latency 658system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13571.428571 # average LoadLockedReq miss latency 659system.cpu.dcache.demand_avg_miss_latency::cpu.data 13301.574049 # average overall miss latency 660system.cpu.dcache.demand_avg_miss_latency::total 13301.574049 # average overall miss latency 661system.cpu.dcache.overall_avg_miss_latency::cpu.data 13301.574049 # average overall miss latency 662system.cpu.dcache.overall_avg_miss_latency::total 13301.574049 # average overall miss latency 663system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 664system.cpu.dcache.blocked_cycles::no_targets 2849 # number of cycles access was blocked 665system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 666system.cpu.dcache.blocked::no_targets 85 # number of cycles access was blocked 667system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 668system.cpu.dcache.avg_blocked_cycles::no_targets 33.517647 # average number of cycles each access was blocked 669system.cpu.dcache.fast_writes 0 # number of fast writes performed 670system.cpu.dcache.cache_copies 0 # number of cache copies performed 671system.cpu.dcache.writebacks::writebacks 1101655 # number of writebacks 672system.cpu.dcache.writebacks::total 1101655 # number of writebacks 673system.cpu.dcache.ReadReq_mshr_hits::cpu.data 356968 # number of ReadReq MSHR hits 674system.cpu.dcache.ReadReq_mshr_hits::total 356968 # number of ReadReq MSHR hits 675system.cpu.dcache.WriteReq_mshr_hits::cpu.data 954898 # number of WriteReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::total 954898 # number of WriteReq MSHR hits 677system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits 678system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits 679system.cpu.dcache.demand_mshr_hits::cpu.data 1311866 # number of demand (read+write) MSHR hits 680system.cpu.dcache.demand_mshr_hits::total 1311866 # number of demand (read+write) MSHR hits 681system.cpu.dcache.overall_mshr_hits::cpu.data 1311866 # number of overall MSHR hits 682system.cpu.dcache.overall_mshr_hits::total 1311866 # number of overall MSHR hits 683system.cpu.dcache.ReadReq_mshr_misses::cpu.data 843105 # number of ReadReq MSHR misses 684system.cpu.dcache.ReadReq_mshr_misses::total 843105 # number of ReadReq MSHR misses 685system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348192 # number of WriteReq MSHR misses 686system.cpu.dcache.WriteReq_mshr_misses::total 348192 # number of WriteReq MSHR misses 687system.cpu.dcache.demand_mshr_misses::cpu.data 1191297 # number of demand (read+write) MSHR misses 688system.cpu.dcache.demand_mshr_misses::total 1191297 # number of demand (read+write) MSHR misses 689system.cpu.dcache.overall_mshr_misses::cpu.data 1191297 # number of overall MSHR misses 690system.cpu.dcache.overall_mshr_misses::total 1191297 # number of overall MSHR misses 691system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3721993000 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.ReadReq_mshr_miss_latency::total 3721993000 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3861767000 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::total 3861767000 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7583760000 # number of demand (read+write) MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::total 7583760000 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7583760000 # number of overall MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::total 7583760000 # number of overall MSHR miss cycles 699system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006079 # mshr miss rate for ReadReq accesses 700system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006079 # mshr miss rate for ReadReq accesses 701system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006420 # mshr miss rate for WriteReq accesses 702system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006420 # mshr miss rate for WriteReq accesses 703system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006175 # mshr miss rate for demand accesses 704system.cpu.dcache.demand_mshr_miss_rate::total 0.006175 # mshr miss rate for demand accesses 705system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006175 # mshr miss rate for overall accesses 706system.cpu.dcache.overall_mshr_miss_rate::total 0.006175 # mshr miss rate for overall accesses 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4414.625699 # average ReadReq mshr miss latency 708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4414.625699 # average ReadReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11090.912485 # average WriteReq mshr miss latency 710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 11090.912485 # average WriteReq mshr miss latency 711system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 6365.969192 # average overall mshr miss latency 712system.cpu.dcache.demand_avg_mshr_miss_latency::total 6365.969192 # average overall mshr miss latency 713system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 6365.969192 # average overall mshr miss latency 714system.cpu.dcache.overall_avg_mshr_miss_latency::total 6365.969192 # average overall mshr miss latency 715system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 716system.cpu.l2cache.replacements 128756 # number of replacements 717system.cpu.l2cache.tagsinuse 26481.749428 # Cycle average of tags in use 718system.cpu.l2cache.total_refs 1725200 # Total number of references to valid blocks. 719system.cpu.l2cache.sampled_refs 159985 # Sample count of references to valid blocks. 720system.cpu.l2cache.avg_refs 10.783511 # Average number of references to valid blocks. 721system.cpu.l2cache.warmup_cycle 105019230500 # Cycle when the warmup percentage was hit. 722system.cpu.l2cache.occ_blocks::writebacks 22651.783337 # Average occupied blocks per requestor 723system.cpu.l2cache.occ_blocks::cpu.inst 310.174210 # Average occupied blocks per requestor 724system.cpu.l2cache.occ_blocks::cpu.data 3519.791881 # Average occupied blocks per requestor 725system.cpu.l2cache.occ_percent::writebacks 0.691278 # Average percentage of cache occupancy 726system.cpu.l2cache.occ_percent::cpu.inst 0.009466 # Average percentage of cache occupancy 727system.cpu.l2cache.occ_percent::cpu.data 0.107416 # Average percentage of cache occupancy 728system.cpu.l2cache.occ_percent::total 0.808159 # Average percentage of cache occupancy 729system.cpu.l2cache.ReadReq_hits::cpu.inst 14188 # number of ReadReq hits 730system.cpu.l2cache.ReadReq_hits::cpu.data 789496 # number of ReadReq hits 731system.cpu.l2cache.ReadReq_hits::total 803684 # number of ReadReq hits 732system.cpu.l2cache.Writeback_hits::writebacks 1101655 # number of Writeback hits 733system.cpu.l2cache.Writeback_hits::total 1101655 # number of Writeback hits 734system.cpu.l2cache.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits 735system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits 736system.cpu.l2cache.ReadExReq_hits::cpu.data 245235 # number of ReadExReq hits 737system.cpu.l2cache.ReadExReq_hits::total 245235 # number of ReadExReq hits 738system.cpu.l2cache.demand_hits::cpu.inst 14188 # number of demand (read+write) hits 739system.cpu.l2cache.demand_hits::cpu.data 1034731 # number of demand (read+write) hits 740system.cpu.l2cache.demand_hits::total 1048919 # number of demand (read+write) hits 741system.cpu.l2cache.overall_hits::cpu.inst 14188 # number of overall hits 742system.cpu.l2cache.overall_hits::cpu.data 1034731 # number of overall hits 743system.cpu.l2cache.overall_hits::total 1048919 # number of overall hits 744system.cpu.l2cache.ReadReq_misses::cpu.inst 3445 # number of ReadReq misses 745system.cpu.l2cache.ReadReq_misses::cpu.data 53061 # number of ReadReq misses 746system.cpu.l2cache.ReadReq_misses::total 56506 # number of ReadReq misses 747system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses 748system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses 749system.cpu.l2cache.ReadExReq_misses::cpu.data 103456 # number of ReadExReq misses 750system.cpu.l2cache.ReadExReq_misses::total 103456 # number of ReadExReq misses 751system.cpu.l2cache.demand_misses::cpu.inst 3445 # number of demand (read+write) misses 752system.cpu.l2cache.demand_misses::cpu.data 156517 # number of demand (read+write) misses 753system.cpu.l2cache.demand_misses::total 159962 # number of demand (read+write) misses 754system.cpu.l2cache.overall_misses::cpu.inst 3445 # number of overall misses 755system.cpu.l2cache.overall_misses::cpu.data 156517 # number of overall misses 756system.cpu.l2cache.overall_misses::total 159962 # number of overall misses 757system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 138047000 # number of ReadReq miss cycles 758system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2057062000 # number of ReadReq miss cycles 759system.cpu.l2cache.ReadReq_miss_latency::total 2195109000 # number of ReadReq miss cycles 760system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 4500 # number of UpgradeReq miss cycles 761system.cpu.l2cache.UpgradeReq_miss_latency::total 4500 # number of UpgradeReq miss cycles 762system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3269316500 # number of ReadExReq miss cycles 763system.cpu.l2cache.ReadExReq_miss_latency::total 3269316500 # number of ReadExReq miss cycles 764system.cpu.l2cache.demand_miss_latency::cpu.inst 138047000 # number of demand (read+write) miss cycles 765system.cpu.l2cache.demand_miss_latency::cpu.data 5326378500 # number of demand (read+write) miss cycles 766system.cpu.l2cache.demand_miss_latency::total 5464425500 # number of demand (read+write) miss cycles 767system.cpu.l2cache.overall_miss_latency::cpu.inst 138047000 # number of overall miss cycles 768system.cpu.l2cache.overall_miss_latency::cpu.data 5326378500 # number of overall miss cycles 769system.cpu.l2cache.overall_miss_latency::total 5464425500 # number of overall miss cycles 770system.cpu.l2cache.ReadReq_accesses::cpu.inst 17633 # number of ReadReq accesses(hits+misses) 771system.cpu.l2cache.ReadReq_accesses::cpu.data 842557 # number of ReadReq accesses(hits+misses) 772system.cpu.l2cache.ReadReq_accesses::total 860190 # number of ReadReq accesses(hits+misses) 773system.cpu.l2cache.Writeback_accesses::writebacks 1101655 # number of Writeback accesses(hits+misses) 774system.cpu.l2cache.Writeback_accesses::total 1101655 # number of Writeback accesses(hits+misses) 775system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49 # number of UpgradeReq accesses(hits+misses) 776system.cpu.l2cache.UpgradeReq_accesses::total 49 # number of UpgradeReq accesses(hits+misses) 777system.cpu.l2cache.ReadExReq_accesses::cpu.data 348691 # number of ReadExReq accesses(hits+misses) 778system.cpu.l2cache.ReadExReq_accesses::total 348691 # number of ReadExReq accesses(hits+misses) 779system.cpu.l2cache.demand_accesses::cpu.inst 17633 # number of demand (read+write) accesses 780system.cpu.l2cache.demand_accesses::cpu.data 1191248 # number of demand (read+write) accesses 781system.cpu.l2cache.demand_accesses::total 1208881 # number of demand (read+write) accesses 782system.cpu.l2cache.overall_accesses::cpu.inst 17633 # number of overall (read+write) accesses 783system.cpu.l2cache.overall_accesses::cpu.data 1191248 # number of overall (read+write) accesses 784system.cpu.l2cache.overall_accesses::total 1208881 # number of overall (read+write) accesses 785system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.195372 # miss rate for ReadReq accesses 786system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062976 # miss rate for ReadReq accesses 787system.cpu.l2cache.ReadReq_miss_rate::total 0.065690 # miss rate for ReadReq accesses 788system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.081633 # miss rate for UpgradeReq accesses 789system.cpu.l2cache.UpgradeReq_miss_rate::total 0.081633 # miss rate for UpgradeReq accesses 790system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.296698 # miss rate for ReadExReq accesses 791system.cpu.l2cache.ReadExReq_miss_rate::total 0.296698 # miss rate for ReadExReq accesses 792system.cpu.l2cache.demand_miss_rate::cpu.inst 0.195372 # miss rate for demand accesses 793system.cpu.l2cache.demand_miss_rate::cpu.data 0.131389 # miss rate for demand accesses 794system.cpu.l2cache.demand_miss_rate::total 0.132322 # miss rate for demand accesses 795system.cpu.l2cache.overall_miss_rate::cpu.inst 0.195372 # miss rate for overall accesses 796system.cpu.l2cache.overall_miss_rate::cpu.data 0.131389 # miss rate for overall accesses 797system.cpu.l2cache.overall_miss_rate::total 0.132322 # miss rate for overall accesses 798system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 40071.698113 # average ReadReq miss latency 799system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38767.870941 # average ReadReq miss latency 800system.cpu.l2cache.ReadReq_avg_miss_latency::total 38847.361342 # average ReadReq miss latency 801system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1125 # average UpgradeReq miss latency 802system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1125 # average UpgradeReq miss latency 803system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 31601.033290 # average ReadExReq miss latency 804system.cpu.l2cache.ReadExReq_avg_miss_latency::total 31601.033290 # average ReadExReq miss latency 805system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 40071.698113 # average overall miss latency 806system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34030.670790 # average overall miss latency 807system.cpu.l2cache.demand_avg_miss_latency::total 34160.772558 # average overall miss latency 808system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 40071.698113 # average overall miss latency 809system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34030.670790 # average overall miss latency 810system.cpu.l2cache.overall_avg_miss_latency::total 34160.772558 # average overall miss latency 811system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 812system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 813system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 814system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 815system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 816system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 817system.cpu.l2cache.fast_writes 0 # number of fast writes performed 818system.cpu.l2cache.cache_copies 0 # number of cache copies performed 819system.cpu.l2cache.writebacks::writebacks 104385 # number of writebacks 820system.cpu.l2cache.writebacks::total 104385 # number of writebacks 821system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits 822system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits 823system.cpu.l2cache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits 824system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits 825system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 826system.cpu.l2cache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits 827system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits 828system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 829system.cpu.l2cache.overall_mshr_hits::total 31 # number of overall MSHR hits 830system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3435 # number of ReadReq MSHR misses 831system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53040 # number of ReadReq MSHR misses 832system.cpu.l2cache.ReadReq_mshr_misses::total 56475 # number of ReadReq MSHR misses 833system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses 834system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses 835system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103456 # number of ReadExReq MSHR misses 836system.cpu.l2cache.ReadExReq_mshr_misses::total 103456 # number of ReadExReq MSHR misses 837system.cpu.l2cache.demand_mshr_misses::cpu.inst 3435 # number of demand (read+write) MSHR misses 838system.cpu.l2cache.demand_mshr_misses::cpu.data 156496 # number of demand (read+write) MSHR misses 839system.cpu.l2cache.demand_mshr_misses::total 159931 # number of demand (read+write) MSHR misses 840system.cpu.l2cache.overall_mshr_misses::cpu.inst 3435 # number of overall MSHR misses 841system.cpu.l2cache.overall_mshr_misses::cpu.data 156496 # number of overall MSHR misses 842system.cpu.l2cache.overall_mshr_misses::total 159931 # number of overall MSHR misses 843system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 125122230 # number of ReadReq MSHR miss cycles 844system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1856378132 # number of ReadReq MSHR miss cycles 845system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1981500362 # number of ReadReq MSHR miss cycles 846system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4004 # number of UpgradeReq MSHR miss cycles 847system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4004 # number of UpgradeReq MSHR miss cycles 848system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2883433623 # number of ReadExReq MSHR miss cycles 849system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2883433623 # number of ReadExReq MSHR miss cycles 850system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 125122230 # number of demand (read+write) MSHR miss cycles 851system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4739811755 # number of demand (read+write) MSHR miss cycles 852system.cpu.l2cache.demand_mshr_miss_latency::total 4864933985 # number of demand (read+write) MSHR miss cycles 853system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 125122230 # number of overall MSHR miss cycles 854system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4739811755 # number of overall MSHR miss cycles 855system.cpu.l2cache.overall_mshr_miss_latency::total 4864933985 # number of overall MSHR miss cycles 856system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194805 # mshr miss rate for ReadReq accesses 857system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.062951 # mshr miss rate for ReadReq accesses 858system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065654 # mshr miss rate for ReadReq accesses 859system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for UpgradeReq accesses 860system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.081633 # mshr miss rate for UpgradeReq accesses 861system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.296698 # mshr miss rate for ReadExReq accesses 862system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.296698 # mshr miss rate for ReadExReq accesses 863system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194805 # mshr miss rate for demand accesses 864system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131371 # mshr miss rate for demand accesses 865system.cpu.l2cache.demand_mshr_miss_rate::total 0.132297 # mshr miss rate for demand accesses 866system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194805 # mshr miss rate for overall accesses 867system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131371 # mshr miss rate for overall accesses 868system.cpu.l2cache.overall_mshr_miss_rate::total 0.132297 # mshr miss rate for overall accesses 869system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36425.685590 # average ReadReq mshr miss latency 870system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34999.587707 # average ReadReq mshr miss latency 871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35086.327791 # average ReadReq mshr miss latency 872system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency 873system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency 874system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 27871.110646 # average ReadExReq mshr miss latency 875system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 27871.110646 # average ReadExReq mshr miss latency 876system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36425.685590 # average overall mshr miss latency 877system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 30287.111204 # average overall mshr miss latency 878system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30418.955581 # average overall mshr miss latency 879system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36425.685590 # average overall mshr miss latency 880system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 30287.111204 # average overall mshr miss latency 881system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30418.955581 # average overall mshr miss latency 882system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 883 884---------- End Simulation Statistics ---------- 885