config.ini revision 8835
15729SN/A[root]
25729SN/Atype=Root
35729SN/Achildren=system
48835SAli.Saidi@ARM.comfull_system=false
57873SN/Atime_sync_enable=false
67873SN/Atime_sync_period=100000000000
77873SN/Atime_sync_spin_threshold=100000000
85729SN/A
95729SN/A[system]
105729SN/Atype=System
115729SN/Achildren=cpu membus physmem
128835SAli.Saidi@ARM.comboot_osflags=a
138835SAli.Saidi@ARM.cominit_param=0
148835SAli.Saidi@ARM.comkernel=
158835SAli.Saidi@ARM.comload_addr_mask=1099511627775
165729SN/Amem_mode=atomic
178673SN/Amemories=system.physmem
188721SN/Anum_work_ids=16
198835SAli.Saidi@ARM.comphysmem=system.physmem
208835SAli.Saidi@ARM.comreadfile=
217935SN/Asymbolfile=
227935SN/Awork_begin_ckpt_count=0
237935SN/Awork_begin_cpu_id_exit=-1
247935SN/Awork_begin_exit_count=0
257935SN/Awork_cpus_ckpt_count=0
267935SN/Awork_end_ckpt_count=0
277935SN/Awork_end_exit_count=0
288983Snate@binkert.orgwork_item_id=-1
295729SN/Asystem_port=system.membus.port[0]
305729SN/A
315729SN/A[system.cpu]
328835SAli.Saidi@ARM.comtype=DerivO3CPU
335876SN/Achildren=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
345729SN/ABTBEntries=4096
355729SN/ABTBTagSize=16
365729SN/ALFSTSize=1024
375876SN/ALQEntries=32
388835SAli.Saidi@ARM.comLSQCheckLoads=true
395876SN/ALSQDepCheckShift=4
405729SN/ARASSize=16
415729SN/ASQEntries=32
425729SN/ASSITSize=1024
438835SAli.Saidi@ARM.comactivity=0
445729SN/AbackComSize=5
455729SN/AcachePorts=200
465729SN/Achecker=Null
475729SN/AchoiceCtrBits=2
485729SN/AchoicePredictorSize=8192
495729SN/Aclock=500
505729SN/AcommitToDecodeDelay=1
518835SAli.Saidi@ARM.comcommitToFetchDelay=1
525729SN/AcommitToIEWDelay=1
535729SN/AcommitToRenameDelay=1
545729SN/AcommitWidth=8
555729SN/Acpu_id=0
565729SN/AdecodeToFetchDelay=1
575729SN/AdecodeToRenameDelay=1
585729SN/AdecodeWidth=8
595729SN/Adefer_registration=false
605729SN/AdispatchWidth=8
618983Snate@binkert.orgdo_checkpoint_insts=true
625729SN/Ado_quiesce=true
635729SN/Ado_statistics_insts=true
646123SN/Adtb=system.cpu.dtb
655729SN/AfetchToDecodeDelay=1
668241SN/AfetchTrapLatency=1
675729SN/AfetchWidth=8
685729SN/AforwardComSize=5
695729SN/AfuPool=system.cpu.fuPool
705876SN/Afunction_trace=false
718835SAli.Saidi@ARM.comfunction_trace_start=0
725729SN/AglobalCtrBits=2
735729SN/AglobalHistoryBits=13
745729SN/AglobalPredictorSize=8192
755729SN/AiewToCommitDelay=1
768835SAli.Saidi@ARM.comiewToDecodeDelay=1
775729SN/AiewToFetchDelay=1
785729SN/AiewToRenameDelay=1
795729SN/AinstShiftAmt=2
805729SN/Ainterrupts=system.cpu.interrupts
815729SN/AissueToExecuteDelay=1
828983Snate@binkert.orgissueWidth=8
835729SN/Aitb=system.cpu.itb
845729SN/AlocalCtrBits=2
856024SN/AlocalHistoryBits=11
868835SAli.Saidi@ARM.comlocalHistoryTableSize=2048
875729SN/AlocalPredictorSize=2048
888835SAli.Saidi@ARM.commax_insts_all_threads=0
898835SAli.Saidi@ARM.commax_insts_any_thread=0
908835SAli.Saidi@ARM.commax_loads_all_threads=0
918835SAli.Saidi@ARM.commax_loads_any_thread=0
928835SAli.Saidi@ARM.comneedsTSO=false
938983Snate@binkert.orgnumIQEntries=64
945729SN/AnumPhysFloatRegs=256
955729SN/AnumPhysIntRegs=256
965729SN/AnumROBEntries=192
978983Snate@binkert.orgnumRobs=1
985729SN/AnumThreads=1
995729SN/Aphase=0
1006123SN/ApredType=tournament
1015729SN/Aprofile=0
1028241SN/Aprogress_interval=0
1035729SN/ArenameToDecodeDelay=1
1045729SN/ArenameToFetchDelay=1
1055729SN/ArenameToIEWDelay=2
1065876SN/ArenameToROBDelay=1
1078835SAli.Saidi@ARM.comrenameWidth=8
1085729SN/AsmtCommitPolicy=RoundRobin
1095729SN/AsmtFetchPolicy=SingleThread
1105729SN/AsmtIQPolicy=Partitioned
1115729SN/AsmtIQThreshold=100
1128835SAli.Saidi@ARM.comsmtLSQPolicy=Partitioned
1135729SN/AsmtLSQThreshold=100
1145729SN/AsmtNumFetchingThreads=1
1155729SN/AsmtROBPolicy=Partitioned
1165729SN/AsmtROBThreshold=100
1175729SN/AsquashWidth=8
1188983Snate@binkert.orgstore_set_clear_period=250000
1195729SN/Asystem=system
1208835SAli.Saidi@ARM.comtracer=system.cpu.tracer
1218835SAli.Saidi@ARM.comtrapLatency=13
1228835SAli.Saidi@ARM.comwbDepth=1
1238835SAli.Saidi@ARM.comwbWidth=8
1248835SAli.Saidi@ARM.comworkload=system.cpu.workload
1258835SAli.Saidi@ARM.comdcache_port=system.cpu.dcache.cpu_side
1268983Snate@binkert.orgicache_port=system.cpu.icache.cpu_side
1278983Snate@binkert.org
1288983Snate@binkert.org[system.cpu.dcache]
1298835SAli.Saidi@ARM.comtype=BaseCache
1305729SN/Aaddr_range=0:18446744073709551615
1316024SN/Aassoc=2
1328835SAli.Saidi@ARM.comblock_size=64
1335729SN/Aforward_snoops=true
1348835SAli.Saidi@ARM.comhash_delay=1
1358835SAli.Saidi@ARM.comis_top_level=true
1368835SAli.Saidi@ARM.comlatency=1000
1378835SAli.Saidi@ARM.commax_miss_count=0
1388835SAli.Saidi@ARM.commshrs=10
1398983Snate@binkert.orgprefetch_on_access=false
1405729SN/Aprefetcher=Null
1415729SN/AprioritizeRequests=false
1425729SN/Arepl=Null
1438983Snate@binkert.orgsize=262144
1445729SN/Asubblock_size=0
1455729SN/Asystem=system
1466123SN/Atgts_per_mshr=20
1475729SN/Atrace_addr=0
1488241SN/Atwo_queue=false
1495729SN/Awrite_buffers=8
1505729SN/Acpu_side=system.cpu.dcache_port
1515729SN/Amem_side=system.cpu.toL2Bus.port[1]
1525876SN/A
1538835SAli.Saidi@ARM.com[system.cpu.dtb]
1545729SN/Atype=ArmTLB
1555729SN/Achildren=walker
1565729SN/Asize=64
1575729SN/Awalker=system.cpu.dtb.walker
1588835SAli.Saidi@ARM.com
1595729SN/A[system.cpu.dtb.walker]
1605729SN/Atype=ArmTableWalker
1615729SN/Amax_backoff=100000
1625729SN/Amin_backoff=0
1638983Snate@binkert.orgsys=system
1648983Snate@binkert.orgport=system.cpu.toL2Bus.port[3]
1655729SN/A
1665729SN/A[system.cpu.fuPool]
1679039Sgblack@eecs.umich.edutype=FUPool
1685729SN/Achildren=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1695729SN/AFUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
1705729SN/A
1717524SN/A[system.cpu.fuPool.FUList0]
1729096Sandreas.hansson@arm.comtype=FUDesc
1738983Snate@binkert.orgchildren=opList
1748983Snate@binkert.orgcount=6
1755729SN/AopList=system.cpu.fuPool.FUList0.opList
1765729SN/A
1775729SN/A[system.cpu.fuPool.FUList0.opList]
1785729SN/Atype=OpDesc
1795729SN/AissueLat=1
1805729SN/AopClass=IntAlu
1815729SN/AopLat=1
1829079SAli.Saidi@ARM.com
1835729SN/A[system.cpu.fuPool.FUList1]
1845729SN/Atype=FUDesc
1855729SN/Achildren=opList0 opList1
1865729SN/Acount=2
1879039Sgblack@eecs.umich.eduopList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
1885729SN/A
1899039Sgblack@eecs.umich.edu[system.cpu.fuPool.FUList1.opList0]
1905729SN/Atype=OpDesc
1915729SN/AissueLat=1
1925729SN/AopClass=IntMult
1935729SN/AopLat=3
1945729SN/A
1955729SN/A[system.cpu.fuPool.FUList1.opList1]
1965729SN/Atype=OpDesc
1975729SN/AissueLat=19
1985729SN/AopClass=IntDiv
1999039Sgblack@eecs.umich.eduopLat=20
2005729SN/A
2015729SN/A[system.cpu.fuPool.FUList2]
2025729SN/Atype=FUDesc
2037524SN/Achildren=opList0 opList1 opList2
2049096Sandreas.hansson@arm.comcount=4
2058983Snate@binkert.orgopList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
2068983Snate@binkert.org
2075729SN/A[system.cpu.fuPool.FUList2.opList0]
2085729SN/Atype=OpDesc
2098983Snate@binkert.orgissueLat=1
2108983Snate@binkert.orgopClass=FloatAdd
2115729SN/AopLat=2
2128983Snate@binkert.org
2135729SN/A[system.cpu.fuPool.FUList2.opList1]
2145729SN/Atype=OpDesc
2155729SN/AissueLat=1
2165729SN/AopClass=FloatCmp
2175729SN/AopLat=2
2188983Snate@binkert.org
2195729SN/A[system.cpu.fuPool.FUList2.opList2]
220type=OpDesc
221issueLat=1
222opClass=FloatCvt
223opLat=2
224
225[system.cpu.fuPool.FUList3]
226type=FUDesc
227children=opList0 opList1 opList2
228count=2
229opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
230
231[system.cpu.fuPool.FUList3.opList0]
232type=OpDesc
233issueLat=1
234opClass=FloatMult
235opLat=4
236
237[system.cpu.fuPool.FUList3.opList1]
238type=OpDesc
239issueLat=12
240opClass=FloatDiv
241opLat=12
242
243[system.cpu.fuPool.FUList3.opList2]
244type=OpDesc
245issueLat=24
246opClass=FloatSqrt
247opLat=24
248
249[system.cpu.fuPool.FUList4]
250type=FUDesc
251children=opList
252count=0
253opList=system.cpu.fuPool.FUList4.opList
254
255[system.cpu.fuPool.FUList4.opList]
256type=OpDesc
257issueLat=1
258opClass=MemRead
259opLat=1
260
261[system.cpu.fuPool.FUList5]
262type=FUDesc
263children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
264count=4
265opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
266
267[system.cpu.fuPool.FUList5.opList00]
268type=OpDesc
269issueLat=1
270opClass=SimdAdd
271opLat=1
272
273[system.cpu.fuPool.FUList5.opList01]
274type=OpDesc
275issueLat=1
276opClass=SimdAddAcc
277opLat=1
278
279[system.cpu.fuPool.FUList5.opList02]
280type=OpDesc
281issueLat=1
282opClass=SimdAlu
283opLat=1
284
285[system.cpu.fuPool.FUList5.opList03]
286type=OpDesc
287issueLat=1
288opClass=SimdCmp
289opLat=1
290
291[system.cpu.fuPool.FUList5.opList04]
292type=OpDesc
293issueLat=1
294opClass=SimdCvt
295opLat=1
296
297[system.cpu.fuPool.FUList5.opList05]
298type=OpDesc
299issueLat=1
300opClass=SimdMisc
301opLat=1
302
303[system.cpu.fuPool.FUList5.opList06]
304type=OpDesc
305issueLat=1
306opClass=SimdMult
307opLat=1
308
309[system.cpu.fuPool.FUList5.opList07]
310type=OpDesc
311issueLat=1
312opClass=SimdMultAcc
313opLat=1
314
315[system.cpu.fuPool.FUList5.opList08]
316type=OpDesc
317issueLat=1
318opClass=SimdShift
319opLat=1
320
321[system.cpu.fuPool.FUList5.opList09]
322type=OpDesc
323issueLat=1
324opClass=SimdShiftAcc
325opLat=1
326
327[system.cpu.fuPool.FUList5.opList10]
328type=OpDesc
329issueLat=1
330opClass=SimdSqrt
331opLat=1
332
333[system.cpu.fuPool.FUList5.opList11]
334type=OpDesc
335issueLat=1
336opClass=SimdFloatAdd
337opLat=1
338
339[system.cpu.fuPool.FUList5.opList12]
340type=OpDesc
341issueLat=1
342opClass=SimdFloatAlu
343opLat=1
344
345[system.cpu.fuPool.FUList5.opList13]
346type=OpDesc
347issueLat=1
348opClass=SimdFloatCmp
349opLat=1
350
351[system.cpu.fuPool.FUList5.opList14]
352type=OpDesc
353issueLat=1
354opClass=SimdFloatCvt
355opLat=1
356
357[system.cpu.fuPool.FUList5.opList15]
358type=OpDesc
359issueLat=1
360opClass=SimdFloatDiv
361opLat=1
362
363[system.cpu.fuPool.FUList5.opList16]
364type=OpDesc
365issueLat=1
366opClass=SimdFloatMisc
367opLat=1
368
369[system.cpu.fuPool.FUList5.opList17]
370type=OpDesc
371issueLat=1
372opClass=SimdFloatMult
373opLat=1
374
375[system.cpu.fuPool.FUList5.opList18]
376type=OpDesc
377issueLat=1
378opClass=SimdFloatMultAcc
379opLat=1
380
381[system.cpu.fuPool.FUList5.opList19]
382type=OpDesc
383issueLat=1
384opClass=SimdFloatSqrt
385opLat=1
386
387[system.cpu.fuPool.FUList6]
388type=FUDesc
389children=opList
390count=0
391opList=system.cpu.fuPool.FUList6.opList
392
393[system.cpu.fuPool.FUList6.opList]
394type=OpDesc
395issueLat=1
396opClass=MemWrite
397opLat=1
398
399[system.cpu.fuPool.FUList7]
400type=FUDesc
401children=opList0 opList1
402count=4
403opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
404
405[system.cpu.fuPool.FUList7.opList0]
406type=OpDesc
407issueLat=1
408opClass=MemRead
409opLat=1
410
411[system.cpu.fuPool.FUList7.opList1]
412type=OpDesc
413issueLat=1
414opClass=MemWrite
415opLat=1
416
417[system.cpu.fuPool.FUList8]
418type=FUDesc
419children=opList
420count=1
421opList=system.cpu.fuPool.FUList8.opList
422
423[system.cpu.fuPool.FUList8.opList]
424type=OpDesc
425issueLat=3
426opClass=IprAccess
427opLat=3
428
429[system.cpu.icache]
430type=BaseCache
431addr_range=0:18446744073709551615
432assoc=2
433block_size=64
434forward_snoops=true
435hash_delay=1
436is_top_level=true
437latency=1000
438max_miss_count=0
439mshrs=10
440prefetch_on_access=false
441prefetcher=Null
442prioritizeRequests=false
443repl=Null
444size=131072
445subblock_size=0
446system=system
447tgts_per_mshr=20
448trace_addr=0
449two_queue=false
450write_buffers=8
451cpu_side=system.cpu.icache_port
452mem_side=system.cpu.toL2Bus.port[0]
453
454[system.cpu.interrupts]
455type=ArmInterrupts
456
457[system.cpu.itb]
458type=ArmTLB
459children=walker
460size=64
461walker=system.cpu.itb.walker
462
463[system.cpu.itb.walker]
464type=ArmTableWalker
465max_backoff=100000
466min_backoff=0
467sys=system
468port=system.cpu.toL2Bus.port[2]
469
470[system.cpu.l2cache]
471type=BaseCache
472addr_range=0:18446744073709551615
473assoc=2
474block_size=64
475forward_snoops=true
476hash_delay=1
477is_top_level=false
478latency=1000
479max_miss_count=0
480mshrs=10
481prefetch_on_access=false
482prefetcher=Null
483prioritizeRequests=false
484repl=Null
485size=2097152
486subblock_size=0
487system=system
488tgts_per_mshr=5
489trace_addr=0
490two_queue=false
491write_buffers=8
492cpu_side=system.cpu.toL2Bus.port[4]
493mem_side=system.membus.port[2]
494
495[system.cpu.toL2Bus]
496type=Bus
497block_size=64
498bus_id=0
499clock=1000
500header_cycles=1
501use_default_range=false
502width=64
503port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
504
505[system.cpu.tracer]
506type=ExeTracer
507
508[system.cpu.workload]
509type=LiveProcess
510cmd=parser 2.1.dict -batch
511cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
512egid=100
513env=
514errout=cerr
515euid=100
516executable=/dist/m5/cpu2000/binaries/arm/linux/parser
517gid=100
518input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
519max_stack_size=67108864
520output=cout
521pid=100
522ppid=99
523simpoint=114600000000
524system=system
525uid=100
526
527[system.membus]
528type=Bus
529block_size=64
530bus_id=0
531clock=1000
532header_cycles=1
533use_default_range=false
534width=64
535port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
536
537[system.physmem]
538type=PhysicalMemory
539file=
540latency=30000
541latency_var=0
542null=false
543range=0:134217727
544zero=false
545port=system.membus.port[1]
546
547