config.ini revision 8802:ef66a9083bc4
13558SN/A[root] 23558SN/Atype=Root 33558SN/Achildren=system 43558SN/Atime_sync_enable=false 53558SN/Atime_sync_period=100000000000 63558SN/Atime_sync_spin_threshold=100000000 73558SN/A 83558SN/A[system] 93558SN/Atype=System 103558SN/Achildren=cpu membus physmem 113558SN/Amem_mode=atomic 123558SN/Amemories=system.physmem 133558SN/Anum_work_ids=16 143558SN/Aphysmem=system.physmem 153558SN/Awork_begin_ckpt_count=0 163558SN/Awork_begin_cpu_id_exit=-1 173558SN/Awork_begin_exit_count=0 183558SN/Awork_cpus_ckpt_count=0 193558SN/Awork_end_ckpt_count=0 203558SN/Awork_end_exit_count=0 213558SN/Awork_item_id=-1 223558SN/Asystem_port=system.membus.port[0] 233558SN/A 243558SN/A[system.cpu] 253558SN/Atype=DerivO3CPU 263558SN/Achildren=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 273558SN/ABTBEntries=4096 283558SN/ABTBTagSize=16 293558SN/ALFSTSize=1024 303558SN/ALQEntries=32 313558SN/ALSQCheckLoads=true 323558SN/ALSQDepCheckShift=4 336757SAli.Saidi@ARM.comRASSize=16 346757SAli.Saidi@ARM.comSQEntries=32 356757SAli.Saidi@ARM.comSSITSize=1024 363558SN/Aactivity=0 373558SN/AbackComSize=5 383558SN/AcachePorts=200 393558SN/Achecker=Null 408706Sandreas.hansson@arm.comchoiceCtrBits=2 413558SN/AchoicePredictorSize=8192 423558SN/Aclock=500 433558SN/AcommitToDecodeDelay=1 446757SAli.Saidi@ARM.comcommitToFetchDelay=1 453570SN/AcommitToIEWDelay=1 463570SN/AcommitToRenameDelay=1 473570SN/AcommitWidth=8 483570SN/Acpu_id=0 493570SN/AdecodeToFetchDelay=1 503558SN/AdecodeToRenameDelay=1 518852Sandreas.hansson@arm.comdecodeWidth=8 523558SN/Adefer_registration=false 533570SN/AdispatchWidth=8 543570SN/Ado_checkpoint_insts=true 558852Sandreas.hansson@arm.comdo_statistics_insts=true 563558SN/Adtb=system.cpu.dtb 573570SN/AfetchToDecodeDelay=1 583570SN/AfetchTrapLatency=1 598852Sandreas.hansson@arm.comfetchWidth=8 603558SN/AforwardComSize=5 613570SN/AfuPool=system.cpu.fuPool 623570SN/Afunction_trace=false 638852Sandreas.hansson@arm.comfunction_trace_start=0 643558SN/AglobalCtrBits=2 653570SN/AglobalHistoryBits=13 663570SN/AglobalPredictorSize=8192 678852Sandreas.hansson@arm.comiewToCommitDelay=1 683558SN/AiewToDecodeDelay=1 693570SN/AiewToFetchDelay=1 703570SN/AiewToRenameDelay=1 718852Sandreas.hansson@arm.cominstShiftAmt=2 723558SN/AissueToExecuteDelay=1 733558SN/AissueWidth=8 743570SN/Aitb=system.cpu.itb 753570SN/AlocalCtrBits=2 763570SN/AlocalHistoryBits=11 779069Satgutier@umich.edulocalHistoryTableSize=2048 789069Satgutier@umich.edulocalPredictorSize=2048 799069Satgutier@umich.edumax_insts_all_threads=0 809069Satgutier@umich.edumax_insts_any_thread=0 819069Satgutier@umich.edumax_loads_all_threads=0 829069Satgutier@umich.edumax_loads_any_thread=0 839069Satgutier@umich.edunumIQEntries=64 849069Satgutier@umich.edunumPhysFloatRegs=256 859069Satgutier@umich.edunumPhysIntRegs=256 869069Satgutier@umich.edunumROBEntries=192 873558SN/AnumRobs=1 883558SN/AnumThreads=1 893570SN/Aphase=0 903570SN/ApredType=tournament 913570SN/Aprogress_interval=0 929069Satgutier@umich.edurenameToDecodeDelay=1 939069Satgutier@umich.edurenameToFetchDelay=1 949069Satgutier@umich.edurenameToIEWDelay=2 959069Satgutier@umich.edurenameToROBDelay=1 969069Satgutier@umich.edurenameWidth=8 979069Satgutier@umich.edusmtCommitPolicy=RoundRobin 989069Satgutier@umich.edusmtFetchPolicy=SingleThread 999069Satgutier@umich.edusmtIQPolicy=Partitioned 1009069Satgutier@umich.edusmtIQThreshold=100 1019069Satgutier@umich.edusmtLSQPolicy=Partitioned 1023558SN/AsmtLSQThreshold=100 1033558SN/AsmtNumFetchingThreads=1 1043570SN/AsmtROBPolicy=Partitioned 1053570SN/AsmtROBThreshold=100 1063570SN/AsquashWidth=8 1079069Satgutier@umich.edustore_set_clear_period=250000 1089069Satgutier@umich.edusystem=system 1099069Satgutier@umich.edutracer=system.cpu.tracer 1109069Satgutier@umich.edutrapLatency=13 1119069Satgutier@umich.eduwbDepth=1 1129069Satgutier@umich.eduwbWidth=8 1139069Satgutier@umich.eduworkload=system.cpu.workload 1149069Satgutier@umich.edudcache_port=system.cpu.dcache.cpu_side 1159069Satgutier@umich.eduicache_port=system.cpu.icache.cpu_side 1169069Satgutier@umich.edu 1173570SN/A[system.cpu.dcache] 1183558SN/Atype=BaseCache 1193570SN/Aaddr_range=0:18446744073709551615 1203570SN/Aassoc=2 1213570SN/Ablock_size=64 1223570SN/Aforward_snoops=true 1233570SN/Ahash_delay=1 1243570SN/Ais_top_level=true 1253570SN/Alatency=1000 1263570SN/Amax_miss_count=0 1273570SN/Amshrs=10 1283570SN/Anum_cpus=1 1293570SN/Aprefetch_data_accesses_only=false 1303570SN/Aprefetch_degree=1 1313570SN/Aprefetch_latency=10000 1323570SN/Aprefetch_on_access=false 1333570SN/Aprefetch_past_page=false 1343570SN/Aprefetch_policy=none 1353570SN/Aprefetch_serial_squash=false 1363570SN/Aprefetch_use_cpu_id=true 1373558SN/Aprefetcher_size=100 1383558SN/AprioritizeRequests=false 1393570SN/Arepl=Null 1403570SN/Asize=262144 1413570SN/Asubblock_size=0 1423558SN/Atgts_per_mshr=20 1433558SN/Atrace_addr=0 1443558SN/Atwo_queue=false 1453570SN/Awrite_buffers=8 1463570SN/Acpu_side=system.cpu.dcache_port 1473570SN/Amem_side=system.cpu.toL2Bus.port[1] 1486757SAli.Saidi@ARM.com 1493570SN/A[system.cpu.dtb] 1503570SN/Atype=ArmTLB 1513570SN/Asize=64 1523570SN/A 1533570SN/A[system.cpu.fuPool] 1546757SAli.Saidi@ARM.comtype=FUPool 1553570SN/Achildren=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1563570SN/AFUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 1573570SN/A 1583570SN/A[system.cpu.fuPool.FUList0] 1593570SN/Atype=FUDesc 1603570SN/Achildren=opList 1613570SN/Acount=6 1623570SN/AopList=system.cpu.fuPool.FUList0.opList 1633570SN/A 1643570SN/A[system.cpu.fuPool.FUList0.opList] 1656757SAli.Saidi@ARM.comtype=OpDesc 1663558SN/AissueLat=1 1673558SN/AopClass=IntAlu 1683570SN/AopLat=1 1693570SN/A 1703570SN/A[system.cpu.fuPool.FUList1] 1713570SN/Atype=FUDesc 1723570SN/Achildren=opList0 opList1 1736757SAli.Saidi@ARM.comcount=2 1746757SAli.Saidi@ARM.comopList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 1753570SN/A 1763570SN/A[system.cpu.fuPool.FUList1.opList0] 1773558SN/Atype=OpDesc 178issueLat=1 179opClass=IntMult 180opLat=3 181 182[system.cpu.fuPool.FUList1.opList1] 183type=OpDesc 184issueLat=19 185opClass=IntDiv 186opLat=20 187 188[system.cpu.fuPool.FUList2] 189type=FUDesc 190children=opList0 opList1 opList2 191count=4 192opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 193 194[system.cpu.fuPool.FUList2.opList0] 195type=OpDesc 196issueLat=1 197opClass=FloatAdd 198opLat=2 199 200[system.cpu.fuPool.FUList2.opList1] 201type=OpDesc 202issueLat=1 203opClass=FloatCmp 204opLat=2 205 206[system.cpu.fuPool.FUList2.opList2] 207type=OpDesc 208issueLat=1 209opClass=FloatCvt 210opLat=2 211 212[system.cpu.fuPool.FUList3] 213type=FUDesc 214children=opList0 opList1 opList2 215count=2 216opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 217 218[system.cpu.fuPool.FUList3.opList0] 219type=OpDesc 220issueLat=1 221opClass=FloatMult 222opLat=4 223 224[system.cpu.fuPool.FUList3.opList1] 225type=OpDesc 226issueLat=12 227opClass=FloatDiv 228opLat=12 229 230[system.cpu.fuPool.FUList3.opList2] 231type=OpDesc 232issueLat=24 233opClass=FloatSqrt 234opLat=24 235 236[system.cpu.fuPool.FUList4] 237type=FUDesc 238children=opList 239count=0 240opList=system.cpu.fuPool.FUList4.opList 241 242[system.cpu.fuPool.FUList4.opList] 243type=OpDesc 244issueLat=1 245opClass=MemRead 246opLat=1 247 248[system.cpu.fuPool.FUList5] 249type=FUDesc 250children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 251count=4 252opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 253 254[system.cpu.fuPool.FUList5.opList00] 255type=OpDesc 256issueLat=1 257opClass=SimdAdd 258opLat=1 259 260[system.cpu.fuPool.FUList5.opList01] 261type=OpDesc 262issueLat=1 263opClass=SimdAddAcc 264opLat=1 265 266[system.cpu.fuPool.FUList5.opList02] 267type=OpDesc 268issueLat=1 269opClass=SimdAlu 270opLat=1 271 272[system.cpu.fuPool.FUList5.opList03] 273type=OpDesc 274issueLat=1 275opClass=SimdCmp 276opLat=1 277 278[system.cpu.fuPool.FUList5.opList04] 279type=OpDesc 280issueLat=1 281opClass=SimdCvt 282opLat=1 283 284[system.cpu.fuPool.FUList5.opList05] 285type=OpDesc 286issueLat=1 287opClass=SimdMisc 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList06] 291type=OpDesc 292issueLat=1 293opClass=SimdMult 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList07] 297type=OpDesc 298issueLat=1 299opClass=SimdMultAcc 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList08] 303type=OpDesc 304issueLat=1 305opClass=SimdShift 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList09] 309type=OpDesc 310issueLat=1 311opClass=SimdShiftAcc 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList10] 315type=OpDesc 316issueLat=1 317opClass=SimdSqrt 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList11] 321type=OpDesc 322issueLat=1 323opClass=SimdFloatAdd 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList12] 327type=OpDesc 328issueLat=1 329opClass=SimdFloatAlu 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList13] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatCmp 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList14] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatCvt 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList15] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatDiv 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList16] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatMisc 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList17] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatMult 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList18] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatMultAcc 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList19] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatSqrt 372opLat=1 373 374[system.cpu.fuPool.FUList6] 375type=FUDesc 376children=opList 377count=0 378opList=system.cpu.fuPool.FUList6.opList 379 380[system.cpu.fuPool.FUList6.opList] 381type=OpDesc 382issueLat=1 383opClass=MemWrite 384opLat=1 385 386[system.cpu.fuPool.FUList7] 387type=FUDesc 388children=opList0 opList1 389count=4 390opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 391 392[system.cpu.fuPool.FUList7.opList0] 393type=OpDesc 394issueLat=1 395opClass=MemRead 396opLat=1 397 398[system.cpu.fuPool.FUList7.opList1] 399type=OpDesc 400issueLat=1 401opClass=MemWrite 402opLat=1 403 404[system.cpu.fuPool.FUList8] 405type=FUDesc 406children=opList 407count=1 408opList=system.cpu.fuPool.FUList8.opList 409 410[system.cpu.fuPool.FUList8.opList] 411type=OpDesc 412issueLat=3 413opClass=IprAccess 414opLat=3 415 416[system.cpu.icache] 417type=BaseCache 418addr_range=0:18446744073709551615 419assoc=2 420block_size=64 421forward_snoops=true 422hash_delay=1 423is_top_level=true 424latency=1000 425max_miss_count=0 426mshrs=10 427num_cpus=1 428prefetch_data_accesses_only=false 429prefetch_degree=1 430prefetch_latency=10000 431prefetch_on_access=false 432prefetch_past_page=false 433prefetch_policy=none 434prefetch_serial_squash=false 435prefetch_use_cpu_id=true 436prefetcher_size=100 437prioritizeRequests=false 438repl=Null 439size=131072 440subblock_size=0 441tgts_per_mshr=20 442trace_addr=0 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port 446mem_side=system.cpu.toL2Bus.port[0] 447 448[system.cpu.itb] 449type=ArmTLB 450size=64 451 452[system.cpu.l2cache] 453type=BaseCache 454addr_range=0:18446744073709551615 455assoc=2 456block_size=64 457forward_snoops=true 458hash_delay=1 459is_top_level=false 460latency=1000 461max_miss_count=0 462mshrs=10 463num_cpus=1 464prefetch_data_accesses_only=false 465prefetch_degree=1 466prefetch_latency=10000 467prefetch_on_access=false 468prefetch_past_page=false 469prefetch_policy=none 470prefetch_serial_squash=false 471prefetch_use_cpu_id=true 472prefetcher_size=100 473prioritizeRequests=false 474repl=Null 475size=2097152 476subblock_size=0 477tgts_per_mshr=5 478trace_addr=0 479two_queue=false 480write_buffers=8 481cpu_side=system.cpu.toL2Bus.port[2] 482mem_side=system.membus.port[2] 483 484[system.cpu.toL2Bus] 485type=Bus 486block_size=64 487bus_id=0 488clock=1000 489header_cycles=1 490use_default_range=false 491width=64 492port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 493 494[system.cpu.tracer] 495type=ExeTracer 496 497[system.cpu.workload] 498type=LiveProcess 499cmd=parser 2.1.dict -batch 500cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing 501egid=100 502env= 503errout=cerr 504euid=100 505executable=/dist/m5/cpu2000/binaries/arm/linux/parser 506gid=100 507input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in 508max_stack_size=67108864 509output=cout 510pid=100 511ppid=99 512simpoint=114600000000 513system=system 514uid=100 515 516[system.membus] 517type=Bus 518block_size=64 519bus_id=0 520clock=1000 521header_cycles=1 522use_default_range=false 523width=64 524port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side 525 526[system.physmem] 527type=PhysicalMemory 528file= 529latency=30000 530latency_var=0 531null=false 532range=0:134217727 533zero=false 534port=system.membus.port[1] 535 536