config.ini revision 8464
17927SN/A[root] 210540Sgabeblack@google.comtype=Root 37927SN/Achildren=system 47927SN/Atime_sync_enable=false 59125Snilay@cs.wisc.edutime_sync_period=100000000000 67927SN/Atime_sync_spin_threshold=100000000 77927SN/A 87927SN/A[system] 9type=System 10children=cpu membus physmem 11mem_mode=atomic 12memories=system.physmem 13physmem=system.physmem 14work_begin_ckpt_count=0 15work_begin_cpu_id_exit=-1 16work_begin_exit_count=0 17work_cpus_ckpt_count=0 18work_end_ckpt_count=0 19work_end_exit_count=0 20work_item_id=-1 21 22[system.cpu] 23type=DerivO3CPU 24children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload 25BTBEntries=4096 26BTBTagSize=16 27LFSTSize=1024 28LQEntries=32 29LSQCheckLoads=true 30LSQDepCheckShift=4 31RASSize=16 32SQEntries=32 33SSITSize=1024 34activity=0 35backComSize=5 36cachePorts=200 37checker=Null 38choiceCtrBits=2 39choicePredictorSize=8192 40clock=500 41commitToDecodeDelay=1 42commitToFetchDelay=1 43commitToIEWDelay=1 44commitToRenameDelay=1 45commitWidth=8 46cpu_id=0 47decodeToFetchDelay=1 48decodeToRenameDelay=1 49decodeWidth=8 50defer_registration=false 51dispatchWidth=8 52do_checkpoint_insts=true 53do_statistics_insts=true 54dtb=system.cpu.dtb 55fetchToDecodeDelay=1 56fetchTrapLatency=1 57fetchWidth=8 58forwardComSize=5 59fuPool=system.cpu.fuPool 60function_trace=false 61function_trace_start=0 62globalCtrBits=2 63globalHistoryBits=13 64globalPredictorSize=8192 65iewToCommitDelay=1 66iewToDecodeDelay=1 67iewToFetchDelay=1 68iewToRenameDelay=1 69instShiftAmt=2 70issueToExecuteDelay=1 71issueWidth=8 72itb=system.cpu.itb 73localCtrBits=2 74localHistoryBits=11 75localHistoryTableSize=2048 76localPredictorSize=2048 77max_insts_all_threads=0 78max_insts_any_thread=0 79max_loads_all_threads=0 80max_loads_any_thread=0 81numIQEntries=64 82numPhysFloatRegs=256 83numPhysIntRegs=256 84numROBEntries=192 85numRobs=1 86numThreads=1 87phase=0 88predType=tournament 89progress_interval=0 90renameToDecodeDelay=1 91renameToFetchDelay=1 92renameToIEWDelay=2 93renameToROBDelay=1 94renameWidth=8 95smtCommitPolicy=RoundRobin 96smtFetchPolicy=SingleThread 97smtIQPolicy=Partitioned 98smtIQThreshold=100 99smtLSQPolicy=Partitioned 100smtLSQThreshold=100 101smtNumFetchingThreads=1 102smtROBPolicy=Partitioned 103smtROBThreshold=100 104squashWidth=8 105system=system 106tracer=system.cpu.tracer 107trapLatency=13 108wbDepth=1 109wbWidth=8 110workload=system.cpu.workload 111dcache_port=system.cpu.dcache.cpu_side 112icache_port=system.cpu.icache.cpu_side 113 114[system.cpu.dcache] 115type=BaseCache 116addr_range=0:18446744073709551615 117assoc=2 118block_size=64 119forward_snoops=true 120hash_delay=1 121is_top_level=true 122latency=1000 123max_miss_count=0 124mshrs=10 125num_cpus=1 126prefetch_data_accesses_only=false 127prefetch_degree=1 128prefetch_latency=10000 129prefetch_on_access=false 130prefetch_past_page=false 131prefetch_policy=none 132prefetch_serial_squash=false 133prefetch_use_cpu_id=true 134prefetcher_size=100 135prioritizeRequests=false 136repl=Null 137size=262144 138subblock_size=0 139tgts_per_mshr=20 140trace_addr=0 141two_queue=false 142write_buffers=8 143cpu_side=system.cpu.dcache_port 144mem_side=system.cpu.toL2Bus.port[1] 145 146[system.cpu.dtb] 147type=ArmTLB 148size=64 149 150[system.cpu.fuPool] 151type=FUPool 152children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 153FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 154 155[system.cpu.fuPool.FUList0] 156type=FUDesc 157children=opList 158count=6 159opList=system.cpu.fuPool.FUList0.opList 160 161[system.cpu.fuPool.FUList0.opList] 162type=OpDesc 163issueLat=1 164opClass=IntAlu 165opLat=1 166 167[system.cpu.fuPool.FUList1] 168type=FUDesc 169children=opList0 opList1 170count=2 171opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 172 173[system.cpu.fuPool.FUList1.opList0] 174type=OpDesc 175issueLat=1 176opClass=IntMult 177opLat=3 178 179[system.cpu.fuPool.FUList1.opList1] 180type=OpDesc 181issueLat=19 182opClass=IntDiv 183opLat=20 184 185[system.cpu.fuPool.FUList2] 186type=FUDesc 187children=opList0 opList1 opList2 188count=4 189opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 190 191[system.cpu.fuPool.FUList2.opList0] 192type=OpDesc 193issueLat=1 194opClass=FloatAdd 195opLat=2 196 197[system.cpu.fuPool.FUList2.opList1] 198type=OpDesc 199issueLat=1 200opClass=FloatCmp 201opLat=2 202 203[system.cpu.fuPool.FUList2.opList2] 204type=OpDesc 205issueLat=1 206opClass=FloatCvt 207opLat=2 208 209[system.cpu.fuPool.FUList3] 210type=FUDesc 211children=opList0 opList1 opList2 212count=2 213opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 214 215[system.cpu.fuPool.FUList3.opList0] 216type=OpDesc 217issueLat=1 218opClass=FloatMult 219opLat=4 220 221[system.cpu.fuPool.FUList3.opList1] 222type=OpDesc 223issueLat=12 224opClass=FloatDiv 225opLat=12 226 227[system.cpu.fuPool.FUList3.opList2] 228type=OpDesc 229issueLat=24 230opClass=FloatSqrt 231opLat=24 232 233[system.cpu.fuPool.FUList4] 234type=FUDesc 235children=opList 236count=0 237opList=system.cpu.fuPool.FUList4.opList 238 239[system.cpu.fuPool.FUList4.opList] 240type=OpDesc 241issueLat=1 242opClass=MemRead 243opLat=1 244 245[system.cpu.fuPool.FUList5] 246type=FUDesc 247children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 248count=4 249opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 250 251[system.cpu.fuPool.FUList5.opList00] 252type=OpDesc 253issueLat=1 254opClass=SimdAdd 255opLat=1 256 257[system.cpu.fuPool.FUList5.opList01] 258type=OpDesc 259issueLat=1 260opClass=SimdAddAcc 261opLat=1 262 263[system.cpu.fuPool.FUList5.opList02] 264type=OpDesc 265issueLat=1 266opClass=SimdAlu 267opLat=1 268 269[system.cpu.fuPool.FUList5.opList03] 270type=OpDesc 271issueLat=1 272opClass=SimdCmp 273opLat=1 274 275[system.cpu.fuPool.FUList5.opList04] 276type=OpDesc 277issueLat=1 278opClass=SimdCvt 279opLat=1 280 281[system.cpu.fuPool.FUList5.opList05] 282type=OpDesc 283issueLat=1 284opClass=SimdMisc 285opLat=1 286 287[system.cpu.fuPool.FUList5.opList06] 288type=OpDesc 289issueLat=1 290opClass=SimdMult 291opLat=1 292 293[system.cpu.fuPool.FUList5.opList07] 294type=OpDesc 295issueLat=1 296opClass=SimdMultAcc 297opLat=1 298 299[system.cpu.fuPool.FUList5.opList08] 300type=OpDesc 301issueLat=1 302opClass=SimdShift 303opLat=1 304 305[system.cpu.fuPool.FUList5.opList09] 306type=OpDesc 307issueLat=1 308opClass=SimdShiftAcc 309opLat=1 310 311[system.cpu.fuPool.FUList5.opList10] 312type=OpDesc 313issueLat=1 314opClass=SimdSqrt 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList11] 318type=OpDesc 319issueLat=1 320opClass=SimdFloatAdd 321opLat=1 322 323[system.cpu.fuPool.FUList5.opList12] 324type=OpDesc 325issueLat=1 326opClass=SimdFloatAlu 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList13] 330type=OpDesc 331issueLat=1 332opClass=SimdFloatCmp 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList14] 336type=OpDesc 337issueLat=1 338opClass=SimdFloatCvt 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList15] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatDiv 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList16] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatMisc 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList17] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatMult 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList18] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatMultAcc 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList19] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatSqrt 369opLat=1 370 371[system.cpu.fuPool.FUList6] 372type=FUDesc 373children=opList 374count=0 375opList=system.cpu.fuPool.FUList6.opList 376 377[system.cpu.fuPool.FUList6.opList] 378type=OpDesc 379issueLat=1 380opClass=MemWrite 381opLat=1 382 383[system.cpu.fuPool.FUList7] 384type=FUDesc 385children=opList0 opList1 386count=4 387opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 388 389[system.cpu.fuPool.FUList7.opList0] 390type=OpDesc 391issueLat=1 392opClass=MemRead 393opLat=1 394 395[system.cpu.fuPool.FUList7.opList1] 396type=OpDesc 397issueLat=1 398opClass=MemWrite 399opLat=1 400 401[system.cpu.fuPool.FUList8] 402type=FUDesc 403children=opList 404count=1 405opList=system.cpu.fuPool.FUList8.opList 406 407[system.cpu.fuPool.FUList8.opList] 408type=OpDesc 409issueLat=3 410opClass=IprAccess 411opLat=3 412 413[system.cpu.icache] 414type=BaseCache 415addr_range=0:18446744073709551615 416assoc=2 417block_size=64 418forward_snoops=true 419hash_delay=1 420is_top_level=true 421latency=1000 422max_miss_count=0 423mshrs=10 424num_cpus=1 425prefetch_data_accesses_only=false 426prefetch_degree=1 427prefetch_latency=10000 428prefetch_on_access=false 429prefetch_past_page=false 430prefetch_policy=none 431prefetch_serial_squash=false 432prefetch_use_cpu_id=true 433prefetcher_size=100 434prioritizeRequests=false 435repl=Null 436size=131072 437subblock_size=0 438tgts_per_mshr=20 439trace_addr=0 440two_queue=false 441write_buffers=8 442cpu_side=system.cpu.icache_port 443mem_side=system.cpu.toL2Bus.port[0] 444 445[system.cpu.itb] 446type=ArmTLB 447size=64 448 449[system.cpu.l2cache] 450type=BaseCache 451addr_range=0:18446744073709551615 452assoc=2 453block_size=64 454forward_snoops=true 455hash_delay=1 456is_top_level=false 457latency=1000 458max_miss_count=0 459mshrs=10 460num_cpus=1 461prefetch_data_accesses_only=false 462prefetch_degree=1 463prefetch_latency=10000 464prefetch_on_access=false 465prefetch_past_page=false 466prefetch_policy=none 467prefetch_serial_squash=false 468prefetch_use_cpu_id=true 469prefetcher_size=100 470prioritizeRequests=false 471repl=Null 472size=2097152 473subblock_size=0 474tgts_per_mshr=5 475trace_addr=0 476two_queue=false 477write_buffers=8 478cpu_side=system.cpu.toL2Bus.port[2] 479mem_side=system.membus.port[1] 480 481[system.cpu.toL2Bus] 482type=Bus 483block_size=64 484bus_id=0 485clock=1000 486header_cycles=1 487use_default_range=false 488width=64 489port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side 490 491[system.cpu.tracer] 492type=ExeTracer 493 494[system.cpu.workload] 495type=LiveProcess 496cmd=parser 2.1.dict -batch 497cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing 498egid=100 499env= 500errout=cerr 501euid=100 502executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser 503gid=100 504input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in 505max_stack_size=67108864 506output=cout 507pid=100 508ppid=99 509simpoint=114600000000 510system=system 511uid=100 512 513[system.membus] 514type=Bus 515block_size=64 516bus_id=0 517clock=1000 518header_cycles=1 519use_default_range=false 520width=64 521port=system.physmem.port[0] system.cpu.l2cache.mem_side 522 523[system.physmem] 524type=PhysicalMemory 525file= 526latency=30000 527latency_var=0 528null=false 529range=0:134217727 530zero=false 531port=system.membus.port[0] 532 533