stats.txt revision 10852:5b58b4cccfd7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.366030 # Number of seconds simulated 4sim_ticks 366029674500 # Number of ticks simulated 5final_tick 366029674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 241467 # Simulator instruction rate (inst/s) 8host_op_rate 261540 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 174471263 # Simulator tick rate (ticks/s) 10host_mem_usage 317880 # Number of bytes of host memory used 11host_seconds 2097.94 # Real time elapsed on the host 12sim_insts 506582156 # Number of instructions simulated 13sim_ops 548695379 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 221440 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9008192 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9229632 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6182144 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6182144 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 3460 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 140753 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 144213 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 96596 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 96596 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 604978 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 24610551 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 25215529 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 604978 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 604978 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 16889734 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 16889734 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 16889734 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 604978 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 24610551 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 42105264 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 144213 # Number of read requests accepted 40system.physmem.writeReqs 96596 # Number of write requests accepted 41system.physmem.readBursts 144213 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 96596 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 9221696 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue 45system.physmem.bytesWritten 6180992 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 9229632 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 6182144 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 9409 # Per bank write bursts 52system.physmem.perBankRdBursts::1 9017 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8952 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8679 # Per bank write bursts 55system.physmem.perBankRdBursts::4 9455 # Per bank write bursts 56system.physmem.perBankRdBursts::5 9348 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8942 # Per bank write bursts 58system.physmem.perBankRdBursts::7 8103 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8564 # Per bank write bursts 60system.physmem.perBankRdBursts::9 8678 # Per bank write bursts 61system.physmem.perBankRdBursts::10 8771 # Per bank write bursts 62system.physmem.perBankRdBursts::11 9482 # Per bank write bursts 63system.physmem.perBankRdBursts::12 9373 # Per bank write bursts 64system.physmem.perBankRdBursts::13 9523 # Per bank write bursts 65system.physmem.perBankRdBursts::14 8716 # Per bank write bursts 66system.physmem.perBankRdBursts::15 9077 # Per bank write bursts 67system.physmem.perBankWrBursts::0 6225 # Per bank write bursts 68system.physmem.perBankWrBursts::1 6098 # Per bank write bursts 69system.physmem.perBankWrBursts::2 6004 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5808 # Per bank write bursts 71system.physmem.perBankWrBursts::4 6164 # Per bank write bursts 72system.physmem.perBankWrBursts::5 6178 # Per bank write bursts 73system.physmem.perBankWrBursts::6 6016 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5497 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5725 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5821 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5961 # Per bank write bursts 78system.physmem.perBankWrBursts::11 6450 # Per bank write bursts 79system.physmem.perBankWrBursts::12 6306 # Per bank write bursts 80system.physmem.perBankWrBursts::13 6280 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5998 # Per bank write bursts 82system.physmem.perBankWrBursts::15 6047 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 366029646000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 144213 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 96596 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 143718 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 350 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 2919 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5685 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5671 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5692 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5661 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5688 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5687 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5676 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5675 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5679 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5674 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5663 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5657 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5600 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5583 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 65352 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 235.682213 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 156.342104 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 241.346143 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 24838 38.01% 38.01% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 18259 27.94% 65.95% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 6996 10.71% 76.65% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7952 12.17% 88.82% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2091 3.20% 92.02% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1098 1.68% 93.70% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 757 1.16% 94.86% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 602 0.92% 95.78% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 2759 4.22% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 65352 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5574 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 25.850018 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 381.983730 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5570 99.93% 99.93% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 5574 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5574 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.326516 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.224346 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 2.427330 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16-17 2648 47.51% 47.51% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18-19 2778 49.84% 97.34% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::20-21 56 1.00% 98.35% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::22-23 28 0.50% 98.85% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-25 12 0.22% 99.07% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::26-27 10 0.18% 99.25% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::28-29 6 0.11% 99.35% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::30-31 9 0.16% 99.52% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-33 4 0.07% 99.59% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::34-35 7 0.13% 99.71% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::36-37 2 0.04% 99.75% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::40-41 4 0.07% 99.82% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::42-43 2 0.04% 99.86% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::44-45 1 0.02% 99.87% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::50-51 1 0.02% 99.91% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::54-55 1 0.02% 99.93% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::64-65 1 0.02% 99.96% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::total 5574 # Writes before turning the bus around for reads 243system.physmem.totQLat 1545997750 # Total ticks spent queuing 244system.physmem.totMemAccLat 4247666500 # Total ticks spent from burst creation until serviced by the DRAM 245system.physmem.totBusLat 720445000 # Total ticks spent in databus transfers 246system.physmem.avgQLat 10729.46 # Average queueing delay per DRAM burst 247system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 248system.physmem.avgMemAccLat 29479.46 # Average memory access latency per DRAM burst 249system.physmem.avgRdBW 25.19 # Average DRAM read bandwidth in MiByte/s 250system.physmem.avgWrBW 16.89 # Average achieved write bandwidth in MiByte/s 251system.physmem.avgRdBWSys 25.22 # Average system read bandwidth in MiByte/s 252system.physmem.avgWrBWSys 16.89 # Average system write bandwidth in MiByte/s 253system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 254system.physmem.busUtil 0.33 # Data bus utilization in percentage 255system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 256system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 257system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 258system.physmem.avgWrQLen 20.60 # Average write queue length when enqueuing 259system.physmem.readRowHits 110923 # Number of row buffer hits during reads 260system.physmem.writeRowHits 64387 # Number of row buffer hits during writes 261system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads 262system.physmem.writeRowHitRate 66.66 # Row buffer hit rate for writes 263system.physmem.avgGap 1519999.86 # Average gap between requests 264system.physmem.pageHitRate 72.84 # Row buffer hit rate, read and write combined 265system.physmem_0.actEnergy 248708880 # Energy for activate commands per rank (pJ) 266system.physmem_0.preEnergy 135704250 # Energy for precharge commands per rank (pJ) 267system.physmem_0.readEnergy 560640600 # Energy for read commands per rank (pJ) 268system.physmem_0.writeEnergy 310761360 # Energy for write commands per rank (pJ) 269system.physmem_0.refreshEnergy 23906897040 # Energy for refresh commands per rank (pJ) 270system.physmem_0.actBackEnergy 47751629445 # Energy for active background per rank (pJ) 271system.physmem_0.preBackEnergy 177727049250 # Energy for precharge background per rank (pJ) 272system.physmem_0.totalEnergy 250641390825 # Total energy per rank (pJ) 273system.physmem_0.averagePower 684.767505 # Core power per rank (mW) 274system.physmem_0.memoryStateTime::IDLE 295355626000 # Time in different power states 275system.physmem_0.memoryStateTime::REF 12222340000 # Time in different power states 276system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 277system.physmem_0.memoryStateTime::ACT 58446120250 # Time in different power states 278system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 279system.physmem_1.actEnergy 245064960 # Energy for activate commands per rank (pJ) 280system.physmem_1.preEnergy 133716000 # Energy for precharge commands per rank (pJ) 281system.physmem_1.readEnergy 562816800 # Energy for read commands per rank (pJ) 282system.physmem_1.writeEnergy 314753040 # Energy for write commands per rank (pJ) 283system.physmem_1.refreshEnergy 23906897040 # Energy for refresh commands per rank (pJ) 284system.physmem_1.actBackEnergy 47056905180 # Energy for active background per rank (pJ) 285system.physmem_1.preBackEnergy 178336456500 # Energy for precharge background per rank (pJ) 286system.physmem_1.totalEnergy 250556609520 # Total energy per rank (pJ) 287system.physmem_1.averagePower 684.535877 # Core power per rank (mW) 288system.physmem_1.memoryStateTime::IDLE 296372694500 # Time in different power states 289system.physmem_1.memoryStateTime::REF 12222340000 # Time in different power states 290system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 291system.physmem_1.memoryStateTime::ACT 57429294500 # Time in different power states 292system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 293system.cpu.branchPred.lookups 132485545 # Number of BP lookups 294system.cpu.branchPred.condPredicted 98435425 # Number of conditional branches predicted 295system.cpu.branchPred.condIncorrect 6553959 # Number of conditional branches incorrect 296system.cpu.branchPred.BTBLookups 68727443 # Number of BTB lookups 297system.cpu.branchPred.BTBHits 64816198 # Number of BTB hits 298system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 299system.cpu.branchPred.BTBHitPct 94.309049 # BTB Hit Percentage 300system.cpu.branchPred.usedRAS 10006764 # Number of times the RAS was used to get a target. 301system.cpu.branchPred.RASInCorrect 17617 # Number of incorrect RAS predictions. 302system.cpu_clk_domain.clock 500 # Clock period in ticks 303system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 312system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 313system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 314system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 315system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 316system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 317system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 321system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 322system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 323system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 324system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 325system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 326system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 327system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 328system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 329system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 330system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 331system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 332system.cpu.dtb.walker.walks 0 # Table walker walks requested 333system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.inst_hits 0 # ITB inst hits 341system.cpu.dtb.inst_misses 0 # ITB inst misses 342system.cpu.dtb.read_hits 0 # DTB read hits 343system.cpu.dtb.read_misses 0 # DTB read misses 344system.cpu.dtb.write_hits 0 # DTB write hits 345system.cpu.dtb.write_misses 0 # DTB write misses 346system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 347system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 348system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 349system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 350system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 351system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 352system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 353system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 354system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.dtb.read_accesses 0 # DTB read accesses 356system.cpu.dtb.write_accesses 0 # DTB write accesses 357system.cpu.dtb.inst_accesses 0 # ITB inst accesses 358system.cpu.dtb.hits 0 # DTB hits 359system.cpu.dtb.misses 0 # DTB misses 360system.cpu.dtb.accesses 0 # DTB accesses 361system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 370system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 371system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 372system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 373system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 374system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 375system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 376system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 377system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 378system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 379system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 380system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 381system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 382system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 383system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 384system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 385system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 386system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 387system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 388system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 389system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 390system.cpu.itb.walker.walks 0 # Table walker walks requested 391system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.inst_hits 0 # ITB inst hits 399system.cpu.itb.inst_misses 0 # ITB inst misses 400system.cpu.itb.read_hits 0 # DTB read hits 401system.cpu.itb.read_misses 0 # DTB read misses 402system.cpu.itb.write_hits 0 # DTB write hits 403system.cpu.itb.write_misses 0 # DTB write misses 404system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 405system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 406system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 407system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 408system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 409system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 410system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 411system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 412system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 413system.cpu.itb.read_accesses 0 # DTB read accesses 414system.cpu.itb.write_accesses 0 # DTB write accesses 415system.cpu.itb.inst_accesses 0 # ITB inst accesses 416system.cpu.itb.hits 0 # DTB hits 417system.cpu.itb.misses 0 # DTB misses 418system.cpu.itb.accesses 0 # DTB accesses 419system.cpu.workload.num_syscalls 548 # Number of system calls 420system.cpu.numCycles 732059349 # number of cpu cycles simulated 421system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 422system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 423system.cpu.committedInsts 506582156 # Number of instructions committed 424system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed 425system.cpu.discardedOps 13911652 # Number of ops (including micro ops) which were discarded before commit 426system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 427system.cpu.cpi 1.445095 # CPI: cycles per instruction 428system.cpu.ipc 0.691996 # IPC: instructions per cycle 429system.cpu.tickCycles 695000552 # Number of cycles that the object actually ticked 430system.cpu.idleCycles 37058797 # Total number of cycles that the object has spent stopped 431system.cpu.dcache.tags.replacements 1139856 # number of replacements 432system.cpu.dcache.tags.tagsinuse 4070.933719 # Cycle average of tags in use 433system.cpu.dcache.tags.total_refs 171285318 # Total number of references to valid blocks. 434system.cpu.dcache.tags.sampled_refs 1143952 # Sample count of references to valid blocks. 435system.cpu.dcache.tags.avg_refs 149.731211 # Average number of references to valid blocks. 436system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit. 437system.cpu.dcache.tags.occ_blocks::cpu.data 4070.933719 # Average occupied blocks per requestor 438system.cpu.dcache.tags.occ_percent::cpu.data 0.993880 # Average percentage of cache occupancy 439system.cpu.dcache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy 440system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 441system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 442system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id 443system.cpu.dcache.tags.age_task_id_blocks_1024::2 552 # Occupied blocks per task id 444system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id 445system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 446system.cpu.dcache.tags.tag_accesses 346825504 # Number of tag accesses 447system.cpu.dcache.tags.data_accesses 346825504 # Number of data accesses 448system.cpu.dcache.ReadReq_hits::cpu.data 114766819 # number of ReadReq hits 449system.cpu.dcache.ReadReq_hits::total 114766819 # number of ReadReq hits 450system.cpu.dcache.WriteReq_hits::cpu.data 53538648 # number of WriteReq hits 451system.cpu.dcache.WriteReq_hits::total 53538648 # number of WriteReq hits 452system.cpu.dcache.SoftPFReq_hits::cpu.data 2769 # number of SoftPFReq hits 453system.cpu.dcache.SoftPFReq_hits::total 2769 # number of SoftPFReq hits 454system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 455system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 456system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 457system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 458system.cpu.dcache.demand_hits::cpu.data 168305467 # number of demand (read+write) hits 459system.cpu.dcache.demand_hits::total 168305467 # number of demand (read+write) hits 460system.cpu.dcache.overall_hits::cpu.data 168308236 # number of overall hits 461system.cpu.dcache.overall_hits::total 168308236 # number of overall hits 462system.cpu.dcache.ReadReq_misses::cpu.data 854784 # number of ReadReq misses 463system.cpu.dcache.ReadReq_misses::total 854784 # number of ReadReq misses 464system.cpu.dcache.WriteReq_misses::cpu.data 700658 # number of WriteReq misses 465system.cpu.dcache.WriteReq_misses::total 700658 # number of WriteReq misses 466system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses 467system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses 468system.cpu.dcache.demand_misses::cpu.data 1555442 # number of demand (read+write) misses 469system.cpu.dcache.demand_misses::total 1555442 # number of demand (read+write) misses 470system.cpu.dcache.overall_misses::cpu.data 1555458 # number of overall misses 471system.cpu.dcache.overall_misses::total 1555458 # number of overall misses 472system.cpu.dcache.ReadReq_miss_latency::cpu.data 14034932732 # number of ReadReq miss cycles 473system.cpu.dcache.ReadReq_miss_latency::total 14034932732 # number of ReadReq miss cycles 474system.cpu.dcache.WriteReq_miss_latency::cpu.data 22036201250 # number of WriteReq miss cycles 475system.cpu.dcache.WriteReq_miss_latency::total 22036201250 # number of WriteReq miss cycles 476system.cpu.dcache.demand_miss_latency::cpu.data 36071133982 # number of demand (read+write) miss cycles 477system.cpu.dcache.demand_miss_latency::total 36071133982 # number of demand (read+write) miss cycles 478system.cpu.dcache.overall_miss_latency::cpu.data 36071133982 # number of overall miss cycles 479system.cpu.dcache.overall_miss_latency::total 36071133982 # number of overall miss cycles 480system.cpu.dcache.ReadReq_accesses::cpu.data 115621603 # number of ReadReq accesses(hits+misses) 481system.cpu.dcache.ReadReq_accesses::total 115621603 # number of ReadReq accesses(hits+misses) 482system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 483system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 484system.cpu.dcache.SoftPFReq_accesses::cpu.data 2785 # number of SoftPFReq accesses(hits+misses) 485system.cpu.dcache.SoftPFReq_accesses::total 2785 # number of SoftPFReq accesses(hits+misses) 486system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 487system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 488system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 489system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 490system.cpu.dcache.demand_accesses::cpu.data 169860909 # number of demand (read+write) accesses 491system.cpu.dcache.demand_accesses::total 169860909 # number of demand (read+write) accesses 492system.cpu.dcache.overall_accesses::cpu.data 169863694 # number of overall (read+write) accesses 493system.cpu.dcache.overall_accesses::total 169863694 # number of overall (read+write) accesses 494system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses 495system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses 496system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses 497system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses 498system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005745 # miss rate for SoftPFReq accesses 499system.cpu.dcache.SoftPFReq_miss_rate::total 0.005745 # miss rate for SoftPFReq accesses 500system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses 501system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses 502system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses 503system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses 504system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16419.274029 # average ReadReq miss latency 505system.cpu.dcache.ReadReq_avg_miss_latency::total 16419.274029 # average ReadReq miss latency 506system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31450.723820 # average WriteReq miss latency 507system.cpu.dcache.WriteReq_avg_miss_latency::total 31450.723820 # average WriteReq miss latency 508system.cpu.dcache.demand_avg_miss_latency::cpu.data 23190.279022 # average overall miss latency 509system.cpu.dcache.demand_avg_miss_latency::total 23190.279022 # average overall miss latency 510system.cpu.dcache.overall_avg_miss_latency::cpu.data 23190.040478 # average overall miss latency 511system.cpu.dcache.overall_avg_miss_latency::total 23190.040478 # average overall miss latency 512system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 513system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 514system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 515system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 516system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 517system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 518system.cpu.dcache.fast_writes 0 # number of fast writes performed 519system.cpu.dcache.cache_copies 0 # number of cache copies performed 520system.cpu.dcache.writebacks::writebacks 1068580 # number of writebacks 521system.cpu.dcache.writebacks::total 1068580 # number of writebacks 522system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67006 # number of ReadReq MSHR hits 523system.cpu.dcache.ReadReq_mshr_hits::total 67006 # number of ReadReq MSHR hits 524system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344497 # number of WriteReq MSHR hits 525system.cpu.dcache.WriteReq_mshr_hits::total 344497 # number of WriteReq MSHR hits 526system.cpu.dcache.demand_mshr_hits::cpu.data 411503 # number of demand (read+write) MSHR hits 527system.cpu.dcache.demand_mshr_hits::total 411503 # number of demand (read+write) MSHR hits 528system.cpu.dcache.overall_mshr_hits::cpu.data 411503 # number of overall MSHR hits 529system.cpu.dcache.overall_mshr_hits::total 411503 # number of overall MSHR hits 530system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787778 # number of ReadReq MSHR misses 531system.cpu.dcache.ReadReq_mshr_misses::total 787778 # number of ReadReq MSHR misses 532system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356161 # number of WriteReq MSHR misses 533system.cpu.dcache.WriteReq_mshr_misses::total 356161 # number of WriteReq MSHR misses 534system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses 535system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses 536system.cpu.dcache.demand_mshr_misses::cpu.data 1143939 # number of demand (read+write) MSHR misses 537system.cpu.dcache.demand_mshr_misses::total 1143939 # number of demand (read+write) MSHR misses 538system.cpu.dcache.overall_mshr_misses::cpu.data 1143952 # number of overall MSHR misses 539system.cpu.dcache.overall_mshr_misses::total 1143952 # number of overall MSHR misses 540system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11938933765 # number of ReadReq MSHR miss cycles 541system.cpu.dcache.ReadReq_mshr_miss_latency::total 11938933765 # number of ReadReq MSHR miss cycles 542system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10970217000 # number of WriteReq MSHR miss cycles 543system.cpu.dcache.WriteReq_mshr_miss_latency::total 10970217000 # number of WriteReq MSHR miss cycles 544system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1208500 # number of SoftPFReq MSHR miss cycles 545system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1208500 # number of SoftPFReq MSHR miss cycles 546system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22909150765 # number of demand (read+write) MSHR miss cycles 547system.cpu.dcache.demand_mshr_miss_latency::total 22909150765 # number of demand (read+write) MSHR miss cycles 548system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22910359265 # number of overall MSHR miss cycles 549system.cpu.dcache.overall_mshr_miss_latency::total 22910359265 # number of overall MSHR miss cycles 550system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses 551system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses 552system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses 553system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses 554system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004668 # mshr miss rate for SoftPFReq accesses 555system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004668 # mshr miss rate for SoftPFReq accesses 556system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses 557system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses 558system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses 559system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses 560system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15155.200786 # average ReadReq mshr miss latency 561system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15155.200786 # average ReadReq mshr miss latency 562system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30801.286497 # average WriteReq mshr miss latency 563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30801.286497 # average WriteReq mshr miss latency 564system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 92961.538462 # average SoftPFReq mshr miss latency 565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92961.538462 # average SoftPFReq mshr miss latency 566system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20026.549287 # average overall mshr miss latency 567system.cpu.dcache.demand_avg_mshr_miss_latency::total 20026.549287 # average overall mshr miss latency 568system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20027.378129 # average overall mshr miss latency 569system.cpu.dcache.overall_avg_mshr_miss_latency::total 20027.378129 # average overall mshr miss latency 570system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 571system.cpu.icache.tags.replacements 17693 # number of replacements 572system.cpu.icache.tags.tagsinuse 1189.692945 # Cycle average of tags in use 573system.cpu.icache.tags.total_refs 200785966 # Total number of references to valid blocks. 574system.cpu.icache.tags.sampled_refs 19565 # Sample count of references to valid blocks. 575system.cpu.icache.tags.avg_refs 10262.507846 # Average number of references to valid blocks. 576system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 577system.cpu.icache.tags.occ_blocks::cpu.inst 1189.692945 # Average occupied blocks per requestor 578system.cpu.icache.tags.occ_percent::cpu.inst 0.580905 # Average percentage of cache occupancy 579system.cpu.icache.tags.occ_percent::total 0.580905 # Average percentage of cache occupancy 580system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 581system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 582system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 583system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id 584system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id 585system.cpu.icache.tags.age_task_id_blocks_1024::4 1410 # Occupied blocks per task id 586system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id 587system.cpu.icache.tags.tag_accesses 401630627 # Number of tag accesses 588system.cpu.icache.tags.data_accesses 401630627 # Number of data accesses 589system.cpu.icache.ReadReq_hits::cpu.inst 200785966 # number of ReadReq hits 590system.cpu.icache.ReadReq_hits::total 200785966 # number of ReadReq hits 591system.cpu.icache.demand_hits::cpu.inst 200785966 # number of demand (read+write) hits 592system.cpu.icache.demand_hits::total 200785966 # number of demand (read+write) hits 593system.cpu.icache.overall_hits::cpu.inst 200785966 # number of overall hits 594system.cpu.icache.overall_hits::total 200785966 # number of overall hits 595system.cpu.icache.ReadReq_misses::cpu.inst 19565 # number of ReadReq misses 596system.cpu.icache.ReadReq_misses::total 19565 # number of ReadReq misses 597system.cpu.icache.demand_misses::cpu.inst 19565 # number of demand (read+write) misses 598system.cpu.icache.demand_misses::total 19565 # number of demand (read+write) misses 599system.cpu.icache.overall_misses::cpu.inst 19565 # number of overall misses 600system.cpu.icache.overall_misses::total 19565 # number of overall misses 601system.cpu.icache.ReadReq_miss_latency::cpu.inst 492369746 # number of ReadReq miss cycles 602system.cpu.icache.ReadReq_miss_latency::total 492369746 # number of ReadReq miss cycles 603system.cpu.icache.demand_miss_latency::cpu.inst 492369746 # number of demand (read+write) miss cycles 604system.cpu.icache.demand_miss_latency::total 492369746 # number of demand (read+write) miss cycles 605system.cpu.icache.overall_miss_latency::cpu.inst 492369746 # number of overall miss cycles 606system.cpu.icache.overall_miss_latency::total 492369746 # number of overall miss cycles 607system.cpu.icache.ReadReq_accesses::cpu.inst 200805531 # number of ReadReq accesses(hits+misses) 608system.cpu.icache.ReadReq_accesses::total 200805531 # number of ReadReq accesses(hits+misses) 609system.cpu.icache.demand_accesses::cpu.inst 200805531 # number of demand (read+write) accesses 610system.cpu.icache.demand_accesses::total 200805531 # number of demand (read+write) accesses 611system.cpu.icache.overall_accesses::cpu.inst 200805531 # number of overall (read+write) accesses 612system.cpu.icache.overall_accesses::total 200805531 # number of overall (read+write) accesses 613system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses 614system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses 615system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses 616system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses 617system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses 618system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses 619system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25165.844416 # average ReadReq miss latency 620system.cpu.icache.ReadReq_avg_miss_latency::total 25165.844416 # average ReadReq miss latency 621system.cpu.icache.demand_avg_miss_latency::cpu.inst 25165.844416 # average overall miss latency 622system.cpu.icache.demand_avg_miss_latency::total 25165.844416 # average overall miss latency 623system.cpu.icache.overall_avg_miss_latency::cpu.inst 25165.844416 # average overall miss latency 624system.cpu.icache.overall_avg_miss_latency::total 25165.844416 # average overall miss latency 625system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 626system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 627system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 628system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 629system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 630system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 631system.cpu.icache.fast_writes 0 # number of fast writes performed 632system.cpu.icache.cache_copies 0 # number of cache copies performed 633system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19565 # number of ReadReq MSHR misses 634system.cpu.icache.ReadReq_mshr_misses::total 19565 # number of ReadReq MSHR misses 635system.cpu.icache.demand_mshr_misses::cpu.inst 19565 # number of demand (read+write) MSHR misses 636system.cpu.icache.demand_mshr_misses::total 19565 # number of demand (read+write) MSHR misses 637system.cpu.icache.overall_mshr_misses::cpu.inst 19565 # number of overall MSHR misses 638system.cpu.icache.overall_mshr_misses::total 19565 # number of overall MSHR misses 639system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 461635754 # number of ReadReq MSHR miss cycles 640system.cpu.icache.ReadReq_mshr_miss_latency::total 461635754 # number of ReadReq MSHR miss cycles 641system.cpu.icache.demand_mshr_miss_latency::cpu.inst 461635754 # number of demand (read+write) MSHR miss cycles 642system.cpu.icache.demand_mshr_miss_latency::total 461635754 # number of demand (read+write) MSHR miss cycles 643system.cpu.icache.overall_mshr_miss_latency::cpu.inst 461635754 # number of overall MSHR miss cycles 644system.cpu.icache.overall_mshr_miss_latency::total 461635754 # number of overall MSHR miss cycles 645system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses 646system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses 647system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses 648system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses 649system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses 650system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses 651system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23594.978482 # average ReadReq mshr miss latency 652system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23594.978482 # average ReadReq mshr miss latency 653system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23594.978482 # average overall mshr miss latency 654system.cpu.icache.demand_avg_mshr_miss_latency::total 23594.978482 # average overall mshr miss latency 655system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23594.978482 # average overall mshr miss latency 656system.cpu.icache.overall_avg_mshr_miss_latency::total 23594.978482 # average overall mshr miss latency 657system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 658system.cpu.l2cache.tags.replacements 111459 # number of replacements 659system.cpu.l2cache.tags.tagsinuse 27647.084057 # Cycle average of tags in use 660system.cpu.l2cache.tags.total_refs 1684517 # Total number of references to valid blocks. 661system.cpu.l2cache.tags.sampled_refs 142645 # Sample count of references to valid blocks. 662system.cpu.l2cache.tags.avg_refs 11.809156 # Average number of references to valid blocks. 663system.cpu.l2cache.tags.warmup_cycle 163718172500 # Cycle when the warmup percentage was hit. 664system.cpu.l2cache.tags.occ_blocks::writebacks 23519.494662 # Average occupied blocks per requestor 665system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.390983 # Average occupied blocks per requestor 666system.cpu.l2cache.tags.occ_blocks::cpu.data 3737.198412 # Average occupied blocks per requestor 667system.cpu.l2cache.tags.occ_percent::writebacks 0.717758 # Average percentage of cache occupancy 668system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011914 # Average percentage of cache occupancy 669system.cpu.l2cache.tags.occ_percent::cpu.data 0.114050 # Average percentage of cache occupancy 670system.cpu.l2cache.tags.occ_percent::total 0.843722 # Average percentage of cache occupancy 671system.cpu.l2cache.tags.occ_task_id_blocks::1024 31186 # Occupied blocks per task id 672system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 673system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id 674system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4936 # Occupied blocks per task id 675system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25861 # Occupied blocks per task id 676system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id 677system.cpu.l2cache.tags.tag_accesses 18355835 # Number of tag accesses 678system.cpu.l2cache.tags.data_accesses 18355835 # Number of data accesses 679system.cpu.l2cache.ReadReq_hits::cpu.inst 16103 # number of ReadReq hits 680system.cpu.l2cache.ReadReq_hits::cpu.data 747676 # number of ReadReq hits 681system.cpu.l2cache.ReadReq_hits::total 763779 # number of ReadReq hits 682system.cpu.l2cache.Writeback_hits::writebacks 1068580 # number of Writeback hits 683system.cpu.l2cache.Writeback_hits::total 1068580 # number of Writeback hits 684system.cpu.l2cache.ReadExReq_hits::cpu.data 255508 # number of ReadExReq hits 685system.cpu.l2cache.ReadExReq_hits::total 255508 # number of ReadExReq hits 686system.cpu.l2cache.demand_hits::cpu.inst 16103 # number of demand (read+write) hits 687system.cpu.l2cache.demand_hits::cpu.data 1003184 # number of demand (read+write) hits 688system.cpu.l2cache.demand_hits::total 1019287 # number of demand (read+write) hits 689system.cpu.l2cache.overall_hits::cpu.inst 16103 # number of overall hits 690system.cpu.l2cache.overall_hits::cpu.data 1003184 # number of overall hits 691system.cpu.l2cache.overall_hits::total 1019287 # number of overall hits 692system.cpu.l2cache.ReadReq_misses::cpu.inst 3462 # number of ReadReq misses 693system.cpu.l2cache.ReadReq_misses::cpu.data 39862 # number of ReadReq misses 694system.cpu.l2cache.ReadReq_misses::total 43324 # number of ReadReq misses 695system.cpu.l2cache.ReadExReq_misses::cpu.data 100906 # number of ReadExReq misses 696system.cpu.l2cache.ReadExReq_misses::total 100906 # number of ReadExReq misses 697system.cpu.l2cache.demand_misses::cpu.inst 3462 # number of demand (read+write) misses 698system.cpu.l2cache.demand_misses::cpu.data 140768 # number of demand (read+write) misses 699system.cpu.l2cache.demand_misses::total 144230 # number of demand (read+write) misses 700system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses 701system.cpu.l2cache.overall_misses::cpu.data 140768 # number of overall misses 702system.cpu.l2cache.overall_misses::total 144230 # number of overall misses 703system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 272932750 # number of ReadReq miss cycles 704system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3295008250 # number of ReadReq miss cycles 705system.cpu.l2cache.ReadReq_miss_latency::total 3567941000 # number of ReadReq miss cycles 706system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7933719500 # number of ReadExReq miss cycles 707system.cpu.l2cache.ReadExReq_miss_latency::total 7933719500 # number of ReadExReq miss cycles 708system.cpu.l2cache.demand_miss_latency::cpu.inst 272932750 # number of demand (read+write) miss cycles 709system.cpu.l2cache.demand_miss_latency::cpu.data 11228727750 # number of demand (read+write) miss cycles 710system.cpu.l2cache.demand_miss_latency::total 11501660500 # number of demand (read+write) miss cycles 711system.cpu.l2cache.overall_miss_latency::cpu.inst 272932750 # number of overall miss cycles 712system.cpu.l2cache.overall_miss_latency::cpu.data 11228727750 # number of overall miss cycles 713system.cpu.l2cache.overall_miss_latency::total 11501660500 # number of overall miss cycles 714system.cpu.l2cache.ReadReq_accesses::cpu.inst 19565 # number of ReadReq accesses(hits+misses) 715system.cpu.l2cache.ReadReq_accesses::cpu.data 787538 # number of ReadReq accesses(hits+misses) 716system.cpu.l2cache.ReadReq_accesses::total 807103 # number of ReadReq accesses(hits+misses) 717system.cpu.l2cache.Writeback_accesses::writebacks 1068580 # number of Writeback accesses(hits+misses) 718system.cpu.l2cache.Writeback_accesses::total 1068580 # number of Writeback accesses(hits+misses) 719system.cpu.l2cache.ReadExReq_accesses::cpu.data 356414 # number of ReadExReq accesses(hits+misses) 720system.cpu.l2cache.ReadExReq_accesses::total 356414 # number of ReadExReq accesses(hits+misses) 721system.cpu.l2cache.demand_accesses::cpu.inst 19565 # number of demand (read+write) accesses 722system.cpu.l2cache.demand_accesses::cpu.data 1143952 # number of demand (read+write) accesses 723system.cpu.l2cache.demand_accesses::total 1163517 # number of demand (read+write) accesses 724system.cpu.l2cache.overall_accesses::cpu.inst 19565 # number of overall (read+write) accesses 725system.cpu.l2cache.overall_accesses::cpu.data 1143952 # number of overall (read+write) accesses 726system.cpu.l2cache.overall_accesses::total 1163517 # number of overall (read+write) accesses 727system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.176949 # miss rate for ReadReq accesses 728system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050616 # miss rate for ReadReq accesses 729system.cpu.l2cache.ReadReq_miss_rate::total 0.053678 # miss rate for ReadReq accesses 730system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283115 # miss rate for ReadExReq accesses 731system.cpu.l2cache.ReadExReq_miss_rate::total 0.283115 # miss rate for ReadExReq accesses 732system.cpu.l2cache.demand_miss_rate::cpu.inst 0.176949 # miss rate for demand accesses 733system.cpu.l2cache.demand_miss_rate::cpu.data 0.123054 # miss rate for demand accesses 734system.cpu.l2cache.demand_miss_rate::total 0.123960 # miss rate for demand accesses 735system.cpu.l2cache.overall_miss_rate::cpu.inst 0.176949 # miss rate for overall accesses 736system.cpu.l2cache.overall_miss_rate::cpu.data 0.123054 # miss rate for overall accesses 737system.cpu.l2cache.overall_miss_rate::total 0.123960 # miss rate for overall accesses 738system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78836.727325 # average ReadReq miss latency 739system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82660.384577 # average ReadReq miss latency 740system.cpu.l2cache.ReadReq_avg_miss_latency::total 82354.837965 # average ReadReq miss latency 741system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78624.853824 # average ReadExReq miss latency 742system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78624.853824 # average ReadExReq miss latency 743system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78836.727325 # average overall miss latency 744system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79767.615864 # average overall miss latency 745system.cpu.l2cache.demand_avg_miss_latency::total 79745.271441 # average overall miss latency 746system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78836.727325 # average overall miss latency 747system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79767.615864 # average overall miss latency 748system.cpu.l2cache.overall_avg_miss_latency::total 79745.271441 # average overall miss latency 749system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 750system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 751system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 752system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 753system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 754system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 755system.cpu.l2cache.fast_writes 0 # number of fast writes performed 756system.cpu.l2cache.cache_copies 0 # number of cache copies performed 757system.cpu.l2cache.writebacks::writebacks 96596 # number of writebacks 758system.cpu.l2cache.writebacks::total 96596 # number of writebacks 759system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 760system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits 761system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 762system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 763system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits 764system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 765system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 766system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits 767system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 768system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3460 # number of ReadReq MSHR misses 769system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39847 # number of ReadReq MSHR misses 770system.cpu.l2cache.ReadReq_mshr_misses::total 43307 # number of ReadReq MSHR misses 771system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100906 # number of ReadExReq MSHR misses 772system.cpu.l2cache.ReadExReq_mshr_misses::total 100906 # number of ReadExReq MSHR misses 773system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses 774system.cpu.l2cache.demand_mshr_misses::cpu.data 140753 # number of demand (read+write) MSHR misses 775system.cpu.l2cache.demand_mshr_misses::total 144213 # number of demand (read+write) MSHR misses 776system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses 777system.cpu.l2cache.overall_mshr_misses::cpu.data 140753 # number of overall MSHR misses 778system.cpu.l2cache.overall_mshr_misses::total 144213 # number of overall MSHR misses 779system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 229496250 # number of ReadReq MSHR miss cycles 780system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2794594500 # number of ReadReq MSHR miss cycles 781system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3024090750 # number of ReadReq MSHR miss cycles 782system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6671817000 # number of ReadExReq MSHR miss cycles 783system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6671817000 # number of ReadExReq MSHR miss cycles 784system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229496250 # number of demand (read+write) MSHR miss cycles 785system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9466411500 # number of demand (read+write) MSHR miss cycles 786system.cpu.l2cache.demand_mshr_miss_latency::total 9695907750 # number of demand (read+write) MSHR miss cycles 787system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229496250 # number of overall MSHR miss cycles 788system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9466411500 # number of overall MSHR miss cycles 789system.cpu.l2cache.overall_mshr_miss_latency::total 9695907750 # number of overall MSHR miss cycles 790system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for ReadReq accesses 791system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses 792system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053657 # mshr miss rate for ReadReq accesses 793system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283115 # mshr miss rate for ReadExReq accesses 794system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283115 # mshr miss rate for ReadExReq accesses 795system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for demand accesses 796system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123041 # mshr miss rate for demand accesses 797system.cpu.l2cache.demand_mshr_miss_rate::total 0.123946 # mshr miss rate for demand accesses 798system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for overall accesses 799system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123041 # mshr miss rate for overall accesses 800system.cpu.l2cache.overall_mshr_miss_rate::total 0.123946 # mshr miss rate for overall accesses 801system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66328.395954 # average ReadReq mshr miss latency 802system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70133.121690 # average ReadReq mshr miss latency 803system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69829.144249 # average ReadReq mshr miss latency 804system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66119.130676 # average ReadExReq mshr miss latency 805system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66119.130676 # average ReadExReq mshr miss latency 806system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66328.395954 # average overall mshr miss latency 807system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67255.486562 # average overall mshr miss latency 808system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67233.243536 # average overall mshr miss latency 809system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66328.395954 # average overall mshr miss latency 810system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67255.486562 # average overall mshr miss latency 811system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67233.243536 # average overall mshr miss latency 812system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 813system.cpu.toL2Bus.trans_dist::ReadReq 807103 # Transaction distribution 814system.cpu.toL2Bus.trans_dist::ReadResp 807103 # Transaction distribution 815system.cpu.toL2Bus.trans_dist::Writeback 1068580 # Transaction distribution 816system.cpu.toL2Bus.trans_dist::ReadExReq 356414 # Transaction distribution 817system.cpu.toL2Bus.trans_dist::ReadExResp 356414 # Transaction distribution 818system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39130 # Packet count per connected master and slave (bytes) 819system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356484 # Packet count per connected master and slave (bytes) 820system.cpu.toL2Bus.pkt_count::total 3395614 # Packet count per connected master and slave (bytes) 821system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252160 # Cumulative packet size per connected master and slave (bytes) 822system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141602048 # Cumulative packet size per connected master and slave (bytes) 823system.cpu.toL2Bus.pkt_size::total 142854208 # Cumulative packet size per connected master and slave (bytes) 824system.cpu.toL2Bus.snoops 0 # Total snoops (count) 825system.cpu.toL2Bus.snoop_fanout::samples 2232097 # Request fanout histogram 826system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 827system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 828system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 829system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 830system.cpu.toL2Bus.snoop_fanout::1 2232097 100.00% 100.00% # Request fanout histogram 831system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 832system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 833system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 834system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 835system.cpu.toL2Bus.snoop_fanout::total 2232097 # Request fanout histogram 836system.cpu.toL2Bus.reqLayer0.occupancy 2184628500 # Layer occupancy (ticks) 837system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 838system.cpu.toL2Bus.respLayer0.occupancy 30040746 # Layer occupancy (ticks) 839system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 840system.cpu.toL2Bus.respLayer1.occupancy 1744732235 # Layer occupancy (ticks) 841system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 842system.membus.trans_dist::ReadReq 43307 # Transaction distribution 843system.membus.trans_dist::ReadResp 43307 # Transaction distribution 844system.membus.trans_dist::Writeback 96596 # Transaction distribution 845system.membus.trans_dist::ReadExReq 100906 # Transaction distribution 846system.membus.trans_dist::ReadExResp 100906 # Transaction distribution 847system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 385022 # Packet count per connected master and slave (bytes) 848system.membus.pkt_count::total 385022 # Packet count per connected master and slave (bytes) 849system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15411776 # Cumulative packet size per connected master and slave (bytes) 850system.membus.pkt_size::total 15411776 # Cumulative packet size per connected master and slave (bytes) 851system.membus.snoops 0 # Total snoops (count) 852system.membus.snoop_fanout::samples 240809 # Request fanout histogram 853system.membus.snoop_fanout::mean 0 # Request fanout histogram 854system.membus.snoop_fanout::stdev 0 # Request fanout histogram 855system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 856system.membus.snoop_fanout::0 240809 100.00% 100.00% # Request fanout histogram 857system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 858system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 859system.membus.snoop_fanout::min_value 0 # Request fanout histogram 860system.membus.snoop_fanout::max_value 0 # Request fanout histogram 861system.membus.snoop_fanout::total 240809 # Request fanout histogram 862system.membus.reqLayer0.occupancy 679106500 # Layer occupancy (ticks) 863system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 864system.membus.respLayer1.occupancy 765494750 # Layer occupancy (ticks) 865system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 866 867---------- End Simulation Statistics ---------- 868