stats.txt revision 10628:c9b7e0c69f88
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365317 # Number of seconds simulated 4sim_ticks 365317233000 # Number of ticks simulated 5final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 241300 # Simulator instruction rate (inst/s) 8host_op_rate 261360 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 174011250 # Simulator tick rate (ticks/s) 10host_mem_usage 315696 # Number of bytes of host memory used 11host_seconds 2099.39 # Real time elapsed on the host 12sim_insts 506582155 # Number of instructions simulated 13sim_ops 548695378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 9226048 # Number of bytes read from this memory 17system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 222144 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory 21system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 144157 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 25254894 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 25254894 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 144157 # Number of read requests accepted 36system.physmem.writeReqs 96561 # Number of write requests accepted 37system.physmem.readBursts 144157 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 96561 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 9219904 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue 41system.physmem.bytesWritten 6178688 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 9226048 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 6179904 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 47system.physmem.perBankRdBursts::0 9347 # Per bank write bursts 48system.physmem.perBankRdBursts::1 8970 # Per bank write bursts 49system.physmem.perBankRdBursts::2 8998 # Per bank write bursts 50system.physmem.perBankRdBursts::3 8695 # Per bank write bursts 51system.physmem.perBankRdBursts::4 9455 # Per bank write bursts 52system.physmem.perBankRdBursts::5 9342 # Per bank write bursts 53system.physmem.perBankRdBursts::6 8947 # Per bank write bursts 54system.physmem.perBankRdBursts::7 8101 # Per bank write bursts 55system.physmem.perBankRdBursts::8 8578 # Per bank write bursts 56system.physmem.perBankRdBursts::9 8679 # Per bank write bursts 57system.physmem.perBankRdBursts::10 8774 # Per bank write bursts 58system.physmem.perBankRdBursts::11 9477 # Per bank write bursts 59system.physmem.perBankRdBursts::12 9374 # Per bank write bursts 60system.physmem.perBankRdBursts::13 9525 # Per bank write bursts 61system.physmem.perBankRdBursts::14 8712 # Per bank write bursts 62system.physmem.perBankRdBursts::15 9087 # Per bank write bursts 63system.physmem.perBankWrBursts::0 6196 # Per bank write bursts 64system.physmem.perBankWrBursts::1 6092 # Per bank write bursts 65system.physmem.perBankWrBursts::2 6006 # Per bank write bursts 66system.physmem.perBankWrBursts::3 5813 # Per bank write bursts 67system.physmem.perBankWrBursts::4 6163 # Per bank write bursts 68system.physmem.perBankWrBursts::5 6172 # Per bank write bursts 69system.physmem.perBankWrBursts::6 6014 # Per bank write bursts 70system.physmem.perBankWrBursts::7 5493 # Per bank write bursts 71system.physmem.perBankWrBursts::8 5728 # Per bank write bursts 72system.physmem.perBankWrBursts::9 5823 # Per bank write bursts 73system.physmem.perBankWrBursts::10 5962 # Per bank write bursts 74system.physmem.perBankWrBursts::11 6445 # Per bank write bursts 75system.physmem.perBankWrBursts::12 6308 # Per bank write bursts 76system.physmem.perBankWrBursts::13 6282 # Per bank write bursts 77system.physmem.perBankWrBursts::14 5997 # Per bank write bursts 78system.physmem.perBankWrBursts::15 6048 # Per bank write bursts 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 81system.physmem.totGap 365317203500 # Total gap between requests 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) 88system.physmem.readPktSize::6 144157 # Read request sizes (log2) 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) 95system.physmem.writePktSize::6 96561 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 128system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::15 2939 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 5543 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 5664 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 5672 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 5680 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 5680 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 5691 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 5692 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 5666 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 5669 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 5692 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 5677 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 5643 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 5596 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 192system.physmem.bytesPerActivate::samples 65080 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 236.601352 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 156.588709 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 242.751381 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 24737 38.01% 38.01% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 18138 27.87% 65.88% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 6930 10.65% 76.53% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 7871 12.09% 88.62% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 2125 3.27% 91.89% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1134 1.74% 93.63% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 708 1.09% 94.72% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 644 0.99% 95.71% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 2793 4.29% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 65080 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 25.854092 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 382.114973 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes 210system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes 213system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads 214system.physmem.wrPerTurnAround::mean 17.326274 # Writes before turning the bus around for reads 215system.physmem.wrPerTurnAround::gmean 17.230410 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::stdev 2.286782 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::16-17 2628 47.16% 47.16% # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::18-19 2789 50.05% 97.22% # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::20-21 53 0.95% 98.17% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::22-23 30 0.54% 98.71% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::24-25 23 0.41% 99.12% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::26-27 9 0.16% 99.28% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::28-29 9 0.16% 99.44% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::30-31 6 0.11% 99.55% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::32-33 7 0.13% 99.68% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::34-35 3 0.05% 99.73% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::36-37 1 0.02% 99.75% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::38-39 4 0.07% 99.82% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::42-43 2 0.04% 99.87% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::44-45 2 0.04% 99.91% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::46-47 2 0.04% 99.95% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::54-55 1 0.02% 99.96% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads 237system.physmem.totQLat 1534207250 # Total ticks spent queuing 238system.physmem.totMemAccLat 4235351000 # Total ticks spent from burst creation until serviced by the DRAM 239system.physmem.totBusLat 720305000 # Total ticks spent in databus transfers 240system.physmem.avgQLat 10649.71 # Average queueing delay per DRAM burst 241system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 242system.physmem.avgMemAccLat 29399.71 # Average memory access latency per DRAM burst 243system.physmem.avgRdBW 25.24 # Average DRAM read bandwidth in MiByte/s 244system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s 245system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s 246system.physmem.avgWrBWSys 16.92 # Average system write bandwidth in MiByte/s 247system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 248system.physmem.busUtil 0.33 # Data bus utilization in percentage 249system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 250system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 251system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 252system.physmem.avgWrQLen 20.29 # Average write queue length when enqueuing 253system.physmem.readRowHits 111019 # Number of row buffer hits during reads 254system.physmem.writeRowHits 64498 # Number of row buffer hits during writes 255system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads 256system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes 257system.physmem.avgGap 1517614.82 # Average gap between requests 258system.physmem.pageHitRate 72.94 # Row buffer hit rate, read and write combined 259system.physmem_0.actEnergy 247892400 # Energy for activate commands per rank (pJ) 260system.physmem_0.preEnergy 135258750 # Energy for precharge commands per rank (pJ) 261system.physmem_0.readEnergy 560445600 # Energy for read commands per rank (pJ) 262system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ) 263system.physmem_0.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) 264system.physmem_0.actBackEnergy 47138982615 # Energy for active background per rank (pJ) 265system.physmem_0.preBackEnergy 177839337750 # Energy for precharge background per rank (pJ) 266system.physmem_0.totalEnergy 250093102155 # Total energy per rank (pJ) 267system.physmem_0.averagePower 684.594758 # Core power per rank (mW) 268system.physmem_0.memoryStateTime::IDLE 295545266000 # Time in different power states 269system.physmem_0.memoryStateTime::REF 12198680000 # Time in different power states 270system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 271system.physmem_0.memoryStateTime::ACT 57571800000 # Time in different power states 272system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 273system.physmem_1.actEnergy 244014120 # Energy for activate commands per rank (pJ) 274system.physmem_1.preEnergy 133142625 # Energy for precharge commands per rank (pJ) 275system.physmem_1.readEnergy 563058600 # Energy for read commands per rank (pJ) 276system.physmem_1.writeEnergy 314817840 # Energy for write commands per rank (pJ) 277system.physmem_1.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) 278system.physmem_1.actBackEnergy 46734210225 # Energy for active background per rank (pJ) 279system.physmem_1.preBackEnergy 178194401250 # Energy for precharge background per rank (pJ) 280system.physmem_1.totalEnergy 250044262740 # Total energy per rank (pJ) 281system.physmem_1.averagePower 684.461067 # Core power per rank (mW) 282system.physmem_1.memoryStateTime::IDLE 296138902500 # Time in different power states 283system.physmem_1.memoryStateTime::REF 12198680000 # Time in different power states 284system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_1.memoryStateTime::ACT 56977968750 # Time in different power states 286system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 287system.cpu.branchPred.lookups 132578917 # Number of BP lookups 288system.cpu.branchPred.condPredicted 98507789 # Number of conditional branches predicted 289system.cpu.branchPred.condIncorrect 6555100 # Number of conditional branches incorrect 290system.cpu.branchPred.BTBLookups 69037584 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 64855119 # Number of BTB hits 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 293system.cpu.branchPred.BTBHitPct 93.941756 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 10014942 # Number of times the RAS was used to get a target. 295system.cpu.branchPred.RASInCorrect 17500 # Number of incorrect RAS predictions. 296system.cpu_clk_domain.clock 500 # Clock period in ticks 297system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 306system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 307system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 308system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 309system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 310system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 311system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 314system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 315system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 316system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 317system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 318system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 319system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 320system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 321system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 322system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 323system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 324system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 325system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 326system.cpu.dtb.walker.walks 0 # Table walker walks requested 327system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.inst_hits 0 # ITB inst hits 335system.cpu.dtb.inst_misses 0 # ITB inst misses 336system.cpu.dtb.read_hits 0 # DTB read hits 337system.cpu.dtb.read_misses 0 # DTB read misses 338system.cpu.dtb.write_hits 0 # DTB write hits 339system.cpu.dtb.write_misses 0 # DTB write misses 340system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 341system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 342system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 343system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 344system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 345system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 346system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 347system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 348system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 349system.cpu.dtb.read_accesses 0 # DTB read accesses 350system.cpu.dtb.write_accesses 0 # DTB write accesses 351system.cpu.dtb.inst_accesses 0 # ITB inst accesses 352system.cpu.dtb.hits 0 # DTB hits 353system.cpu.dtb.misses 0 # DTB misses 354system.cpu.dtb.accesses 0 # DTB accesses 355system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 364system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 365system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 366system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 367system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 368system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 371system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 372system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 373system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 374system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 375system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 376system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 379system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 380system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 381system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 382system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 383system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 384system.cpu.itb.walker.walks 0 # Table walker walks requested 385system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.inst_hits 0 # ITB inst hits 393system.cpu.itb.inst_misses 0 # ITB inst misses 394system.cpu.itb.read_hits 0 # DTB read hits 395system.cpu.itb.read_misses 0 # DTB read misses 396system.cpu.itb.write_hits 0 # DTB write hits 397system.cpu.itb.write_misses 0 # DTB write misses 398system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 399system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 400system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 401system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 402system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 403system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 404system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 405system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 406system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 407system.cpu.itb.read_accesses 0 # DTB read accesses 408system.cpu.itb.write_accesses 0 # DTB write accesses 409system.cpu.itb.inst_accesses 0 # ITB inst accesses 410system.cpu.itb.hits 0 # DTB hits 411system.cpu.itb.misses 0 # DTB misses 412system.cpu.itb.accesses 0 # DTB accesses 413system.cpu.workload.num_syscalls 548 # Number of system calls 414system.cpu.numCycles 730634466 # number of cpu cycles simulated 415system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 416system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 417system.cpu.committedInsts 506582155 # Number of instructions committed 418system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed 419system.cpu.discardedOps 13461155 # Number of ops (including micro ops) which were discarded before commit 420system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 421system.cpu.cpi 1.442282 # CPI: cycles per instruction 422system.cpu.ipc 0.693346 # IPC: instructions per cycle 423system.cpu.tickCycles 695780172 # Number of cycles that the object actually ticked 424system.cpu.idleCycles 34854294 # Total number of cycles that the object has spent stopped 425system.cpu.dcache.tags.replacements 1139812 # number of replacements 426system.cpu.dcache.tags.tagsinuse 4071.074819 # Cycle average of tags in use 427system.cpu.dcache.tags.total_refs 171281876 # Total number of references to valid blocks. 428system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks. 429system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks. 430system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. 431system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.074819 # Average occupied blocks per requestor 432system.cpu.dcache.tags.occ_percent::cpu.inst 0.993915 # Average percentage of cache occupancy 433system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy 434system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 435system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 436system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 437system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id 438system.cpu.dcache.tags.age_task_id_blocks_1024::3 3506 # Occupied blocks per task id 439system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 440system.cpu.dcache.tags.tag_accesses 346818362 # Number of tag accesses 441system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses 442system.cpu.dcache.ReadReq_hits::cpu.inst 114766084 # number of ReadReq hits 443system.cpu.dcache.ReadReq_hits::total 114766084 # number of ReadReq hits 444system.cpu.dcache.WriteReq_hits::cpu.inst 53538710 # number of WriteReq hits 445system.cpu.dcache.WriteReq_hits::total 53538710 # number of WriteReq hits 446system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits 447system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 448system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits 449system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 450system.cpu.dcache.demand_hits::cpu.inst 168304794 # number of demand (read+write) hits 451system.cpu.dcache.demand_hits::total 168304794 # number of demand (read+write) hits 452system.cpu.dcache.overall_hits::cpu.inst 168304794 # number of overall hits 453system.cpu.dcache.overall_hits::total 168304794 # number of overall hits 454system.cpu.dcache.ReadReq_misses::cpu.inst 854755 # number of ReadReq misses 455system.cpu.dcache.ReadReq_misses::total 854755 # number of ReadReq misses 456system.cpu.dcache.WriteReq_misses::cpu.inst 700596 # number of WriteReq misses 457system.cpu.dcache.WriteReq_misses::total 700596 # number of WriteReq misses 458system.cpu.dcache.demand_misses::cpu.inst 1555351 # number of demand (read+write) misses 459system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses 460system.cpu.dcache.overall_misses::cpu.inst 1555351 # number of overall misses 461system.cpu.dcache.overall_misses::total 1555351 # number of overall misses 462system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13707430482 # number of ReadReq miss cycles 463system.cpu.dcache.ReadReq_miss_latency::total 13707430482 # number of ReadReq miss cycles 464system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20521575250 # number of WriteReq miss cycles 465system.cpu.dcache.WriteReq_miss_latency::total 20521575250 # number of WriteReq miss cycles 466system.cpu.dcache.demand_miss_latency::cpu.inst 34229005732 # number of demand (read+write) miss cycles 467system.cpu.dcache.demand_miss_latency::total 34229005732 # number of demand (read+write) miss cycles 468system.cpu.dcache.overall_miss_latency::cpu.inst 34229005732 # number of overall miss cycles 469system.cpu.dcache.overall_miss_latency::total 34229005732 # number of overall miss cycles 470system.cpu.dcache.ReadReq_accesses::cpu.inst 115620839 # number of ReadReq accesses(hits+misses) 471system.cpu.dcache.ReadReq_accesses::total 115620839 # number of ReadReq accesses(hits+misses) 472system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) 473system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 474system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) 475system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 476system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) 477system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 478system.cpu.dcache.demand_accesses::cpu.inst 169860145 # number of demand (read+write) accesses 479system.cpu.dcache.demand_accesses::total 169860145 # number of demand (read+write) accesses 480system.cpu.dcache.overall_accesses::cpu.inst 169860145 # number of overall (read+write) accesses 481system.cpu.dcache.overall_accesses::total 169860145 # number of overall (read+write) accesses 482system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007393 # miss rate for ReadReq accesses 483system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses 484system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses 485system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses 486system.cpu.dcache.demand_miss_rate::cpu.inst 0.009157 # miss rate for demand accesses 487system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses 488system.cpu.dcache.overall_miss_rate::cpu.inst 0.009157 # miss rate for overall accesses 489system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses 490system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16036.677740 # average ReadReq miss latency 491system.cpu.dcache.ReadReq_avg_miss_latency::total 16036.677740 # average ReadReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29291.596369 # average WriteReq miss latency 493system.cpu.dcache.WriteReq_avg_miss_latency::total 29291.596369 # average WriteReq miss latency 494system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22007.254782 # average overall miss latency 495system.cpu.dcache.demand_avg_miss_latency::total 22007.254782 # average overall miss latency 496system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22007.254782 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::total 22007.254782 # average overall miss latency 498system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 499system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 500system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 501system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 502system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 504system.cpu.dcache.fast_writes 0 # number of fast writes performed 505system.cpu.dcache.cache_copies 0 # number of cache copies performed 506system.cpu.dcache.writebacks::writebacks 1068525 # number of writebacks 507system.cpu.dcache.writebacks::total 1068525 # number of writebacks 508system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66991 # number of ReadReq MSHR hits 509system.cpu.dcache.ReadReq_mshr_hits::total 66991 # number of ReadReq MSHR hits 510system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344452 # number of WriteReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::total 344452 # number of WriteReq MSHR hits 512system.cpu.dcache.demand_mshr_hits::cpu.inst 411443 # number of demand (read+write) MSHR hits 513system.cpu.dcache.demand_mshr_hits::total 411443 # number of demand (read+write) MSHR hits 514system.cpu.dcache.overall_mshr_hits::cpu.inst 411443 # number of overall MSHR hits 515system.cpu.dcache.overall_mshr_hits::total 411443 # number of overall MSHR hits 516system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787764 # number of ReadReq MSHR misses 517system.cpu.dcache.ReadReq_mshr_misses::total 787764 # number of ReadReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356144 # number of WriteReq MSHR misses 519system.cpu.dcache.WriteReq_mshr_misses::total 356144 # number of WriteReq MSHR misses 520system.cpu.dcache.demand_mshr_misses::cpu.inst 1143908 # number of demand (read+write) MSHR misses 521system.cpu.dcache.demand_mshr_misses::total 1143908 # number of demand (read+write) MSHR misses 522system.cpu.dcache.overall_mshr_misses::cpu.inst 1143908 # number of overall MSHR misses 523system.cpu.dcache.overall_mshr_misses::total 1143908 # number of overall MSHR misses 524system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11252029015 # number of ReadReq MSHR miss cycles 525system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252029015 # number of ReadReq MSHR miss cycles 526system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10073374750 # number of WriteReq MSHR miss cycles 527system.cpu.dcache.WriteReq_mshr_miss_latency::total 10073374750 # number of WriteReq MSHR miss cycles 528system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21325403765 # number of demand (read+write) MSHR miss cycles 529system.cpu.dcache.demand_mshr_miss_latency::total 21325403765 # number of demand (read+write) MSHR miss cycles 530system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21325403765 # number of overall MSHR miss cycles 531system.cpu.dcache.overall_mshr_miss_latency::total 21325403765 # number of overall MSHR miss cycles 532system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for ReadReq accesses 533system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses 534system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses 535system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses 536system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006734 # mshr miss rate for demand accesses 537system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses 538system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006734 # mshr miss rate for overall accesses 539system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses 540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14283.502439 # average ReadReq mshr miss latency 541system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14283.502439 # average ReadReq mshr miss latency 542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28284.555545 # average WriteReq mshr miss latency 543system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28284.555545 # average WriteReq mshr miss latency 544system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18642.586436 # average overall mshr miss latency 545system.cpu.dcache.demand_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency 546system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18642.586436 # average overall mshr miss latency 547system.cpu.dcache.overall_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency 548system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 549system.cpu.icache.tags.replacements 17690 # number of replacements 550system.cpu.icache.tags.tagsinuse 1190.635807 # Cycle average of tags in use 551system.cpu.icache.tags.total_refs 200942292 # Total number of references to valid blocks. 552system.cpu.icache.tags.sampled_refs 19563 # Sample count of references to valid blocks. 553system.cpu.icache.tags.avg_refs 10271.547922 # Average number of references to valid blocks. 554system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 555system.cpu.icache.tags.occ_blocks::cpu.inst 1190.635807 # Average occupied blocks per requestor 556system.cpu.icache.tags.occ_percent::cpu.inst 0.581365 # Average percentage of cache occupancy 557system.cpu.icache.tags.occ_percent::total 0.581365 # Average percentage of cache occupancy 558system.cpu.icache.tags.occ_task_id_blocks::1024 1873 # Occupied blocks per task id 559system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 560system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id 561system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id 562system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id 563system.cpu.icache.tags.age_task_id_blocks_1024::4 1406 # Occupied blocks per task id 564system.cpu.icache.tags.occ_task_id_percent::1024 0.914551 # Percentage of cache occupancy per task id 565system.cpu.icache.tags.tag_accesses 401943273 # Number of tag accesses 566system.cpu.icache.tags.data_accesses 401943273 # Number of data accesses 567system.cpu.icache.ReadReq_hits::cpu.inst 200942292 # number of ReadReq hits 568system.cpu.icache.ReadReq_hits::total 200942292 # number of ReadReq hits 569system.cpu.icache.demand_hits::cpu.inst 200942292 # number of demand (read+write) hits 570system.cpu.icache.demand_hits::total 200942292 # number of demand (read+write) hits 571system.cpu.icache.overall_hits::cpu.inst 200942292 # number of overall hits 572system.cpu.icache.overall_hits::total 200942292 # number of overall hits 573system.cpu.icache.ReadReq_misses::cpu.inst 19563 # number of ReadReq misses 574system.cpu.icache.ReadReq_misses::total 19563 # number of ReadReq misses 575system.cpu.icache.demand_misses::cpu.inst 19563 # number of demand (read+write) misses 576system.cpu.icache.demand_misses::total 19563 # number of demand (read+write) misses 577system.cpu.icache.overall_misses::cpu.inst 19563 # number of overall misses 578system.cpu.icache.overall_misses::total 19563 # number of overall misses 579system.cpu.icache.ReadReq_miss_latency::cpu.inst 469537995 # number of ReadReq miss cycles 580system.cpu.icache.ReadReq_miss_latency::total 469537995 # number of ReadReq miss cycles 581system.cpu.icache.demand_miss_latency::cpu.inst 469537995 # number of demand (read+write) miss cycles 582system.cpu.icache.demand_miss_latency::total 469537995 # number of demand (read+write) miss cycles 583system.cpu.icache.overall_miss_latency::cpu.inst 469537995 # number of overall miss cycles 584system.cpu.icache.overall_miss_latency::total 469537995 # number of overall miss cycles 585system.cpu.icache.ReadReq_accesses::cpu.inst 200961855 # number of ReadReq accesses(hits+misses) 586system.cpu.icache.ReadReq_accesses::total 200961855 # number of ReadReq accesses(hits+misses) 587system.cpu.icache.demand_accesses::cpu.inst 200961855 # number of demand (read+write) accesses 588system.cpu.icache.demand_accesses::total 200961855 # number of demand (read+write) accesses 589system.cpu.icache.overall_accesses::cpu.inst 200961855 # number of overall (read+write) accesses 590system.cpu.icache.overall_accesses::total 200961855 # number of overall (read+write) accesses 591system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses 592system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses 593system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses 594system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses 595system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses 596system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses 597system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24001.328784 # average ReadReq miss latency 598system.cpu.icache.ReadReq_avg_miss_latency::total 24001.328784 # average ReadReq miss latency 599system.cpu.icache.demand_avg_miss_latency::cpu.inst 24001.328784 # average overall miss latency 600system.cpu.icache.demand_avg_miss_latency::total 24001.328784 # average overall miss latency 601system.cpu.icache.overall_avg_miss_latency::cpu.inst 24001.328784 # average overall miss latency 602system.cpu.icache.overall_avg_miss_latency::total 24001.328784 # average overall miss latency 603system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 604system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 605system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 606system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 607system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 608system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 609system.cpu.icache.fast_writes 0 # number of fast writes performed 610system.cpu.icache.cache_copies 0 # number of cache copies performed 611system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19563 # number of ReadReq MSHR misses 612system.cpu.icache.ReadReq_mshr_misses::total 19563 # number of ReadReq MSHR misses 613system.cpu.icache.demand_mshr_misses::cpu.inst 19563 # number of demand (read+write) MSHR misses 614system.cpu.icache.demand_mshr_misses::total 19563 # number of demand (read+write) MSHR misses 615system.cpu.icache.overall_mshr_misses::cpu.inst 19563 # number of overall MSHR misses 616system.cpu.icache.overall_mshr_misses::total 19563 # number of overall MSHR misses 617system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429024005 # number of ReadReq MSHR miss cycles 618system.cpu.icache.ReadReq_mshr_miss_latency::total 429024005 # number of ReadReq MSHR miss cycles 619system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429024005 # number of demand (read+write) MSHR miss cycles 620system.cpu.icache.demand_mshr_miss_latency::total 429024005 # number of demand (read+write) MSHR miss cycles 621system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429024005 # number of overall MSHR miss cycles 622system.cpu.icache.overall_mshr_miss_latency::total 429024005 # number of overall MSHR miss cycles 623system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses 624system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses 625system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses 626system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses 627system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses 628system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses 629system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21930.379032 # average ReadReq mshr miss latency 630system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21930.379032 # average ReadReq mshr miss latency 631system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21930.379032 # average overall mshr miss latency 632system.cpu.icache.demand_avg_mshr_miss_latency::total 21930.379032 # average overall mshr miss latency 633system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21930.379032 # average overall mshr miss latency 634system.cpu.icache.overall_avg_mshr_miss_latency::total 21930.379032 # average overall mshr miss latency 635system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 636system.cpu.l2cache.tags.replacements 111403 # number of replacements 637system.cpu.l2cache.tags.tagsinuse 27648.458293 # Cycle average of tags in use 638system.cpu.l2cache.tags.total_refs 1684717 # Total number of references to valid blocks. 639system.cpu.l2cache.tags.sampled_refs 142590 # Sample count of references to valid blocks. 640system.cpu.l2cache.tags.avg_refs 11.815113 # Average number of references to valid blocks. 641system.cpu.l2cache.tags.warmup_cycle 163177408500 # Cycle when the warmup percentage was hit. 642system.cpu.l2cache.tags.occ_blocks::writebacks 23523.224801 # Average occupied blocks per requestor 643system.cpu.l2cache.tags.occ_blocks::cpu.inst 4125.233493 # Average occupied blocks per requestor 644system.cpu.l2cache.tags.occ_percent::writebacks 0.717872 # Average percentage of cache occupancy 645system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125892 # Average percentage of cache occupancy 646system.cpu.l2cache.tags.occ_percent::total 0.843764 # Average percentage of cache occupancy 647system.cpu.l2cache.tags.occ_task_id_blocks::1024 31187 # Occupied blocks per task id 648system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 649system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id 650system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4940 # Occupied blocks per task id 651system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25856 # Occupied blocks per task id 652system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951752 # Percentage of cache occupancy per task id 653system.cpu.l2cache.tags.tag_accesses 18354956 # Number of tag accesses 654system.cpu.l2cache.tags.data_accesses 18354956 # Number of data accesses 655system.cpu.l2cache.ReadReq_hits::cpu.inst 763767 # number of ReadReq hits 656system.cpu.l2cache.ReadReq_hits::total 763767 # number of ReadReq hits 657system.cpu.l2cache.Writeback_hits::writebacks 1068525 # number of Writeback hits 658system.cpu.l2cache.Writeback_hits::total 1068525 # number of Writeback hits 659system.cpu.l2cache.ReadExReq_hits::cpu.inst 255530 # number of ReadExReq hits 660system.cpu.l2cache.ReadExReq_hits::total 255530 # number of ReadExReq hits 661system.cpu.l2cache.demand_hits::cpu.inst 1019297 # number of demand (read+write) hits 662system.cpu.l2cache.demand_hits::total 1019297 # number of demand (read+write) hits 663system.cpu.l2cache.overall_hits::cpu.inst 1019297 # number of overall hits 664system.cpu.l2cache.overall_hits::total 1019297 # number of overall hits 665system.cpu.l2cache.ReadReq_misses::cpu.inst 43306 # number of ReadReq misses 666system.cpu.l2cache.ReadReq_misses::total 43306 # number of ReadReq misses 667system.cpu.l2cache.ReadExReq_misses::cpu.inst 100868 # number of ReadExReq misses 668system.cpu.l2cache.ReadExReq_misses::total 100868 # number of ReadExReq misses 669system.cpu.l2cache.demand_misses::cpu.inst 144174 # number of demand (read+write) misses 670system.cpu.l2cache.demand_misses::total 144174 # number of demand (read+write) misses 671system.cpu.l2cache.overall_misses::cpu.inst 144174 # number of overall misses 672system.cpu.l2cache.overall_misses::total 144174 # number of overall misses 673system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3229271000 # number of ReadReq miss cycles 674system.cpu.l2cache.ReadReq_miss_latency::total 3229271000 # number of ReadReq miss cycles 675system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7164307250 # number of ReadExReq miss cycles 676system.cpu.l2cache.ReadExReq_miss_latency::total 7164307250 # number of ReadExReq miss cycles 677system.cpu.l2cache.demand_miss_latency::cpu.inst 10393578250 # number of demand (read+write) miss cycles 678system.cpu.l2cache.demand_miss_latency::total 10393578250 # number of demand (read+write) miss cycles 679system.cpu.l2cache.overall_miss_latency::cpu.inst 10393578250 # number of overall miss cycles 680system.cpu.l2cache.overall_miss_latency::total 10393578250 # number of overall miss cycles 681system.cpu.l2cache.ReadReq_accesses::cpu.inst 807073 # number of ReadReq accesses(hits+misses) 682system.cpu.l2cache.ReadReq_accesses::total 807073 # number of ReadReq accesses(hits+misses) 683system.cpu.l2cache.Writeback_accesses::writebacks 1068525 # number of Writeback accesses(hits+misses) 684system.cpu.l2cache.Writeback_accesses::total 1068525 # number of Writeback accesses(hits+misses) 685system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356398 # number of ReadExReq accesses(hits+misses) 686system.cpu.l2cache.ReadExReq_accesses::total 356398 # number of ReadExReq accesses(hits+misses) 687system.cpu.l2cache.demand_accesses::cpu.inst 1163471 # number of demand (read+write) accesses 688system.cpu.l2cache.demand_accesses::total 1163471 # number of demand (read+write) accesses 689system.cpu.l2cache.overall_accesses::cpu.inst 1163471 # number of overall (read+write) accesses 690system.cpu.l2cache.overall_accesses::total 1163471 # number of overall (read+write) accesses 691system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053658 # miss rate for ReadReq accesses 692system.cpu.l2cache.ReadReq_miss_rate::total 0.053658 # miss rate for ReadReq accesses 693system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283021 # miss rate for ReadExReq accesses 694system.cpu.l2cache.ReadExReq_miss_rate::total 0.283021 # miss rate for ReadExReq accesses 695system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123917 # miss rate for demand accesses 696system.cpu.l2cache.demand_miss_rate::total 0.123917 # miss rate for demand accesses 697system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123917 # miss rate for overall accesses 698system.cpu.l2cache.overall_miss_rate::total 0.123917 # miss rate for overall accesses 699system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74568.674087 # average ReadReq miss latency 700system.cpu.l2cache.ReadReq_avg_miss_latency::total 74568.674087 # average ReadReq miss latency 701system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71026.561942 # average ReadExReq miss latency 702system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71026.561942 # average ReadExReq miss latency 703system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72090.517361 # average overall miss latency 704system.cpu.l2cache.demand_avg_miss_latency::total 72090.517361 # average overall miss latency 705system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72090.517361 # average overall miss latency 706system.cpu.l2cache.overall_avg_miss_latency::total 72090.517361 # average overall miss latency 707system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 708system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 709system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 710system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 711system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 712system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 713system.cpu.l2cache.fast_writes 0 # number of fast writes performed 714system.cpu.l2cache.cache_copies 0 # number of cache copies performed 715system.cpu.l2cache.writebacks::writebacks 96561 # number of writebacks 716system.cpu.l2cache.writebacks::total 96561 # number of writebacks 717system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits 718system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 719system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits 720system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 721system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits 722system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 723system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43289 # number of ReadReq MSHR misses 724system.cpu.l2cache.ReadReq_mshr_misses::total 43289 # number of ReadReq MSHR misses 725system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100868 # number of ReadExReq MSHR misses 726system.cpu.l2cache.ReadExReq_mshr_misses::total 100868 # number of ReadExReq MSHR misses 727system.cpu.l2cache.demand_mshr_misses::cpu.inst 144157 # number of demand (read+write) MSHR misses 728system.cpu.l2cache.demand_mshr_misses::total 144157 # number of demand (read+write) MSHR misses 729system.cpu.l2cache.overall_mshr_misses::cpu.inst 144157 # number of overall MSHR misses 730system.cpu.l2cache.overall_mshr_misses::total 144157 # number of overall MSHR misses 731system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2680290500 # number of ReadReq MSHR miss cycles 732system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2680290500 # number of ReadReq MSHR miss cycles 733system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5883442250 # number of ReadExReq MSHR miss cycles 734system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5883442250 # number of ReadExReq MSHR miss cycles 735system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8563732750 # number of demand (read+write) MSHR miss cycles 736system.cpu.l2cache.demand_mshr_miss_latency::total 8563732750 # number of demand (read+write) MSHR miss cycles 737system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8563732750 # number of overall MSHR miss cycles 738system.cpu.l2cache.overall_mshr_miss_latency::total 8563732750 # number of overall MSHR miss cycles 739system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053637 # mshr miss rate for ReadReq accesses 740system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053637 # mshr miss rate for ReadReq accesses 741system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283021 # mshr miss rate for ReadExReq accesses 742system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283021 # mshr miss rate for ReadExReq accesses 743system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for demand accesses 744system.cpu.l2cache.demand_mshr_miss_rate::total 0.123903 # mshr miss rate for demand accesses 745system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123903 # mshr miss rate for overall accesses 746system.cpu.l2cache.overall_mshr_miss_rate::total 0.123903 # mshr miss rate for overall accesses 747system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61916.202730 # average ReadReq mshr miss latency 748system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61916.202730 # average ReadReq mshr miss latency 749system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58328.134294 # average ReadExReq mshr miss latency 750system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294 # average ReadExReq mshr miss latency 751system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency 752system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency 753system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59405.597716 # average overall mshr miss latency 754system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency 755system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 756system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution 757system.cpu.toL2Bus.trans_dist::ReadResp 807073 # Transaction distribution 758system.cpu.toL2Bus.trans_dist::Writeback 1068525 # Transaction distribution 759system.cpu.toL2Bus.trans_dist::ReadExReq 356398 # Transaction distribution 760system.cpu.toL2Bus.trans_dist::ReadExResp 356398 # Transaction distribution 761system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39126 # Packet count per connected master and slave (bytes) 762system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356341 # Packet count per connected master and slave (bytes) 763system.cpu.toL2Bus.pkt_count::total 3395467 # Packet count per connected master and slave (bytes) 764system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252032 # Cumulative packet size per connected master and slave (bytes) 765system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141595712 # Cumulative packet size per connected master and slave (bytes) 766system.cpu.toL2Bus.pkt_size::total 142847744 # Cumulative packet size per connected master and slave (bytes) 767system.cpu.toL2Bus.snoops 0 # Total snoops (count) 768system.cpu.toL2Bus.snoop_fanout::samples 2231996 # Request fanout histogram 769system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 770system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 771system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 772system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 773system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 774system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 775system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 776system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 777system.cpu.toL2Bus.snoop_fanout::5 2231996 100.00% 100.00% # Request fanout histogram 778system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 779system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 780system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 781system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 782system.cpu.toL2Bus.snoop_fanout::total 2231996 # Request fanout histogram 783system.cpu.toL2Bus.reqLayer0.occupancy 2184523000 # Layer occupancy (ticks) 784system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 785system.cpu.toL2Bus.respLayer0.occupancy 30038495 # Layer occupancy (ticks) 786system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 787system.cpu.toL2Bus.respLayer1.occupancy 1744651235 # Layer occupancy (ticks) 788system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 789system.membus.trans_dist::ReadReq 43289 # Transaction distribution 790system.membus.trans_dist::ReadResp 43289 # Transaction distribution 791system.membus.trans_dist::Writeback 96561 # Transaction distribution 792system.membus.trans_dist::ReadExReq 100868 # Transaction distribution 793system.membus.trans_dist::ReadExResp 100868 # Transaction distribution 794system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384875 # Packet count per connected master and slave (bytes) 795system.membus.pkt_count::total 384875 # Packet count per connected master and slave (bytes) 796system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15405952 # Cumulative packet size per connected master and slave (bytes) 797system.membus.pkt_size::total 15405952 # Cumulative packet size per connected master and slave (bytes) 798system.membus.snoops 0 # Total snoops (count) 799system.membus.snoop_fanout::samples 240718 # Request fanout histogram 800system.membus.snoop_fanout::mean 0 # Request fanout histogram 801system.membus.snoop_fanout::stdev 0 # Request fanout histogram 802system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 803system.membus.snoop_fanout::0 240718 100.00% 100.00% # Request fanout histogram 804system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 805system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 806system.membus.snoop_fanout::min_value 0 # Request fanout histogram 807system.membus.snoop_fanout::max_value 0 # Request fanout histogram 808system.membus.snoop_fanout::total 240718 # Request fanout histogram 809system.membus.reqLayer0.occupancy 1081999000 # Layer occupancy (ticks) 810system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) 811system.membus.respLayer1.occupancy 1366864750 # Layer occupancy (ticks) 812system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 813 814---------- End Simulation Statistics ---------- 815