stats.txt revision 11687
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 0.368600 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 368600034500 # Number of ticks simulated 511680SCurtis.Dunham@arm.comfinal_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711687Sandreas.hansson@arm.comhost_inst_rate 368828 # Simulator instruction rate (inst/s) 811687Sandreas.hansson@arm.comhost_op_rate 399489 # Simulator op (including micro ops) rate (op/s) 911687Sandreas.hansson@arm.comhost_tick_rate 268368313 # Simulator tick rate (ticks/s) 1011687Sandreas.hansson@arm.comhost_mem_usage 276836 # Number of bytes of host memory used 1111687Sandreas.hansson@arm.comhost_seconds 1373.49 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 506579366 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 548692589 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611680SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 1711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory 1811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory 1911606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 9233216 # Number of bytes read from this memory 2011570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory 2111570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory 2211606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory 2311606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 6241792 # Number of bytes written to this memory 2411570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory 2611606Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 144269 # Number of read requests responded to by this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory 2811606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 97528 # Number of write requests responded to by this memory 2911680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 487900 # Total read bandwidth from this memory (bytes/s) 3011680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 24561517 # Total read bandwidth from this memory (bytes/s) 3111680SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 25049417 # Total read bandwidth from this memory (bytes/s) 3211680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 487900 # Instruction read bandwidth from this memory (bytes/s) 3311680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 487900 # Instruction read bandwidth from this memory (bytes/s) 3411680SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 16933780 # Write bandwidth from this memory (bytes/s) 3511680SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 16933780 # Write bandwidth from this memory (bytes/s) 3611680SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 16933780 # Total bandwidth to/from this memory (bytes/s) 3711680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 487900 # Total bandwidth to/from this memory (bytes/s) 3811680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 24561517 # Total bandwidth to/from this memory (bytes/s) 3911680SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 41983197 # Total bandwidth to/from this memory (bytes/s) 4011606Sandreas.sandberg@arm.comsystem.physmem.readReqs 144269 # Number of read requests accepted 4111606Sandreas.sandberg@arm.comsystem.physmem.writeReqs 97528 # Number of write requests accepted 4211606Sandreas.sandberg@arm.comsystem.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue 4311606Sandreas.sandberg@arm.comsystem.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue 4411680SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 9225856 # Total number of bytes read from DRAM 4511680SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue 4611680SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 6240448 # Total number of bytes written to DRAM 4711606Sandreas.sandberg@arm.comsystem.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side 4811606Sandreas.sandberg@arm.comsystem.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side 4911680SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue 5011507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5111507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5211680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 9372 # Per bank write bursts 5311606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::1 8929 # Per bank write bursts 5411680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 8963 # Per bank write bursts 5511680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 8667 # Per bank write bursts 5611680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 9424 # Per bank write bursts 5711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 9372 # Per bank write bursts 5811606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::6 8974 # Per bank write bursts 5911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 8127 # Per bank write bursts 6011680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 8635 # Per bank write bursts 6111606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::9 8697 # Per bank write bursts 6211680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 8761 # Per bank write bursts 6311680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 9485 # Per bank write bursts 6411680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 9346 # Per bank write bursts 6511680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 9545 # Per bank write bursts 6611680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 8729 # Per bank write bursts 6711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 9128 # Per bank write bursts 6811680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 6253 # Per bank write bursts 6911606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::1 6118 # Per bank write bursts 7011606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::2 6042 # Per bank write bursts 7111606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::3 5901 # Per bank write bursts 7211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::4 6273 # Per bank write bursts 7311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::5 6263 # Per bank write bursts 7411606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::6 6069 # Per bank write bursts 7511680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 5535 # Per bank write bursts 7611680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 5819 # Per bank write bursts 7711606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::9 5920 # Per bank write bursts 7811606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::10 5985 # Per bank write bursts 7911606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::11 6510 # Per bank write bursts 8011606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::12 6360 # Per bank write bursts 8111606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::13 6344 # Per bank write bursts 8211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::14 6013 # Per bank write bursts 8311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::15 6102 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8511507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8611680SCurtis.Dunham@arm.comsystem.physmem.totGap 368600009000 # Total gap between requests 8711507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9311606Sandreas.sandberg@arm.comsystem.physmem.readPktSize::6 144269 # Read request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10011606Sandreas.sandberg@arm.comsystem.physmem.writePktSize::6 97528 # Write request sizes (log2) 10111680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 143801 # What read queue length does an incoming req see 10211680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 333 # What read queue length does an incoming req see 10311680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 14811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 2730 # What write queue length does an incoming req see 14911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see 15011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 5701 # What write queue length does an incoming req see 15111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 5739 # What write queue length does an incoming req see 15211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 5742 # What write queue length does an incoming req see 15311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 5743 # What write queue length does an incoming req see 15411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 5741 # What write queue length does an incoming req see 15511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 5741 # What write queue length does an incoming req see 15611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 5741 # What write queue length does an incoming req see 15711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 5744 # What write queue length does an incoming req see 15811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 5746 # What write queue length does an incoming req see 15911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 5749 # What write queue length does an incoming req see 16011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see 16111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 5745 # What write queue length does an incoming req see 16211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see 16311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 5752 # What write queue length does an incoming req see 16411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 5747 # What write queue length does an incoming req see 16511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 5741 # What write queue length does an incoming req see 16611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see 16711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see 16811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see 16911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see 17011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 17111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 17211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see 17311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see 17411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19711680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 63970 # Bytes accessed per row activation 19811680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 241.763327 # Bytes accessed per row activation 19911680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 162.115864 # Bytes accessed per row activation 20011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 241.210402 # Bytes accessed per row activation 20111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 22774 35.60% 35.60% # Bytes accessed per row activation 20211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 18302 28.61% 64.21% # Bytes accessed per row activation 20311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 7461 11.66% 75.87% # Bytes accessed per row activation 20411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 8049 12.58% 88.46% # Bytes accessed per row activation 20511680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 2117 3.31% 91.77% # Bytes accessed per row activation 20611680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 1180 1.84% 93.61% # Bytes accessed per row activation 20711680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 776 1.21% 94.82% # Bytes accessed per row activation 20811680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 623 0.97% 95.80% # Bytes accessed per row activation 20911680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 2688 4.20% 100.00% # Bytes accessed per row activation 21011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 63970 # Bytes accessed per row activation 21111680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 5740 # Reads before turning the bus around for writes 21211680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 25.113240 # Reads before turning the bus around for writes 21311680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 375.658190 # Reads before turning the bus around for writes 21411680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 5737 99.95% 99.95% # Reads before turning the bus around for writes 21511606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes 21611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 21711680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 5740 # Reads before turning the bus around for writes 21811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 5740 # Writes before turning the bus around for reads 21911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 16.987282 # Writes before turning the bus around for reads 22011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 16.957535 # Writes before turning the bus around for reads 22111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 1.009458 # Writes before turning the bus around for reads 22211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16 2852 49.69% 49.69% # Writes before turning the bus around for reads 22311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::17 159 2.77% 52.46% # Writes before turning the bus around for reads 22411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::18 2701 47.06% 99.51% # Writes before turning the bus around for reads 22511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::19 19 0.33% 99.84% # Writes before turning the bus around for reads 22611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20 6 0.10% 99.95% # Writes before turning the bus around for reads 22711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::23 1 0.02% 99.97% # Writes before turning the bus around for reads 22811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads 22911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads 23011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 5740 # Writes before turning the bus around for reads 23111680SCurtis.Dunham@arm.comsystem.physmem.totQLat 3577413000 # Total ticks spent queuing 23211680SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 6280300500 # Total ticks spent from burst creation until serviced by the DRAM 23311680SCurtis.Dunham@arm.comsystem.physmem.totBusLat 720770000 # Total ticks spent in databus transfers 23411680SCurtis.Dunham@arm.comsystem.physmem.avgQLat 24816.61 # Average queueing delay per DRAM burst 23511507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 23611680SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 43566.61 # Average memory access latency per DRAM burst 23711680SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 25.03 # Average DRAM read bandwidth in MiByte/s 23811680SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s 23911680SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 25.05 # Average system read bandwidth in MiByte/s 24011680SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 16.93 # Average system write bandwidth in MiByte/s 24111507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 24211507SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.33 # Data bus utilization in percentage 24311507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 24411507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 24511507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 24611680SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 20.06 # Average write queue length when enqueuing 24711680SCurtis.Dunham@arm.comsystem.physmem.readRowHits 110541 # Number of row buffer hits during reads 24811680SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 67141 # Number of row buffer hits during writes 24911680SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads 25011680SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes 25111680SCurtis.Dunham@arm.comsystem.physmem.avgGap 1524419.28 # Average gap between requests 25211680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 73.52 # Row buffer hit rate, read and write combined 25311680SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 229615260 # Energy for activate commands per rank (pJ) 25411680SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 122028225 # Energy for precharge commands per rank (pJ) 25511680SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 512851920 # Energy for read commands per rank (pJ) 25611680SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 252929880 # Energy for write commands per rank (pJ) 25711680SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 7711888080.000002 # Energy for refresh commands per rank (pJ) 25811680SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 3985238790 # Energy for active background per rank (pJ) 25911680SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 353652480 # Energy for precharge background per rank (pJ) 26011680SCurtis.Dunham@arm.comsystem.physmem_0.actPowerDownEnergy 24742370760 # Energy for active power-down per rank (pJ) 26111680SCurtis.Dunham@arm.comsystem.physmem_0.prePowerDownEnergy 8329193280 # Energy for precharge power-down per rank (pJ) 26211680SCurtis.Dunham@arm.comsystem.physmem_0.selfRefreshEnergy 68838779610 # Energy for self refresh per rank (pJ) 26311680SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 115080424995 # Total energy per rank (pJ) 26411680SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 312.209476 # Core power per rank (mW) 26511680SCurtis.Dunham@arm.comsystem.physmem_0.totalIdleTime 358934915250 # Total Idle time Per DRAM Rank 26611680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 533175250 # Time in different power states 26711680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 3272498000 # Time in different power states 26811680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::SREF 282985145000 # Time in different power states 26911680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 21690770000 # Time in different power states 27011680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 5858999750 # Time in different power states 27111680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 54259446500 # Time in different power states 27211680SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 227194800 # Energy for activate commands per rank (pJ) 27311680SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 120737925 # Energy for precharge commands per rank (pJ) 27411680SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 516407640 # Energy for read commands per rank (pJ) 27511680SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 256056660 # Energy for write commands per rank (pJ) 27611680SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 7588960080.000002 # Energy for refresh commands per rank (pJ) 27711680SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 3990658350 # Energy for active background per rank (pJ) 27811680SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 342745440 # Energy for precharge background per rank (pJ) 27911680SCurtis.Dunham@arm.comsystem.physmem_1.actPowerDownEnergy 24389253480 # Energy for active power-down per rank (pJ) 28011680SCurtis.Dunham@arm.comsystem.physmem_1.prePowerDownEnergy 8128930080 # Energy for precharge power-down per rank (pJ) 28111680SCurtis.Dunham@arm.comsystem.physmem_1.selfRefreshEnergy 69135041760 # Energy for self refresh per rank (pJ) 28211680SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 114698280525 # Total energy per rank (pJ) 28311680SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 311.172732 # Core power per rank (mW) 28411680SCurtis.Dunham@arm.comsystem.physmem_1.totalIdleTime 358951286500 # Total Idle time Per DRAM Rank 28511680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 511434000 # Time in different power states 28611680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 3220288000 # Time in different power states 28711680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::SREF 284296674500 # Time in different power states 28811680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 21168817000 # Time in different power states 28911680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 5916972250 # Time in different power states 29011680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 53485848750 # Time in different power states 29111680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 29211680SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 132103819 # Number of BP lookups 29311680SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 98193306 # Number of conditional branches predicted 29411606Sandreas.sandberg@arm.comsystem.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect 29511680SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 68601561 # Number of BTB lookups 29611680SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 60590477 # Number of BTB hits 29711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 29811680SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 88.322301 # BTB Hit Percentage 29911680SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 10017121 # Number of times the RAS was used to get a target. 30011570SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. 30111680SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 3891575 # Number of indirect predictor lookups. 30211680SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 3883028 # Number of indirect target hits. 30311606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. 30411570SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. 30511507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 30611680SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 30711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 30811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 30911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 31011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 31111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 31211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 31311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 31411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 31911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 32011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 32111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 32211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 32511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 32611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 32711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 32811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 32911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 33111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 33211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 33311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 33411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 33511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 33611680SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 33711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 33811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 33911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 34011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 34211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 34311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 34811507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 34911507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 35011507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 35111507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 35211507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35311507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 35411507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35511507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 35611507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 35711507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 35811507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 35911507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36011507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 36111507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 36211507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 36311507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 36411507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 36511507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 36611680SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 36711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 36811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 36911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 37011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 37211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 37711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 37811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 37911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 38011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 38111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 38211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 38411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 38511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 38611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 38711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 38811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 38911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 39111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 39211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 39311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 39411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 39511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 39611680SCurtis.Dunham@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 39711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 39811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 40011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 40211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 40611507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 40711507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 40811507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 40911507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 41011507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 41111507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 41211507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41311507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41511507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 41611507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 41711507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 41811507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 41911507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 42011507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 42111507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 42211507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 42311507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 42411507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 42511507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 42611507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 548 # Number of system calls 42711680SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON 368600034500 # Cumulative time (in ticks) in various power states 42811680SCurtis.Dunham@arm.comsystem.cpu.numCycles 737200069 # number of cpu cycles simulated 42911507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43011507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 43111507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 506579366 # Number of instructions committed 43211507SCurtis.Dunham@arm.comsystem.cpu.committedOps 548692589 # Number of ops (including micro ops) committed 43311680SCurtis.Dunham@arm.comsystem.cpu.discardedOps 12939783 # Number of ops (including micro ops) which were discarded before commit 43411507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 43511680SCurtis.Dunham@arm.comsystem.cpu.cpi 1.455251 # CPI: cycles per instruction 43611680SCurtis.Dunham@arm.comsystem.cpu.ipc 0.687167 # IPC: instructions per cycle 43711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 43811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction 43911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 44011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 44111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 44211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 44311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 44411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 44511687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction 44611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 44711687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction 44811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 44911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 45011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 45111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 45211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 45311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 45411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 45511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 45611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 45711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 45811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 45911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 46011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 46111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 46211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 46311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 46411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 46511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 46611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 46711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 46811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 46911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 47011687Sandreas.hansson@arm.comsystem.cpu.op_class_0::MemWrite 56860206 10.36% 100.00% # Class of committed instruction 47111687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 47211687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction 47311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 47411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 47511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 548692589 # Class of committed instruction 47611680SCurtis.Dunham@arm.comsystem.cpu.tickCycles 694074439 # Number of cycles that the object actually ticked 47711680SCurtis.Dunham@arm.comsystem.cpu.idleCycles 43125630 # Total number of cycles that the object has spent stopped 47811680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 47911570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 1141337 # number of replacements 48011680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 4070.214597 # Cycle average of tags in use 48111680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 171083824 # Total number of references to valid blocks. 48211570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. 48311680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 149.361703 # Average number of references to valid blocks. 48411680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 5072633500 # Cycle when the warmup percentage was hit. 48511680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4070.214597 # Average occupied blocks per requestor 48611680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy 48711680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy 48811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 48911680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 49011680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 49111680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id 49211680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id 49311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 49411680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 346338045 # Number of tag accesses 49511680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 346338045 # Number of data accesses 49611680SCurtis.Dunham@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 49711680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 114566013 # number of ReadReq hits 49811680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 114566013 # number of ReadReq hits 49911680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 53537935 # number of WriteReq hits 50011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 53537935 # number of WriteReq hits 50111570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits 50211570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits 50311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 50411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 50511507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 50611507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 50711680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 168103948 # number of demand (read+write) hits 50811680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 168103948 # number of demand (read+write) hits 50911680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 168106742 # number of overall hits 51011680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 168106742 # number of overall hits 51111680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 811353 # number of ReadReq misses 51211680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 811353 # number of ReadReq misses 51311680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 701114 # number of WriteReq misses 51411680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 701114 # number of WriteReq misses 51511570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses 51611570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses 51711680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1512467 # number of demand (read+write) misses 51811680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 1512467 # number of demand (read+write) misses 51911680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1512482 # number of overall misses 52011680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 1512482 # number of overall misses 52111680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 14511838000 # number of ReadReq miss cycles 52211680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 14511838000 # number of ReadReq miss cycles 52311680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 24015669000 # number of WriteReq miss cycles 52411680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 24015669000 # number of WriteReq miss cycles 52511680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 38527507000 # number of demand (read+write) miss cycles 52611680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 38527507000 # number of demand (read+write) miss cycles 52711680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 38527507000 # number of overall miss cycles 52811680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 38527507000 # number of overall miss cycles 52911680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 115377366 # number of ReadReq accesses(hits+misses) 53011680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 115377366 # number of ReadReq accesses(hits+misses) 53111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 53211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 53311570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) 53411570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2809 # number of SoftPFReq accesses(hits+misses) 53511507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 53611507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 53711507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 53811507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 53911680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 169616415 # number of demand (read+write) accesses 54011680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 169616415 # number of demand (read+write) accesses 54111680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 169619224 # number of overall (read+write) accesses 54211680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 169619224 # number of overall (read+write) accesses 54311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses 54411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses 54511570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses 54611570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses 54711570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005340 # miss rate for SoftPFReq accesses 54811570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.005340 # miss rate for SoftPFReq accesses 54911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.008917 # miss rate for demand accesses 55011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses 55111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses 55211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses 55311680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183 # average ReadReq miss latency 55411680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183 # average ReadReq miss latency 55511680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435 # average WriteReq miss latency 55611680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435 # average WriteReq miss latency 55711680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682 # average overall miss latency 55811680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 25473.287682 # average overall miss latency 55911680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051 # average overall miss latency 56011680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 25473.035051 # average overall miss latency 56111507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 56211507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 56311507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 56411507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 56511507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 56611507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 56711606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks 56811606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::total 1068942 # number of writebacks 56911680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 22320 # number of ReadReq MSHR hits 57011680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 22320 # number of ReadReq MSHR hits 57111680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 344726 # number of WriteReq MSHR hits 57211680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 344726 # number of WriteReq MSHR hits 57311680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 367046 # number of demand (read+write) MSHR hits 57411680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 367046 # number of demand (read+write) MSHR hits 57511680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 367046 # number of overall MSHR hits 57611680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 367046 # number of overall MSHR hits 57711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses 57811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses 57911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses 58011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 356388 # number of WriteReq MSHR misses 58111570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses 58211570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses 58311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1145421 # number of demand (read+write) MSHR misses 58411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses 58511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses 58611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses 58711680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416891000 # number of ReadReq MSHR miss cycles 58811680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 13416891000 # number of ReadReq MSHR miss cycles 58911680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191000 # number of WriteReq MSHR miss cycles 59011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191000 # number of WriteReq MSHR miss cycles 59111680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4297000 # number of SoftPFReq MSHR miss cycles 59211680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4297000 # number of SoftPFReq MSHR miss cycles 59311680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613082000 # number of demand (read+write) MSHR miss cycles 59411680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 25613082000 # number of demand (read+write) MSHR miss cycles 59511680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617379000 # number of overall MSHR miss cycles 59611680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 25617379000 # number of overall MSHR miss cycles 59711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses 59811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses 59911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses 60011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses 60111570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004272 # mshr miss rate for SoftPFReq accesses 60211570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004272 # mshr miss rate for SoftPFReq accesses 60311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses 60411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses 60511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses 60611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses 60711680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356 # average ReadReq mshr miss latency 60811680SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356 # average ReadReq mshr miss latency 60911680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713 # average WriteReq mshr miss latency 61011680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713 # average WriteReq mshr miss latency 61111680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333 # average SoftPFReq mshr miss latency 61211680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333 # average SoftPFReq mshr miss latency 61311680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009 # average overall mshr miss latency 61411680SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.282009 # average overall mshr miss latency 61511680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.799163 # average overall mshr miss latency 61611680SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.799163 # average overall mshr miss latency 61711680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 61811680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 18178 # number of replacements 61911680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 1186.508914 # Cycle average of tags in use 62011680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 199149017 # Total number of references to valid blocks. 62111680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 20050 # Sample count of references to valid blocks. 62211680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 9932.619302 # Average number of references to valid blocks. 62311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 62411680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1186.508914 # Average occupied blocks per requestor 62511680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.579350 # Average percentage of cache occupancy 62611680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.579350 # Average percentage of cache occupancy 62711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 62811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 62911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 63011570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 63111570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id 63211570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id 63311570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id 63411680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 398358184 # Number of tag accesses 63511680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 398358184 # Number of data accesses 63611680SCurtis.Dunham@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 63711680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 199149017 # number of ReadReq hits 63811680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 199149017 # number of ReadReq hits 63911680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 199149017 # number of demand (read+write) hits 64011680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 199149017 # number of demand (read+write) hits 64111680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 199149017 # number of overall hits 64211680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 199149017 # number of overall hits 64311680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 20050 # number of ReadReq misses 64411680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 20050 # number of ReadReq misses 64511680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 20050 # number of demand (read+write) misses 64611680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 20050 # number of demand (read+write) misses 64711680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 20050 # number of overall misses 64811680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 20050 # number of overall misses 64911680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 544281000 # number of ReadReq miss cycles 65011680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 544281000 # number of ReadReq miss cycles 65111680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 544281000 # number of demand (read+write) miss cycles 65211680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 544281000 # number of demand (read+write) miss cycles 65311680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 544281000 # number of overall miss cycles 65411680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 544281000 # number of overall miss cycles 65511680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 199169067 # number of ReadReq accesses(hits+misses) 65611680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 199169067 # number of ReadReq accesses(hits+misses) 65711680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 199169067 # number of demand (read+write) accesses 65811680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 199169067 # number of demand (read+write) accesses 65911680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 199169067 # number of overall (read+write) accesses 66011680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 199169067 # number of overall (read+write) accesses 66111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses 66211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses 66311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses 66411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses 66511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses 66611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses 66711680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539 # average ReadReq miss latency 66811680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539 # average ReadReq miss latency 66911680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency 67011680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 27146.184539 # average overall miss latency 67111680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency 67211680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 27146.184539 # average overall miss latency 67311507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 67411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 67511507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 67611507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 67711507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 67811507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 67911680SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 18178 # number of writebacks 68011680SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 18178 # number of writebacks 68111680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 20050 # number of ReadReq MSHR misses 68211680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 20050 # number of ReadReq MSHR misses 68311680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 20050 # number of demand (read+write) MSHR misses 68411680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 20050 # number of demand (read+write) MSHR misses 68511680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 20050 # number of overall MSHR misses 68611680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 20050 # number of overall MSHR misses 68711680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524231000 # number of ReadReq MSHR miss cycles 68811680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 524231000 # number of ReadReq MSHR miss cycles 68911680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 524231000 # number of demand (read+write) MSHR miss cycles 69011680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 524231000 # number of demand (read+write) MSHR miss cycles 69111680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 524231000 # number of overall MSHR miss cycles 69211680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 524231000 # number of overall MSHR miss cycles 69311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses 69411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses 69511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses 69611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses 69711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 69811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses 69911680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539 # average ReadReq mshr miss latency 70011680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539 # average ReadReq mshr miss latency 70111680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency 70211680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency 70311680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency 70411680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency 70511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 70611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.replacements 112761 # number of replacements 70711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 29076.847904 # Cycle average of tags in use 70811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 2174458 # Total number of references to valid blocks. 70911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. 71011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 14.941750 # Average number of references to valid blocks. 71111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 102118428000 # Cycle when the warmup percentage was hit. 71211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 133.889042 # Average occupied blocks per requestor 71311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541070 # Average occupied blocks per requestor 71411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417793 # Average occupied blocks per requestor 71511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.004086 # Average percentage of cache occupancy 71611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.009385 # Average percentage of cache occupancy 71711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.873884 # Average percentage of cache occupancy 71811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.887355 # Average percentage of cache occupancy 71911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 72011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 72111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id 72211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id 72311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id 72411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 72511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 18705537 # Number of tag accesses 72611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 18705537 # Number of data accesses 72711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 72811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits 72911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits 73011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 17940 # number of WritebackClean hits 73111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 17940 # number of WritebackClean hits 73211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 255660 # number of ReadExReq hits 73311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 255660 # number of ReadExReq hits 73411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17239 # number of ReadCleanReq hits 73511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 17239 # number of ReadCleanReq hits 73611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 748301 # number of ReadSharedReq hits 73711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 748301 # number of ReadSharedReq hits 73811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 17239 # number of demand (read+write) hits 73911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1003961 # number of demand (read+write) hits 74011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 1021200 # number of demand (read+write) hits 74111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 17239 # number of overall hits 74211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1003961 # number of overall hits 74311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 1021200 # number of overall hits 74411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 100978 # number of ReadExReq misses 74511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 100978 # number of ReadExReq misses 74611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2811 # number of ReadCleanReq misses 74711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 2811 # number of ReadCleanReq misses 74811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 40494 # number of ReadSharedReq misses 74911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 40494 # number of ReadSharedReq misses 75011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2811 # number of demand (read+write) misses 75111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 141472 # number of demand (read+write) misses 75211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 144283 # number of demand (read+write) misses 75311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses 75411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses 75511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 144283 # number of overall misses 75611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653000 # number of ReadExReq miss cycles 75711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 8979653000 # number of ReadExReq miss cycles 75811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312477500 # number of ReadCleanReq miss cycles 75911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 312477500 # number of ReadCleanReq miss cycles 76011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360667500 # number of ReadSharedReq miss cycles 76111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 4360667500 # number of ReadSharedReq miss cycles 76211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 312477500 # number of demand (read+write) miss cycles 76311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 13340320500 # number of demand (read+write) miss cycles 76411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 13652798000 # number of demand (read+write) miss cycles 76511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 312477500 # number of overall miss cycles 76611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 13340320500 # number of overall miss cycles 76711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 13652798000 # number of overall miss cycles 76811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) 76911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) 77011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 17940 # number of WritebackClean accesses(hits+misses) 77111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 17940 # number of WritebackClean accesses(hits+misses) 77211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses) 77311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 356638 # number of ReadExReq accesses(hits+misses) 77411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20050 # number of ReadCleanReq accesses(hits+misses) 77511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 20050 # number of ReadCleanReq accesses(hits+misses) 77611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788795 # number of ReadSharedReq accesses(hits+misses) 77711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 788795 # number of ReadSharedReq accesses(hits+misses) 77811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 20050 # number of demand (read+write) accesses 77911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1145433 # number of demand (read+write) accesses 78011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 1165483 # number of demand (read+write) accesses 78111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 20050 # number of overall (read+write) accesses 78211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses 78311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 1165483 # number of overall (read+write) accesses 78411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283139 # miss rate for ReadExReq accesses 78511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.283139 # miss rate for ReadExReq accesses 78611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140200 # miss rate for ReadCleanReq accesses 78711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140200 # miss rate for ReadCleanReq accesses 78811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051337 # miss rate for ReadSharedReq accesses 78911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051337 # miss rate for ReadSharedReq accesses 79011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.140200 # miss rate for demand accesses 79111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.123510 # miss rate for demand accesses 79211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.123797 # miss rate for demand accesses 79311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.140200 # miss rate for overall accesses 79411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses 79511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.123797 # miss rate for overall accesses 79611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.825645 # average ReadExReq miss latency 79711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.825645 # average ReadExReq miss latency 79811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111162.397723 # average ReadCleanReq miss latency 79911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111162.397723 # average ReadCleanReq miss latency 80011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.756063 # average ReadSharedReq miss latency 80111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.756063 # average ReadSharedReq miss latency 80211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency 80311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency 80411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 94625.132552 # average overall miss latency 80511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency 80611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency 80711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 94625.132552 # average overall miss latency 80811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 80911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 81011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 81111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 81211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 81311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 81411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks 81511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::total 97528 # number of writebacks 81611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 81711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 81811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits 81911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits 82011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 82111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits 82211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 82311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 82411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits 82511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits 82611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses 82711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses 82811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses 82911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses 83011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses 83111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses 83211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses 83311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses 83411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses 83511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses 83611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses 83711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses 83811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873000 # number of ReadExReq MSHR miss cycles 83911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873000 # number of ReadExReq MSHR miss cycles 84011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284302500 # number of ReadCleanReq MSHR miss cycles 84111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284302500 # number of ReadCleanReq MSHR miss cycles 84211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953965500 # number of ReadSharedReq MSHR miss cycles 84311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953965500 # number of ReadSharedReq MSHR miss cycles 84411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284302500 # number of demand (read+write) MSHR miss cycles 84511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923838500 # number of demand (read+write) MSHR miss cycles 84611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 12208141000 # number of demand (read+write) MSHR miss cycles 84711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284302500 # number of overall MSHR miss cycles 84811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923838500 # number of overall MSHR miss cycles 84911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 12208141000 # number of overall MSHR miss cycles 85011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses 85111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses 85211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for ReadCleanReq accesses 85311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140150 # mshr miss rate for ReadCleanReq accesses 85411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses 85511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses 85611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for demand accesses 85711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses 85811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses 85911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for overall accesses 86011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses 86111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses 86211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645 # average ReadExReq mshr miss latency 86311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645 # average ReadExReq mshr miss latency 86411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904 # average ReadCleanReq mshr miss latency 86511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904 # average ReadCleanReq mshr miss latency 86611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430 # average ReadSharedReq mshr miss latency 86711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430 # average ReadSharedReq mshr miss latency 86811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency 86911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency 87011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency 87111680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency 87211680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency 87311680SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency 87411680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 2324998 # Total number of requests made to the snoop filter. 87511680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 1159585 # Number of requests hitting in the snoop filter with a single holder of the requested data. 87611680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 87711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. 87811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 87911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 88011680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 88111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 808845 # Transaction distribution 88211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution 88311680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 18178 # Transaction distribution 88411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution 88511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution 88611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution 88711680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 20050 # Transaction distribution 88811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution 88911680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58278 # Packet count per connected master and slave (bytes) 89011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) 89111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 3490481 # Packet count per connected master and slave (bytes) 89211680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446592 # Cumulative packet size per connected master and slave (bytes) 89311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) 89411680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 144166592 # Cumulative packet size per connected master and slave (bytes) 89511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoops 112761 # Total snoops (count) 89611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) 89711680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 1278244 # Request fanout histogram 89811680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.006015 # Request fanout histogram 89911680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.077350 # Request fanout histogram 90011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 90111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 1270559 99.40% 99.40% # Request fanout histogram 90211680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 7682 0.60% 100.00% # Request fanout histogram 90311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 90411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 90511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 90611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 90711680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 1278244 # Request fanout histogram 90811680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2249619000 # Layer occupancy (ticks) 90911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 91011680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 30098453 # Layer occupancy (ticks) 91111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 91211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) 91311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 91411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. 91511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 91611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 91711606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 91811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 91911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 92011680SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states 92111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 43291 # Transaction distribution 92211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 97528 # Transaction distribution 92311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::CleanEvict 12615 # Transaction distribution 92411606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExReq 100978 # Transaction distribution 92511606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExResp 100978 # Transaction distribution 92611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution 92711606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) 92811606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) 92911606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes) 93011606Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes) 93111507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 93211570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 93311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 144269 # Request fanout histogram 93411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 93511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 93611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 93711606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram 93811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 93911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 94011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 94111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 94211606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 144269 # Request fanout histogram 94311680SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 685124000 # Layer occupancy (ticks) 94411507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 94511680SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 765885250 # Layer occupancy (ticks) 94611507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 94711507SCurtis.Dunham@arm.com 94811507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 949