stats.txt revision 9797:9cd5f91e7a79
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.365989 # Number of seconds simulated 4sim_ticks 365989065000 # Number of ticks simulated 5final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 466388 # Simulator instruction rate (inst/s) 8host_op_rate 821234 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1080412484 # Simulator tick rate (ticks/s) 10host_mem_usage 431468 # Number of bytes of host memory used 11host_seconds 338.75 # Real time elapsed on the host 12sim_insts 157988548 # Number of instructions simulated 13sim_ops 278192465 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory 20system.physmem.bytes_written::total 6400 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 100 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) 37system.membus.throughput 5272114 # Throughput (bytes/s) 38system.membus.trans_dist::ReadReq 1025 # Transaction distribution 39system.membus.trans_dist::ReadResp 1025 # Transaction distribution 40system.membus.trans_dist::Writeback 100 # Transaction distribution 41system.membus.trans_dist::ReadExReq 29024 # Transaction distribution 42system.membus.trans_dist::ReadExResp 29024 # Transaction distribution 43system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) 44system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) 45system.membus.pkt_count::system.physmem.port 60198 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) 47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) 48system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) 49system.membus.tot_pkt_size::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) 50system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) 51system.membus.data_through_bus 1929536 # Total data (bytes) 52system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 53system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks) 54system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 55system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) 56system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 57system.cpu.workload.num_syscalls 444 # Number of system calls 58system.cpu.numCycles 731978130 # number of cpu cycles simulated 59system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 60system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 61system.cpu.committedInsts 157988548 # Number of instructions committed 62system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 63system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses 64system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 65system.cpu.num_func_calls 8475189 # number of times a function call or return occured 66system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls 67system.cpu.num_int_insts 278186175 # number of integer instructions 68system.cpu.num_fp_insts 40 # number of float instructions 69system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read 70system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written 71system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 72system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 73system.cpu.num_mem_refs 122219137 # number of memory refs 74system.cpu.num_load_insts 90779385 # Number of load instructions 75system.cpu.num_store_insts 31439752 # Number of store instructions 76system.cpu.num_idle_cycles 0 # Number of idle cycles 77system.cpu.num_busy_cycles 731978130 # Number of busy cycles 78system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 79system.cpu.idle_fraction 0 # Percentage of idle cycles 80system.cpu.icache.tags.replacements 24 # number of replacements 81system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use 82system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. 83system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 84system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks. 85system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 86system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor 87system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy 88system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy 89system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits 90system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits 91system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits 92system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits 93system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits 94system.cpu.icache.overall_hits::total 217695357 # number of overall hits 95system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 96system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 97system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 98system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 99system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 100system.cpu.icache.overall_misses::total 808 # number of overall misses 101system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles 102system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles 103system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles 104system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles 105system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles 106system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles 107system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses) 108system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses) 109system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses 110system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses 111system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses 112system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses 113system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 114system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 115system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 116system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 117system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 118system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 119system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency 120system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency 121system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency 122system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency 123system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency 124system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency 125system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 126system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 127system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 128system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 129system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 130system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 131system.cpu.icache.fast_writes 0 # number of fast writes performed 132system.cpu.icache.cache_copies 0 # number of cache copies performed 133system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 134system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 135system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 136system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 137system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 138system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses 139system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles 140system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles 141system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles 142system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles 143system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles 144system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles 145system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 146system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 147system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 148system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 149system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 150system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 151system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency 152system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency 153system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 154system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency 155system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency 156system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency 157system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 158system.cpu.l2cache.tags.replacements 318 # number of replacements 159system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use 160system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. 161system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. 162system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. 163system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 164system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor 165system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor 166system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor 167system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy 168system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy 169system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy 170system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy 171system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits 172system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits 173system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits 174system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits 175system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits 176system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits 177system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits 178system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits 179system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits 180system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits 181system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits 182system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits 183system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits 184system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses 185system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses 186system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses 187system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses 188system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses 189system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 190system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses 191system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses 192system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses 193system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses 194system.cpu.l2cache.overall_misses::total 30049 # number of overall misses 195system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles 196system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles 197system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles 198system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles 199system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles 200system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles 201system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles 202system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles 203system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles 204system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles 205system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles 206system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) 207system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) 208system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) 209system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses) 210system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses) 211system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) 212system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) 213system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses 214system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses 215system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses 216system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses 217system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses 218system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses 219system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses 220system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses 221system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses 222system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses 223system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses 224system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses 225system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses 226system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses 227system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses 228system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses 229system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses 230system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 231system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 232system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 233system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency 234system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency 235system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 236system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency 237system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency 238system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 239system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency 240system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency 241system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 242system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 243system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 244system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 245system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 246system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247system.cpu.l2cache.fast_writes 0 # number of fast writes performed 248system.cpu.l2cache.cache_copies 0 # number of cache copies performed 249system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks 250system.cpu.l2cache.writebacks::total 100 # number of writebacks 251system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses 252system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses 253system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses 254system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 255system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 256system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 257system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses 258system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses 259system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 260system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses 261system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses 262system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles 263system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles 264system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles 265system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles 266system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles 267system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles 268system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles 269system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles 270system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles 271system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles 272system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles 273system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses 274system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses 275system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses 276system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses 277system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses 278system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses 279system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses 280system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses 281system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses 282system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses 283system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses 284system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 285system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 286system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 287system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 288system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 289system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 290system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 291system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 292system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 293system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 294system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 295system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 296system.cpu.dcache.tags.replacements 2062733 # number of replacements 297system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use 298system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. 299system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. 300system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. 301system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. 302system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor 303system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy 304system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy 305system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits 306system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits 307system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits 308system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits 309system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits 310system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits 311system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits 312system.cpu.dcache.overall_hits::total 120152370 # number of overall hits 313system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 314system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 315system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 316system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 317system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 318system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 319system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 320system.cpu.dcache.overall_misses::total 2066829 # number of overall misses 321system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles 322system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles 323system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles 324system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles 325system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles 326system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles 327system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles 328system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles 329system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) 330system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) 331system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 332system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 333system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses 334system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses 335system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses 336system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses 337system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 338system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 339system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 340system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 341system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 342system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 343system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 344system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses 345system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency 346system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency 347system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency 348system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency 349system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 350system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency 351system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency 352system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency 353system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 354system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 355system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 356system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 357system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 358system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 359system.cpu.dcache.fast_writes 0 # number of fast writes performed 360system.cpu.dcache.cache_copies 0 # number of cache copies performed 361system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks 362system.cpu.dcache.writebacks::total 2062484 # number of writebacks 363system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 364system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 365system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 366system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 367system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 368system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses 369system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses 370system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses 371system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles 372system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles 373system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles 374system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles 375system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles 376system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles 377system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles 378system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles 379system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses 380system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses 381system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses 382system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses 383system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses 384system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses 385system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses 386system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses 387system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency 388system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency 389system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency 390system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency 391system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 392system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 393system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency 394system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency 395system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 396system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s) 397system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution 398system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 399system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution 400system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution 401system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution 402system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1616 # Packet count per connected master and slave (bytes) 403system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6196142 # Packet count per connected master and slave (bytes) 404system.cpu.toL2Bus.pkt_count 6197758 # Packet count per connected master and slave (bytes) 405system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51712 # Cumulative packet size per connected master and slave (bytes) 406system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 264276032 # Cumulative packet size per connected master and slave (bytes) 407system.cpu.toL2Bus.tot_pkt_size 264327744 # Cumulative packet size per connected master and slave (bytes) 408system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes) 409system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 410system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) 411system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 412system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) 413system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 414system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) 415system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 416 417---------- End Simulation Statistics ---------- 418