stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.370011 # Number of seconds simulated 4sim_ticks 370010840000 # Number of ticks simulated 5final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1163147 # Simulator instruction rate (inst/s) 8host_tick_rate 1547047043 # Simulator tick rate (ticks/s) 9host_mem_usage 348152 # Number of bytes of host memory used 10host_seconds 239.17 # Real time elapsed on the host 11sim_insts 278192520 # Number of instructions simulated 12system.physmem.bytes_read 4900800 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 1885440 # Number of bytes written to this memory 15system.physmem.num_reads 76575 # Number of read requests responded to by this memory 16system.physmem.num_writes 29460 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 13245017 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 139758 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 5095634 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 18340652 # Total bandwidth to/from this memory (bytes/s) 22system.cpu.workload.num_syscalls 444 # Number of system calls 23system.cpu.numCycles 740021680 # number of cpu cycles simulated 24system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 25system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 26system.cpu.num_insts 278192520 # Number of instructions executed 27system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses 28system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 29system.cpu.num_func_calls 0 # number of times a function call or return occured 30system.cpu.num_conditional_control_insts 18628012 # number of instructions that are conditional controls 31system.cpu.num_int_insts 278186228 # number of integer instructions 32system.cpu.num_fp_insts 40 # number of float instructions 33system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read 34system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written 35system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 36system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 37system.cpu.num_mem_refs 122219139 # number of memory refs 38system.cpu.num_load_insts 90779388 # Number of load instructions 39system.cpu.num_store_insts 31439751 # Number of store instructions 40system.cpu.num_idle_cycles 0 # Number of idle cycles 41system.cpu.num_busy_cycles 740021680 # Number of busy cycles 42system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 43system.cpu.idle_fraction 0 # Percentage of idle cycles 44system.cpu.icache.replacements 24 # number of replacements 45system.cpu.icache.tagsinuse 666.191948 # Cycle average of tags in use 46system.cpu.icache.total_refs 217695401 # Total number of references to valid blocks. 47system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. 48system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks. 49system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 50system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context 51system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy 52system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits 53system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits 54system.cpu.icache.overall_hits 217695401 # number of overall hits 55system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses 56system.cpu.icache.demand_misses 808 # number of demand (read+write) misses 57system.cpu.icache.overall_misses 808 # number of overall misses 58system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles 59system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles 60system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles 61system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses) 62system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses 63system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses 64system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses 65system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses 66system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses 67system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency 68system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency 69system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency 70system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 71system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 72system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 73system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 74system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 75system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 76system.cpu.icache.fast_writes 0 # number of fast writes performed 77system.cpu.icache.cache_copies 0 # number of cache copies performed 78system.cpu.icache.writebacks 0 # number of writebacks 79system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 80system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 81system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses 82system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses 83system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses 84system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 85system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles 86system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles 87system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles 88system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 89system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses 90system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses 91system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses 92system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency 93system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency 94system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency 95system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 96system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 97system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 98system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 99system.cpu.dcache.replacements 2062733 # number of replacements 100system.cpu.dcache.tagsinuse 4076.661903 # Cycle average of tags in use 101system.cpu.dcache.total_refs 120152372 # Total number of references to valid blocks. 102system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks. 103system.cpu.dcache.avg_refs 58.133678 # Average number of references to valid blocks. 104system.cpu.dcache.warmup_cycle 126200130000 # Cycle when the warmup percentage was hit. 105system.cpu.dcache.occ_blocks::0 4076.661903 # Average occupied blocks per context 106system.cpu.dcache.occ_percent::0 0.995279 # Average percentage of cache occupancy 107system.cpu.dcache.ReadReq_hits 88818730 # number of ReadReq hits 108system.cpu.dcache.WriteReq_hits 31333642 # number of WriteReq hits 109system.cpu.dcache.demand_hits 120152372 # number of demand (read+write) hits 110system.cpu.dcache.overall_hits 120152372 # number of overall hits 111system.cpu.dcache.ReadReq_misses 1960720 # number of ReadReq misses 112system.cpu.dcache.WriteReq_misses 106109 # number of WriteReq misses 113system.cpu.dcache.demand_misses 2066829 # number of demand (read+write) misses 114system.cpu.dcache.overall_misses 2066829 # number of overall misses 115system.cpu.dcache.ReadReq_miss_latency 28849058000 # number of ReadReq miss cycles 116system.cpu.dcache.WriteReq_miss_latency 3268793000 # number of WriteReq miss cycles 117system.cpu.dcache.demand_miss_latency 32117851000 # number of demand (read+write) miss cycles 118system.cpu.dcache.overall_miss_latency 32117851000 # number of overall miss cycles 119system.cpu.dcache.ReadReq_accesses 90779450 # number of ReadReq accesses(hits+misses) 120system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) 121system.cpu.dcache.demand_accesses 122219201 # number of demand (read+write) accesses 122system.cpu.dcache.overall_accesses 122219201 # number of overall (read+write) accesses 123system.cpu.dcache.ReadReq_miss_rate 0.021599 # miss rate for ReadReq accesses 124system.cpu.dcache.WriteReq_miss_rate 0.003375 # miss rate for WriteReq accesses 125system.cpu.dcache.demand_miss_rate 0.016911 # miss rate for demand accesses 126system.cpu.dcache.overall_miss_rate 0.016911 # miss rate for overall accesses 127system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183 # average ReadReq miss latency 128system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952 # average WriteReq miss latency 129system.cpu.dcache.demand_avg_miss_latency 15539.675029 # average overall miss latency 130system.cpu.dcache.overall_avg_miss_latency 15539.675029 # average overall miss latency 131system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 132system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 133system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 134system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 135system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 136system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 137system.cpu.dcache.fast_writes 0 # number of fast writes performed 138system.cpu.dcache.cache_copies 0 # number of cache copies performed 139system.cpu.dcache.writebacks 1437080 # number of writebacks 140system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 141system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 142system.cpu.dcache.ReadReq_mshr_misses 1960720 # number of ReadReq MSHR misses 143system.cpu.dcache.WriteReq_mshr_misses 106109 # number of WriteReq MSHR misses 144system.cpu.dcache.demand_mshr_misses 2066829 # number of demand (read+write) MSHR misses 145system.cpu.dcache.overall_mshr_misses 2066829 # number of overall MSHR misses 146system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 147system.cpu.dcache.ReadReq_mshr_miss_latency 22966898000 # number of ReadReq MSHR miss cycles 148system.cpu.dcache.WriteReq_mshr_miss_latency 2950464500 # number of WriteReq MSHR miss cycles 149system.cpu.dcache.demand_mshr_miss_latency 25917362500 # number of demand (read+write) MSHR miss cycles 150system.cpu.dcache.overall_mshr_miss_latency 25917362500 # number of overall MSHR miss cycles 151system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 152system.cpu.dcache.ReadReq_mshr_miss_rate 0.021599 # mshr miss rate for ReadReq accesses 153system.cpu.dcache.WriteReq_mshr_miss_rate 0.003375 # mshr miss rate for WriteReq accesses 154system.cpu.dcache.demand_mshr_miss_rate 0.016911 # mshr miss rate for demand accesses 155system.cpu.dcache.overall_mshr_miss_rate 0.016911 # mshr miss rate for overall accesses 156system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183 # average ReadReq mshr miss latency 157system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815 # average WriteReq mshr miss latency 158system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency 159system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303 # average overall mshr miss latency 160system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 161system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 162system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 163system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 164system.cpu.l2cache.replacements 49212 # number of replacements 165system.cpu.l2cache.tagsinuse 18614.603260 # Cycle average of tags in use 166system.cpu.l2cache.total_refs 3296079 # Total number of references to valid blocks. 167system.cpu.l2cache.sampled_refs 77127 # Sample count of references to valid blocks. 168system.cpu.l2cache.avg_refs 42.735735 # Average number of references to valid blocks. 169system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 170system.cpu.l2cache.occ_blocks::0 6551.798271 # Average occupied blocks per context 171system.cpu.l2cache.occ_blocks::1 12062.804989 # Average occupied blocks per context 172system.cpu.l2cache.occ_percent::0 0.199945 # Average percentage of cache occupancy 173system.cpu.l2cache.occ_percent::1 0.368128 # Average percentage of cache occupancy 174system.cpu.l2cache.ReadReq_hits 1927411 # number of ReadReq hits 175system.cpu.l2cache.Writeback_hits 1437080 # number of Writeback hits 176system.cpu.l2cache.ReadExReq_hits 63651 # number of ReadExReq hits 177system.cpu.l2cache.demand_hits 1991062 # number of demand (read+write) hits 178system.cpu.l2cache.overall_hits 1991062 # number of overall hits 179system.cpu.l2cache.ReadReq_misses 34117 # number of ReadReq misses 180system.cpu.l2cache.ReadExReq_misses 42458 # number of ReadExReq misses 181system.cpu.l2cache.demand_misses 76575 # number of demand (read+write) misses 182system.cpu.l2cache.overall_misses 76575 # number of overall misses 183system.cpu.l2cache.ReadReq_miss_latency 1774084000 # number of ReadReq miss cycles 184system.cpu.l2cache.ReadExReq_miss_latency 2207845500 # number of ReadExReq miss cycles 185system.cpu.l2cache.demand_miss_latency 3981929500 # number of demand (read+write) miss cycles 186system.cpu.l2cache.overall_miss_latency 3981929500 # number of overall miss cycles 187system.cpu.l2cache.ReadReq_accesses 1961528 # number of ReadReq accesses(hits+misses) 188system.cpu.l2cache.Writeback_accesses 1437080 # number of Writeback accesses(hits+misses) 189system.cpu.l2cache.ReadExReq_accesses 106109 # number of ReadExReq accesses(hits+misses) 190system.cpu.l2cache.demand_accesses 2067637 # number of demand (read+write) accesses 191system.cpu.l2cache.overall_accesses 2067637 # number of overall (read+write) accesses 192system.cpu.l2cache.ReadReq_miss_rate 0.017393 # miss rate for ReadReq accesses 193system.cpu.l2cache.ReadExReq_miss_rate 0.400136 # miss rate for ReadExReq accesses 194system.cpu.l2cache.demand_miss_rate 0.037035 # miss rate for demand accesses 195system.cpu.l2cache.overall_miss_rate 0.037035 # miss rate for overall accesses 196system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency 197system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804 # average ReadExReq miss latency 198system.cpu.l2cache.demand_avg_miss_latency 52000.385243 # average overall miss latency 199system.cpu.l2cache.overall_avg_miss_latency 52000.385243 # average overall miss latency 200system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 201system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 202system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 203system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 204system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 205system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 206system.cpu.l2cache.fast_writes 0 # number of fast writes performed 207system.cpu.l2cache.cache_copies 0 # number of cache copies performed 208system.cpu.l2cache.writebacks 29460 # number of writebacks 209system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 210system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 211system.cpu.l2cache.ReadReq_mshr_misses 34117 # number of ReadReq MSHR misses 212system.cpu.l2cache.ReadExReq_mshr_misses 42458 # number of ReadExReq MSHR misses 213system.cpu.l2cache.demand_mshr_misses 76575 # number of demand (read+write) MSHR misses 214system.cpu.l2cache.overall_mshr_misses 76575 # number of overall MSHR misses 215system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 216system.cpu.l2cache.ReadReq_mshr_miss_latency 1364680000 # number of ReadReq MSHR miss cycles 217system.cpu.l2cache.ReadExReq_mshr_miss_latency 1698320000 # number of ReadExReq MSHR miss cycles 218system.cpu.l2cache.demand_mshr_miss_latency 3063000000 # number of demand (read+write) MSHR miss cycles 219system.cpu.l2cache.overall_mshr_miss_latency 3063000000 # number of overall MSHR miss cycles 220system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 221system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017393 # mshr miss rate for ReadReq accesses 222system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.400136 # mshr miss rate for ReadExReq accesses 223system.cpu.l2cache.demand_mshr_miss_rate 0.037035 # mshr miss rate for demand accesses 224system.cpu.l2cache.overall_mshr_miss_rate 0.037035 # mshr miss rate for overall accesses 225system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency 226system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency 227system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency 228system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency 229system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 230system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 231system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 232system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 233 234---------- End Simulation Statistics ---------- 235