stats.txt revision 11570:4aac82f10951
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.366199 # Number of seconds simulated 4sim_ticks 366199170500 # Number of ticks simulated 5final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 454673 # Simulator instruction rate (inst/s) 8host_op_rate 800606 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1053878980 # Simulator tick rate (ticks/s) 10host_mem_usage 406480 # Number of bytes of host memory used 11host_seconds 347.48 # Real time elapsed on the host 12sim_insts 157988548 # Number of instructions simulated 13sim_ops 278192465 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6528 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 102 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s) 40system.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 43system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 44system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 45system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 46system.cpu.workload.num_syscalls 444 # Number of system calls 47system.cpu.pwrStateResidencyTicks::ON 366199170500 # Cumulative time (in ticks) in various power states 48system.cpu.numCycles 732398341 # number of cpu cycles simulated 49system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 50system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 51system.cpu.committedInsts 157988548 # Number of instructions committed 52system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 53system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses 54system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 55system.cpu.num_func_calls 8475189 # number of times a function call or return occured 56system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls 57system.cpu.num_int_insts 278169482 # number of integer instructions 58system.cpu.num_fp_insts 40 # number of float instructions 59system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read 60system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written 61system.cpu.num_fp_register_reads 40 # number of times the floating registers were read 62system.cpu.num_fp_register_writes 26 # number of times the floating registers were written 63system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read 64system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written 65system.cpu.num_mem_refs 122219137 # number of memory refs 66system.cpu.num_load_insts 90779385 # Number of load instructions 67system.cpu.num_store_insts 31439752 # Number of store instructions 68system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 69system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles 70system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 71system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 72system.cpu.Branches 29309705 # Number of branches fetched 73system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction 74system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction 75system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction 76system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction 77system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction 78system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction 79system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction 80system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction 81system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction 82system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction 83system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction 84system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction 85system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction 86system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction 87system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction 88system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction 89system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction 90system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction 91system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction 92system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction 93system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction 94system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction 95system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction 96system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction 97system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction 98system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction 99system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction 100system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction 101system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction 102system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction 103system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction 104system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction 105system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 106system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 107system.cpu.op_class::total 278192465 # Class of executed instruction 108system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 109system.cpu.dcache.tags.replacements 2062733 # number of replacements 110system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use 111system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. 112system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. 113system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. 114system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit. 115system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor 116system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy 117system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy 118system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 119system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 120system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id 121system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id 122system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 123system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 124system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses 125system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses 126system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 127system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits 128system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits 129system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits 130system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits 131system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits 132system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits 133system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits 134system.cpu.dcache.overall_hits::total 120152370 # number of overall hits 135system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 136system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 137system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 138system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 139system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 140system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 141system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 142system.cpu.dcache.overall_misses::total 2066829 # number of overall misses 143system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles 144system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles 145system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles 146system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles 147system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles 148system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles 149system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles 150system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles 151system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) 152system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) 153system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 154system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 155system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses 156system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses 157system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses 158system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses 159system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 160system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 161system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 162system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 163system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 164system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 165system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 166system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses 167system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency 168system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency 169system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency 170system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency 171system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency 172system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency 173system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency 174system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency 175system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 176system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 179system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 181system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks 182system.cpu.dcache.writebacks::total 2062482 # number of writebacks 183system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 184system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 185system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 186system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 187system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 188system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses 189system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses 190system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses 191system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles 192system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles 193system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles 194system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles 195system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles 196system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles 197system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles 198system.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles 199system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses 200system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses 201system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses 202system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses 203system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses 204system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses 205system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses 206system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses 207system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency 208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency 209system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency 210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency 211system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency 212system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency 213system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency 214system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency 215system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 216system.cpu.icache.tags.replacements 24 # number of replacements 217system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use 218system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. 219system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 220system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. 221system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 222system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor 223system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy 224system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy 225system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id 226system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 227system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 228system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id 229system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id 230system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses 231system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses 232system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 233system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits 234system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits 235system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits 236system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits 237system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits 238system.cpu.icache.overall_hits::total 217695356 # number of overall hits 239system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 240system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 241system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 242system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 243system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 244system.cpu.icache.overall_misses::total 808 # number of overall misses 245system.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles 246system.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles 247system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles 248system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles 249system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles 250system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles 251system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) 252system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) 253system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses 254system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses 255system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses 256system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses 257system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 258system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 259system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 260system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 261system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 262system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 263system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency 264system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency 265system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency 266system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency 267system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency 268system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency 269system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 270system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 271system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 272system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 273system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 274system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 275system.cpu.icache.writebacks::writebacks 24 # number of writebacks 276system.cpu.icache.writebacks::total 24 # number of writebacks 277system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 278system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 279system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 280system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 281system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 282system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses 283system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles 284system.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles 285system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles 286system.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles 287system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles 288system.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles 289system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 290system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 291system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 292system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 293system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 294system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 295system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency 296system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency 297system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency 298system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency 299system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency 300system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency 301system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 302system.cpu.l2cache.tags.replacements 313 # number of replacements 303system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use 304system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. 305system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. 306system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. 307system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 308system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor 309system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor 310system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor 311system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy 312system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy 313system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy 314system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy 315system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id 316system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 317system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 318system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 319system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id 320system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id 321system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id 322system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses 323system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses 324system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 325system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits 326system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits 327system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits 328system.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits 329system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits 330system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits 331system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits 332system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits 333system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960503 # number of ReadSharedReq hits 334system.cpu.l2cache.ReadSharedReq_hits::total 1960503 # number of ReadSharedReq hits 335system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits 336system.cpu.l2cache.demand_hits::cpu.data 2037588 # number of demand (read+write) hits 337system.cpu.l2cache.demand_hits::total 2037593 # number of demand (read+write) hits 338system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits 339system.cpu.l2cache.overall_hits::cpu.data 2037588 # number of overall hits 340system.cpu.l2cache.overall_hits::total 2037593 # number of overall hits 341system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses 342system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses 343system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses 344system.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses 345system.cpu.l2cache.ReadSharedReq_misses::cpu.data 217 # number of ReadSharedReq misses 346system.cpu.l2cache.ReadSharedReq_misses::total 217 # number of ReadSharedReq misses 347system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 348system.cpu.l2cache.demand_misses::cpu.data 29241 # number of demand (read+write) misses 349system.cpu.l2cache.demand_misses::total 30044 # number of demand (read+write) misses 350system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses 351system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses 352system.cpu.l2cache.overall_misses::total 30044 # number of overall misses 353system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles 354system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles 355system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles 356system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles 357system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles 358system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles 359system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles 360system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles 361system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles 362system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles 363system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles 364system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles 365system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses) 366system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses) 367system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses) 368system.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses) 369system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) 370system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) 371system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses) 372system.cpu.l2cache.ReadCleanReq_accesses::total 808 # number of ReadCleanReq accesses(hits+misses) 373system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720 # number of ReadSharedReq accesses(hits+misses) 374system.cpu.l2cache.ReadSharedReq_accesses::total 1960720 # number of ReadSharedReq accesses(hits+misses) 375system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses 376system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses 377system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses 378system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses 379system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses 380system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses 381system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses 382system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses 383system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses 384system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses 385system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000111 # miss rate for ReadSharedReq accesses 386system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000111 # miss rate for ReadSharedReq accesses 387system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses 388system.cpu.l2cache.demand_miss_rate::cpu.data 0.014148 # miss rate for demand accesses 389system.cpu.l2cache.demand_miss_rate::total 0.014531 # miss rate for demand accesses 390system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses 391system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses 392system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses 393system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency 394system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency 395system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency 396system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency 397system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 398system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 399system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency 400system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency 401system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency 402system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency 403system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency 404system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency 405system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 406system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 407system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 408system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 409system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 410system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 411system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks 412system.cpu.l2cache.writebacks::total 102 # number of writebacks 413system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 414system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 415system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses 416system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses 417system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses 418system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses 419system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 420system.cpu.l2cache.demand_mshr_misses::cpu.data 29241 # number of demand (read+write) MSHR misses 421system.cpu.l2cache.demand_mshr_misses::total 30044 # number of demand (read+write) MSHR misses 422system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 423system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses 424system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses 425system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles 426system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles 427system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles 428system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles 429system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles 430system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles 431system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles 432system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles 433system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles 434system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles 435system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles 436system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles 437system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses 438system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses 439system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses 440system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses 441system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses 442system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses 443system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses 444system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses 445system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses 446system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses 447system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses 448system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses 449system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency 450system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency 451system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency 452system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency 453system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 454system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 455system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency 456system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency 457system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency 458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency 459system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency 460system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency 461system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. 462system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. 463system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 464system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. 465system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 466system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 467system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 468system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution 473system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution 474system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution 475system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution 476system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) 477system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) 478system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) 479system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) 480system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) 481system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) 482system.cpu.toL2Bus.snoops 313 # Total snoops (count) 483system.cpu.toL2Bus.snoopTraffic 6528 # Total snoop traffic (bytes) 484system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram 485system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram 486system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram 487system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 488system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram 490system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 491system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 492system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 493system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram 495system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) 496system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 497system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) 498system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 499system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) 500system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 501system.membus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states 502system.membus.trans_dist::ReadResp 1020 # Transaction distribution 503system.membus.trans_dist::WritebackDirty 102 # Transaction distribution 504system.membus.trans_dist::CleanEvict 14 # Transaction distribution 505system.membus.trans_dist::ReadExReq 29024 # Transaction distribution 506system.membus.trans_dist::ReadExResp 29024 # Transaction distribution 507system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution 508system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes) 509system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes) 510system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes) 511system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes) 512system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes) 513system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes) 514system.membus.snoops 0 # Total snoops (count) 515system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 516system.membus.snoop_fanout::samples 30160 # Request fanout histogram 517system.membus.snoop_fanout::mean 0 # Request fanout histogram 518system.membus.snoop_fanout::stdev 0 # Request fanout histogram 519system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 520system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram 521system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 522system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 523system.membus.snoop_fanout::min_value 0 # Request fanout histogram 524system.membus.snoop_fanout::max_value 0 # Request fanout histogram 525system.membus.snoop_fanout::total 30160 # Request fanout histogram 526system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks) 527system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 528system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks) 529system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 530 531---------- End Simulation Statistics ---------- 532