stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.366199 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 366199170500 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 433838 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 763918 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 1005585249 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 405532 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 364.17 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 157988548 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 278192465 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 1922816 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 6528 # Number of bytes written to this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 30044 # Number of read requests responded to by this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 102 # Number of write requests responded to by this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s) 2911507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s) 3011507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s) 3111507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s) 3211507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s) 3311507SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s) 3411507SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s) 3511507SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s) 3611507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s) 3711507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s) 3811507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s) 3911507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 4011507SCurtis.Dunham@arm.comsystem.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 4111507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 444 # Number of system calls 4211507SCurtis.Dunham@arm.comsystem.cpu.numCycles 732398341 # number of cpu cycles simulated 4311507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4411507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 4511507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 157988548 # Number of instructions committed 4611507SCurtis.Dunham@arm.comsystem.cpu.committedOps 278192465 # Number of ops (including micro ops) committed 4711507SCurtis.Dunham@arm.comsystem.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses 4811507SCurtis.Dunham@arm.comsystem.cpu.num_fp_alu_accesses 40 # Number of float alu accesses 4911507SCurtis.Dunham@arm.comsystem.cpu.num_func_calls 8475189 # number of times a function call or return occured 5011507SCurtis.Dunham@arm.comsystem.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls 5111507SCurtis.Dunham@arm.comsystem.cpu.num_int_insts 278169482 # number of integer instructions 5211507SCurtis.Dunham@arm.comsystem.cpu.num_fp_insts 40 # number of float instructions 5311507SCurtis.Dunham@arm.comsystem.cpu.num_int_register_reads 635379407 # number of times the integer registers were read 5411507SCurtis.Dunham@arm.comsystem.cpu.num_int_register_writes 217447860 # number of times the integer registers were written 5511507SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_reads 40 # number of times the floating registers were read 5611507SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_writes 26 # number of times the floating registers were written 5711507SCurtis.Dunham@arm.comsystem.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read 5811507SCurtis.Dunham@arm.comsystem.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written 5911507SCurtis.Dunham@arm.comsystem.cpu.num_mem_refs 122219137 # number of memory refs 6011507SCurtis.Dunham@arm.comsystem.cpu.num_load_insts 90779385 # Number of load instructions 6111507SCurtis.Dunham@arm.comsystem.cpu.num_store_insts 31439752 # Number of store instructions 6211507SCurtis.Dunham@arm.comsystem.cpu.num_idle_cycles 0.002000 # Number of idle cycles 6311507SCurtis.Dunham@arm.comsystem.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles 6411507SCurtis.Dunham@arm.comsystem.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 6511507SCurtis.Dunham@arm.comsystem.cpu.idle_fraction 0.000000 # Percentage of idle cycles 6611507SCurtis.Dunham@arm.comsystem.cpu.Branches 29309705 # Number of branches fetched 6711507SCurtis.Dunham@arm.comsystem.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction 6811507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction 6911507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction 7011507SCurtis.Dunham@arm.comsystem.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction 7111507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction 7211507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction 7311507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction 7411507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction 7511507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction 7611507SCurtis.Dunham@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction 7711507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction 7811507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction 7911507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction 8011507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction 8111507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction 8211507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction 8311507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction 8411507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction 8511507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction 8611507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction 8711507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction 8811507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction 8911507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction 9011507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction 9111507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction 9211507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction 9311507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction 9411507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction 9511507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction 9611507SCurtis.Dunham@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction 9711507SCurtis.Dunham@arm.comsystem.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction 9811507SCurtis.Dunham@arm.comsystem.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction 9911507SCurtis.Dunham@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 10011507SCurtis.Dunham@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 10111507SCurtis.Dunham@arm.comsystem.cpu.op_class::total 278192465 # Class of executed instruction 10211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 2062733 # number of replacements 10311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use 10411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. 10511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. 10611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. 10711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit. 10811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor 10911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy 11011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy 11111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 11211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 11311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id 11411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id 11511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 11611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 11711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses 11811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses 11911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits 12011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits 12111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits 12211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits 12311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits 12411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits 12511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits 12611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 120152370 # number of overall hits 12711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses 12811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses 12911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses 13011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses 13111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses 13211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses 13311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses 13411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 2066829 # number of overall misses 13511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles 13611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles 13711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles 13811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles 13911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles 14011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles 14111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles 14211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles 14311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) 14411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) 14511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 14611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 14711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses 14811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses 14911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses 15011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses 15111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses 15211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 15311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses 15411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses 15511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses 15611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses 15711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses 15811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses 15911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency 16011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency 16111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency 16211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency 16311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency 16411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency 16511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency 16611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency 16711507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 16811507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 16911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 17011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 17111507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 17211507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 17311507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks 17411507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 2062482 # number of writebacks 17511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses 17611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses 17711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses 17811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses 17911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses 18011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses 18111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses 18211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses 18311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles 18411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles 18511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles 18611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles 18711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles 18811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles 18911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles 19011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles 19111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses 19211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses 19311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses 19411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses 19511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses 19611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses 19711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses 19811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses 19911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency 20011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency 20111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency 20211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency 20311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency 20411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency 20511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency 20611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency 20711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 24 # number of replacements 20811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use 20911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. 21011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. 21111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. 21211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 21311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor 21411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy 21511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy 21611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id 21711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 21811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id 21911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id 22011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id 22111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses 22211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 435393136 # Number of data accesses 22311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits 22411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits 22511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits 22611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits 22711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits 22811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 217695356 # number of overall hits 22911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses 23011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses 23111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses 23211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses 23311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses 23411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 808 # number of overall misses 23511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles 23611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles 23711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles 23811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles 23911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles 24011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles 24111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) 24211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) 24311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses 24411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses 24511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses 24611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses 24711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 24811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 24911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 25011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 25111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 25211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 25311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency 25411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency 25511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency 25611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency 25711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency 25811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency 25911507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 26011507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 26111507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 26211507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 26311507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 26411507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 26511507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 24 # number of writebacks 26611507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 24 # number of writebacks 26711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses 26811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses 26911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses 27011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses 27111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses 27211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses 27311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles 27411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles 27511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles 27611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles 27711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles 27811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles 27911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses 28011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses 28111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses 28211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses 28311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses 28411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses 28511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency 28611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency 28711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency 28811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency 28911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency 29011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency 29111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 313 # number of replacements 29211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use 29311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. 29411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. 29511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. 29611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 29711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor 29811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor 29911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor 30011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy 30111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy 30211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy 30311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy 30411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id 30511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 30611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id 30711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 30811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id 30911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id 31011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id 31111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses 31211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses 31311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits 31411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits 31511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits 31611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits 31711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits 31811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits 31911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits 32011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits 32111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960503 # number of ReadSharedReq hits 32211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 1960503 # number of ReadSharedReq hits 32311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits 32411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 2037588 # number of demand (read+write) hits 32511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 2037593 # number of demand (read+write) hits 32611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits 32711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 2037588 # number of overall hits 32811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 2037593 # number of overall hits 32911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses 33011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses 33111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses 33211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses 33311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 217 # number of ReadSharedReq misses 33411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 217 # number of ReadSharedReq misses 33511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses 33611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 29241 # number of demand (read+write) misses 33711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 30044 # number of demand (read+write) misses 33811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses 33911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses 34011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 30044 # number of overall misses 34111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles 34211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles 34311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles 34411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles 34511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles 34611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles 34711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles 34811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles 34911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles 35011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles 35111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles 35211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles 35311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses) 35411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses) 35511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses) 35611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses) 35711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) 35811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) 35911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses) 36011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 808 # number of ReadCleanReq accesses(hits+misses) 36111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720 # number of ReadSharedReq accesses(hits+misses) 36211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1960720 # number of ReadSharedReq accesses(hits+misses) 36311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses 36411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses 36511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses 36611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses 36711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses 36811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses 36911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses 37011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses 37111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses 37211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses 37311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000111 # miss rate for ReadSharedReq accesses 37411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000111 # miss rate for ReadSharedReq accesses 37511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses 37611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.014148 # miss rate for demand accesses 37711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.014531 # miss rate for demand accesses 37811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses 37911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses 38011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses 38111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency 38211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency 38311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency 38411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency 38511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 38611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 38711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency 38811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency 38911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency 39011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency 39111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency 39211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency 39311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 39411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 39511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 39611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 39711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 102 # number of writebacks 40011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 102 # number of writebacks 40111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses 40211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses 40311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses 40411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses 40511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses 40611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses 40711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses 40811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 29241 # number of demand (read+write) MSHR misses 40911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 30044 # number of demand (read+write) MSHR misses 41011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses 41111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses 41211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses 41311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles 41411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles 41511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles 41611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles 41711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles 41811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles 41911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles 42011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles 42111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles 42211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles 42311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles 42411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles 42511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses 42611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses 42711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses 42811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses 42911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses 43011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses 43111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses 43211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses 43311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses 43411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses 43511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses 43611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses 43711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency 43811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency 43911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency 44011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency 44111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 44211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 44311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency 44411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency 44511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency 44611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency 44711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency 44811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency 44911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. 45011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. 45111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 45211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. 45311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 45411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 45511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution 45611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution 45711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution 45811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution 45911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution 46011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution 46111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution 46211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution 46311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) 46411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) 46511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) 46611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) 46711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) 46811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) 46911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 313 # Total snoops (count) 47011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram 47111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram 47211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram 47311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 47411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram 47511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram 47611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 47711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 47811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 47911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 48011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram 48111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) 48211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 48311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) 48411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 48511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) 48611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 48711507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 1020 # Transaction distribution 48811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 102 # Transaction distribution 48911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 14 # Transaction distribution 49011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 29024 # Transaction distribution 49111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 29024 # Transaction distribution 49211507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution 49311507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes) 49411507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes) 49511507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes) 49611507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes) 49711507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes) 49811507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes) 49911507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 50011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 30160 # Request fanout histogram 50111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 50211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 50311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 50411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram 50511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 50611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 50711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 50811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 50911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 30160 # Request fanout histogram 51011507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks) 51111507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 51211507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks) 51311507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.0 # Layer utilization (%) 51411507SCurtis.Dunham@arm.com 51511507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 516