stats.txt revision 9013:afa278317136
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.067388 # Number of seconds simulated 4sim_ticks 67388458000 # Number of ticks simulated 5final_tick 67388458000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 49866 # Simulator instruction rate (inst/s) 8host_op_rate 87805 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 21269638 # Simulator tick rate (ticks/s) 10host_mem_usage 411868 # Number of bytes of host memory used 11host_seconds 3168.29 # Real time elapsed on the host 12sim_insts 157988582 # Number of instructions simulated 13sim_ops 278192519 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 3907520 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 69248 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 897536 # Number of bytes written to this memory 17system.physmem.num_reads 61055 # Number of read requests responded to by this memory 18system.physmem.num_writes 14024 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 57985004 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1027594 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 13318839 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 71303843 # Total bandwidth to/from this memory (bytes/s) 24system.cpu.workload.num_syscalls 444 # Number of system calls 25system.cpu.numCycles 134776917 # number of cpu cycles simulated 26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 28system.cpu.BPredUnit.lookups 36128556 # Number of BP lookups 29system.cpu.BPredUnit.condPredicted 36128556 # Number of conditional branches predicted 30system.cpu.BPredUnit.condIncorrect 1088012 # Number of conditional branches incorrect 31system.cpu.BPredUnit.BTBLookups 25661198 # Number of BTB lookups 32system.cpu.BPredUnit.BTBHits 25550813 # Number of BTB hits 33system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 34system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 35system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 36system.cpu.fetch.icacheStallCycles 27997413 # Number of cycles fetch is stalled on an Icache miss 37system.cpu.fetch.Insts 196488492 # Number of instructions fetch has processed 38system.cpu.fetch.Branches 36128556 # Number of branches that fetch encountered 39system.cpu.fetch.predictedBranches 25550813 # Number of branches that fetch has predicted taken 40system.cpu.fetch.Cycles 59432634 # Number of cycles fetch has run and was not squashing or blocked 41system.cpu.fetch.SquashCycles 8416233 # Number of cycles fetch has spent squashing 42system.cpu.fetch.BlockedCycles 39238726 # Number of cycles fetch has spent blocked 43system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 44system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 45system.cpu.fetch.CacheLines 27278821 # Number of cache lines fetched 46system.cpu.fetch.IcacheSquashes 142192 # Number of outstanding Icache misses that were squashed 47system.cpu.fetch.rateDist::samples 133966907 # Number of instructions fetched each cycle (Total) 48system.cpu.fetch.rateDist::mean 2.578141 # Number of instructions fetched each cycle (Total) 49system.cpu.fetch.rateDist::stdev 3.358289 # Number of instructions fetched each cycle (Total) 50system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 51system.cpu.fetch.rateDist::0 77274639 57.68% 57.68% # Number of instructions fetched each cycle (Total) 52system.cpu.fetch.rateDist::1 2166516 1.62% 59.30% # Number of instructions fetched each cycle (Total) 53system.cpu.fetch.rateDist::2 2997281 2.24% 61.54% # Number of instructions fetched each cycle (Total) 54system.cpu.fetch.rateDist::3 4102912 3.06% 64.60% # Number of instructions fetched each cycle (Total) 55system.cpu.fetch.rateDist::4 8026102 5.99% 70.59% # Number of instructions fetched each cycle (Total) 56system.cpu.fetch.rateDist::5 5043006 3.76% 74.35% # Number of instructions fetched each cycle (Total) 57system.cpu.fetch.rateDist::6 2893464 2.16% 76.51% # Number of instructions fetched each cycle (Total) 58system.cpu.fetch.rateDist::7 1468336 1.10% 77.61% # Number of instructions fetched each cycle (Total) 59system.cpu.fetch.rateDist::8 29994651 22.39% 100.00% # Number of instructions fetched each cycle (Total) 60system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 61system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 62system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 63system.cpu.fetch.rateDist::total 133966907 # Number of instructions fetched each cycle (Total) 64system.cpu.fetch.branchRate 0.268062 # Number of branch fetches per cycle 65system.cpu.fetch.rate 1.457879 # Number of inst fetches per cycle 66system.cpu.decode.IdleCycles 40465112 # Number of cycles decode is idle 67system.cpu.decode.BlockedCycles 30125694 # Number of cycles decode is blocked 68system.cpu.decode.RunCycles 46506148 # Number of cycles decode is running 69system.cpu.decode.UnblockCycles 9571987 # Number of cycles decode is unblocking 70system.cpu.decode.SquashCycles 7297966 # Number of cycles decode is squashing 71system.cpu.decode.DecodedInsts 341297669 # Number of instructions handled by decode 72system.cpu.rename.SquashCycles 7297966 # Number of cycles rename is squashing 73system.cpu.rename.IdleCycles 45865108 # Number of cycles rename is idle 74system.cpu.rename.BlockCycles 5065508 # Number of cycles rename is blocking 75system.cpu.rename.serializeStallCycles 9277 # count of cycles rename stalled for serializing inst 76system.cpu.rename.RunCycles 50351191 # Number of cycles rename is running 77system.cpu.rename.UnblockCycles 25377857 # Number of cycles rename is unblocking 78system.cpu.rename.RenamedInsts 337406380 # Number of instructions processed by rename 79system.cpu.rename.ROBFullEvents 13 # Number of times rename has blocked due to ROB full 80system.cpu.rename.IQFullEvents 3712 # Number of times rename has blocked due to IQ full 81system.cpu.rename.LSQFullEvents 23187560 # Number of times rename has blocked due to LSQ full 82system.cpu.rename.FullRegisterEvents 79157 # Number of times there has been no free registers 83system.cpu.rename.RenamedOperands 414755881 # Number of destination operands rename has renamed 84system.cpu.rename.RenameLookups 1009935088 # Number of register rename lookups that rename has made 85system.cpu.rename.int_rename_lookups 1009932388 # Number of integer rename lookups 86system.cpu.rename.fp_rename_lookups 2700 # Number of floating rename lookups 87system.cpu.rename.CommittedMaps 341010940 # Number of HB maps that are committed 88system.cpu.rename.UndoneMaps 73744941 # Number of HB maps that are undone due to squashing 89system.cpu.rename.serializingInsts 481 # count of serializing insts renamed 90system.cpu.rename.tempSerializingInsts 474 # count of temporary serializing insts renamed 91system.cpu.rename.skidInsts 56192967 # count of insts added to the skid buffer 92system.cpu.memDep0.insertedLoads 108162580 # Number of loads inserted to the mem dependence unit. 93system.cpu.memDep0.insertedStores 37173372 # Number of stores inserted to the mem dependence unit. 94system.cpu.memDep0.conflictingLoads 46311356 # Number of conflicting loads. 95system.cpu.memDep0.conflictingStores 7909478 # Number of conflicting stores. 96system.cpu.iq.iqInstsAdded 331723465 # Number of instructions added to the IQ (excludes non-spec) 97system.cpu.iq.iqNonSpecInstsAdded 2616 # Number of non-speculative instructions added to the IQ 98system.cpu.iq.iqInstsIssued 311412241 # Number of instructions issued 99system.cpu.iq.iqSquashedInstsIssued 185399 # Number of squashed instructions issued 100system.cpu.iq.iqSquashedInstsExamined 53269773 # Number of squashed instructions iterated over during squash; mainly for profiling 101system.cpu.iq.iqSquashedOperandsExamined 92543278 # Number of squashed operands that are examined and possibly removed from graph 102system.cpu.iq.iqSquashedNonSpecRemoved 2170 # Number of squashed non-spec instructions that were removed 103system.cpu.iq.issued_per_cycle::samples 133966907 # Number of insts issued each cycle 104system.cpu.iq.issued_per_cycle::mean 2.324546 # Number of insts issued each cycle 105system.cpu.iq.issued_per_cycle::stdev 1.724461 # Number of insts issued each cycle 106system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 107system.cpu.iq.issued_per_cycle::0 27936582 20.85% 20.85% # Number of insts issued each cycle 108system.cpu.iq.issued_per_cycle::1 17254518 12.88% 33.73% # Number of insts issued each cycle 109system.cpu.iq.issued_per_cycle::2 25564521 19.08% 52.82% # Number of insts issued each cycle 110system.cpu.iq.issued_per_cycle::3 31166509 23.26% 76.08% # Number of insts issued each cycle 111system.cpu.iq.issued_per_cycle::4 17676068 13.19% 89.27% # Number of insts issued each cycle 112system.cpu.iq.issued_per_cycle::5 9033591 6.74% 96.02% # Number of insts issued each cycle 113system.cpu.iq.issued_per_cycle::6 3761456 2.81% 98.83% # Number of insts issued each cycle 114system.cpu.iq.issued_per_cycle::7 1501105 1.12% 99.95% # Number of insts issued each cycle 115system.cpu.iq.issued_per_cycle::8 72557 0.05% 100.00% # Number of insts issued each cycle 116system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 117system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 118system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 119system.cpu.iq.issued_per_cycle::total 133966907 # Number of insts issued each cycle 120system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 121system.cpu.iq.fu_full::IntAlu 23354 1.11% 1.11% # attempts to use FU when none available 122system.cpu.iq.fu_full::IntMult 0 0.00% 1.11% # attempts to use FU when none available 123system.cpu.iq.fu_full::IntDiv 0 0.00% 1.11% # attempts to use FU when none available 124system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.11% # attempts to use FU when none available 125system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.11% # attempts to use FU when none available 126system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.11% # attempts to use FU when none available 127system.cpu.iq.fu_full::FloatMult 0 0.00% 1.11% # attempts to use FU when none available 128system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.11% # attempts to use FU when none available 129system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.11% # attempts to use FU when none available 130system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.11% # attempts to use FU when none available 131system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.11% # attempts to use FU when none available 132system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.11% # attempts to use FU when none available 133system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.11% # attempts to use FU when none available 134system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.11% # attempts to use FU when none available 135system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.11% # attempts to use FU when none available 136system.cpu.iq.fu_full::SimdMult 0 0.00% 1.11% # attempts to use FU when none available 137system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.11% # attempts to use FU when none available 138system.cpu.iq.fu_full::SimdShift 0 0.00% 1.11% # attempts to use FU when none available 139system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.11% # attempts to use FU when none available 140system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.11% # attempts to use FU when none available 141system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.11% # attempts to use FU when none available 142system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.11% # attempts to use FU when none available 143system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.11% # attempts to use FU when none available 144system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.11% # attempts to use FU when none available 145system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.11% # attempts to use FU when none available 146system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.11% # attempts to use FU when none available 147system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.11% # attempts to use FU when none available 148system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.11% # attempts to use FU when none available 149system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.11% # attempts to use FU when none available 150system.cpu.iq.fu_full::MemRead 1960413 92.78% 93.89% # attempts to use FU when none available 151system.cpu.iq.fu_full::MemWrite 129107 6.11% 100.00% # attempts to use FU when none available 152system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 153system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 154system.cpu.iq.FU_type_0::No_OpClass 31371 0.01% 0.01% # Type of FU issued 155system.cpu.iq.FU_type_0::IntAlu 177196652 56.90% 56.91% # Type of FU issued 156system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.91% # Type of FU issued 157system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.91% # Type of FU issued 158system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 56.91% # Type of FU issued 159system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.91% # Type of FU issued 160system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.91% # Type of FU issued 161system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.91% # Type of FU issued 162system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.91% # Type of FU issued 163system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.91% # Type of FU issued 164system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.91% # Type of FU issued 165system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.91% # Type of FU issued 166system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.91% # Type of FU issued 167system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.91% # Type of FU issued 168system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.91% # Type of FU issued 169system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.91% # Type of FU issued 170system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.91% # Type of FU issued 171system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.91% # Type of FU issued 172system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.91% # Type of FU issued 173system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.91% # Type of FU issued 174system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.91% # Type of FU issued 175system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.91% # Type of FU issued 176system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.91% # Type of FU issued 177system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.91% # Type of FU issued 178system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.91% # Type of FU issued 179system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.91% # Type of FU issued 180system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.91% # Type of FU issued 181system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.91% # Type of FU issued 182system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.91% # Type of FU issued 183system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.91% # Type of FU issued 184system.cpu.iq.FU_type_0::MemRead 99714062 32.02% 88.93% # Type of FU issued 185system.cpu.iq.FU_type_0::MemWrite 34470040 11.07% 100.00% # Type of FU issued 186system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 187system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 188system.cpu.iq.FU_type_0::total 311412241 # Type of FU issued 189system.cpu.iq.rate 2.310575 # Inst issue rate 190system.cpu.iq.fu_busy_cnt 2112874 # FU busy when requested 191system.cpu.iq.fu_busy_rate 0.006785 # FU busy rate (busy events/executed inst) 192system.cpu.iq.int_inst_queue_reads 759088710 # Number of integer instruction queue reads 193system.cpu.iq.int_inst_queue_writes 385026224 # Number of integer instruction queue writes 194system.cpu.iq.int_inst_queue_wakeup_accesses 308270248 # Number of integer instruction queue wakeup accesses 195system.cpu.iq.fp_inst_queue_reads 952 # Number of floating instruction queue reads 196system.cpu.iq.fp_inst_queue_writes 1427 # Number of floating instruction queue writes 197system.cpu.iq.fp_inst_queue_wakeup_accesses 314 # Number of floating instruction queue wakeup accesses 198system.cpu.iq.int_alu_accesses 313493303 # Number of integer alu accesses 199system.cpu.iq.fp_alu_accesses 441 # Number of floating point alu accesses 200system.cpu.iew.lsq.thread0.forwLoads 52569930 # Number of loads that had data forwarded from stores 201system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 202system.cpu.iew.lsq.thread0.squashedLoads 17383192 # Number of loads squashed 203system.cpu.iew.lsq.thread0.ignoredResponses 98849 # Number of memory responses ignored because the instruction is squashed 204system.cpu.iew.lsq.thread0.memOrderViolation 32443 # Number of memory ordering violations 205system.cpu.iew.lsq.thread0.squashedStores 5733621 # Number of stores squashed 206system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 207system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 208system.cpu.iew.lsq.thread0.rescheduledLoads 3316 # Number of loads that were rescheduled 209system.cpu.iew.lsq.thread0.cacheBlocked 3845 # Number of times an access to memory failed due to the cache being blocked 210system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 211system.cpu.iew.iewSquashCycles 7297966 # Number of cycles IEW is squashing 212system.cpu.iew.iewBlockCycles 891871 # Number of cycles IEW is blocking 213system.cpu.iew.iewUnblockCycles 89086 # Number of cycles IEW is unblocking 214system.cpu.iew.iewDispatchedInsts 331726081 # Number of instructions dispatched to IQ 215system.cpu.iew.iewDispSquashedInsts 45756 # Number of squashed instructions skipped by dispatch 216system.cpu.iew.iewDispLoadInsts 108162580 # Number of dispatched load instructions 217system.cpu.iew.iewDispStoreInsts 37173372 # Number of dispatched store instructions 218system.cpu.iew.iewDispNonSpecInsts 476 # Number of dispatched non-speculative instructions 219system.cpu.iew.iewIQFullEvents 224 # Number of times the IQ has become full, causing a stall 220system.cpu.iew.iewLSQFullEvents 43423 # Number of times the LSQ has become full, causing a stall 221system.cpu.iew.memOrderViolationEvents 32443 # Number of memory order violations 222system.cpu.iew.predictedTakenIncorrect 615219 # Number of branches that were predicted taken incorrectly 223system.cpu.iew.predictedNotTakenIncorrect 578970 # Number of branches that were predicted not taken incorrectly 224system.cpu.iew.branchMispredicts 1194189 # Number of branch mispredicts detected at execute 225system.cpu.iew.iewExecutedInsts 309448819 # Number of executed instructions 226system.cpu.iew.iewExecLoadInsts 99181332 # Number of load instructions executed 227system.cpu.iew.iewExecSquashedInsts 1963422 # Number of squashed instructions skipped in execute 228system.cpu.iew.exec_swp 0 # number of swp insts executed 229system.cpu.iew.exec_nop 0 # number of nop insts executed 230system.cpu.iew.exec_refs 133262430 # number of memory reference insts executed 231system.cpu.iew.exec_branches 31528913 # Number of branches executed 232system.cpu.iew.exec_stores 34081098 # Number of stores executed 233system.cpu.iew.exec_rate 2.296008 # Inst execution rate 234system.cpu.iew.wb_sent 308818207 # cumulative count of insts sent to commit 235system.cpu.iew.wb_count 308270562 # cumulative count of insts written-back 236system.cpu.iew.wb_producers 227514859 # num instructions producing a value 237system.cpu.iew.wb_consumers 467066838 # num instructions consuming a value 238system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 239system.cpu.iew.wb_rate 2.287265 # insts written-back per cycle 240system.cpu.iew.wb_fanout 0.487114 # average fanout of values written-back 241system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 242system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions 243system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions 244system.cpu.commit.commitSquashedInsts 53537768 # The number of squashed insts skipped by commit 245system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards 246system.cpu.commit.branchMispredicts 1088027 # The number of times a branch was mispredicted 247system.cpu.commit.committed_per_cycle::samples 126668941 # Number of insts commited each cycle 248system.cpu.commit.committed_per_cycle::mean 2.196217 # Number of insts commited each cycle 249system.cpu.commit.committed_per_cycle::stdev 2.674380 # Number of insts commited each cycle 250system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 251system.cpu.commit.committed_per_cycle::0 46359304 36.60% 36.60% # Number of insts commited each cycle 252system.cpu.commit.committed_per_cycle::1 24201081 19.11% 55.70% # Number of insts commited each cycle 253system.cpu.commit.committed_per_cycle::2 16849760 13.30% 69.01% # Number of insts commited each cycle 254system.cpu.commit.committed_per_cycle::3 12619079 9.96% 78.97% # Number of insts commited each cycle 255system.cpu.commit.committed_per_cycle::4 3360251 2.65% 81.62% # Number of insts commited each cycle 256system.cpu.commit.committed_per_cycle::5 3556898 2.81% 84.43% # Number of insts commited each cycle 257system.cpu.commit.committed_per_cycle::6 2707142 2.14% 86.57% # Number of insts commited each cycle 258system.cpu.commit.committed_per_cycle::7 1157073 0.91% 87.48% # Number of insts commited each cycle 259system.cpu.commit.committed_per_cycle::8 15858353 12.52% 100.00% # Number of insts commited each cycle 260system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 261system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 262system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 263system.cpu.commit.committed_per_cycle::total 126668941 # Number of insts commited each cycle 264system.cpu.commit.committedInsts 157988582 # Number of instructions committed 265system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed 266system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 267system.cpu.commit.refs 122219139 # Number of memory references committed 268system.cpu.commit.loads 90779388 # Number of loads committed 269system.cpu.commit.membars 0 # Number of memory barriers committed 270system.cpu.commit.branches 29309710 # Number of branches committed 271system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 272system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. 273system.cpu.commit.function_calls 0 # Number of function calls committed. 274system.cpu.commit.bw_lim_events 15858353 # number cycles where commit BW limit reached 275system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 276system.cpu.rob.rob_reads 442540875 # The number of ROB reads 277system.cpu.rob.rob_writes 670767297 # The number of ROB writes 278system.cpu.timesIdled 23993 # Number of times that the entire CPU went into an idle state and unscheduled itself 279system.cpu.idleCycles 810010 # Total number of cycles that the CPU has spent unscheduled due to idling 280system.cpu.committedInsts 157988582 # Number of Instructions Simulated 281system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated 282system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated 283system.cpu.cpi 0.853080 # CPI: Cycles Per Instruction 284system.cpu.cpi_total 0.853080 # CPI: Total CPI of All Threads 285system.cpu.ipc 1.172223 # IPC: Instructions Per Cycle 286system.cpu.ipc_total 1.172223 # IPC: Total IPC of All Threads 287system.cpu.int_regfile_reads 705322543 # number of integer regfile reads 288system.cpu.int_regfile_writes 373244258 # number of integer regfile writes 289system.cpu.fp_regfile_reads 361 # number of floating regfile reads 290system.cpu.fp_regfile_writes 193 # number of floating regfile writes 291system.cpu.misc_regfile_reads 197929880 # number of misc regfile reads 292system.cpu.icache.replacements 97 # number of replacements 293system.cpu.icache.tagsinuse 846.508998 # Cycle average of tags in use 294system.cpu.icache.total_refs 27277404 # Total number of references to valid blocks. 295system.cpu.icache.sampled_refs 1093 # Sample count of references to valid blocks. 296system.cpu.icache.avg_refs 24956.453797 # Average number of references to valid blocks. 297system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 298system.cpu.icache.occ_blocks::cpu.inst 846.508998 # Average occupied blocks per requestor 299system.cpu.icache.occ_percent::cpu.inst 0.413334 # Average percentage of cache occupancy 300system.cpu.icache.occ_percent::total 0.413334 # Average percentage of cache occupancy 301system.cpu.icache.ReadReq_hits::cpu.inst 27277408 # number of ReadReq hits 302system.cpu.icache.ReadReq_hits::total 27277408 # number of ReadReq hits 303system.cpu.icache.demand_hits::cpu.inst 27277408 # number of demand (read+write) hits 304system.cpu.icache.demand_hits::total 27277408 # number of demand (read+write) hits 305system.cpu.icache.overall_hits::cpu.inst 27277408 # number of overall hits 306system.cpu.icache.overall_hits::total 27277408 # number of overall hits 307system.cpu.icache.ReadReq_misses::cpu.inst 1413 # number of ReadReq misses 308system.cpu.icache.ReadReq_misses::total 1413 # number of ReadReq misses 309system.cpu.icache.demand_misses::cpu.inst 1413 # number of demand (read+write) misses 310system.cpu.icache.demand_misses::total 1413 # number of demand (read+write) misses 311system.cpu.icache.overall_misses::cpu.inst 1413 # number of overall misses 312system.cpu.icache.overall_misses::total 1413 # number of overall misses 313system.cpu.icache.ReadReq_miss_latency::cpu.inst 50201500 # number of ReadReq miss cycles 314system.cpu.icache.ReadReq_miss_latency::total 50201500 # number of ReadReq miss cycles 315system.cpu.icache.demand_miss_latency::cpu.inst 50201500 # number of demand (read+write) miss cycles 316system.cpu.icache.demand_miss_latency::total 50201500 # number of demand (read+write) miss cycles 317system.cpu.icache.overall_miss_latency::cpu.inst 50201500 # number of overall miss cycles 318system.cpu.icache.overall_miss_latency::total 50201500 # number of overall miss cycles 319system.cpu.icache.ReadReq_accesses::cpu.inst 27278821 # number of ReadReq accesses(hits+misses) 320system.cpu.icache.ReadReq_accesses::total 27278821 # number of ReadReq accesses(hits+misses) 321system.cpu.icache.demand_accesses::cpu.inst 27278821 # number of demand (read+write) accesses 322system.cpu.icache.demand_accesses::total 27278821 # number of demand (read+write) accesses 323system.cpu.icache.overall_accesses::cpu.inst 27278821 # number of overall (read+write) accesses 324system.cpu.icache.overall_accesses::total 27278821 # number of overall (read+write) accesses 325system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses 326system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses 327system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses 328system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35528.308563 # average ReadReq miss latency 329system.cpu.icache.demand_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency 330system.cpu.icache.overall_avg_miss_latency::cpu.inst 35528.308563 # average overall miss latency 331system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 332system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 333system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 334system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 335system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 336system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 337system.cpu.icache.fast_writes 0 # number of fast writes performed 338system.cpu.icache.cache_copies 0 # number of cache copies performed 339system.cpu.icache.ReadReq_mshr_hits::cpu.inst 315 # number of ReadReq MSHR hits 340system.cpu.icache.ReadReq_mshr_hits::total 315 # number of ReadReq MSHR hits 341system.cpu.icache.demand_mshr_hits::cpu.inst 315 # number of demand (read+write) MSHR hits 342system.cpu.icache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits 343system.cpu.icache.overall_mshr_hits::cpu.inst 315 # number of overall MSHR hits 344system.cpu.icache.overall_mshr_hits::total 315 # number of overall MSHR hits 345system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1098 # number of ReadReq MSHR misses 346system.cpu.icache.ReadReq_mshr_misses::total 1098 # number of ReadReq MSHR misses 347system.cpu.icache.demand_mshr_misses::cpu.inst 1098 # number of demand (read+write) MSHR misses 348system.cpu.icache.demand_mshr_misses::total 1098 # number of demand (read+write) MSHR misses 349system.cpu.icache.overall_mshr_misses::cpu.inst 1098 # number of overall MSHR misses 350system.cpu.icache.overall_mshr_misses::total 1098 # number of overall MSHR misses 351system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38330500 # number of ReadReq MSHR miss cycles 352system.cpu.icache.ReadReq_mshr_miss_latency::total 38330500 # number of ReadReq MSHR miss cycles 353system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38330500 # number of demand (read+write) MSHR miss cycles 354system.cpu.icache.demand_mshr_miss_latency::total 38330500 # number of demand (read+write) MSHR miss cycles 355system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38330500 # number of overall MSHR miss cycles 356system.cpu.icache.overall_mshr_miss_latency::total 38330500 # number of overall MSHR miss cycles 357system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses 358system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses 359system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses 360system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34909.380692 # average ReadReq mshr miss latency 361system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency 362system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34909.380692 # average overall mshr miss latency 363system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 364system.cpu.dcache.replacements 2072128 # number of replacements 365system.cpu.dcache.tagsinuse 4072.706371 # Cycle average of tags in use 366system.cpu.dcache.total_refs 75623437 # Total number of references to valid blocks. 367system.cpu.dcache.sampled_refs 2076224 # Sample count of references to valid blocks. 368system.cpu.dcache.avg_refs 36.423544 # Average number of references to valid blocks. 369system.cpu.dcache.warmup_cycle 22601159000 # Cycle when the warmup percentage was hit. 370system.cpu.dcache.occ_blocks::cpu.data 4072.706371 # Average occupied blocks per requestor 371system.cpu.dcache.occ_percent::cpu.data 0.994313 # Average percentage of cache occupancy 372system.cpu.dcache.occ_percent::total 0.994313 # Average percentage of cache occupancy 373system.cpu.dcache.ReadReq_hits::cpu.data 44269678 # number of ReadReq hits 374system.cpu.dcache.ReadReq_hits::total 44269678 # number of ReadReq hits 375system.cpu.dcache.WriteReq_hits::cpu.data 31353743 # number of WriteReq hits 376system.cpu.dcache.WriteReq_hits::total 31353743 # number of WriteReq hits 377system.cpu.dcache.demand_hits::cpu.data 75623421 # number of demand (read+write) hits 378system.cpu.dcache.demand_hits::total 75623421 # number of demand (read+write) hits 379system.cpu.dcache.overall_hits::cpu.data 75623421 # number of overall hits 380system.cpu.dcache.overall_hits::total 75623421 # number of overall hits 381system.cpu.dcache.ReadReq_misses::cpu.data 2291019 # number of ReadReq misses 382system.cpu.dcache.ReadReq_misses::total 2291019 # number of ReadReq misses 383system.cpu.dcache.WriteReq_misses::cpu.data 86008 # number of WriteReq misses 384system.cpu.dcache.WriteReq_misses::total 86008 # number of WriteReq misses 385system.cpu.dcache.demand_misses::cpu.data 2377027 # number of demand (read+write) misses 386system.cpu.dcache.demand_misses::total 2377027 # number of demand (read+write) misses 387system.cpu.dcache.overall_misses::cpu.data 2377027 # number of overall misses 388system.cpu.dcache.overall_misses::total 2377027 # number of overall misses 389system.cpu.dcache.ReadReq_miss_latency::cpu.data 13818885500 # number of ReadReq miss cycles 390system.cpu.dcache.ReadReq_miss_latency::total 13818885500 # number of ReadReq miss cycles 391system.cpu.dcache.WriteReq_miss_latency::cpu.data 1502429791 # number of WriteReq miss cycles 392system.cpu.dcache.WriteReq_miss_latency::total 1502429791 # number of WriteReq miss cycles 393system.cpu.dcache.demand_miss_latency::cpu.data 15321315291 # number of demand (read+write) miss cycles 394system.cpu.dcache.demand_miss_latency::total 15321315291 # number of demand (read+write) miss cycles 395system.cpu.dcache.overall_miss_latency::cpu.data 15321315291 # number of overall miss cycles 396system.cpu.dcache.overall_miss_latency::total 15321315291 # number of overall miss cycles 397system.cpu.dcache.ReadReq_accesses::cpu.data 46560697 # number of ReadReq accesses(hits+misses) 398system.cpu.dcache.ReadReq_accesses::total 46560697 # number of ReadReq accesses(hits+misses) 399system.cpu.dcache.WriteReq_accesses::cpu.data 31439751 # number of WriteReq accesses(hits+misses) 400system.cpu.dcache.WriteReq_accesses::total 31439751 # number of WriteReq accesses(hits+misses) 401system.cpu.dcache.demand_accesses::cpu.data 78000448 # number of demand (read+write) accesses 402system.cpu.dcache.demand_accesses::total 78000448 # number of demand (read+write) accesses 403system.cpu.dcache.overall_accesses::cpu.data 78000448 # number of overall (read+write) accesses 404system.cpu.dcache.overall_accesses::total 78000448 # number of overall (read+write) accesses 405system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049205 # miss rate for ReadReq accesses 406system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002736 # miss rate for WriteReq accesses 407system.cpu.dcache.demand_miss_rate::cpu.data 0.030475 # miss rate for demand accesses 408system.cpu.dcache.overall_miss_rate::cpu.data 0.030475 # miss rate for overall accesses 409system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 6031.763813 # average ReadReq miss latency 410system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17468.488873 # average WriteReq miss latency 411system.cpu.dcache.demand_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency 412system.cpu.dcache.overall_avg_miss_latency::cpu.data 6445.578990 # average overall miss latency 413system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 414system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 415system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 417system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 418system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.cpu.dcache.fast_writes 0 # number of fast writes performed 420system.cpu.dcache.cache_copies 0 # number of cache copies performed 421system.cpu.dcache.writebacks::writebacks 1878988 # number of writebacks 422system.cpu.dcache.writebacks::total 1878988 # number of writebacks 423system.cpu.dcache.ReadReq_mshr_hits::cpu.data 296886 # number of ReadReq MSHR hits 424system.cpu.dcache.ReadReq_mshr_hits::total 296886 # number of ReadReq MSHR hits 425system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3910 # number of WriteReq MSHR hits 426system.cpu.dcache.WriteReq_mshr_hits::total 3910 # number of WriteReq MSHR hits 427system.cpu.dcache.demand_mshr_hits::cpu.data 300796 # number of demand (read+write) MSHR hits 428system.cpu.dcache.demand_mshr_hits::total 300796 # number of demand (read+write) MSHR hits 429system.cpu.dcache.overall_mshr_hits::cpu.data 300796 # number of overall MSHR hits 430system.cpu.dcache.overall_mshr_hits::total 300796 # number of overall MSHR hits 431system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994133 # number of ReadReq MSHR misses 432system.cpu.dcache.ReadReq_mshr_misses::total 1994133 # number of ReadReq MSHR misses 433system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82098 # number of WriteReq MSHR misses 434system.cpu.dcache.WriteReq_mshr_misses::total 82098 # number of WriteReq MSHR misses 435system.cpu.dcache.demand_mshr_misses::cpu.data 2076231 # number of demand (read+write) MSHR misses 436system.cpu.dcache.demand_mshr_misses::total 2076231 # number of demand (read+write) MSHR misses 437system.cpu.dcache.overall_mshr_misses::cpu.data 2076231 # number of overall MSHR misses 438system.cpu.dcache.overall_mshr_misses::total 2076231 # number of overall MSHR misses 439system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5596231500 # number of ReadReq MSHR miss cycles 440system.cpu.dcache.ReadReq_mshr_miss_latency::total 5596231500 # number of ReadReq MSHR miss cycles 441system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1158803791 # number of WriteReq MSHR miss cycles 442system.cpu.dcache.WriteReq_mshr_miss_latency::total 1158803791 # number of WriteReq MSHR miss cycles 443system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6755035291 # number of demand (read+write) MSHR miss cycles 444system.cpu.dcache.demand_mshr_miss_latency::total 6755035291 # number of demand (read+write) MSHR miss cycles 445system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6755035291 # number of overall MSHR miss cycles 446system.cpu.dcache.overall_mshr_miss_latency::total 6755035291 # number of overall MSHR miss cycles 447system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.042829 # mshr miss rate for ReadReq accesses 448system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002611 # mshr miss rate for WriteReq accesses 449system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for demand accesses 450system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for overall accesses 451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2806.348172 # average ReadReq mshr miss latency 452system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14114.884540 # average WriteReq mshr miss latency 453system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency 454system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3253.508541 # average overall mshr miss latency 455system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 456system.cpu.l2cache.replacements 33429 # number of replacements 457system.cpu.l2cache.tagsinuse 18994.164700 # Cycle average of tags in use 458system.cpu.l2cache.total_refs 3761791 # Total number of references to valid blocks. 459system.cpu.l2cache.sampled_refs 61439 # Sample count of references to valid blocks. 460system.cpu.l2cache.avg_refs 61.228064 # Average number of references to valid blocks. 461system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 462system.cpu.l2cache.occ_blocks::writebacks 12943.264838 # Average occupied blocks per requestor 463system.cpu.l2cache.occ_blocks::cpu.inst 249.609803 # Average occupied blocks per requestor 464system.cpu.l2cache.occ_blocks::cpu.data 5801.290058 # Average occupied blocks per requestor 465system.cpu.l2cache.occ_percent::writebacks 0.394997 # Average percentage of cache occupancy 466system.cpu.l2cache.occ_percent::cpu.inst 0.007617 # Average percentage of cache occupancy 467system.cpu.l2cache.occ_percent::cpu.data 0.177041 # Average percentage of cache occupancy 468system.cpu.l2cache.occ_percent::total 0.579656 # Average percentage of cache occupancy 469system.cpu.l2cache.ReadReq_hits::cpu.inst 12 # number of ReadReq hits 470system.cpu.l2cache.ReadReq_hits::cpu.data 1963548 # number of ReadReq hits 471system.cpu.l2cache.ReadReq_hits::total 1963560 # number of ReadReq hits 472system.cpu.l2cache.Writeback_hits::writebacks 1878988 # number of Writeback hits 473system.cpu.l2cache.Writeback_hits::total 1878988 # number of Writeback hits 474system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 475system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 476system.cpu.l2cache.ReadExReq_hits::cpu.data 52705 # number of ReadExReq hits 477system.cpu.l2cache.ReadExReq_hits::total 52705 # number of ReadExReq hits 478system.cpu.l2cache.demand_hits::cpu.inst 12 # number of demand (read+write) hits 479system.cpu.l2cache.demand_hits::cpu.data 2016253 # number of demand (read+write) hits 480system.cpu.l2cache.demand_hits::total 2016265 # number of demand (read+write) hits 481system.cpu.l2cache.overall_hits::cpu.inst 12 # number of overall hits 482system.cpu.l2cache.overall_hits::cpu.data 2016253 # number of overall hits 483system.cpu.l2cache.overall_hits::total 2016265 # number of overall hits 484system.cpu.l2cache.ReadReq_misses::cpu.inst 1082 # number of ReadReq misses 485system.cpu.l2cache.ReadReq_misses::cpu.data 30455 # number of ReadReq misses 486system.cpu.l2cache.ReadReq_misses::total 31537 # number of ReadReq misses 487system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses 488system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses 489system.cpu.l2cache.ReadExReq_misses::cpu.data 29518 # number of ReadExReq misses 490system.cpu.l2cache.ReadExReq_misses::total 29518 # number of ReadExReq misses 491system.cpu.l2cache.demand_misses::cpu.inst 1082 # number of demand (read+write) misses 492system.cpu.l2cache.demand_misses::cpu.data 59973 # number of demand (read+write) misses 493system.cpu.l2cache.demand_misses::total 61055 # number of demand (read+write) misses 494system.cpu.l2cache.overall_misses::cpu.inst 1082 # number of overall misses 495system.cpu.l2cache.overall_misses::cpu.data 59973 # number of overall misses 496system.cpu.l2cache.overall_misses::total 61055 # number of overall misses 497system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37085000 # number of ReadReq miss cycles 498system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1040283500 # number of ReadReq miss cycles 499system.cpu.l2cache.ReadReq_miss_latency::total 1077368500 # number of ReadReq miss cycles 500system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1006135000 # number of ReadExReq miss cycles 501system.cpu.l2cache.ReadExReq_miss_latency::total 1006135000 # number of ReadExReq miss cycles 502system.cpu.l2cache.demand_miss_latency::cpu.inst 37085000 # number of demand (read+write) miss cycles 503system.cpu.l2cache.demand_miss_latency::cpu.data 2046418500 # number of demand (read+write) miss cycles 504system.cpu.l2cache.demand_miss_latency::total 2083503500 # number of demand (read+write) miss cycles 505system.cpu.l2cache.overall_miss_latency::cpu.inst 37085000 # number of overall miss cycles 506system.cpu.l2cache.overall_miss_latency::cpu.data 2046418500 # number of overall miss cycles 507system.cpu.l2cache.overall_miss_latency::total 2083503500 # number of overall miss cycles 508system.cpu.l2cache.ReadReq_accesses::cpu.inst 1094 # number of ReadReq accesses(hits+misses) 509system.cpu.l2cache.ReadReq_accesses::cpu.data 1994003 # number of ReadReq accesses(hits+misses) 510system.cpu.l2cache.ReadReq_accesses::total 1995097 # number of ReadReq accesses(hits+misses) 511system.cpu.l2cache.Writeback_accesses::writebacks 1878988 # number of Writeback accesses(hits+misses) 512system.cpu.l2cache.Writeback_accesses::total 1878988 # number of Writeback accesses(hits+misses) 513system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) 514system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) 515system.cpu.l2cache.ReadExReq_accesses::cpu.data 82223 # number of ReadExReq accesses(hits+misses) 516system.cpu.l2cache.ReadExReq_accesses::total 82223 # number of ReadExReq accesses(hits+misses) 517system.cpu.l2cache.demand_accesses::cpu.inst 1094 # number of demand (read+write) accesses 518system.cpu.l2cache.demand_accesses::cpu.data 2076226 # number of demand (read+write) accesses 519system.cpu.l2cache.demand_accesses::total 2077320 # number of demand (read+write) accesses 520system.cpu.l2cache.overall_accesses::cpu.inst 1094 # number of overall (read+write) accesses 521system.cpu.l2cache.overall_accesses::cpu.data 2076226 # number of overall (read+write) accesses 522system.cpu.l2cache.overall_accesses::total 2077320 # number of overall (read+write) accesses 523system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.989031 # miss rate for ReadReq accesses 524system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.015273 # miss rate for ReadReq accesses 525system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800000 # miss rate for UpgradeReq accesses 526system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358999 # miss rate for ReadExReq accesses 527system.cpu.l2cache.demand_miss_rate::cpu.inst 0.989031 # miss rate for demand accesses 528system.cpu.l2cache.demand_miss_rate::cpu.data 0.028886 # miss rate for demand accesses 529system.cpu.l2cache.overall_miss_rate::cpu.inst 0.989031 # miss rate for overall accesses 530system.cpu.l2cache.overall_miss_rate::cpu.data 0.028886 # miss rate for overall accesses 531system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34274.491682 # average ReadReq miss latency 532system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34158.052865 # average ReadReq miss latency 533system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.473271 # average ReadExReq miss latency 534system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency 535system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency 536system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34274.491682 # average overall miss latency 537system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34122.330049 # average overall miss latency 538system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 539system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 540system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 542system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 543system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 544system.cpu.l2cache.fast_writes 0 # number of fast writes performed 545system.cpu.l2cache.cache_copies 0 # number of cache copies performed 546system.cpu.l2cache.writebacks::writebacks 14024 # number of writebacks 547system.cpu.l2cache.writebacks::total 14024 # number of writebacks 548system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1082 # number of ReadReq MSHR misses 549system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30455 # number of ReadReq MSHR misses 550system.cpu.l2cache.ReadReq_mshr_misses::total 31537 # number of ReadReq MSHR misses 551system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4 # number of UpgradeReq MSHR misses 552system.cpu.l2cache.UpgradeReq_mshr_misses::total 4 # number of UpgradeReq MSHR misses 553system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29518 # number of ReadExReq MSHR misses 554system.cpu.l2cache.ReadExReq_mshr_misses::total 29518 # number of ReadExReq MSHR misses 555system.cpu.l2cache.demand_mshr_misses::cpu.inst 1082 # number of demand (read+write) MSHR misses 556system.cpu.l2cache.demand_mshr_misses::cpu.data 59973 # number of demand (read+write) MSHR misses 557system.cpu.l2cache.demand_mshr_misses::total 61055 # number of demand (read+write) MSHR misses 558system.cpu.l2cache.overall_mshr_misses::cpu.inst 1082 # number of overall MSHR misses 559system.cpu.l2cache.overall_mshr_misses::cpu.data 59973 # number of overall MSHR misses 560system.cpu.l2cache.overall_mshr_misses::total 61055 # number of overall MSHR misses 561system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 33615000 # number of ReadReq MSHR miss cycles 562system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 944732500 # number of ReadReq MSHR miss cycles 563system.cpu.l2cache.ReadReq_mshr_miss_latency::total 978347500 # number of ReadReq MSHR miss cycles 564system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 124000 # number of UpgradeReq MSHR miss cycles 565system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 124000 # number of UpgradeReq MSHR miss cycles 566system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 915134000 # number of ReadExReq MSHR miss cycles 567system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 915134000 # number of ReadExReq MSHR miss cycles 568system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33615000 # number of demand (read+write) MSHR miss cycles 569system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1859866500 # number of demand (read+write) MSHR miss cycles 570system.cpu.l2cache.demand_mshr_miss_latency::total 1893481500 # number of demand (read+write) MSHR miss cycles 571system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33615000 # number of overall MSHR miss cycles 572system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1859866500 # number of overall MSHR miss cycles 573system.cpu.l2cache.overall_mshr_miss_latency::total 1893481500 # number of overall MSHR miss cycles 574system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for ReadReq accesses 575system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015273 # mshr miss rate for ReadReq accesses 576system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses 577system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358999 # mshr miss rate for ReadExReq accesses 578system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for demand accesses 579system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for demand accesses 580system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.989031 # mshr miss rate for overall accesses 581system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028886 # mshr miss rate for overall accesses 582system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31067.467652 # average ReadReq mshr miss latency 583system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.604170 # average ReadReq mshr miss latency 584system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 585system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.574700 # average ReadExReq mshr miss latency 586system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency 587system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency 588system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31067.467652 # average overall mshr miss latency 589system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31011.730279 # average overall mshr miss latency 590system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 591 592---------- End Simulation Statistics ---------- 593