stats.txt revision 11754:c209cb86278a
1
2---------- Begin Simulation Statistics ----------
3sim_seconds                                  0.065833                       # Number of seconds simulated
4sim_ticks                                 65832730500                       # Number of ticks simulated
5final_tick                                65832730500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq                                 1000000000000                       # Frequency of simulated ticks
7host_inst_rate                                 190384                       # Simulator instruction rate (inst/s)
8host_op_rate                                   335236                       # Simulator op (including micro ops) rate (op/s)
9host_tick_rate                               79331786                       # Simulator tick rate (ticks/s)
10host_mem_usage                                 416808                       # Number of bytes of host memory used
11host_seconds                                   829.84                       # Real time elapsed on the host
12sim_insts                                   157988547                       # Number of instructions simulated
13sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage                       1                       # Voltage in Volts
15system.clk_domain.clock                          1000                       # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst             69952                       # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data           1892544                       # Number of bytes read from this memory
19system.physmem.bytes_read::total              1962496                       # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst        69952                       # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total           69952                       # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks        19776                       # Number of bytes written to this memory
23system.physmem.bytes_written::total             19776                       # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst               1093                       # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data              29571                       # Number of read requests responded to by this memory
26system.physmem.num_reads::total                 30664                       # Number of read requests responded to by this memory
27system.physmem.num_writes::writebacks             309                       # Number of write requests responded to by this memory
28system.physmem.num_writes::total                  309                       # Number of write requests responded to by this memory
29system.physmem.bw_read::cpu.inst              1062572                       # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::cpu.data             28747767                       # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total                29810339                       # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst         1062572                       # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total            1062572                       # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks            300398                       # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total                 300398                       # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks            300398                       # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst             1062572                       # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data            28747767                       # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::total               30110736                       # Total bandwidth to/from this memory (bytes/s)
40system.physmem.readReqs                         30664                       # Number of read requests accepted
41system.physmem.writeReqs                          309                       # Number of write requests accepted
42system.physmem.readBursts                       30664                       # Number of DRAM read bursts, including those serviced by the write queue
43system.physmem.writeBursts                        309                       # Number of DRAM write bursts, including those merged in the write queue
44system.physmem.bytesReadDRAM                  1954304                       # Total number of bytes read from DRAM
45system.physmem.bytesReadWrQ                      8192                       # Total number of bytes read from write queue
46system.physmem.bytesWritten                     18368                       # Total number of bytes written to DRAM
47system.physmem.bytesReadSys                   1962496                       # Total read bytes from the system interface side
48system.physmem.bytesWrittenSys                  19776                       # Total written bytes from the system interface side
49system.physmem.servicedByWrQ                      128                       # Number of DRAM read bursts serviced by the write queue
50system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
51system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
52system.physmem.perBankRdBursts::0                1947                       # Per bank write bursts
53system.physmem.perBankRdBursts::1                2076                       # Per bank write bursts
54system.physmem.perBankRdBursts::2                2053                       # Per bank write bursts
55system.physmem.perBankRdBursts::3                1954                       # Per bank write bursts
56system.physmem.perBankRdBursts::4                2067                       # Per bank write bursts
57system.physmem.perBankRdBursts::5                1911                       # Per bank write bursts
58system.physmem.perBankRdBursts::6                1975                       # Per bank write bursts
59system.physmem.perBankRdBursts::7                1868                       # Per bank write bursts
60system.physmem.perBankRdBursts::8                1952                       # Per bank write bursts
61system.physmem.perBankRdBursts::9                1938                       # Per bank write bursts
62system.physmem.perBankRdBursts::10               1805                       # Per bank write bursts
63system.physmem.perBankRdBursts::11               1794                       # Per bank write bursts
64system.physmem.perBankRdBursts::12               1792                       # Per bank write bursts
65system.physmem.perBankRdBursts::13               1799                       # Per bank write bursts
66system.physmem.perBankRdBursts::14               1826                       # Per bank write bursts
67system.physmem.perBankRdBursts::15               1779                       # Per bank write bursts
68system.physmem.perBankWrBursts::0                  25                       # Per bank write bursts
69system.physmem.perBankWrBursts::1                 120                       # Per bank write bursts
70system.physmem.perBankWrBursts::2                  28                       # Per bank write bursts
71system.physmem.perBankWrBursts::3                  32                       # Per bank write bursts
72system.physmem.perBankWrBursts::4                  54                       # Per bank write bursts
73system.physmem.perBankWrBursts::5                   2                       # Per bank write bursts
74system.physmem.perBankWrBursts::6                  17                       # Per bank write bursts
75system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
76system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
77system.physmem.perBankWrBursts::9                   6                       # Per bank write bursts
78system.physmem.perBankWrBursts::10                  3                       # Per bank write bursts
79system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
80system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
81system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
82system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
83system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
84system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
85system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
86system.physmem.totGap                     65832525500                       # Total gap between requests
87system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
88system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
89system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
90system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
91system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
92system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
93system.physmem.readPktSize::6                   30664                       # Read request sizes (log2)
94system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
95system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
96system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
97system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
98system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
99system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
100system.physmem.writePktSize::6                    309                       # Write request sizes (log2)
101system.physmem.rdQLenPdf::0                     29955                       # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1                       437                       # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2                       101                       # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3                        29                       # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::5                         4                       # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
133system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::15                       14                       # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::16                       14                       # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::17                       15                       # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::18                       16                       # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::19                       16                       # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::20                       16                       # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::21                       16                       # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::22                       15                       # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::23                       16                       # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::24                       16                       # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::25                       16                       # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::26                       16                       # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::27                       16                       # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::28                       16                       # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::29                       16                       # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::30                       17                       # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::31                       16                       # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::32                       16                       # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::33                        2                       # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
197system.physmem.bytesPerActivate::samples         2862                       # Bytes accessed per row activation
198system.physmem.bytesPerActivate::mean      688.995108                       # Bytes accessed per row activation
199system.physmem.bytesPerActivate::gmean     484.121076                       # Bytes accessed per row activation
200system.physmem.bytesPerActivate::stdev     395.829774                       # Bytes accessed per row activation
201system.physmem.bytesPerActivate::0-127            415     14.50%     14.50% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::128-255          275      9.61%     24.11% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::256-383          149      5.21%     29.32% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::384-511          128      4.47%     33.79% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::512-639          140      4.89%     38.68% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::640-767          122      4.26%     42.94% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::768-895           77      2.69%     45.63% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::896-1023           86      3.00%     48.64% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::1024-1151         1470     51.36%    100.00% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::total           2862                       # Bytes accessed per row activation
211system.physmem.rdPerTurnAround::samples            16                       # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::mean      1905.625000                       # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::gmean       24.516989                       # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::stdev     7552.373489                       # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::0-1023             15     93.75%     93.75% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::29696-30719            1      6.25%    100.00% # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::total              16                       # Reads before turning the bus around for writes
218system.physmem.wrPerTurnAround::samples            16                       # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::mean        17.937500                       # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::gmean       17.914548                       # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::stdev        0.928709                       # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::16                  2     12.50%     12.50% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::18                 12     75.00%     87.50% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::19                  1      6.25%     93.75% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::20                  1      6.25%    100.00% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::total              16                       # Writes before turning the bus around for reads
227system.physmem.totQLat                      411710000                       # Total ticks spent queuing
228system.physmem.totMemAccLat                 984260000                       # Total ticks spent from burst creation until serviced by the DRAM
229system.physmem.totBusLat                    152680000                       # Total ticks spent in databus transfers
230system.physmem.avgQLat                       13482.77                       # Average queueing delay per DRAM burst
231system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
232system.physmem.avgMemAccLat                  32232.77                       # Average memory access latency per DRAM burst
233system.physmem.avgRdBW                          29.69                       # Average DRAM read bandwidth in MiByte/s
234system.physmem.avgWrBW                           0.28                       # Average achieved write bandwidth in MiByte/s
235system.physmem.avgRdBWSys                       29.81                       # Average system read bandwidth in MiByte/s
236system.physmem.avgWrBWSys                        0.30                       # Average system write bandwidth in MiByte/s
237system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
238system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
239system.physmem.busUtilRead                       0.23                       # Data bus utilization in percentage for reads
240system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
241system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
242system.physmem.avgWrQLen                        14.03                       # Average write queue length when enqueuing
243system.physmem.readRowHits                      27751                       # Number of row buffer hits during reads
244system.physmem.writeRowHits                       206                       # Number of row buffer hits during writes
245system.physmem.readRowHitRate                   90.88                       # Row buffer hit rate for reads
246system.physmem.writeRowHitRate                  66.67                       # Row buffer hit rate for writes
247system.physmem.avgGap                      2125481.08                       # Average gap between requests
248system.physmem.pageHitRate                      90.64                       # Row buffer hit rate, read and write combined
249system.physmem_0.actEnergy                   11059860                       # Energy for activate commands per rank (pJ)
250system.physmem_0.preEnergy                    5878455                       # Energy for precharge commands per rank (pJ)
251system.physmem_0.readEnergy                 113176140                       # Energy for read commands per rank (pJ)
252system.physmem_0.writeEnergy                  1451160                       # Energy for write commands per rank (pJ)
253system.physmem_0.refreshEnergy           315310320.000000                       # Energy for refresh commands per rank (pJ)
254system.physmem_0.actBackEnergy              256763340                       # Energy for active background per rank (pJ)
255system.physmem_0.preBackEnergy               17698560                       # Energy for precharge background per rank (pJ)
256system.physmem_0.actPowerDownEnergy         981638610                       # Energy for active power-down per rank (pJ)
257system.physmem_0.prePowerDownEnergy         270128640                       # Energy for precharge power-down per rank (pJ)
258system.physmem_0.selfRefreshEnergy        15008515620                       # Energy for self refresh per rank (pJ)
259system.physmem_0.totalEnergy              16981623105                       # Total energy per rank (pJ)
260system.physmem_0.averagePower              257.950589                       # Core power per rank (mW)
261system.physmem_0.totalIdleTime            65223686000                       # Total Idle time Per DRAM Rank
262system.physmem_0.memoryStateTime::IDLE       24830750                       # Time in different power states
263system.physmem_0.memoryStateTime::REF       133713250                       # Time in different power states
264system.physmem_0.memoryStateTime::SREF    62367507500                       # Time in different power states
265system.physmem_0.memoryStateTime::PRE_PDN    703478750                       # Time in different power states
266system.physmem_0.memoryStateTime::ACT       450500500                       # Time in different power states
267system.physmem_0.memoryStateTime::ACT_PDN   2152699750                       # Time in different power states
268system.physmem_1.actEnergy                    9403380                       # Energy for activate commands per rank (pJ)
269system.physmem_1.preEnergy                    4982835                       # Energy for precharge commands per rank (pJ)
270system.physmem_1.readEnergy                 104850900                       # Energy for read commands per rank (pJ)
271system.physmem_1.writeEnergy                    46980                       # Energy for write commands per rank (pJ)
272system.physmem_1.refreshEnergy           389067120.000000                       # Energy for refresh commands per rank (pJ)
273system.physmem_1.actBackEnergy              256987920                       # Energy for active background per rank (pJ)
274system.physmem_1.preBackEnergy               20546880                       # Energy for precharge background per rank (pJ)
275system.physmem_1.actPowerDownEnergy        1156119600                       # Energy for active power-down per rank (pJ)
276system.physmem_1.prePowerDownEnergy         409490400                       # Energy for precharge power-down per rank (pJ)
277system.physmem_1.selfRefreshEnergy        14841811380                       # Energy for self refresh per rank (pJ)
278system.physmem_1.totalEnergy              17194149375                       # Total energy per rank (pJ)
279system.physmem_1.averagePower              261.179341                       # Core power per rank (mW)
280system.physmem_1.totalIdleTime            65212352000                       # Total Idle time Per DRAM Rank
281system.physmem_1.memoryStateTime::IDLE       31901000                       # Time in different power states
282system.physmem_1.memoryStateTime::REF       165222000                       # Time in different power states
283system.physmem_1.memoryStateTime::SREF    61612056250                       # Time in different power states
284system.physmem_1.memoryStateTime::PRE_PDN   1066374000                       # Time in different power states
285system.physmem_1.memoryStateTime::ACT       421666750                       # Time in different power states
286system.physmem_1.memoryStateTime::ACT_PDN   2535510500                       # Time in different power states
287system.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
288system.cpu.branchPred.lookups                40426123                       # Number of BP lookups
289system.cpu.branchPred.condPredicted          40426123                       # Number of conditional branches predicted
290system.cpu.branchPred.condIncorrect           1402729                       # Number of conditional branches incorrect
291system.cpu.branchPred.BTBLookups             26580139                       # Number of BTB lookups
292system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
293system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
294system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
295system.cpu.branchPred.usedRAS                 6011508                       # Number of times the RAS was used to get a target.
296system.cpu.branchPred.RASInCorrect              87453                       # Number of incorrect RAS predictions.
297system.cpu.branchPred.indirectLookups        26580139                       # Number of indirect predictor lookups.
298system.cpu.branchPred.indirectHits           21161652                       # Number of indirect target hits.
299system.cpu.branchPred.indirectMisses          5418487                       # Number of indirect misses.
300system.cpu.branchPredindirectMispredicted       517301                       # Number of mispredicted indirect branches.
301system.cpu_clk_domain.clock                       500                       # Clock period in ticks
302system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
303system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
304system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
305system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
306system.cpu.workload.num_syscalls                  444                       # Number of system calls
307system.cpu.pwrStateResidencyTicks::ON     65832730500                       # Cumulative time (in ticks) in various power states
308system.cpu.numCycles                        131665462                       # number of cpu cycles simulated
309system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
310system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
311system.cpu.fetch.icacheStallCycles           30553171                       # Number of cycles fetch is stalled on an Icache miss
312system.cpu.fetch.Insts                      219967171                       # Number of instructions fetch has processed
313system.cpu.fetch.Branches                    40426123                       # Number of branches that fetch encountered
314system.cpu.fetch.predictedBranches           27173160                       # Number of branches that fetch has predicted taken
315system.cpu.fetch.Cycles                      99460538                       # Number of cycles fetch has run and was not squashing or blocked
316system.cpu.fetch.SquashCycles                 2919977                       # Number of cycles fetch has spent squashing
317system.cpu.fetch.TlbCycles                        306                       # Number of cycles fetch has spent waiting for tlb
318system.cpu.fetch.MiscStallCycles                 5927                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
319system.cpu.fetch.PendingTrapStallCycles        105822                       # Number of stall cycles due to pending traps
320system.cpu.fetch.PendingQuiesceStallCycles           73                       # Number of stall cycles due to pending quiesce instructions
321system.cpu.fetch.IcacheWaitRetryStallCycles          157                       # Number of stall cycles due to full MSHR
322system.cpu.fetch.CacheLines                  29763575                       # Number of cache lines fetched
323system.cpu.fetch.IcacheSquashes                354176                       # Number of outstanding Icache misses that were squashed
324system.cpu.fetch.ItlbSquashes                      15                       # Number of outstanding ITLB misses that were squashed
325system.cpu.fetch.rateDist::samples          131585982                       # Number of instructions fetched each cycle (Total)
326system.cpu.fetch.rateDist::mean              2.941987                       # Number of instructions fetched each cycle (Total)
327system.cpu.fetch.rateDist::stdev             3.406730                       # Number of instructions fetched each cycle (Total)
328system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
329system.cpu.fetch.rateDist::0                 65985920     50.15%     50.15% # Number of instructions fetched each cycle (Total)
330system.cpu.fetch.rateDist::1                  4028379      3.06%     53.21% # Number of instructions fetched each cycle (Total)
331system.cpu.fetch.rateDist::2                  3611314      2.74%     55.95% # Number of instructions fetched each cycle (Total)
332system.cpu.fetch.rateDist::3                  6113229      4.65%     60.60% # Number of instructions fetched each cycle (Total)
333system.cpu.fetch.rateDist::4                  7745533      5.89%     66.48% # Number of instructions fetched each cycle (Total)
334system.cpu.fetch.rateDist::5                  5553246      4.22%     70.70% # Number of instructions fetched each cycle (Total)
335system.cpu.fetch.rateDist::6                  3377028      2.57%     73.27% # Number of instructions fetched each cycle (Total)
336system.cpu.fetch.rateDist::7                  2847646      2.16%     75.44% # Number of instructions fetched each cycle (Total)
337system.cpu.fetch.rateDist::8                 32323687     24.56%    100.00% # Number of instructions fetched each cycle (Total)
338system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
339system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
340system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
341system.cpu.fetch.rateDist::total            131585982                       # Number of instructions fetched each cycle (Total)
342system.cpu.fetch.branchRate                  0.307037                       # Number of branch fetches per cycle
343system.cpu.fetch.rate                        1.670652                       # Number of inst fetches per cycle
344system.cpu.decode.IdleCycles                 15243618                       # Number of cycles decode is idle
345system.cpu.decode.BlockedCycles              64765794                       # Number of cycles decode is blocked
346system.cpu.decode.RunCycles                  40224064                       # Number of cycles decode is running
347system.cpu.decode.UnblockCycles               9892518                       # Number of cycles decode is unblocking
348system.cpu.decode.SquashCycles                1459988                       # Number of cycles decode is squashing
349system.cpu.decode.DecodedInsts              362269877                       # Number of instructions handled by decode
350system.cpu.rename.SquashCycles                1459988                       # Number of cycles rename is squashing
351system.cpu.rename.IdleCycles                 20789530                       # Number of cycles rename is idle
352system.cpu.rename.BlockCycles                11237370                       # Number of cycles rename is blocking
353system.cpu.rename.serializeStallCycles          18362                       # count of cycles rename stalled for serializing inst
354system.cpu.rename.RunCycles                  44279240                       # Number of cycles rename is running
355system.cpu.rename.UnblockCycles              53801492                       # Number of cycles rename is unblocking
356system.cpu.rename.RenamedInsts              352719757                       # Number of instructions processed by rename
357system.cpu.rename.ROBFullEvents                 16498                       # Number of times rename has blocked due to ROB full
358system.cpu.rename.IQFullEvents                 793095                       # Number of times rename has blocked due to IQ full
359system.cpu.rename.LQFullEvents               46882908                       # Number of times rename has blocked due to LQ full
360system.cpu.rename.SQFullEvents                5193491                       # Number of times rename has blocked due to SQ full
361system.cpu.rename.RenamedOperands           355158766                       # Number of destination operands rename has renamed
362system.cpu.rename.RenameLookups             934950269                       # Number of register rename lookups that rename has made
363system.cpu.rename.int_rename_lookups        575705414                       # Number of integer rename lookups
364system.cpu.rename.fp_rename_lookups             24139                       # Number of floating rename lookups
365system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
366system.cpu.rename.UndoneMaps                 75946019                       # Number of HB maps that are undone due to squashing
367system.cpu.rename.serializingInsts                487                       # count of serializing insts renamed
368system.cpu.rename.tempSerializingInsts            484                       # count of temporary serializing insts renamed
369system.cpu.rename.skidInsts                  64820498                       # count of insts added to the skid buffer
370system.cpu.memDep0.insertedLoads            112428453                       # Number of loads inserted to the mem dependence unit.
371system.cpu.memDep0.insertedStores            38501164                       # Number of stores inserted to the mem dependence unit.
372system.cpu.memDep0.conflictingLoads          51645718                       # Number of conflicting loads.
373system.cpu.memDep0.conflictingStores          9056873                       # Number of conflicting stores.
374system.cpu.iq.iqInstsAdded                  344114716                       # Number of instructions added to the IQ (excludes non-spec)
375system.cpu.iq.iqNonSpecInstsAdded                4351                       # Number of non-speculative instructions added to the IQ
376system.cpu.iq.iqInstsIssued                 317908509                       # Number of instructions issued
377system.cpu.iq.iqSquashedInstsIssued            166833                       # Number of squashed instructions issued
378system.cpu.iq.iqSquashedInstsExamined        65926603                       # Number of squashed instructions iterated over during squash; mainly for profiling
379system.cpu.iq.iqSquashedOperandsExamined    102202913                       # Number of squashed operands that are examined and possibly removed from graph
380system.cpu.iq.iqSquashedNonSpecRemoved           3906                       # Number of squashed non-spec instructions that were removed
381system.cpu.iq.issued_per_cycle::samples     131585982                       # Number of insts issued each cycle
382system.cpu.iq.issued_per_cycle::mean         2.415976                       # Number of insts issued each cycle
383system.cpu.iq.issued_per_cycle::stdev        2.164934                       # Number of insts issued each cycle
384system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
385system.cpu.iq.issued_per_cycle::0            35686444     27.12%     27.12% # Number of insts issued each cycle
386system.cpu.iq.issued_per_cycle::1            20105227     15.28%     42.40% # Number of insts issued each cycle
387system.cpu.iq.issued_per_cycle::2            17162197     13.04%     55.44% # Number of insts issued each cycle
388system.cpu.iq.issued_per_cycle::3            17623881     13.39%     68.84% # Number of insts issued each cycle
389system.cpu.iq.issued_per_cycle::4            15350950     11.67%     80.50% # Number of insts issued each cycle
390system.cpu.iq.issued_per_cycle::5            12863479      9.78%     90.28% # Number of insts issued each cycle
391system.cpu.iq.issued_per_cycle::6             6692822      5.09%     95.36% # Number of insts issued each cycle
392system.cpu.iq.issued_per_cycle::7             4078738      3.10%     98.46% # Number of insts issued each cycle
393system.cpu.iq.issued_per_cycle::8             2022244      1.54%    100.00% # Number of insts issued each cycle
394system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
395system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
396system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
397system.cpu.iq.issued_per_cycle::total       131585982                       # Number of insts issued each cycle
398system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
399system.cpu.iq.fu_full::IntAlu                  364988      8.91%      8.91% # attempts to use FU when none available
400system.cpu.iq.fu_full::IntMult                      0      0.00%      8.91% # attempts to use FU when none available
401system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.91% # attempts to use FU when none available
402system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.91% # attempts to use FU when none available
403system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.91% # attempts to use FU when none available
404system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.91% # attempts to use FU when none available
405system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.91% # attempts to use FU when none available
406system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%      8.91% # attempts to use FU when none available
407system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.91% # attempts to use FU when none available
408system.cpu.iq.fu_full::FloatMisc                    0      0.00%      8.91% # attempts to use FU when none available
409system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.91% # attempts to use FU when none available
410system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.91% # attempts to use FU when none available
411system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.91% # attempts to use FU when none available
412system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.91% # attempts to use FU when none available
413system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.91% # attempts to use FU when none available
414system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.91% # attempts to use FU when none available
415system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.91% # attempts to use FU when none available
416system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.91% # attempts to use FU when none available
417system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.91% # attempts to use FU when none available
418system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.91% # attempts to use FU when none available
419system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.91% # attempts to use FU when none available
420system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.91% # attempts to use FU when none available
421system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.91% # attempts to use FU when none available
422system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.91% # attempts to use FU when none available
423system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.91% # attempts to use FU when none available
424system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.91% # attempts to use FU when none available
425system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.91% # attempts to use FU when none available
426system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.91% # attempts to use FU when none available
427system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.91% # attempts to use FU when none available
428system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.91% # attempts to use FU when none available
429system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.91% # attempts to use FU when none available
430system.cpu.iq.fu_full::MemRead                3541451     86.44%     95.35% # attempts to use FU when none available
431system.cpu.iq.fu_full::MemWrite                188937      4.61%     99.96% # attempts to use FU when none available
432system.cpu.iq.fu_full::FloatMemRead                10      0.00%     99.96% # attempts to use FU when none available
433system.cpu.iq.fu_full::FloatMemWrite             1524      0.04%    100.00% # attempts to use FU when none available
434system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
435system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
436system.cpu.iq.FU_type_0::No_OpClass             33340      0.01%      0.01% # Type of FU issued
437system.cpu.iq.FU_type_0::IntAlu             181836417     57.20%     57.21% # Type of FU issued
438system.cpu.iq.FU_type_0::IntMult                11458      0.00%     57.21% # Type of FU issued
439system.cpu.iq.FU_type_0::IntDiv                   362      0.00%     57.21% # Type of FU issued
440system.cpu.iq.FU_type_0::FloatAdd                 334      0.00%     57.21% # Type of FU issued
441system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.21% # Type of FU issued
442system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.21% # Type of FU issued
443system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.21% # Type of FU issued
444system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     57.21% # Type of FU issued
445system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     57.21% # Type of FU issued
446system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     57.21% # Type of FU issued
447system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     57.21% # Type of FU issued
448system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     57.21% # Type of FU issued
449system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     57.21% # Type of FU issued
450system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     57.21% # Type of FU issued
451system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     57.21% # Type of FU issued
452system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     57.21% # Type of FU issued
453system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     57.21% # Type of FU issued
454system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     57.21% # Type of FU issued
455system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     57.21% # Type of FU issued
456system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     57.21% # Type of FU issued
457system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     57.21% # Type of FU issued
458system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     57.21% # Type of FU issued
459system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     57.21% # Type of FU issued
460system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     57.21% # Type of FU issued
461system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     57.21% # Type of FU issued
462system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     57.21% # Type of FU issued
463system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     57.21% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.21% # Type of FU issued
465system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.21% # Type of FU issued
466system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.21% # Type of FU issued
467system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.21% # Type of FU issued
468system.cpu.iq.FU_type_0::MemRead            101309174     31.87%     89.08% # Type of FU issued
469system.cpu.iq.FU_type_0::MemWrite            34711229     10.92%    100.00% # Type of FU issued
470system.cpu.iq.FU_type_0::FloatMemRead             553      0.00%    100.00% # Type of FU issued
471system.cpu.iq.FU_type_0::FloatMemWrite           5642      0.00%    100.00% # Type of FU issued
472system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
473system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
474system.cpu.iq.FU_type_0::total              317908509                       # Type of FU issued
475system.cpu.iq.rate                           2.414517                       # Inst issue rate
476system.cpu.iq.fu_busy_cnt                     4096910                       # FU busy when requested
477system.cpu.iq.fu_busy_rate                   0.012887                       # FU busy rate (busy events/executed inst)
478system.cpu.iq.int_inst_queue_reads          771648435                       # Number of integer instruction queue reads
479system.cpu.iq.int_inst_queue_writes         410069961                       # Number of integer instruction queue writes
480system.cpu.iq.int_inst_queue_wakeup_accesses    313720076                       # Number of integer instruction queue wakeup accesses
481system.cpu.iq.fp_inst_queue_reads               18308                       # Number of floating instruction queue reads
482system.cpu.iq.fp_inst_queue_writes              36184                       # Number of floating instruction queue writes
483system.cpu.iq.fp_inst_queue_wakeup_accesses         4316                       # Number of floating instruction queue wakeup accesses
484system.cpu.iq.int_alu_accesses              321964016                       # Number of integer alu accesses
485system.cpu.iq.fp_alu_accesses                    8063                       # Number of floating point alu accesses
486system.cpu.iew.lsq.thread0.forwLoads         57535034                       # Number of loads that had data forwarded from stores
487system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
488system.cpu.iew.lsq.thread0.squashedLoads     21649068                       # Number of loads squashed
489system.cpu.iew.lsq.thread0.ignoredResponses        67666                       # Number of memory responses ignored because the instruction is squashed
490system.cpu.iew.lsq.thread0.memOrderViolation        63141                       # Number of memory ordering violations
491system.cpu.iew.lsq.thread0.squashedStores      7061412                       # Number of stores squashed
492system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
493system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
494system.cpu.iew.lsq.thread0.rescheduledLoads         4025                       # Number of loads that were rescheduled
495system.cpu.iew.lsq.thread0.cacheBlocked        141941                       # Number of times an access to memory failed due to the cache being blocked
496system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
497system.cpu.iew.iewSquashCycles                1459988                       # Number of cycles IEW is squashing
498system.cpu.iew.iewBlockCycles                 8072611                       # Number of cycles IEW is blocking
499system.cpu.iew.iewUnblockCycles               3068372                       # Number of cycles IEW is unblocking
500system.cpu.iew.iewDispatchedInsts           344119067                       # Number of instructions dispatched to IQ
501system.cpu.iew.iewDispSquashedInsts            127232                       # Number of squashed instructions skipped by dispatch
502system.cpu.iew.iewDispLoadInsts             112428453                       # Number of dispatched load instructions
503system.cpu.iew.iewDispStoreInsts             38501164                       # Number of dispatched store instructions
504system.cpu.iew.iewDispNonSpecInsts               1782                       # Number of dispatched non-speculative instructions
505system.cpu.iew.iewIQFullEvents                   2921                       # Number of times the IQ has become full, causing a stall
506system.cpu.iew.iewLSQFullEvents               3074772                       # Number of times the LSQ has become full, causing a stall
507system.cpu.iew.memOrderViolationEvents          63141                       # Number of memory order violations
508system.cpu.iew.predictedTakenIncorrect         534039                       # Number of branches that were predicted taken incorrectly
509system.cpu.iew.predictedNotTakenIncorrect      1041947                       # Number of branches that were predicted not taken incorrectly
510system.cpu.iew.branchMispredicts              1575986                       # Number of branch mispredicts detected at execute
511system.cpu.iew.iewExecutedInsts             315496434                       # Number of executed instructions
512system.cpu.iew.iewExecLoadInsts             100557512                       # Number of load instructions executed
513system.cpu.iew.iewExecSquashedInsts           2412075                       # Number of squashed instructions skipped in execute
514system.cpu.iew.exec_swp                             0                       # number of swp insts executed
515system.cpu.iew.exec_nop                             0                       # number of nop insts executed
516system.cpu.iew.exec_refs                    134869578                       # number of memory reference insts executed
517system.cpu.iew.exec_branches                 32108537                       # Number of branches executed
518system.cpu.iew.exec_stores                   34312066                       # Number of stores executed
519system.cpu.iew.exec_rate                     2.396197                       # Inst execution rate
520system.cpu.iew.wb_sent                      314359591                       # cumulative count of insts sent to commit
521system.cpu.iew.wb_count                     313724392                       # cumulative count of insts written-back
522system.cpu.iew.wb_producers                 237724315                       # num instructions producing a value
523system.cpu.iew.wb_consumers                 343443925                       # num instructions consuming a value
524system.cpu.iew.wb_rate                       2.382739                       # insts written-back per cycle
525system.cpu.iew.wb_fanout                     0.692178                       # average fanout of values written-back
526system.cpu.commit.commitSquashedInsts        66051294                       # The number of squashed insts skipped by commit
527system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
528system.cpu.commit.branchMispredicts           1408834                       # The number of times a branch was mispredicted
529system.cpu.commit.committed_per_cycle::samples    122136825                       # Number of insts commited each cycle
530system.cpu.commit.committed_per_cycle::mean     2.277712                       # Number of insts commited each cycle
531system.cpu.commit.committed_per_cycle::stdev     3.048100                       # Number of insts commited each cycle
532system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
533system.cpu.commit.committed_per_cycle::0     57021615     46.69%     46.69% # Number of insts commited each cycle
534system.cpu.commit.committed_per_cycle::1     16508640     13.52%     60.20% # Number of insts commited each cycle
535system.cpu.commit.committed_per_cycle::2     11210798      9.18%     69.38% # Number of insts commited each cycle
536system.cpu.commit.committed_per_cycle::3      8746505      7.16%     76.54% # Number of insts commited each cycle
537system.cpu.commit.committed_per_cycle::4      2078517      1.70%     78.25% # Number of insts commited each cycle
538system.cpu.commit.committed_per_cycle::5      1759712      1.44%     79.69% # Number of insts commited each cycle
539system.cpu.commit.committed_per_cycle::6       926228      0.76%     80.44% # Number of insts commited each cycle
540system.cpu.commit.committed_per_cycle::7       725763      0.59%     81.04% # Number of insts commited each cycle
541system.cpu.commit.committed_per_cycle::8     23159047     18.96%    100.00% # Number of insts commited each cycle
542system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
543system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
544system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
545system.cpu.commit.committed_per_cycle::total    122136825                       # Number of insts commited each cycle
546system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
547system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
548system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
549system.cpu.commit.refs                      122219137                       # Number of memory references committed
550system.cpu.commit.loads                      90779385                       # Number of loads committed
551system.cpu.commit.membars                           0                       # Number of memory barriers committed
552system.cpu.commit.branches                   29309705                       # Number of branches committed
553system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
554system.cpu.commit.int_insts                 278169481                       # Number of committed integer instructions.
555system.cpu.commit.function_calls              4237596                       # Number of function calls committed.
556system.cpu.commit.op_class_0::No_OpClass        16695      0.01%      0.01% # Class of committed instruction
557system.cpu.commit.op_class_0::IntAlu        155945353     56.06%     56.06% # Class of committed instruction
558system.cpu.commit.op_class_0::IntMult           10938      0.00%     56.07% # Class of committed instruction
559system.cpu.commit.op_class_0::IntDiv              329      0.00%     56.07% # Class of committed instruction
560system.cpu.commit.op_class_0::FloatAdd             12      0.00%     56.07% # Class of committed instruction
561system.cpu.commit.op_class_0::FloatCmp              0      0.00%     56.07% # Class of committed instruction
562system.cpu.commit.op_class_0::FloatCvt              0      0.00%     56.07% # Class of committed instruction
563system.cpu.commit.op_class_0::FloatMult             0      0.00%     56.07% # Class of committed instruction
564system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     56.07% # Class of committed instruction
565system.cpu.commit.op_class_0::FloatDiv              0      0.00%     56.07% # Class of committed instruction
566system.cpu.commit.op_class_0::FloatMisc             0      0.00%     56.07% # Class of committed instruction
567system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     56.07% # Class of committed instruction
568system.cpu.commit.op_class_0::SimdAdd               0      0.00%     56.07% # Class of committed instruction
569system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     56.07% # Class of committed instruction
570system.cpu.commit.op_class_0::SimdAlu               0      0.00%     56.07% # Class of committed instruction
571system.cpu.commit.op_class_0::SimdCmp               0      0.00%     56.07% # Class of committed instruction
572system.cpu.commit.op_class_0::SimdCvt               0      0.00%     56.07% # Class of committed instruction
573system.cpu.commit.op_class_0::SimdMisc              0      0.00%     56.07% # Class of committed instruction
574system.cpu.commit.op_class_0::SimdMult              0      0.00%     56.07% # Class of committed instruction
575system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     56.07% # Class of committed instruction
576system.cpu.commit.op_class_0::SimdShift             0      0.00%     56.07% # Class of committed instruction
577system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     56.07% # Class of committed instruction
578system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     56.07% # Class of committed instruction
579system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     56.07% # Class of committed instruction
580system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     56.07% # Class of committed instruction
581system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     56.07% # Class of committed instruction
582system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     56.07% # Class of committed instruction
583system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     56.07% # Class of committed instruction
584system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     56.07% # Class of committed instruction
585system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     56.07% # Class of committed instruction
586system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     56.07% # Class of committed instruction
587system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     56.07% # Class of committed instruction
588system.cpu.commit.op_class_0::MemRead        90779371     32.63%     88.70% # Class of committed instruction
589system.cpu.commit.op_class_0::MemWrite       31439738     11.30%    100.00% # Class of committed instruction
590system.cpu.commit.op_class_0::FloatMemRead           14      0.00%    100.00% # Class of committed instruction
591system.cpu.commit.op_class_0::FloatMemWrite           14      0.00%    100.00% # Class of committed instruction
592system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
593system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
594system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
595system.cpu.commit.bw_lim_events              23159047                       # number cycles where commit BW limit reached
596system.cpu.rob.rob_reads                    443221536                       # The number of ROB reads
597system.cpu.rob.rob_writes                   698006714                       # The number of ROB writes
598system.cpu.timesIdled                             877                       # Number of times that the entire CPU went into an idle state and unscheduled itself
599system.cpu.idleCycles                           79480                       # Total number of cycles that the CPU has spent unscheduled due to idling
600system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
601system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
602system.cpu.cpi                               0.833386                       # CPI: Cycles Per Instruction
603system.cpu.cpi_total                         0.833386                       # CPI: Total CPI of All Threads
604system.cpu.ipc                               1.199924                       # IPC: Instructions Per Cycle
605system.cpu.ipc_total                         1.199924                       # IPC: Total IPC of All Threads
606system.cpu.int_regfile_reads                502917784                       # number of integer regfile reads
607system.cpu.int_regfile_writes               247848787                       # number of integer regfile writes
608system.cpu.fp_regfile_reads                      4075                       # number of floating regfile reads
609system.cpu.fp_regfile_writes                      819                       # number of floating regfile writes
610system.cpu.cc_regfile_reads                 109098841                       # number of cc regfile reads
611system.cpu.cc_regfile_writes                 65494445                       # number of cc regfile writes
612system.cpu.misc_regfile_reads               201957201                       # number of misc regfile reads
613system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
614system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
615system.cpu.dcache.tags.replacements           2073306                       # number of replacements
616system.cpu.dcache.tags.tagsinuse          4067.354566                       # Cycle average of tags in use
617system.cpu.dcache.tags.total_refs            71520008                       # Total number of references to valid blocks.
618system.cpu.dcache.tags.sampled_refs           2077402                       # Sample count of references to valid blocks.
619system.cpu.dcache.tags.avg_refs             34.427621                       # Average number of references to valid blocks.
620system.cpu.dcache.tags.warmup_cycle       21024099500                       # Cycle when the warmup percentage was hit.
621system.cpu.dcache.tags.occ_blocks::cpu.data  4067.354566                       # Average occupied blocks per requestor
622system.cpu.dcache.tags.occ_percent::cpu.data     0.993006                       # Average percentage of cache occupancy
623system.cpu.dcache.tags.occ_percent::total     0.993006                       # Average percentage of cache occupancy
624system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
625system.cpu.dcache.tags.age_task_id_blocks_1024::0          500                       # Occupied blocks per task id
626system.cpu.dcache.tags.age_task_id_blocks_1024::1         3447                       # Occupied blocks per task id
627system.cpu.dcache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
628system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
629system.cpu.dcache.tags.tag_accesses         150691296                       # Number of tag accesses
630system.cpu.dcache.tags.data_accesses        150691296                       # Number of data accesses
631system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
632system.cpu.dcache.ReadReq_hits::cpu.data     40173982                       # number of ReadReq hits
633system.cpu.dcache.ReadReq_hits::total        40173982                       # number of ReadReq hits
634system.cpu.dcache.WriteReq_hits::cpu.data     31346026                       # number of WriteReq hits
635system.cpu.dcache.WriteReq_hits::total       31346026                       # number of WriteReq hits
636system.cpu.dcache.demand_hits::cpu.data      71520008                       # number of demand (read+write) hits
637system.cpu.dcache.demand_hits::total         71520008                       # number of demand (read+write) hits
638system.cpu.dcache.overall_hits::cpu.data     71520008                       # number of overall hits
639system.cpu.dcache.overall_hits::total        71520008                       # number of overall hits
640system.cpu.dcache.ReadReq_misses::cpu.data      2693213                       # number of ReadReq misses
641system.cpu.dcache.ReadReq_misses::total       2693213                       # number of ReadReq misses
642system.cpu.dcache.WriteReq_misses::cpu.data        93726                       # number of WriteReq misses
643system.cpu.dcache.WriteReq_misses::total        93726                       # number of WriteReq misses
644system.cpu.dcache.demand_misses::cpu.data      2786939                       # number of demand (read+write) misses
645system.cpu.dcache.demand_misses::total        2786939                       # number of demand (read+write) misses
646system.cpu.dcache.overall_misses::cpu.data      2786939                       # number of overall misses
647system.cpu.dcache.overall_misses::total       2786939                       # number of overall misses
648system.cpu.dcache.ReadReq_miss_latency::cpu.data  32416728500                       # number of ReadReq miss cycles
649system.cpu.dcache.ReadReq_miss_latency::total  32416728500                       # number of ReadReq miss cycles
650system.cpu.dcache.WriteReq_miss_latency::cpu.data   3181034987                       # number of WriteReq miss cycles
651system.cpu.dcache.WriteReq_miss_latency::total   3181034987                       # number of WriteReq miss cycles
652system.cpu.dcache.demand_miss_latency::cpu.data  35597763487                       # number of demand (read+write) miss cycles
653system.cpu.dcache.demand_miss_latency::total  35597763487                       # number of demand (read+write) miss cycles
654system.cpu.dcache.overall_miss_latency::cpu.data  35597763487                       # number of overall miss cycles
655system.cpu.dcache.overall_miss_latency::total  35597763487                       # number of overall miss cycles
656system.cpu.dcache.ReadReq_accesses::cpu.data     42867195                       # number of ReadReq accesses(hits+misses)
657system.cpu.dcache.ReadReq_accesses::total     42867195                       # number of ReadReq accesses(hits+misses)
658system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
659system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
660system.cpu.dcache.demand_accesses::cpu.data     74306947                       # number of demand (read+write) accesses
661system.cpu.dcache.demand_accesses::total     74306947                       # number of demand (read+write) accesses
662system.cpu.dcache.overall_accesses::cpu.data     74306947                       # number of overall (read+write) accesses
663system.cpu.dcache.overall_accesses::total     74306947                       # number of overall (read+write) accesses
664system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.062827                       # miss rate for ReadReq accesses
665system.cpu.dcache.ReadReq_miss_rate::total     0.062827                       # miss rate for ReadReq accesses
666system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002981                       # miss rate for WriteReq accesses
667system.cpu.dcache.WriteReq_miss_rate::total     0.002981                       # miss rate for WriteReq accesses
668system.cpu.dcache.demand_miss_rate::cpu.data     0.037506                       # miss rate for demand accesses
669system.cpu.dcache.demand_miss_rate::total     0.037506                       # miss rate for demand accesses
670system.cpu.dcache.overall_miss_rate::cpu.data     0.037506                       # miss rate for overall accesses
671system.cpu.dcache.overall_miss_rate::total     0.037506                       # miss rate for overall accesses
672system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12036.451814                       # average ReadReq miss latency
673system.cpu.dcache.ReadReq_avg_miss_latency::total 12036.451814                       # average ReadReq miss latency
674system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33939.728432                       # average WriteReq miss latency
675system.cpu.dcache.WriteReq_avg_miss_latency::total 33939.728432                       # average WriteReq miss latency
676system.cpu.dcache.demand_avg_miss_latency::cpu.data 12773.068764                       # average overall miss latency
677system.cpu.dcache.demand_avg_miss_latency::total 12773.068764                       # average overall miss latency
678system.cpu.dcache.overall_avg_miss_latency::cpu.data 12773.068764                       # average overall miss latency
679system.cpu.dcache.overall_avg_miss_latency::total 12773.068764                       # average overall miss latency
680system.cpu.dcache.blocked_cycles::no_mshrs       220832                       # number of cycles access was blocked
681system.cpu.dcache.blocked_cycles::no_targets          385                       # number of cycles access was blocked
682system.cpu.dcache.blocked::no_mshrs             43178                       # number of cycles access was blocked
683system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
684system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.114456                       # average number of cycles each access was blocked
685system.cpu.dcache.avg_blocked_cycles::no_targets    96.250000                       # average number of cycles each access was blocked
686system.cpu.dcache.writebacks::writebacks      2066926                       # number of writebacks
687system.cpu.dcache.writebacks::total           2066926                       # number of writebacks
688system.cpu.dcache.ReadReq_mshr_hits::cpu.data       697625                       # number of ReadReq MSHR hits
689system.cpu.dcache.ReadReq_mshr_hits::total       697625                       # number of ReadReq MSHR hits
690system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11912                       # number of WriteReq MSHR hits
691system.cpu.dcache.WriteReq_mshr_hits::total        11912                       # number of WriteReq MSHR hits
692system.cpu.dcache.demand_mshr_hits::cpu.data       709537                       # number of demand (read+write) MSHR hits
693system.cpu.dcache.demand_mshr_hits::total       709537                       # number of demand (read+write) MSHR hits
694system.cpu.dcache.overall_mshr_hits::cpu.data       709537                       # number of overall MSHR hits
695system.cpu.dcache.overall_mshr_hits::total       709537                       # number of overall MSHR hits
696system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1995588                       # number of ReadReq MSHR misses
697system.cpu.dcache.ReadReq_mshr_misses::total      1995588                       # number of ReadReq MSHR misses
698system.cpu.dcache.WriteReq_mshr_misses::cpu.data        81814                       # number of WriteReq MSHR misses
699system.cpu.dcache.WriteReq_mshr_misses::total        81814                       # number of WriteReq MSHR misses
700system.cpu.dcache.demand_mshr_misses::cpu.data      2077402                       # number of demand (read+write) MSHR misses
701system.cpu.dcache.demand_mshr_misses::total      2077402                       # number of demand (read+write) MSHR misses
702system.cpu.dcache.overall_mshr_misses::cpu.data      2077402                       # number of overall MSHR misses
703system.cpu.dcache.overall_mshr_misses::total      2077402                       # number of overall MSHR misses
704system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24271228500                       # number of ReadReq MSHR miss cycles
705system.cpu.dcache.ReadReq_mshr_miss_latency::total  24271228500                       # number of ReadReq MSHR miss cycles
706system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3023849487                       # number of WriteReq MSHR miss cycles
707system.cpu.dcache.WriteReq_mshr_miss_latency::total   3023849487                       # number of WriteReq MSHR miss cycles
708system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27295077987                       # number of demand (read+write) MSHR miss cycles
709system.cpu.dcache.demand_mshr_miss_latency::total  27295077987                       # number of demand (read+write) MSHR miss cycles
710system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27295077987                       # number of overall MSHR miss cycles
711system.cpu.dcache.overall_mshr_miss_latency::total  27295077987                       # number of overall MSHR miss cycles
712system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046553                       # mshr miss rate for ReadReq accesses
713system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046553                       # mshr miss rate for ReadReq accesses
714system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002602                       # mshr miss rate for WriteReq accesses
715system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002602                       # mshr miss rate for WriteReq accesses
716system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027957                       # mshr miss rate for demand accesses
717system.cpu.dcache.demand_mshr_miss_rate::total     0.027957                       # mshr miss rate for demand accesses
718system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027957                       # mshr miss rate for overall accesses
719system.cpu.dcache.overall_mshr_miss_rate::total     0.027957                       # mshr miss rate for overall accesses
720system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.444603                       # average ReadReq mshr miss latency
721system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.444603                       # average ReadReq mshr miss latency
722system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36960.049466                       # average WriteReq mshr miss latency
723system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36960.049466                       # average WriteReq mshr miss latency
724system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13139.044820                       # average overall mshr miss latency
725system.cpu.dcache.demand_avg_mshr_miss_latency::total 13139.044820                       # average overall mshr miss latency
726system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13139.044820                       # average overall mshr miss latency
727system.cpu.dcache.overall_avg_mshr_miss_latency::total 13139.044820                       # average overall mshr miss latency
728system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
729system.cpu.icache.tags.replacements                93                       # number of replacements
730system.cpu.icache.tags.tagsinuse           878.108473                       # Cycle average of tags in use
731system.cpu.icache.tags.total_refs            29762089                       # Total number of references to valid blocks.
732system.cpu.icache.tags.sampled_refs              1121                       # Sample count of references to valid blocks.
733system.cpu.icache.tags.avg_refs          26549.588760                       # Average number of references to valid blocks.
734system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
735system.cpu.icache.tags.occ_blocks::cpu.inst   878.108473                       # Average occupied blocks per requestor
736system.cpu.icache.tags.occ_percent::cpu.inst     0.428764                       # Average percentage of cache occupancy
737system.cpu.icache.tags.occ_percent::total     0.428764                       # Average percentage of cache occupancy
738system.cpu.icache.tags.occ_task_id_blocks::1024         1028                       # Occupied blocks per task id
739system.cpu.icache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
740system.cpu.icache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
741system.cpu.icache.tags.age_task_id_blocks_1024::3           38                       # Occupied blocks per task id
742system.cpu.icache.tags.age_task_id_blocks_1024::4          910                       # Occupied blocks per task id
743system.cpu.icache.tags.occ_task_id_percent::1024     0.501953                       # Percentage of cache occupancy per task id
744system.cpu.icache.tags.tag_accesses          59528269                       # Number of tag accesses
745system.cpu.icache.tags.data_accesses         59528269                       # Number of data accesses
746system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
747system.cpu.icache.ReadReq_hits::cpu.inst     29762089                       # number of ReadReq hits
748system.cpu.icache.ReadReq_hits::total        29762089                       # number of ReadReq hits
749system.cpu.icache.demand_hits::cpu.inst      29762089                       # number of demand (read+write) hits
750system.cpu.icache.demand_hits::total         29762089                       # number of demand (read+write) hits
751system.cpu.icache.overall_hits::cpu.inst     29762089                       # number of overall hits
752system.cpu.icache.overall_hits::total        29762089                       # number of overall hits
753system.cpu.icache.ReadReq_misses::cpu.inst         1485                       # number of ReadReq misses
754system.cpu.icache.ReadReq_misses::total          1485                       # number of ReadReq misses
755system.cpu.icache.demand_misses::cpu.inst         1485                       # number of demand (read+write) misses
756system.cpu.icache.demand_misses::total           1485                       # number of demand (read+write) misses
757system.cpu.icache.overall_misses::cpu.inst         1485                       # number of overall misses
758system.cpu.icache.overall_misses::total          1485                       # number of overall misses
759system.cpu.icache.ReadReq_miss_latency::cpu.inst    149774999                       # number of ReadReq miss cycles
760system.cpu.icache.ReadReq_miss_latency::total    149774999                       # number of ReadReq miss cycles
761system.cpu.icache.demand_miss_latency::cpu.inst    149774999                       # number of demand (read+write) miss cycles
762system.cpu.icache.demand_miss_latency::total    149774999                       # number of demand (read+write) miss cycles
763system.cpu.icache.overall_miss_latency::cpu.inst    149774999                       # number of overall miss cycles
764system.cpu.icache.overall_miss_latency::total    149774999                       # number of overall miss cycles
765system.cpu.icache.ReadReq_accesses::cpu.inst     29763574                       # number of ReadReq accesses(hits+misses)
766system.cpu.icache.ReadReq_accesses::total     29763574                       # number of ReadReq accesses(hits+misses)
767system.cpu.icache.demand_accesses::cpu.inst     29763574                       # number of demand (read+write) accesses
768system.cpu.icache.demand_accesses::total     29763574                       # number of demand (read+write) accesses
769system.cpu.icache.overall_accesses::cpu.inst     29763574                       # number of overall (read+write) accesses
770system.cpu.icache.overall_accesses::total     29763574                       # number of overall (read+write) accesses
771system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000050                       # miss rate for ReadReq accesses
772system.cpu.icache.ReadReq_miss_rate::total     0.000050                       # miss rate for ReadReq accesses
773system.cpu.icache.demand_miss_rate::cpu.inst     0.000050                       # miss rate for demand accesses
774system.cpu.icache.demand_miss_rate::total     0.000050                       # miss rate for demand accesses
775system.cpu.icache.overall_miss_rate::cpu.inst     0.000050                       # miss rate for overall accesses
776system.cpu.icache.overall_miss_rate::total     0.000050                       # miss rate for overall accesses
777system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100858.585185                       # average ReadReq miss latency
778system.cpu.icache.ReadReq_avg_miss_latency::total 100858.585185                       # average ReadReq miss latency
779system.cpu.icache.demand_avg_miss_latency::cpu.inst 100858.585185                       # average overall miss latency
780system.cpu.icache.demand_avg_miss_latency::total 100858.585185                       # average overall miss latency
781system.cpu.icache.overall_avg_miss_latency::cpu.inst 100858.585185                       # average overall miss latency
782system.cpu.icache.overall_avg_miss_latency::total 100858.585185                       # average overall miss latency
783system.cpu.icache.blocked_cycles::no_mshrs         2965                       # number of cycles access was blocked
784system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
785system.cpu.icache.blocked::no_mshrs                14                       # number of cycles access was blocked
786system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
787system.cpu.icache.avg_blocked_cycles::no_mshrs   211.785714                       # average number of cycles each access was blocked
788system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
789system.cpu.icache.writebacks::writebacks           93                       # number of writebacks
790system.cpu.icache.writebacks::total                93                       # number of writebacks
791system.cpu.icache.ReadReq_mshr_hits::cpu.inst          364                       # number of ReadReq MSHR hits
792system.cpu.icache.ReadReq_mshr_hits::total          364                       # number of ReadReq MSHR hits
793system.cpu.icache.demand_mshr_hits::cpu.inst          364                       # number of demand (read+write) MSHR hits
794system.cpu.icache.demand_mshr_hits::total          364                       # number of demand (read+write) MSHR hits
795system.cpu.icache.overall_mshr_hits::cpu.inst          364                       # number of overall MSHR hits
796system.cpu.icache.overall_mshr_hits::total          364                       # number of overall MSHR hits
797system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1121                       # number of ReadReq MSHR misses
798system.cpu.icache.ReadReq_mshr_misses::total         1121                       # number of ReadReq MSHR misses
799system.cpu.icache.demand_mshr_misses::cpu.inst         1121                       # number of demand (read+write) MSHR misses
800system.cpu.icache.demand_mshr_misses::total         1121                       # number of demand (read+write) MSHR misses
801system.cpu.icache.overall_mshr_misses::cpu.inst         1121                       # number of overall MSHR misses
802system.cpu.icache.overall_mshr_misses::total         1121                       # number of overall MSHR misses
803system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    114880499                       # number of ReadReq MSHR miss cycles
804system.cpu.icache.ReadReq_mshr_miss_latency::total    114880499                       # number of ReadReq MSHR miss cycles
805system.cpu.icache.demand_mshr_miss_latency::cpu.inst    114880499                       # number of demand (read+write) MSHR miss cycles
806system.cpu.icache.demand_mshr_miss_latency::total    114880499                       # number of demand (read+write) MSHR miss cycles
807system.cpu.icache.overall_mshr_miss_latency::cpu.inst    114880499                       # number of overall MSHR miss cycles
808system.cpu.icache.overall_mshr_miss_latency::total    114880499                       # number of overall MSHR miss cycles
809system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for ReadReq accesses
810system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000038                       # mshr miss rate for ReadReq accesses
811system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for demand accesses
812system.cpu.icache.demand_mshr_miss_rate::total     0.000038                       # mshr miss rate for demand accesses
813system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000038                       # mshr miss rate for overall accesses
814system.cpu.icache.overall_mshr_miss_rate::total     0.000038                       # mshr miss rate for overall accesses
815system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 102480.373773                       # average ReadReq mshr miss latency
816system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 102480.373773                       # average ReadReq mshr miss latency
817system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 102480.373773                       # average overall mshr miss latency
818system.cpu.icache.demand_avg_mshr_miss_latency::total 102480.373773                       # average overall mshr miss latency
819system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 102480.373773                       # average overall mshr miss latency
820system.cpu.icache.overall_avg_mshr_miss_latency::total 102480.373773                       # average overall mshr miss latency
821system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
822system.cpu.l2cache.tags.replacements              694                       # number of replacements
823system.cpu.l2cache.tags.tagsinuse        21678.088627                       # Cycle average of tags in use
824system.cpu.l2cache.tags.total_refs            4121221                       # Total number of references to valid blocks.
825system.cpu.l2cache.tags.sampled_refs            30681                       # Sample count of references to valid blocks.
826system.cpu.l2cache.tags.avg_refs           134.324859                       # Average number of references to valid blocks.
827system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
828system.cpu.l2cache.tags.occ_blocks::writebacks     2.638364                       # Average occupied blocks per requestor
829system.cpu.l2cache.tags.occ_blocks::cpu.inst   712.370564                       # Average occupied blocks per requestor
830system.cpu.l2cache.tags.occ_blocks::cpu.data 20963.079700                       # Average occupied blocks per requestor
831system.cpu.l2cache.tags.occ_percent::writebacks     0.000081                       # Average percentage of cache occupancy
832system.cpu.l2cache.tags.occ_percent::cpu.inst     0.021740                       # Average percentage of cache occupancy
833system.cpu.l2cache.tags.occ_percent::cpu.data     0.639742                       # Average percentage of cache occupancy
834system.cpu.l2cache.tags.occ_percent::total     0.661563                       # Average percentage of cache occupancy
835system.cpu.l2cache.tags.occ_task_id_blocks::1024        29987                       # Occupied blocks per task id
836system.cpu.l2cache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
837system.cpu.l2cache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
838system.cpu.l2cache.tags.age_task_id_blocks_1024::2          186                       # Occupied blocks per task id
839system.cpu.l2cache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
840system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29624                       # Occupied blocks per task id
841system.cpu.l2cache.tags.occ_task_id_percent::1024     0.915131                       # Percentage of cache occupancy per task id
842system.cpu.l2cache.tags.tag_accesses         33245897                       # Number of tag accesses
843system.cpu.l2cache.tags.data_accesses        33245897                       # Number of data accesses
844system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
845system.cpu.l2cache.WritebackDirty_hits::writebacks      2066926                       # number of WritebackDirty hits
846system.cpu.l2cache.WritebackDirty_hits::total      2066926                       # number of WritebackDirty hits
847system.cpu.l2cache.WritebackClean_hits::writebacks           93                       # number of WritebackClean hits
848system.cpu.l2cache.WritebackClean_hits::total           93                       # number of WritebackClean hits
849system.cpu.l2cache.ReadExReq_hits::cpu.data        52858                       # number of ReadExReq hits
850system.cpu.l2cache.ReadExReq_hits::total        52858                       # number of ReadExReq hits
851system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           28                       # number of ReadCleanReq hits
852system.cpu.l2cache.ReadCleanReq_hits::total           28                       # number of ReadCleanReq hits
853system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1994973                       # number of ReadSharedReq hits
854system.cpu.l2cache.ReadSharedReq_hits::total      1994973                       # number of ReadSharedReq hits
855system.cpu.l2cache.demand_hits::cpu.inst           28                       # number of demand (read+write) hits
856system.cpu.l2cache.demand_hits::cpu.data      2047831                       # number of demand (read+write) hits
857system.cpu.l2cache.demand_hits::total         2047859                       # number of demand (read+write) hits
858system.cpu.l2cache.overall_hits::cpu.inst           28                       # number of overall hits
859system.cpu.l2cache.overall_hits::cpu.data      2047831                       # number of overall hits
860system.cpu.l2cache.overall_hits::total        2047859                       # number of overall hits
861system.cpu.l2cache.ReadExReq_misses::cpu.data        28990                       # number of ReadExReq misses
862system.cpu.l2cache.ReadExReq_misses::total        28990                       # number of ReadExReq misses
863system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1093                       # number of ReadCleanReq misses
864system.cpu.l2cache.ReadCleanReq_misses::total         1093                       # number of ReadCleanReq misses
865system.cpu.l2cache.ReadSharedReq_misses::cpu.data          581                       # number of ReadSharedReq misses
866system.cpu.l2cache.ReadSharedReq_misses::total          581                       # number of ReadSharedReq misses
867system.cpu.l2cache.demand_misses::cpu.inst         1093                       # number of demand (read+write) misses
868system.cpu.l2cache.demand_misses::cpu.data        29571                       # number of demand (read+write) misses
869system.cpu.l2cache.demand_misses::total         30664                       # number of demand (read+write) misses
870system.cpu.l2cache.overall_misses::cpu.inst         1093                       # number of overall misses
871system.cpu.l2cache.overall_misses::cpu.data        29571                       # number of overall misses
872system.cpu.l2cache.overall_misses::total        30664                       # number of overall misses
873system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2345791000                       # number of ReadExReq miss cycles
874system.cpu.l2cache.ReadExReq_miss_latency::total   2345791000                       # number of ReadExReq miss cycles
875system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    112890000                       # number of ReadCleanReq miss cycles
876system.cpu.l2cache.ReadCleanReq_miss_latency::total    112890000                       # number of ReadCleanReq miss cycles
877system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     92689500                       # number of ReadSharedReq miss cycles
878system.cpu.l2cache.ReadSharedReq_miss_latency::total     92689500                       # number of ReadSharedReq miss cycles
879system.cpu.l2cache.demand_miss_latency::cpu.inst    112890000                       # number of demand (read+write) miss cycles
880system.cpu.l2cache.demand_miss_latency::cpu.data   2438480500                       # number of demand (read+write) miss cycles
881system.cpu.l2cache.demand_miss_latency::total   2551370500                       # number of demand (read+write) miss cycles
882system.cpu.l2cache.overall_miss_latency::cpu.inst    112890000                       # number of overall miss cycles
883system.cpu.l2cache.overall_miss_latency::cpu.data   2438480500                       # number of overall miss cycles
884system.cpu.l2cache.overall_miss_latency::total   2551370500                       # number of overall miss cycles
885system.cpu.l2cache.WritebackDirty_accesses::writebacks      2066926                       # number of WritebackDirty accesses(hits+misses)
886system.cpu.l2cache.WritebackDirty_accesses::total      2066926                       # number of WritebackDirty accesses(hits+misses)
887system.cpu.l2cache.WritebackClean_accesses::writebacks           93                       # number of WritebackClean accesses(hits+misses)
888system.cpu.l2cache.WritebackClean_accesses::total           93                       # number of WritebackClean accesses(hits+misses)
889system.cpu.l2cache.ReadExReq_accesses::cpu.data        81848                       # number of ReadExReq accesses(hits+misses)
890system.cpu.l2cache.ReadExReq_accesses::total        81848                       # number of ReadExReq accesses(hits+misses)
891system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1121                       # number of ReadCleanReq accesses(hits+misses)
892system.cpu.l2cache.ReadCleanReq_accesses::total         1121                       # number of ReadCleanReq accesses(hits+misses)
893system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1995554                       # number of ReadSharedReq accesses(hits+misses)
894system.cpu.l2cache.ReadSharedReq_accesses::total      1995554                       # number of ReadSharedReq accesses(hits+misses)
895system.cpu.l2cache.demand_accesses::cpu.inst         1121                       # number of demand (read+write) accesses
896system.cpu.l2cache.demand_accesses::cpu.data      2077402                       # number of demand (read+write) accesses
897system.cpu.l2cache.demand_accesses::total      2078523                       # number of demand (read+write) accesses
898system.cpu.l2cache.overall_accesses::cpu.inst         1121                       # number of overall (read+write) accesses
899system.cpu.l2cache.overall_accesses::cpu.data      2077402                       # number of overall (read+write) accesses
900system.cpu.l2cache.overall_accesses::total      2078523                       # number of overall (read+write) accesses
901system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.354193                       # miss rate for ReadExReq accesses
902system.cpu.l2cache.ReadExReq_miss_rate::total     0.354193                       # miss rate for ReadExReq accesses
903system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.975022                       # miss rate for ReadCleanReq accesses
904system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.975022                       # miss rate for ReadCleanReq accesses
905system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000291                       # miss rate for ReadSharedReq accesses
906system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000291                       # miss rate for ReadSharedReq accesses
907system.cpu.l2cache.demand_miss_rate::cpu.inst     0.975022                       # miss rate for demand accesses
908system.cpu.l2cache.demand_miss_rate::cpu.data     0.014235                       # miss rate for demand accesses
909system.cpu.l2cache.demand_miss_rate::total     0.014753                       # miss rate for demand accesses
910system.cpu.l2cache.overall_miss_rate::cpu.inst     0.975022                       # miss rate for overall accesses
911system.cpu.l2cache.overall_miss_rate::cpu.data     0.014235                       # miss rate for overall accesses
912system.cpu.l2cache.overall_miss_rate::total     0.014753                       # miss rate for overall accesses
913system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80917.247327                       # average ReadExReq miss latency
914system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80917.247327                       # average ReadExReq miss latency
915system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103284.537969                       # average ReadCleanReq miss latency
916system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103284.537969                       # average ReadCleanReq miss latency
917system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 159534.423408                       # average ReadSharedReq miss latency
918system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 159534.423408                       # average ReadSharedReq miss latency
919system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103284.537969                       # average overall miss latency
920system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82461.888337                       # average overall miss latency
921system.cpu.l2cache.demand_avg_miss_latency::total 83204.099270                       # average overall miss latency
922system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103284.537969                       # average overall miss latency
923system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82461.888337                       # average overall miss latency
924system.cpu.l2cache.overall_avg_miss_latency::total 83204.099270                       # average overall miss latency
925system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
926system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
927system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
928system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
929system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
930system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
931system.cpu.l2cache.writebacks::writebacks          309                       # number of writebacks
932system.cpu.l2cache.writebacks::total              309                       # number of writebacks
933system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28990                       # number of ReadExReq MSHR misses
934system.cpu.l2cache.ReadExReq_mshr_misses::total        28990                       # number of ReadExReq MSHR misses
935system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1093                       # number of ReadCleanReq MSHR misses
936system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1093                       # number of ReadCleanReq MSHR misses
937system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          581                       # number of ReadSharedReq MSHR misses
938system.cpu.l2cache.ReadSharedReq_mshr_misses::total          581                       # number of ReadSharedReq MSHR misses
939system.cpu.l2cache.demand_mshr_misses::cpu.inst         1093                       # number of demand (read+write) MSHR misses
940system.cpu.l2cache.demand_mshr_misses::cpu.data        29571                       # number of demand (read+write) MSHR misses
941system.cpu.l2cache.demand_mshr_misses::total        30664                       # number of demand (read+write) MSHR misses
942system.cpu.l2cache.overall_mshr_misses::cpu.inst         1093                       # number of overall MSHR misses
943system.cpu.l2cache.overall_mshr_misses::cpu.data        29571                       # number of overall MSHR misses
944system.cpu.l2cache.overall_mshr_misses::total        30664                       # number of overall MSHR misses
945system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2055891000                       # number of ReadExReq MSHR miss cycles
946system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2055891000                       # number of ReadExReq MSHR miss cycles
947system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    101960000                       # number of ReadCleanReq MSHR miss cycles
948system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    101960000                       # number of ReadCleanReq MSHR miss cycles
949system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     86879500                       # number of ReadSharedReq MSHR miss cycles
950system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     86879500                       # number of ReadSharedReq MSHR miss cycles
951system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    101960000                       # number of demand (read+write) MSHR miss cycles
952system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   2142770500                       # number of demand (read+write) MSHR miss cycles
953system.cpu.l2cache.demand_mshr_miss_latency::total   2244730500                       # number of demand (read+write) MSHR miss cycles
954system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    101960000                       # number of overall MSHR miss cycles
955system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   2142770500                       # number of overall MSHR miss cycles
956system.cpu.l2cache.overall_mshr_miss_latency::total   2244730500                       # number of overall MSHR miss cycles
957system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.354193                       # mshr miss rate for ReadExReq accesses
958system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.354193                       # mshr miss rate for ReadExReq accesses
959system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.975022                       # mshr miss rate for ReadCleanReq accesses
960system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.975022                       # mshr miss rate for ReadCleanReq accesses
961system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000291                       # mshr miss rate for ReadSharedReq accesses
962system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000291                       # mshr miss rate for ReadSharedReq accesses
963system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.975022                       # mshr miss rate for demand accesses
964system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014235                       # mshr miss rate for demand accesses
965system.cpu.l2cache.demand_mshr_miss_rate::total     0.014753                       # mshr miss rate for demand accesses
966system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.975022                       # mshr miss rate for overall accesses
967system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014235                       # mshr miss rate for overall accesses
968system.cpu.l2cache.overall_mshr_miss_rate::total     0.014753                       # mshr miss rate for overall accesses
969system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70917.247327                       # average ReadExReq mshr miss latency
970system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70917.247327                       # average ReadExReq mshr miss latency
971system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93284.537969                       # average ReadCleanReq mshr miss latency
972system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93284.537969                       # average ReadCleanReq mshr miss latency
973system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 149534.423408                       # average ReadSharedReq mshr miss latency
974system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 149534.423408                       # average ReadSharedReq mshr miss latency
975system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93284.537969                       # average overall mshr miss latency
976system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72461.888337                       # average overall mshr miss latency
977system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73204.099270                       # average overall mshr miss latency
978system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93284.537969                       # average overall mshr miss latency
979system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72461.888337                       # average overall mshr miss latency
980system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73204.099270                       # average overall mshr miss latency
981system.cpu.toL2Bus.snoop_filter.tot_requests      4151922                       # Total number of requests made to the snoop filter.
982system.cpu.toL2Bus.snoop_filter.hit_single_requests      2073402                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
983system.cpu.toL2Bus.snoop_filter.hit_multi_requests           20                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
984system.cpu.toL2Bus.snoop_filter.tot_snoops          335                       # Total number of snoops made to the snoop filter.
985system.cpu.toL2Bus.snoop_filter.hit_single_snoops          335                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
986system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
987system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
988system.cpu.toL2Bus.trans_dist::ReadResp       1996675                       # Transaction distribution
989system.cpu.toL2Bus.trans_dist::WritebackDirty      2067235                       # Transaction distribution
990system.cpu.toL2Bus.trans_dist::WritebackClean           93                       # Transaction distribution
991system.cpu.toL2Bus.trans_dist::CleanEvict         6765                       # Transaction distribution
992system.cpu.toL2Bus.trans_dist::ReadExReq        81848                       # Transaction distribution
993system.cpu.toL2Bus.trans_dist::ReadExResp        81848                       # Transaction distribution
994system.cpu.toL2Bus.trans_dist::ReadCleanReq         1121                       # Transaction distribution
995system.cpu.toL2Bus.trans_dist::ReadSharedReq      1995554                       # Transaction distribution
996system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2335                       # Packet count per connected master and slave (bytes)
997system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6228110                       # Packet count per connected master and slave (bytes)
998system.cpu.toL2Bus.pkt_count::total           6230445                       # Packet count per connected master and slave (bytes)
999system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77696                       # Cumulative packet size per connected master and slave (bytes)
1000system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265236992                       # Cumulative packet size per connected master and slave (bytes)
1001system.cpu.toL2Bus.pkt_size::total          265314688                       # Cumulative packet size per connected master and slave (bytes)
1002system.cpu.toL2Bus.snoops                         694                       # Total snoops (count)
1003system.cpu.toL2Bus.snoopTraffic                 19776                       # Total snoop traffic (bytes)
1004system.cpu.toL2Bus.snoop_fanout::samples      2079217                       # Request fanout histogram
1005system.cpu.toL2Bus.snoop_fanout::mean        0.000172                       # Request fanout histogram
1006system.cpu.toL2Bus.snoop_fanout::stdev       0.013121                       # Request fanout histogram
1007system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
1008system.cpu.toL2Bus.snoop_fanout::0            2078859     99.98%     99.98% # Request fanout histogram
1009system.cpu.toL2Bus.snoop_fanout::1                358      0.02%    100.00% # Request fanout histogram
1010system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
1011system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
1012system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
1013system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
1014system.cpu.toL2Bus.snoop_fanout::total        2079217                       # Request fanout histogram
1015system.cpu.toL2Bus.reqLayer0.occupancy     4142980000                       # Layer occupancy (ticks)
1016system.cpu.toL2Bus.reqLayer0.utilization          6.3                       # Layer utilization (%)
1017system.cpu.toL2Bus.respLayer0.occupancy       1681500                       # Layer occupancy (ticks)
1018system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
1019system.cpu.toL2Bus.respLayer1.occupancy    3116103000                       # Layer occupancy (ticks)
1020system.cpu.toL2Bus.respLayer1.utilization          4.7                       # Layer utilization (%)
1021system.membus.snoop_filter.tot_requests         31023                       # Total number of requests made to the snoop filter.
1022system.membus.snoop_filter.hit_single_requests          359                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
1023system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1024system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
1025system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1026system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1027system.membus.pwrStateResidencyTicks::UNDEFINED  65832730500                       # Cumulative time (in ticks) in various power states
1028system.membus.trans_dist::ReadResp               1674                       # Transaction distribution
1029system.membus.trans_dist::WritebackDirty          309                       # Transaction distribution
1030system.membus.trans_dist::CleanEvict               50                       # Transaction distribution
1031system.membus.trans_dist::ReadExReq             28990                       # Transaction distribution
1032system.membus.trans_dist::ReadExResp            28990                       # Transaction distribution
1033system.membus.trans_dist::ReadSharedReq          1674                       # Transaction distribution
1034system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61687                       # Packet count per connected master and slave (bytes)
1035system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61687                       # Packet count per connected master and slave (bytes)
1036system.membus.pkt_count::total                  61687                       # Packet count per connected master and slave (bytes)
1037system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1982272                       # Cumulative packet size per connected master and slave (bytes)
1038system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1982272                       # Cumulative packet size per connected master and slave (bytes)
1039system.membus.pkt_size::total                 1982272                       # Cumulative packet size per connected master and slave (bytes)
1040system.membus.snoops                                0                       # Total snoops (count)
1041system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
1042system.membus.snoop_fanout::samples             30664                       # Request fanout histogram
1043system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
1044system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
1045system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
1046system.membus.snoop_fanout::0                   30664    100.00%    100.00% # Request fanout histogram
1047system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
1048system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
1049system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
1050system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
1051system.membus.snoop_fanout::total               30664                       # Request fanout histogram
1052system.membus.reqLayer0.occupancy            43676000                       # Layer occupancy (ticks)
1053system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
1054system.membus.respLayer1.occupancy          161581250                       # Layer occupancy (ticks)
1055system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
1056
1057---------- End Simulation Statistics   ----------
1058