stats.txt revision 10242:cb4e86c17767
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.064361 # Number of seconds simulated 4sim_ticks 64361067000 # Number of ticks simulated 5final_tick 64361067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 110006 # Simulator instruction rate (inst/s) 8host_op_rate 193702 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44813910 # Simulator tick rate (ticks/s) 10host_mem_usage 383472 # Number of bytes of host memory used 11host_seconds 1436.19 # Real time elapsed on the host 12sim_insts 157988547 # Number of instructions simulated 13sim_ops 278192464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 64000 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1883008 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 64000 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 64000 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 10944 # Number of bytes written to this memory 22system.physmem.bytes_written::total 10944 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1000 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 29422 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 171 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 171 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 994390 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 29256942 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 30251332 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 994390 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 994390 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 170041 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 170041 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 170041 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 994390 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 29256942 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 30421373 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 30424 # Number of read requests accepted 40system.physmem.writeReqs 171 # Number of write requests accepted 41system.physmem.readBursts 30424 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 171 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 1942272 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 4864 # Total number of bytes read from write queue 45system.physmem.bytesWritten 9152 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 1947136 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 10944 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 76 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 1923 # Per bank write bursts 52system.physmem.perBankRdBursts::1 2059 # Per bank write bursts 53system.physmem.perBankRdBursts::2 2030 # Per bank write bursts 54system.physmem.perBankRdBursts::3 1927 # Per bank write bursts 55system.physmem.perBankRdBursts::4 2025 # Per bank write bursts 56system.physmem.perBankRdBursts::5 1901 # Per bank write bursts 57system.physmem.perBankRdBursts::6 1962 # Per bank write bursts 58system.physmem.perBankRdBursts::7 1863 # Per bank write bursts 59system.physmem.perBankRdBursts::8 1938 # Per bank write bursts 60system.physmem.perBankRdBursts::9 1933 # Per bank write bursts 61system.physmem.perBankRdBursts::10 1804 # Per bank write bursts 62system.physmem.perBankRdBursts::11 1796 # Per bank write bursts 63system.physmem.perBankRdBursts::12 1792 # Per bank write bursts 64system.physmem.perBankRdBursts::13 1800 # Per bank write bursts 65system.physmem.perBankRdBursts::14 1817 # Per bank write bursts 66system.physmem.perBankRdBursts::15 1778 # Per bank write bursts 67system.physmem.perBankWrBursts::0 9 # Per bank write bursts 68system.physmem.perBankWrBursts::1 79 # Per bank write bursts 69system.physmem.perBankWrBursts::2 8 # Per bank write bursts 70system.physmem.perBankWrBursts::3 14 # Per bank write bursts 71system.physmem.perBankWrBursts::4 6 # Per bank write bursts 72system.physmem.perBankWrBursts::5 7 # Per bank write bursts 73system.physmem.perBankWrBursts::6 12 # Per bank write bursts 74system.physmem.perBankWrBursts::7 0 # Per bank write bursts 75system.physmem.perBankWrBursts::8 0 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5 # Per bank write bursts 77system.physmem.perBankWrBursts::10 3 # Per bank write bursts 78system.physmem.perBankWrBursts::11 0 # Per bank write bursts 79system.physmem.perBankWrBursts::12 0 # Per bank write bursts 80system.physmem.perBankWrBursts::13 0 # Per bank write bursts 81system.physmem.perBankWrBursts::14 0 # Per bank write bursts 82system.physmem.perBankWrBursts::15 0 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 64361050000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 30424 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 171 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 29879 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 374 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 75 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 8 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 8 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 2692 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 724.017831 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 522.534866 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 387.414799 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 354 13.15% 13.15% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 226 8.40% 21.55% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 117 4.35% 25.89% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 114 4.23% 30.13% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 102 3.79% 33.92% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 97 3.60% 37.52% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 103 3.83% 41.34% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 99 3.68% 45.02% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 1480 54.98% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 2692 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 3785.250000 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 36.090663 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 10663.878800 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 7 87.50% 87.50% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::29696-30719 1 12.50% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.875000 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.857209 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 0.834523 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16 1 12.50% 12.50% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18 6 75.00% 87.50% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::19 1 12.50% 100.00% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads 225system.physmem.totQLat 124712250 # Total ticks spent queuing 226system.physmem.totMemAccLat 693737250 # Total ticks spent from burst creation until serviced by the DRAM 227system.physmem.totBusLat 151740000 # Total ticks spent in databus transfers 228system.physmem.avgQLat 4109.41 # Average queueing delay per DRAM burst 229system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 230system.physmem.avgMemAccLat 22859.41 # Average memory access latency per DRAM burst 231system.physmem.avgRdBW 30.18 # Average DRAM read bandwidth in MiByte/s 232system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MiByte/s 233system.physmem.avgRdBWSys 30.25 # Average system read bandwidth in MiByte/s 234system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s 235system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 236system.physmem.busUtil 0.24 # Data bus utilization in percentage 237system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads 238system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 239system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 240system.physmem.avgWrQLen 19.95 # Average write queue length when enqueuing 241system.physmem.readRowHits 27697 # Number of row buffer hits during reads 242system.physmem.writeRowHits 92 # Number of row buffer hits during writes 243system.physmem.readRowHitRate 91.26 # Row buffer hit rate for reads 244system.physmem.writeRowHitRate 53.80 # Row buffer hit rate for writes 245system.physmem.avgGap 2103646.02 # Average gap between requests 246system.physmem.pageHitRate 91.05 # Row buffer hit rate, read and write combined 247system.physmem.memoryStateTime::IDLE 58016949500 # Time in different power states 248system.physmem.memoryStateTime::REF 2148900000 # Time in different power states 249system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.physmem.memoryStateTime::ACT 4191773500 # Time in different power states 251system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 252system.membus.throughput 30420378 # Throughput (bytes/s) 253system.membus.trans_dist::ReadReq 1422 # Transaction distribution 254system.membus.trans_dist::ReadResp 1419 # Transaction distribution 255system.membus.trans_dist::Writeback 171 # Transaction distribution 256system.membus.trans_dist::ReadExReq 29002 # Transaction distribution 257system.membus.trans_dist::ReadExResp 29002 # Transaction distribution 258system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61016 # Packet count per connected master and slave (bytes) 259system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61016 # Packet count per connected master and slave (bytes) 260system.membus.pkt_count::total 61016 # Packet count per connected master and slave (bytes) 261system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957888 # Cumulative packet size per connected master and slave (bytes) 262system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957888 # Cumulative packet size per connected master and slave (bytes) 263system.membus.tot_pkt_size::total 1957888 # Cumulative packet size per connected master and slave (bytes) 264system.membus.data_through_bus 1957888 # Total data (bytes) 265system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 266system.membus.reqLayer0.occupancy 35504500 # Layer occupancy (ticks) 267system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 268system.membus.respLayer1.occupancy 284722250 # Layer occupancy (ticks) 269system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 270system.cpu_clk_domain.clock 500 # Clock period in ticks 271system.cpu.branchPred.lookups 34798086 # Number of BP lookups 272system.cpu.branchPred.condPredicted 34798086 # Number of conditional branches predicted 273system.cpu.branchPred.condIncorrect 784118 # Number of conditional branches incorrect 274system.cpu.branchPred.BTBLookups 19722572 # Number of BTB lookups 275system.cpu.branchPred.BTBHits 19623609 # Number of BTB hits 276system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 277system.cpu.branchPred.BTBHitPct 99.498225 # BTB Hit Percentage 278system.cpu.branchPred.usedRAS 5229209 # Number of times the RAS was used to get a target. 279system.cpu.branchPred.RASInCorrect 5537 # Number of incorrect RAS predictions. 280system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 281system.cpu.workload.num_syscalls 444 # Number of system calls 282system.cpu.numCycles 128722137 # number of cpu cycles simulated 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 285system.cpu.fetch.icacheStallCycles 26886538 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 188337970 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 34798086 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 24852818 # Number of branches that fetch has predicted taken 289system.cpu.fetch.Cycles 57142929 # Number of cycles fetch has run and was not squashing or blocked 290system.cpu.fetch.SquashCycles 6497811 # Number of cycles fetch has spent squashing 291system.cpu.fetch.BlockedCycles 38531317 # Number of cycles fetch has spent blocked 292system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 293system.cpu.fetch.PendingTrapStallCycles 400 # Number of stall cycles due to pending traps 294system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR 295system.cpu.fetch.CacheLines 26333180 # Number of cache lines fetched 296system.cpu.fetch.IcacheSquashes 202728 # Number of outstanding Icache misses that were squashed 297system.cpu.fetch.rateDist::samples 128229739 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::mean 2.583672 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::stdev 3.351921 # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::0 73621715 57.41% 57.41% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::1 2024375 1.58% 58.99% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::2 3018246 2.35% 61.35% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::3 3935135 3.07% 64.42% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::4 7973611 6.22% 70.63% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::5 4963159 3.87% 74.50% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::6 2723923 2.12% 76.63% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::7 1373007 1.07% 77.70% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::8 28596568 22.30% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::total 128229739 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.branchRate 0.270335 # Number of branch fetches per cycle 315system.cpu.fetch.rate 1.463136 # Number of inst fetches per cycle 316system.cpu.decode.IdleCycles 33273315 # Number of cycles decode is idle 317system.cpu.decode.BlockedCycles 35123523 # Number of cycles decode is blocked 318system.cpu.decode.RunCycles 52275495 # Number of cycles decode is running 319system.cpu.decode.UnblockCycles 1888908 # Number of cycles decode is unblocking 320system.cpu.decode.SquashCycles 5668498 # Number of cycles decode is squashing 321system.cpu.decode.DecodedInsts 328717141 # Number of instructions handled by decode 322system.cpu.rename.SquashCycles 5668498 # Number of cycles rename is squashing 323system.cpu.rename.IdleCycles 37218540 # Number of cycles rename is idle 324system.cpu.rename.BlockCycles 3059312 # Number of cycles rename is blocking 325system.cpu.rename.serializeStallCycles 10022 # count of cycles rename stalled for serializing inst 326system.cpu.rename.RunCycles 50252159 # Number of cycles rename is running 327system.cpu.rename.UnblockCycles 32021208 # Number of cycles rename is unblocking 328system.cpu.rename.RenamedInsts 323526783 # Number of instructions processed by rename 329system.cpu.rename.ROBFullEvents 1441 # Number of times rename has blocked due to ROB full 330system.cpu.rename.IQFullEvents 292036 # Number of times rename has blocked due to IQ full 331system.cpu.rename.LQFullEvents 27143978 # Number of times rename has blocked due to LQ full 332system.cpu.rename.SQFullEvents 4136186 # Number of times rename has blocked due to SQ full 333system.cpu.rename.RenamedOperands 325451198 # Number of destination operands rename has renamed 334system.cpu.rename.RenameLookups 859036392 # Number of register rename lookups that rename has made 335system.cpu.rename.int_rename_lookups 529005653 # Number of integer rename lookups 336system.cpu.rename.fp_rename_lookups 495 # Number of floating rename lookups 337system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed 338system.cpu.rename.UndoneMaps 46238451 # Number of HB maps that are undone due to squashing 339system.cpu.rename.serializingInsts 482 # count of serializing insts renamed 340system.cpu.rename.tempSerializingInsts 480 # count of temporary serializing insts renamed 341system.cpu.rename.skidInsts 38827180 # count of insts added to the skid buffer 342system.cpu.memDep0.insertedLoads 104278858 # Number of loads inserted to the mem dependence unit. 343system.cpu.memDep0.insertedStores 35723148 # Number of stores inserted to the mem dependence unit. 344system.cpu.memDep0.conflictingLoads 46025226 # Number of conflicting loads. 345system.cpu.memDep0.conflictingStores 6660051 # Number of conflicting stores. 346system.cpu.iq.iqInstsAdded 319586854 # Number of instructions added to the IQ (excludes non-spec) 347system.cpu.iq.iqNonSpecInstsAdded 1670 # Number of non-speculative instructions added to the IQ 348system.cpu.iq.iqInstsIssued 304359156 # Number of instructions issued 349system.cpu.iq.iqSquashedInstsIssued 192192 # Number of squashed instructions issued 350system.cpu.iq.iqSquashedInstsExamined 40795282 # Number of squashed instructions iterated over during squash; mainly for profiling 351system.cpu.iq.iqSquashedOperandsExamined 60346573 # Number of squashed operands that are examined and possibly removed from graph 352system.cpu.iq.iqSquashedNonSpecRemoved 1225 # Number of squashed non-spec instructions that were removed 353system.cpu.iq.issued_per_cycle::samples 128229739 # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::mean 2.373546 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::stdev 1.813536 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::0 28989242 22.61% 22.61% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::1 17448953 13.61% 36.21% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::2 19181395 14.96% 51.17% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::3 24360940 19.00% 70.17% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::4 22567411 17.60% 87.77% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::5 10236760 7.98% 95.75% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::6 4240558 3.31% 99.06% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::7 1068039 0.83% 99.89% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::8 136441 0.11% 100.00% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::total 128229739 # Number of insts issued each cycle 370system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 371system.cpu.iq.fu_full::IntAlu 85597 3.62% 3.62% # attempts to use FU when none available 372system.cpu.iq.fu_full::IntMult 0 0.00% 3.62% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntDiv 0 0.00% 3.62% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.62% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.62% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.62% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatMult 0 0.00% 3.62% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.62% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.62% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.62% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.62% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.62% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.62% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.62% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.62% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdMult 0 0.00% 3.62% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.62% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdShift 0 0.00% 3.62% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.62% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.62% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.62% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.62% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.62% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.62% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.62% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.62% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.62% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.62% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.62% # attempts to use FU when none available 400system.cpu.iq.fu_full::MemRead 2173481 92.00% 95.62% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemWrite 103394 4.38% 100.00% # attempts to use FU when none available 402system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% # Type of FU issued 405system.cpu.iq.FU_type_0::IntAlu 172841480 56.79% 56.80% # Type of FU issued 406system.cpu.iq.FU_type_0::IntMult 11196 0.00% 56.80% # Type of FU issued 407system.cpu.iq.FU_type_0::IntDiv 333 0.00% 56.80% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatAdd 41 0.00% 56.80% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.80% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.80% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.80% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.80% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.80% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.80% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.80% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.80% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.80% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.80% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.80% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.80% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.80% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.80% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.80% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.80% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.80% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.80% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.80% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.80% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.80% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.80% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.80% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.80% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.80% # Type of FU issued 434system.cpu.iq.FU_type_0::MemRead 97881417 32.16% 88.96% # Type of FU issued 435system.cpu.iq.FU_type_0::MemWrite 33591350 11.04% 100.00% # Type of FU issued 436system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::total 304359156 # Type of FU issued 439system.cpu.iq.rate 2.364466 # Inst issue rate 440system.cpu.iq.fu_busy_cnt 2362472 # FU busy when requested 441system.cpu.iq.fu_busy_rate 0.007762 # FU busy rate (busy events/executed inst) 442system.cpu.iq.int_inst_queue_reads 739502310 # Number of integer instruction queue reads 443system.cpu.iq.int_inst_queue_writes 360419132 # Number of integer instruction queue writes 444system.cpu.iq.int_inst_queue_wakeup_accesses 302118974 # Number of integer instruction queue wakeup accesses 445system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads 446system.cpu.iq.fp_inst_queue_writes 682 # Number of floating instruction queue writes 447system.cpu.iq.fp_inst_queue_wakeup_accesses 144 # Number of floating instruction queue wakeup accesses 448system.cpu.iq.int_alu_accesses 306688087 # Number of integer alu accesses 449system.cpu.iq.fp_alu_accesses 202 # Number of floating point alu accesses 450system.cpu.iew.lsq.thread0.forwLoads 56122672 # Number of loads that had data forwarded from stores 451system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 452system.cpu.iew.lsq.thread0.squashedLoads 13499473 # Number of loads squashed 453system.cpu.iew.lsq.thread0.ignoredResponses 33923 # Number of memory responses ignored because the instruction is squashed 454system.cpu.iew.lsq.thread0.memOrderViolation 36991 # Number of memory ordering violations 455system.cpu.iew.lsq.thread0.squashedStores 4283396 # Number of stores squashed 456system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 457system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 458system.cpu.iew.lsq.thread0.rescheduledLoads 3583 # Number of loads that were rescheduled 459system.cpu.iew.lsq.thread0.cacheBlocked 18172 # Number of times an access to memory failed due to the cache being blocked 460system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 461system.cpu.iew.iewSquashCycles 5668498 # Number of cycles IEW is squashing 462system.cpu.iew.iewBlockCycles 78601 # Number of cycles IEW is blocking 463system.cpu.iew.iewUnblockCycles 2898580 # Number of cycles IEW is unblocking 464system.cpu.iew.iewDispatchedInsts 319588524 # Number of instructions dispatched to IQ 465system.cpu.iew.iewDispSquashedInsts 72060 # Number of squashed instructions skipped by dispatch 466system.cpu.iew.iewDispLoadInsts 104278858 # Number of dispatched load instructions 467system.cpu.iew.iewDispStoreInsts 35723148 # Number of dispatched store instructions 468system.cpu.iew.iewDispNonSpecInsts 467 # Number of dispatched non-speculative instructions 469system.cpu.iew.iewIQFullEvents 4947 # Number of times the IQ has become full, causing a stall 470system.cpu.iew.iewLSQFullEvents 2697345 # Number of times the LSQ has become full, causing a stall 471system.cpu.iew.memOrderViolationEvents 36991 # Number of memory order violations 472system.cpu.iew.predictedTakenIncorrect 397417 # Number of branches that were predicted taken incorrectly 473system.cpu.iew.predictedNotTakenIncorrect 436010 # Number of branches that were predicted not taken incorrectly 474system.cpu.iew.branchMispredicts 833427 # Number of branch mispredicts detected at execute 475system.cpu.iew.iewExecutedInsts 302993807 # Number of executed instructions 476system.cpu.iew.iewExecLoadInsts 97430054 # Number of load instructions executed 477system.cpu.iew.iewExecSquashedInsts 1365349 # Number of squashed instructions skipped in execute 478system.cpu.iew.exec_swp 0 # number of swp insts executed 479system.cpu.iew.exec_nop 0 # number of nop insts executed 480system.cpu.iew.exec_refs 130824453 # number of memory reference insts executed 481system.cpu.iew.exec_branches 31189297 # Number of branches executed 482system.cpu.iew.exec_stores 33394399 # Number of stores executed 483system.cpu.iew.exec_rate 2.353859 # Inst execution rate 484system.cpu.iew.wb_sent 302554101 # cumulative count of insts sent to commit 485system.cpu.iew.wb_count 302119118 # cumulative count of insts written-back 486system.cpu.iew.wb_producers 223057856 # num instructions producing a value 487system.cpu.iew.wb_consumers 305896063 # num instructions consuming a value 488system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 489system.cpu.iew.wb_rate 2.347064 # insts written-back per cycle 490system.cpu.iew.wb_fanout 0.729195 # average fanout of values written-back 491system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 492system.cpu.commit.commitSquashedInsts 41496946 # The number of squashed insts skipped by commit 493system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 494system.cpu.commit.branchMispredicts 784165 # The number of times a branch was mispredicted 495system.cpu.commit.committed_per_cycle::samples 122561241 # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::mean 2.269824 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::stdev 3.033262 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::0 56600375 46.18% 46.18% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::1 17466589 14.25% 60.43% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::2 11063696 9.03% 69.46% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::3 8855238 7.23% 76.68% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::4 1990404 1.62% 78.31% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::5 1890723 1.54% 79.85% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::6 1087341 0.89% 80.74% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::7 761508 0.62% 81.36% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::8 22845367 18.64% 100.00% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::total 122561241 # Number of insts commited each cycle 512system.cpu.commit.committedInsts 157988547 # Number of instructions committed 513system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 514system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 515system.cpu.commit.refs 122219137 # Number of memory references committed 516system.cpu.commit.loads 90779385 # Number of loads committed 517system.cpu.commit.membars 0 # Number of memory barriers committed 518system.cpu.commit.branches 29309705 # Number of branches committed 519system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 520system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 521system.cpu.commit.function_calls 4237596 # Number of function calls committed. 522system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction 523system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction 524system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction 525system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction 526system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction 527system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction 528system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction 529system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction 530system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction 531system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction 552system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction 553system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction 554system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction 557system.cpu.commit.bw_lim_events 22845367 # number cycles where commit BW limit reached 558system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 559system.cpu.rob.rob_reads 419405284 # The number of ROB reads 560system.cpu.rob.rob_writes 645053666 # The number of ROB writes 561system.cpu.timesIdled 104925 # Number of times that the entire CPU went into an idle state and unscheduled itself 562system.cpu.idleCycles 492398 # Total number of cycles that the CPU has spent unscheduled due to idling 563system.cpu.committedInsts 157988547 # Number of Instructions Simulated 564system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 565system.cpu.cpi 0.814756 # CPI: Cycles Per Instruction 566system.cpu.cpi_total 0.814756 # CPI: Total CPI of All Threads 567system.cpu.ipc 1.227361 # IPC: Instructions Per Cycle 568system.cpu.ipc_total 1.227361 # IPC: Total IPC of All Threads 569system.cpu.int_regfile_reads 488589645 # number of integer regfile reads 570system.cpu.int_regfile_writes 237913555 # number of integer regfile writes 571system.cpu.fp_regfile_reads 124 # number of floating regfile reads 572system.cpu.fp_regfile_writes 93 # number of floating regfile writes 573system.cpu.cc_regfile_reads 107415229 # number of cc regfile reads 574system.cpu.cc_regfile_writes 64109444 # number of cc regfile writes 575system.cpu.misc_regfile_reads 194048137 # number of misc regfile reads 576system.cpu.misc_regfile_writes 1 # number of misc regfile writes 577system.cpu.toL2Bus.throughput 4120563135 # Throughput (bytes/s) 578system.cpu.toL2Bus.trans_dist::ReadReq 1995370 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::ReadResp 1995367 # Transaction distribution 580system.cpu.toL2Bus.trans_dist::Writeback 2066178 # Transaction distribution 581system.cpu.toL2Bus.trans_dist::ReadExReq 82265 # Transaction distribution 582system.cpu.toL2Bus.trans_dist::ReadExResp 82265 # Transaction distribution 583system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2034 # Packet count per connected master and slave (bytes) 584system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219411 # Packet count per connected master and slave (bytes) 585system.cpu.toL2Bus.pkt_count::total 6221445 # Packet count per connected master and slave (bytes) 586system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65088 # Cumulative packet size per connected master and slave (bytes) 587system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265138752 # Cumulative packet size per connected master and slave (bytes) 588system.cpu.toL2Bus.tot_pkt_size::total 265203840 # Cumulative packet size per connected master and slave (bytes) 589system.cpu.toL2Bus.data_through_bus 265203840 # Total data (bytes) 590system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 591system.cpu.toL2Bus.reqLayer0.occupancy 4138084500 # Layer occupancy (ticks) 592system.cpu.toL2Bus.reqLayer0.utilization 6.4 # Layer utilization (%) 593system.cpu.toL2Bus.respLayer0.occupancy 1694000 # Layer occupancy (ticks) 594system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 595system.cpu.toL2Bus.respLayer1.occupancy 3121568749 # Layer occupancy (ticks) 596system.cpu.toL2Bus.respLayer1.utilization 4.9 # Layer utilization (%) 597system.cpu.icache.tags.replacements 56 # number of replacements 598system.cpu.icache.tags.tagsinuse 820.274669 # Cycle average of tags in use 599system.cpu.icache.tags.total_refs 26331871 # Total number of references to valid blocks. 600system.cpu.icache.tags.sampled_refs 1017 # Sample count of references to valid blocks. 601system.cpu.icache.tags.avg_refs 25891.711898 # Average number of references to valid blocks. 602system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 603system.cpu.icache.tags.occ_blocks::cpu.inst 820.274669 # Average occupied blocks per requestor 604system.cpu.icache.tags.occ_percent::cpu.inst 0.400525 # Average percentage of cache occupancy 605system.cpu.icache.tags.occ_percent::total 0.400525 # Average percentage of cache occupancy 606system.cpu.icache.tags.occ_task_id_blocks::1024 961 # Occupied blocks per task id 607system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 608system.cpu.icache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id 609system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 610system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id 611system.cpu.icache.tags.occ_task_id_percent::1024 0.469238 # Percentage of cache occupancy per task id 612system.cpu.icache.tags.tag_accesses 52667377 # Number of tag accesses 613system.cpu.icache.tags.data_accesses 52667377 # Number of data accesses 614system.cpu.icache.ReadReq_hits::cpu.inst 26331871 # number of ReadReq hits 615system.cpu.icache.ReadReq_hits::total 26331871 # number of ReadReq hits 616system.cpu.icache.demand_hits::cpu.inst 26331871 # number of demand (read+write) hits 617system.cpu.icache.demand_hits::total 26331871 # number of demand (read+write) hits 618system.cpu.icache.overall_hits::cpu.inst 26331871 # number of overall hits 619system.cpu.icache.overall_hits::total 26331871 # number of overall hits 620system.cpu.icache.ReadReq_misses::cpu.inst 1309 # number of ReadReq misses 621system.cpu.icache.ReadReq_misses::total 1309 # number of ReadReq misses 622system.cpu.icache.demand_misses::cpu.inst 1309 # number of demand (read+write) misses 623system.cpu.icache.demand_misses::total 1309 # number of demand (read+write) misses 624system.cpu.icache.overall_misses::cpu.inst 1309 # number of overall misses 625system.cpu.icache.overall_misses::total 1309 # number of overall misses 626system.cpu.icache.ReadReq_miss_latency::cpu.inst 89709250 # number of ReadReq miss cycles 627system.cpu.icache.ReadReq_miss_latency::total 89709250 # number of ReadReq miss cycles 628system.cpu.icache.demand_miss_latency::cpu.inst 89709250 # number of demand (read+write) miss cycles 629system.cpu.icache.demand_miss_latency::total 89709250 # number of demand (read+write) miss cycles 630system.cpu.icache.overall_miss_latency::cpu.inst 89709250 # number of overall miss cycles 631system.cpu.icache.overall_miss_latency::total 89709250 # number of overall miss cycles 632system.cpu.icache.ReadReq_accesses::cpu.inst 26333180 # number of ReadReq accesses(hits+misses) 633system.cpu.icache.ReadReq_accesses::total 26333180 # number of ReadReq accesses(hits+misses) 634system.cpu.icache.demand_accesses::cpu.inst 26333180 # number of demand (read+write) accesses 635system.cpu.icache.demand_accesses::total 26333180 # number of demand (read+write) accesses 636system.cpu.icache.overall_accesses::cpu.inst 26333180 # number of overall (read+write) accesses 637system.cpu.icache.overall_accesses::total 26333180 # number of overall (read+write) accesses 638system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses 640system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses 641system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses 642system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses 643system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses 644system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68532.658518 # average ReadReq miss latency 645system.cpu.icache.ReadReq_avg_miss_latency::total 68532.658518 # average ReadReq miss latency 646system.cpu.icache.demand_avg_miss_latency::cpu.inst 68532.658518 # average overall miss latency 647system.cpu.icache.demand_avg_miss_latency::total 68532.658518 # average overall miss latency 648system.cpu.icache.overall_avg_miss_latency::cpu.inst 68532.658518 # average overall miss latency 649system.cpu.icache.overall_avg_miss_latency::total 68532.658518 # average overall miss latency 650system.cpu.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked 651system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 652system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 653system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 654system.cpu.icache.avg_blocked_cycles::no_mshrs 39 # average number of cycles each access was blocked 655system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 656system.cpu.icache.fast_writes 0 # number of fast writes performed 657system.cpu.icache.cache_copies 0 # number of cache copies performed 658system.cpu.icache.ReadReq_mshr_hits::cpu.inst 292 # number of ReadReq MSHR hits 659system.cpu.icache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits 660system.cpu.icache.demand_mshr_hits::cpu.inst 292 # number of demand (read+write) MSHR hits 661system.cpu.icache.demand_mshr_hits::total 292 # number of demand (read+write) MSHR hits 662system.cpu.icache.overall_mshr_hits::cpu.inst 292 # number of overall MSHR hits 663system.cpu.icache.overall_mshr_hits::total 292 # number of overall MSHR hits 664system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1017 # number of ReadReq MSHR misses 665system.cpu.icache.ReadReq_mshr_misses::total 1017 # number of ReadReq MSHR misses 666system.cpu.icache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses 667system.cpu.icache.demand_mshr_misses::total 1017 # number of demand (read+write) MSHR misses 668system.cpu.icache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses 669system.cpu.icache.overall_mshr_misses::total 1017 # number of overall MSHR misses 670system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70297000 # number of ReadReq MSHR miss cycles 671system.cpu.icache.ReadReq_mshr_miss_latency::total 70297000 # number of ReadReq MSHR miss cycles 672system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70297000 # number of demand (read+write) MSHR miss cycles 673system.cpu.icache.demand_mshr_miss_latency::total 70297000 # number of demand (read+write) MSHR miss cycles 674system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70297000 # number of overall MSHR miss cycles 675system.cpu.icache.overall_mshr_miss_latency::total 70297000 # number of overall MSHR miss cycles 676system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses 677system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses 678system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses 679system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses 680system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses 681system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses 682system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69121.927237 # average ReadReq mshr miss latency 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69121.927237 # average ReadReq mshr miss latency 684system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69121.927237 # average overall mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::total 69121.927237 # average overall mshr miss latency 686system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69121.927237 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::total 69121.927237 # average overall mshr miss latency 688system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 689system.cpu.l2cache.tags.replacements 489 # number of replacements 690system.cpu.l2cache.tags.tagsinuse 20838.141939 # Cycle average of tags in use 691system.cpu.l2cache.tags.total_refs 4029004 # Total number of references to valid blocks. 692system.cpu.l2cache.tags.sampled_refs 30405 # Sample count of references to valid blocks. 693system.cpu.l2cache.tags.avg_refs 132.511232 # Average number of references to valid blocks. 694system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 695system.cpu.l2cache.tags.occ_blocks::writebacks 19919.361133 # Average occupied blocks per requestor 696system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.825750 # Average occupied blocks per requestor 697system.cpu.l2cache.tags.occ_blocks::cpu.data 250.955056 # Average occupied blocks per requestor 698system.cpu.l2cache.tags.occ_percent::writebacks 0.607891 # Average percentage of cache occupancy 699system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020380 # Average percentage of cache occupancy 700system.cpu.l2cache.tags.occ_percent::cpu.data 0.007659 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::total 0.635930 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_task_id_blocks::1024 29916 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::2 769 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1376 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27649 # Occupied blocks per task id 708system.cpu.l2cache.tags.occ_task_id_percent::1024 0.912964 # Percentage of cache occupancy per task id 709system.cpu.l2cache.tags.tag_accesses 33263174 # Number of tag accesses 710system.cpu.l2cache.tags.data_accesses 33263174 # Number of data accesses 711system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 712system.cpu.l2cache.ReadReq_hits::cpu.data 1993931 # number of ReadReq hits 713system.cpu.l2cache.ReadReq_hits::total 1993948 # number of ReadReq hits 714system.cpu.l2cache.Writeback_hits::writebacks 2066178 # number of Writeback hits 715system.cpu.l2cache.Writeback_hits::total 2066178 # number of Writeback hits 716system.cpu.l2cache.ReadExReq_hits::cpu.data 53263 # number of ReadExReq hits 717system.cpu.l2cache.ReadExReq_hits::total 53263 # number of ReadExReq hits 718system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 719system.cpu.l2cache.demand_hits::cpu.data 2047194 # number of demand (read+write) hits 720system.cpu.l2cache.demand_hits::total 2047211 # number of demand (read+write) hits 721system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 722system.cpu.l2cache.overall_hits::cpu.data 2047194 # number of overall hits 723system.cpu.l2cache.overall_hits::total 2047211 # number of overall hits 724system.cpu.l2cache.ReadReq_misses::cpu.inst 1000 # number of ReadReq misses 725system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses 726system.cpu.l2cache.ReadReq_misses::total 1422 # number of ReadReq misses 727system.cpu.l2cache.ReadExReq_misses::cpu.data 29002 # number of ReadExReq misses 728system.cpu.l2cache.ReadExReq_misses::total 29002 # number of ReadExReq misses 729system.cpu.l2cache.demand_misses::cpu.inst 1000 # number of demand (read+write) misses 730system.cpu.l2cache.demand_misses::cpu.data 29424 # number of demand (read+write) misses 731system.cpu.l2cache.demand_misses::total 30424 # number of demand (read+write) misses 732system.cpu.l2cache.overall_misses::cpu.inst 1000 # number of overall misses 733system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses 734system.cpu.l2cache.overall_misses::total 30424 # number of overall misses 735system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 69106000 # number of ReadReq miss cycles 736system.cpu.l2cache.ReadReq_miss_latency::cpu.data 29389750 # number of ReadReq miss cycles 737system.cpu.l2cache.ReadReq_miss_latency::total 98495750 # number of ReadReq miss cycles 738system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1891412500 # number of ReadExReq miss cycles 739system.cpu.l2cache.ReadExReq_miss_latency::total 1891412500 # number of ReadExReq miss cycles 740system.cpu.l2cache.demand_miss_latency::cpu.inst 69106000 # number of demand (read+write) miss cycles 741system.cpu.l2cache.demand_miss_latency::cpu.data 1920802250 # number of demand (read+write) miss cycles 742system.cpu.l2cache.demand_miss_latency::total 1989908250 # number of demand (read+write) miss cycles 743system.cpu.l2cache.overall_miss_latency::cpu.inst 69106000 # number of overall miss cycles 744system.cpu.l2cache.overall_miss_latency::cpu.data 1920802250 # number of overall miss cycles 745system.cpu.l2cache.overall_miss_latency::total 1989908250 # number of overall miss cycles 746system.cpu.l2cache.ReadReq_accesses::cpu.inst 1017 # number of ReadReq accesses(hits+misses) 747system.cpu.l2cache.ReadReq_accesses::cpu.data 1994353 # number of ReadReq accesses(hits+misses) 748system.cpu.l2cache.ReadReq_accesses::total 1995370 # number of ReadReq accesses(hits+misses) 749system.cpu.l2cache.Writeback_accesses::writebacks 2066178 # number of Writeback accesses(hits+misses) 750system.cpu.l2cache.Writeback_accesses::total 2066178 # number of Writeback accesses(hits+misses) 751system.cpu.l2cache.ReadExReq_accesses::cpu.data 82265 # number of ReadExReq accesses(hits+misses) 752system.cpu.l2cache.ReadExReq_accesses::total 82265 # number of ReadExReq accesses(hits+misses) 753system.cpu.l2cache.demand_accesses::cpu.inst 1017 # number of demand (read+write) accesses 754system.cpu.l2cache.demand_accesses::cpu.data 2076618 # number of demand (read+write) accesses 755system.cpu.l2cache.demand_accesses::total 2077635 # number of demand (read+write) accesses 756system.cpu.l2cache.overall_accesses::cpu.inst 1017 # number of overall (read+write) accesses 757system.cpu.l2cache.overall_accesses::cpu.data 2076618 # number of overall (read+write) accesses 758system.cpu.l2cache.overall_accesses::total 2077635 # number of overall (read+write) accesses 759system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983284 # miss rate for ReadReq accesses 760system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000212 # miss rate for ReadReq accesses 761system.cpu.l2cache.ReadReq_miss_rate::total 0.000713 # miss rate for ReadReq accesses 762system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352544 # miss rate for ReadExReq accesses 763system.cpu.l2cache.ReadExReq_miss_rate::total 0.352544 # miss rate for ReadExReq accesses 764system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983284 # miss rate for demand accesses 765system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses 766system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses 767system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983284 # miss rate for overall accesses 768system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses 769system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses 770system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106 # average ReadReq miss latency 771system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69643.957346 # average ReadReq miss latency 772system.cpu.l2cache.ReadReq_avg_miss_latency::total 69265.646976 # average ReadReq miss latency 773system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65216.622992 # average ReadExReq miss latency 774system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65216.622992 # average ReadExReq miss latency 775system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69106 # average overall miss latency 776system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65280.119970 # average overall miss latency 777system.cpu.l2cache.demand_avg_miss_latency::total 65405.872009 # average overall miss latency 778system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69106 # average overall miss latency 779system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65280.119970 # average overall miss latency 780system.cpu.l2cache.overall_avg_miss_latency::total 65405.872009 # average overall miss latency 781system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 782system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 783system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 784system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 785system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 786system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 787system.cpu.l2cache.fast_writes 0 # number of fast writes performed 788system.cpu.l2cache.cache_copies 0 # number of cache copies performed 789system.cpu.l2cache.writebacks::writebacks 171 # number of writebacks 790system.cpu.l2cache.writebacks::total 171 # number of writebacks 791system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1000 # number of ReadReq MSHR misses 792system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses 793system.cpu.l2cache.ReadReq_mshr_misses::total 1422 # number of ReadReq MSHR misses 794system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29002 # number of ReadExReq MSHR misses 795system.cpu.l2cache.ReadExReq_mshr_misses::total 29002 # number of ReadExReq MSHR misses 796system.cpu.l2cache.demand_mshr_misses::cpu.inst 1000 # number of demand (read+write) MSHR misses 797system.cpu.l2cache.demand_mshr_misses::cpu.data 29424 # number of demand (read+write) MSHR misses 798system.cpu.l2cache.demand_mshr_misses::total 30424 # number of demand (read+write) MSHR misses 799system.cpu.l2cache.overall_mshr_misses::cpu.inst 1000 # number of overall MSHR misses 800system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses 801system.cpu.l2cache.overall_mshr_misses::total 30424 # number of overall MSHR misses 802system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 56577000 # number of ReadReq MSHR miss cycles 803system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24214250 # number of ReadReq MSHR miss cycles 804system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80791250 # number of ReadReq MSHR miss cycles 805system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1526186500 # number of ReadExReq MSHR miss cycles 806system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1526186500 # number of ReadExReq MSHR miss cycles 807system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56577000 # number of demand (read+write) MSHR miss cycles 808system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1550400750 # number of demand (read+write) MSHR miss cycles 809system.cpu.l2cache.demand_mshr_miss_latency::total 1606977750 # number of demand (read+write) MSHR miss cycles 810system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56577000 # number of overall MSHR miss cycles 811system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1550400750 # number of overall MSHR miss cycles 812system.cpu.l2cache.overall_mshr_miss_latency::total 1606977750 # number of overall MSHR miss cycles 813system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for ReadReq accesses 814system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000212 # mshr miss rate for ReadReq accesses 815system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000713 # mshr miss rate for ReadReq accesses 816system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352544 # mshr miss rate for ReadExReq accesses 817system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352544 # mshr miss rate for ReadExReq accesses 818system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for demand accesses 819system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses 820system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses 821system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983284 # mshr miss rate for overall accesses 822system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses 823system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses 824system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577 # average ReadReq mshr miss latency 825system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57379.739336 # average ReadReq mshr miss latency 826system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56815.225035 # average ReadReq mshr miss latency 827system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52623.491483 # average ReadExReq mshr miss latency 828system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52623.491483 # average ReadExReq mshr miss latency 829system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56577 # average overall mshr miss latency 830system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52691.705750 # average overall mshr miss latency 831system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52819.410663 # average overall mshr miss latency 832system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56577 # average overall mshr miss latency 833system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52691.705750 # average overall mshr miss latency 834system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52819.410663 # average overall mshr miss latency 835system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 836system.cpu.dcache.tags.replacements 2072519 # number of replacements 837system.cpu.dcache.tags.tagsinuse 4069.536250 # Cycle average of tags in use 838system.cpu.dcache.tags.total_refs 69938402 # Total number of references to valid blocks. 839system.cpu.dcache.tags.sampled_refs 2076615 # Sample count of references to valid blocks. 840system.cpu.dcache.tags.avg_refs 33.679041 # Average number of references to valid blocks. 841system.cpu.dcache.tags.warmup_cycle 20171577250 # Cycle when the warmup percentage was hit. 842system.cpu.dcache.tags.occ_blocks::cpu.data 4069.536250 # Average occupied blocks per requestor 843system.cpu.dcache.tags.occ_percent::cpu.data 0.993539 # Average percentage of cache occupancy 844system.cpu.dcache.tags.occ_percent::total 0.993539 # Average percentage of cache occupancy 845system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 846system.cpu.dcache.tags.age_task_id_blocks_1024::0 595 # Occupied blocks per task id 847system.cpu.dcache.tags.age_task_id_blocks_1024::1 3363 # Occupied blocks per task id 848system.cpu.dcache.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id 849system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 850system.cpu.dcache.tags.tag_accesses 147464213 # Number of tag accesses 851system.cpu.dcache.tags.data_accesses 147464213 # Number of data accesses 852system.cpu.dcache.ReadReq_hits::cpu.data 38592969 # number of ReadReq hits 853system.cpu.dcache.ReadReq_hits::total 38592969 # number of ReadReq hits 854system.cpu.dcache.WriteReq_hits::cpu.data 31345433 # number of WriteReq hits 855system.cpu.dcache.WriteReq_hits::total 31345433 # number of WriteReq hits 856system.cpu.dcache.demand_hits::cpu.data 69938402 # number of demand (read+write) hits 857system.cpu.dcache.demand_hits::total 69938402 # number of demand (read+write) hits 858system.cpu.dcache.overall_hits::cpu.data 69938402 # number of overall hits 859system.cpu.dcache.overall_hits::total 69938402 # number of overall hits 860system.cpu.dcache.ReadReq_misses::cpu.data 2661078 # number of ReadReq misses 861system.cpu.dcache.ReadReq_misses::total 2661078 # number of ReadReq misses 862system.cpu.dcache.WriteReq_misses::cpu.data 94319 # number of WriteReq misses 863system.cpu.dcache.WriteReq_misses::total 94319 # number of WriteReq misses 864system.cpu.dcache.demand_misses::cpu.data 2755397 # number of demand (read+write) misses 865system.cpu.dcache.demand_misses::total 2755397 # number of demand (read+write) misses 866system.cpu.dcache.overall_misses::cpu.data 2755397 # number of overall misses 867system.cpu.dcache.overall_misses::total 2755397 # number of overall misses 868system.cpu.dcache.ReadReq_miss_latency::cpu.data 31651251499 # number of ReadReq miss cycles 869system.cpu.dcache.ReadReq_miss_latency::total 31651251499 # number of ReadReq miss cycles 870system.cpu.dcache.WriteReq_miss_latency::cpu.data 2775683247 # number of WriteReq miss cycles 871system.cpu.dcache.WriteReq_miss_latency::total 2775683247 # number of WriteReq miss cycles 872system.cpu.dcache.demand_miss_latency::cpu.data 34426934746 # number of demand (read+write) miss cycles 873system.cpu.dcache.demand_miss_latency::total 34426934746 # number of demand (read+write) miss cycles 874system.cpu.dcache.overall_miss_latency::cpu.data 34426934746 # number of overall miss cycles 875system.cpu.dcache.overall_miss_latency::total 34426934746 # number of overall miss cycles 876system.cpu.dcache.ReadReq_accesses::cpu.data 41254047 # number of ReadReq accesses(hits+misses) 877system.cpu.dcache.ReadReq_accesses::total 41254047 # number of ReadReq accesses(hits+misses) 878system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 879system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 880system.cpu.dcache.demand_accesses::cpu.data 72693799 # number of demand (read+write) accesses 881system.cpu.dcache.demand_accesses::total 72693799 # number of demand (read+write) accesses 882system.cpu.dcache.overall_accesses::cpu.data 72693799 # number of overall (read+write) accesses 883system.cpu.dcache.overall_accesses::total 72693799 # number of overall (read+write) accesses 884system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064505 # miss rate for ReadReq accesses 885system.cpu.dcache.ReadReq_miss_rate::total 0.064505 # miss rate for ReadReq accesses 886system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003000 # miss rate for WriteReq accesses 887system.cpu.dcache.WriteReq_miss_rate::total 0.003000 # miss rate for WriteReq accesses 888system.cpu.dcache.demand_miss_rate::cpu.data 0.037904 # miss rate for demand accesses 889system.cpu.dcache.demand_miss_rate::total 0.037904 # miss rate for demand accesses 890system.cpu.dcache.overall_miss_rate::cpu.data 0.037904 # miss rate for overall accesses 891system.cpu.dcache.overall_miss_rate::total 0.037904 # miss rate for overall accesses 892system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11894.146470 # average ReadReq miss latency 893system.cpu.dcache.ReadReq_avg_miss_latency::total 11894.146470 # average ReadReq miss latency 894system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29428.675527 # average WriteReq miss latency 895system.cpu.dcache.WriteReq_avg_miss_latency::total 29428.675527 # average WriteReq miss latency 896system.cpu.dcache.demand_avg_miss_latency::cpu.data 12494.364604 # average overall miss latency 897system.cpu.dcache.demand_avg_miss_latency::total 12494.364604 # average overall miss latency 898system.cpu.dcache.overall_avg_miss_latency::cpu.data 12494.364604 # average overall miss latency 899system.cpu.dcache.overall_avg_miss_latency::total 12494.364604 # average overall miss latency 900system.cpu.dcache.blocked_cycles::no_mshrs 86474 # number of cycles access was blocked 901system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 902system.cpu.dcache.blocked::no_mshrs 16255 # number of cycles access was blocked 903system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 904system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.319840 # average number of cycles each access was blocked 905system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 906system.cpu.dcache.fast_writes 0 # number of fast writes performed 907system.cpu.dcache.cache_copies 0 # number of cache copies performed 908system.cpu.dcache.writebacks::writebacks 2066178 # number of writebacks 909system.cpu.dcache.writebacks::total 2066178 # number of writebacks 910system.cpu.dcache.ReadReq_mshr_hits::cpu.data 666601 # number of ReadReq MSHR hits 911system.cpu.dcache.ReadReq_mshr_hits::total 666601 # number of ReadReq MSHR hits 912system.cpu.dcache.WriteReq_mshr_hits::cpu.data 12178 # number of WriteReq MSHR hits 913system.cpu.dcache.WriteReq_mshr_hits::total 12178 # number of WriteReq MSHR hits 914system.cpu.dcache.demand_mshr_hits::cpu.data 678779 # number of demand (read+write) MSHR hits 915system.cpu.dcache.demand_mshr_hits::total 678779 # number of demand (read+write) MSHR hits 916system.cpu.dcache.overall_mshr_hits::cpu.data 678779 # number of overall MSHR hits 917system.cpu.dcache.overall_mshr_hits::total 678779 # number of overall MSHR hits 918system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994477 # number of ReadReq MSHR misses 919system.cpu.dcache.ReadReq_mshr_misses::total 1994477 # number of ReadReq MSHR misses 920system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82141 # number of WriteReq MSHR misses 921system.cpu.dcache.WriteReq_mshr_misses::total 82141 # number of WriteReq MSHR misses 922system.cpu.dcache.demand_mshr_misses::cpu.data 2076618 # number of demand (read+write) MSHR misses 923system.cpu.dcache.demand_mshr_misses::total 2076618 # number of demand (read+write) MSHR misses 924system.cpu.dcache.overall_mshr_misses::cpu.data 2076618 # number of overall MSHR misses 925system.cpu.dcache.overall_mshr_misses::total 2076618 # number of overall MSHR misses 926system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21991461751 # number of ReadReq MSHR miss cycles 927system.cpu.dcache.ReadReq_mshr_miss_latency::total 21991461751 # number of ReadReq MSHR miss cycles 928system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2506217997 # number of WriteReq MSHR miss cycles 929system.cpu.dcache.WriteReq_mshr_miss_latency::total 2506217997 # number of WriteReq MSHR miss cycles 930system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24497679748 # number of demand (read+write) MSHR miss cycles 931system.cpu.dcache.demand_mshr_miss_latency::total 24497679748 # number of demand (read+write) MSHR miss cycles 932system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24497679748 # number of overall MSHR miss cycles 933system.cpu.dcache.overall_mshr_miss_latency::total 24497679748 # number of overall MSHR miss cycles 934system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048346 # mshr miss rate for ReadReq accesses 935system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048346 # mshr miss rate for ReadReq accesses 936system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002613 # mshr miss rate for WriteReq accesses 937system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002613 # mshr miss rate for WriteReq accesses 938system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028567 # mshr miss rate for demand accesses 939system.cpu.dcache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses 940system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028567 # mshr miss rate for overall accesses 941system.cpu.dcache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses 942system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11026.179671 # average ReadReq mshr miss latency 943system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11026.179671 # average ReadReq mshr miss latency 944system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30511.169781 # average WriteReq mshr miss latency 945system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30511.169781 # average WriteReq mshr miss latency 946system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11796.911973 # average overall mshr miss latency 947system.cpu.dcache.demand_avg_mshr_miss_latency::total 11796.911973 # average overall mshr miss latency 948system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11796.911973 # average overall mshr miss latency 949system.cpu.dcache.overall_avg_mshr_miss_latency::total 11796.911973 # average overall mshr miss latency 950system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 951 952---------- End Simulation Statistics ---------- 953