config.ini revision 9449:56610ab73040
12SN/A[root] 21762SN/Atype=Root 32SN/Achildren=system 42SN/Afull_system=false 52SN/Atime_sync_enable=false 62SN/Atime_sync_period=100000000000 72SN/Atime_sync_spin_threshold=100000000 82SN/A 92SN/A[system] 102SN/Atype=System 112SN/Achildren=cpu membus physmem 122SN/Aboot_osflags=a 132SN/Aclock=1000 142SN/Ainit_param=0 152SN/Akernel= 162SN/Aload_addr_mask=1099511627775 172SN/Amem_mode=timing 182SN/Amem_ranges= 192SN/Amemories=system.physmem 202SN/Anum_work_ids=16 212SN/Areadfile= 222SN/Asymbolfile= 232SN/Awork_begin_ckpt_count=0 242SN/Awork_begin_cpu_id_exit=-1 252SN/Awork_begin_exit_count=0 262SN/Awork_cpus_ckpt_count=0 272665Ssaidi@eecs.umich.eduwork_end_ckpt_count=0 282665Ssaidi@eecs.umich.eduwork_end_exit_count=0 292665Ssaidi@eecs.umich.eduwork_item_id=-1 302665Ssaidi@eecs.umich.edusystem_port=system.membus.slave[0] 312665Ssaidi@eecs.umich.edu 322SN/A[system.cpu] 332SN/Atype=DerivO3CPU 342SN/Achildren=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 352SN/ABTBEntries=4096 3656SN/ABTBTagSize=16 371717SN/ALFSTSize=1024 382518SN/ALQEntries=32 3956SN/ALSQCheckLoads=true 404776Sgblack@eecs.umich.eduLSQDepCheckShift=4 414762Snate@binkert.orgRASSize=16 423065Sgblack@eecs.umich.eduSQEntries=32 432SN/ASSITSize=1024 442973Sgblack@eecs.umich.eduactivity=0 452SN/AbackComSize=5 463506Ssaidi@eecs.umich.educachePorts=200 474054Sbinkertn@umich.educhecker=Null 484054Sbinkertn@umich.educhoiceCtrBits=2 495866Sksewell@umich.educhoicePredictorSize=8192 505866Sksewell@umich.educlock=500 515866Sksewell@umich.educommitToDecodeDelay=1 525866Sksewell@umich.educommitToFetchDelay=1 535866Sksewell@umich.educommitToIEWDelay=1 545866Sksewell@umich.educommitToRenameDelay=1 555784Sgblack@eecs.umich.educommitWidth=8 564054Sbinkertn@umich.educpu_id=0 574776Sgblack@eecs.umich.edudecodeToFetchDelay=1 584054Sbinkertn@umich.edudecodeToRenameDelay=1 594776Sgblack@eecs.umich.edudecodeWidth=8 605866Sksewell@umich.edudispatchWidth=8 614054Sbinkertn@umich.edudo_checkpoint_insts=true 624776Sgblack@eecs.umich.edudo_quiesce=true 634054Sbinkertn@umich.edudo_statistics_insts=true 644776Sgblack@eecs.umich.edudtb=system.cpu.dtb 654776Sgblack@eecs.umich.edufetchToDecodeDelay=1 664054Sbinkertn@umich.edufetchTrapLatency=1 674776Sgblack@eecs.umich.edufetchWidth=8 685715Shsul@eecs.umich.eduforwardComSize=5 694776Sgblack@eecs.umich.edufuPool=system.cpu.fuPool 704776Sgblack@eecs.umich.edufunction_trace=false 714776Sgblack@eecs.umich.edufunction_trace_start=0 724776Sgblack@eecs.umich.eduglobalCtrBits=2 734776Sgblack@eecs.umich.eduglobalHistoryBits=13 745947Sgblack@eecs.umich.eduglobalPredictorSize=8192 755947Sgblack@eecs.umich.eduiewToCommitDelay=1 765947Sgblack@eecs.umich.eduiewToDecodeDelay=1 774776Sgblack@eecs.umich.eduiewToFetchDelay=1 784776Sgblack@eecs.umich.eduiewToRenameDelay=1 794776Sgblack@eecs.umich.eduinstShiftAmt=2 805784Sgblack@eecs.umich.eduinterrupts=system.cpu.interrupts 814776Sgblack@eecs.umich.eduisa=system.cpu.isa 824776Sgblack@eecs.umich.eduissueToExecuteDelay=1 835784Sgblack@eecs.umich.eduissueWidth=8 844776Sgblack@eecs.umich.eduitb=system.cpu.itb 854776Sgblack@eecs.umich.edulocalCtrBits=2 865784Sgblack@eecs.umich.edulocalHistoryBits=11 875784Sgblack@eecs.umich.edulocalHistoryTableSize=2048 885784Sgblack@eecs.umich.edulocalPredictorSize=2048 895784Sgblack@eecs.umich.edumax_insts_all_threads=0 905784Sgblack@eecs.umich.edumax_insts_any_thread=0 915784Sgblack@eecs.umich.edumax_loads_all_threads=0 925784Sgblack@eecs.umich.edumax_loads_any_thread=0 935784Sgblack@eecs.umich.eduneedsTSO=true 944776Sgblack@eecs.umich.edunumIQEntries=64 954776Sgblack@eecs.umich.edunumPhysFloatRegs=256 964776Sgblack@eecs.umich.edunumPhysIntRegs=256 974776Sgblack@eecs.umich.edunumROBEntries=192 984776Sgblack@eecs.umich.edunumRobs=1 995784Sgblack@eecs.umich.edunumThreads=1 1004776Sgblack@eecs.umich.edupredType=tournament 1015784Sgblack@eecs.umich.eduprofile=0 1025784Sgblack@eecs.umich.eduprogress_interval=0 1035784Sgblack@eecs.umich.edurenameToDecodeDelay=1 1045784Sgblack@eecs.umich.edurenameToFetchDelay=1 1055784Sgblack@eecs.umich.edurenameToIEWDelay=2 1065784Sgblack@eecs.umich.edurenameToROBDelay=1 1075784Sgblack@eecs.umich.edurenameWidth=8 1085784Sgblack@eecs.umich.edusmtCommitPolicy=RoundRobin 1095784Sgblack@eecs.umich.edusmtFetchPolicy=SingleThread 1105784Sgblack@eecs.umich.edusmtIQPolicy=Partitioned 1115784Sgblack@eecs.umich.edusmtIQThreshold=100 1125784Sgblack@eecs.umich.edusmtLSQPolicy=Partitioned 1135784Sgblack@eecs.umich.edusmtLSQThreshold=100 1145784Sgblack@eecs.umich.edusmtNumFetchingThreads=1 1155784Sgblack@eecs.umich.edusmtROBPolicy=Partitioned 1165784Sgblack@eecs.umich.edusmtROBThreshold=100 1175784Sgblack@eecs.umich.edusquashWidth=8 1185784Sgblack@eecs.umich.edustore_set_clear_period=250000 1195784Sgblack@eecs.umich.eduswitched_out=false 1204776Sgblack@eecs.umich.edusystem=system 1214776Sgblack@eecs.umich.edutracer=system.cpu.tracer 1224776Sgblack@eecs.umich.edutrapLatency=13 1234776Sgblack@eecs.umich.eduwbDepth=1 1244776Sgblack@eecs.umich.eduwbWidth=8 1254776Sgblack@eecs.umich.eduworkload=system.cpu.workload 1263506Ssaidi@eecs.umich.edudcache_port=system.cpu.dcache.cpu_side 1273506Ssaidi@eecs.umich.eduicache_port=system.cpu.icache.cpu_side 1285784Sgblack@eecs.umich.edu 1295784Sgblack@eecs.umich.edu[system.cpu.dcache] 1305784Sgblack@eecs.umich.edutype=BaseCache 1315784Sgblack@eecs.umich.eduaddr_ranges=0:18446744073709551615 1325784Sgblack@eecs.umich.eduassoc=2 1335784Sgblack@eecs.umich.edublock_size=64 1345784Sgblack@eecs.umich.educlock=500 1355784Sgblack@eecs.umich.eduforward_snoops=true 1365784Sgblack@eecs.umich.eduhit_latency=2 1375784Sgblack@eecs.umich.eduis_top_level=true 1385784Sgblack@eecs.umich.edumax_miss_count=0 1395784Sgblack@eecs.umich.edumshrs=4 1405791Srstrong@cs.ucsd.eduprefetch_on_access=false 1415784Sgblack@eecs.umich.eduprefetcher=Null 1425784Sgblack@eecs.umich.eduresponse_latency=2 1435791Srstrong@cs.ucsd.edusize=262144 1445784Sgblack@eecs.umich.edusystem=system 1455784Sgblack@eecs.umich.edutgts_per_mshr=20 1465784Sgblack@eecs.umich.edutwo_queue=false 1475784Sgblack@eecs.umich.eduwrite_buffers=8 1485784Sgblack@eecs.umich.educpu_side=system.cpu.dcache_port 1495784Sgblack@eecs.umich.edumem_side=system.cpu.toL2Bus.slave[1] 1505784Sgblack@eecs.umich.edu 1514776Sgblack@eecs.umich.edu[system.cpu.dtb] 1524776Sgblack@eecs.umich.edutype=X86TLB 1532SN/Achildren=walker 1542SN/Asize=64 1554776Sgblack@eecs.umich.eduwalker=system.cpu.dtb.walker 1562SN/A 1574776Sgblack@eecs.umich.edu[system.cpu.dtb.walker] 1584776Sgblack@eecs.umich.edutype=X86PagetableWalker 1593748Sgblack@eecs.umich.educlock=500 1605034Smilesck@eecs.umich.edusystem=system 1614776Sgblack@eecs.umich.eduport=system.cpu.toL2Bus.slave[3] 162 163[system.cpu.fuPool] 164type=FUPool 165children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 166FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 167 168[system.cpu.fuPool.FUList0] 169type=FUDesc 170children=opList 171count=6 172opList=system.cpu.fuPool.FUList0.opList 173 174[system.cpu.fuPool.FUList0.opList] 175type=OpDesc 176issueLat=1 177opClass=IntAlu 178opLat=1 179 180[system.cpu.fuPool.FUList1] 181type=FUDesc 182children=opList0 opList1 183count=2 184opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 185 186[system.cpu.fuPool.FUList1.opList0] 187type=OpDesc 188issueLat=1 189opClass=IntMult 190opLat=3 191 192[system.cpu.fuPool.FUList1.opList1] 193type=OpDesc 194issueLat=19 195opClass=IntDiv 196opLat=20 197 198[system.cpu.fuPool.FUList2] 199type=FUDesc 200children=opList0 opList1 opList2 201count=4 202opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 203 204[system.cpu.fuPool.FUList2.opList0] 205type=OpDesc 206issueLat=1 207opClass=FloatAdd 208opLat=2 209 210[system.cpu.fuPool.FUList2.opList1] 211type=OpDesc 212issueLat=1 213opClass=FloatCmp 214opLat=2 215 216[system.cpu.fuPool.FUList2.opList2] 217type=OpDesc 218issueLat=1 219opClass=FloatCvt 220opLat=2 221 222[system.cpu.fuPool.FUList3] 223type=FUDesc 224children=opList0 opList1 opList2 225count=2 226opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 227 228[system.cpu.fuPool.FUList3.opList0] 229type=OpDesc 230issueLat=1 231opClass=FloatMult 232opLat=4 233 234[system.cpu.fuPool.FUList3.opList1] 235type=OpDesc 236issueLat=12 237opClass=FloatDiv 238opLat=12 239 240[system.cpu.fuPool.FUList3.opList2] 241type=OpDesc 242issueLat=24 243opClass=FloatSqrt 244opLat=24 245 246[system.cpu.fuPool.FUList4] 247type=FUDesc 248children=opList 249count=0 250opList=system.cpu.fuPool.FUList4.opList 251 252[system.cpu.fuPool.FUList4.opList] 253type=OpDesc 254issueLat=1 255opClass=MemRead 256opLat=1 257 258[system.cpu.fuPool.FUList5] 259type=FUDesc 260children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 261count=4 262opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 263 264[system.cpu.fuPool.FUList5.opList00] 265type=OpDesc 266issueLat=1 267opClass=SimdAdd 268opLat=1 269 270[system.cpu.fuPool.FUList5.opList01] 271type=OpDesc 272issueLat=1 273opClass=SimdAddAcc 274opLat=1 275 276[system.cpu.fuPool.FUList5.opList02] 277type=OpDesc 278issueLat=1 279opClass=SimdAlu 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList03] 283type=OpDesc 284issueLat=1 285opClass=SimdCmp 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList04] 289type=OpDesc 290issueLat=1 291opClass=SimdCvt 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList05] 295type=OpDesc 296issueLat=1 297opClass=SimdMisc 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList06] 301type=OpDesc 302issueLat=1 303opClass=SimdMult 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList07] 307type=OpDesc 308issueLat=1 309opClass=SimdMultAcc 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList08] 313type=OpDesc 314issueLat=1 315opClass=SimdShift 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList09] 319type=OpDesc 320issueLat=1 321opClass=SimdShiftAcc 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList10] 325type=OpDesc 326issueLat=1 327opClass=SimdSqrt 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList11] 331type=OpDesc 332issueLat=1 333opClass=SimdFloatAdd 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList12] 337type=OpDesc 338issueLat=1 339opClass=SimdFloatAlu 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList13] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatCmp 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList14] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatCvt 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList15] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatDiv 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList16] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatMisc 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList17] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatMult 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList18] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatMultAcc 376opLat=1 377 378[system.cpu.fuPool.FUList5.opList19] 379type=OpDesc 380issueLat=1 381opClass=SimdFloatSqrt 382opLat=1 383 384[system.cpu.fuPool.FUList6] 385type=FUDesc 386children=opList 387count=0 388opList=system.cpu.fuPool.FUList6.opList 389 390[system.cpu.fuPool.FUList6.opList] 391type=OpDesc 392issueLat=1 393opClass=MemWrite 394opLat=1 395 396[system.cpu.fuPool.FUList7] 397type=FUDesc 398children=opList0 opList1 399count=4 400opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 401 402[system.cpu.fuPool.FUList7.opList0] 403type=OpDesc 404issueLat=1 405opClass=MemRead 406opLat=1 407 408[system.cpu.fuPool.FUList7.opList1] 409type=OpDesc 410issueLat=1 411opClass=MemWrite 412opLat=1 413 414[system.cpu.fuPool.FUList8] 415type=FUDesc 416children=opList 417count=1 418opList=system.cpu.fuPool.FUList8.opList 419 420[system.cpu.fuPool.FUList8.opList] 421type=OpDesc 422issueLat=3 423opClass=IprAccess 424opLat=3 425 426[system.cpu.icache] 427type=BaseCache 428addr_ranges=0:18446744073709551615 429assoc=2 430block_size=64 431clock=500 432forward_snoops=true 433hit_latency=2 434is_top_level=true 435max_miss_count=0 436mshrs=4 437prefetch_on_access=false 438prefetcher=Null 439response_latency=2 440size=131072 441system=system 442tgts_per_mshr=20 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port 446mem_side=system.cpu.toL2Bus.slave[0] 447 448[system.cpu.interrupts] 449type=X86LocalApic 450clock=500 451int_latency=1000 452pio_addr=2305843009213693952 453pio_latency=100000 454system=system 455int_master=system.membus.slave[2] 456int_slave=system.membus.master[2] 457pio=system.membus.master[1] 458 459[system.cpu.isa] 460type=X86ISA 461 462[system.cpu.itb] 463type=X86TLB 464children=walker 465size=64 466walker=system.cpu.itb.walker 467 468[system.cpu.itb.walker] 469type=X86PagetableWalker 470clock=500 471system=system 472port=system.cpu.toL2Bus.slave[2] 473 474[system.cpu.l2cache] 475type=BaseCache 476addr_ranges=0:18446744073709551615 477assoc=8 478block_size=64 479clock=500 480forward_snoops=true 481hit_latency=20 482is_top_level=false 483max_miss_count=0 484mshrs=20 485prefetch_on_access=false 486prefetcher=Null 487response_latency=20 488size=2097152 489system=system 490tgts_per_mshr=12 491two_queue=false 492write_buffers=8 493cpu_side=system.cpu.toL2Bus.master[0] 494mem_side=system.membus.slave[1] 495 496[system.cpu.toL2Bus] 497type=CoherentBus 498block_size=64 499clock=500 500header_cycles=1 501use_default_range=false 502width=32 503master=system.cpu.l2cache.cpu_side 504slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 505 506[system.cpu.tracer] 507type=ExeTracer 508 509[system.cpu.workload] 510type=LiveProcess 511cmd=mcf mcf.in 512cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing 513egid=100 514env= 515errout=cerr 516euid=100 517executable=/gem5/dist/cpu2000/binaries/x86/linux/mcf 518gid=100 519input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in 520max_stack_size=67108864 521output=cout 522pid=100 523ppid=99 524simpoint=55300000000 525system=system 526uid=100 527 528[system.membus] 529type=CoherentBus 530block_size=64 531clock=1000 532header_cycles=1 533use_default_range=false 534width=8 535master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave 536slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master 537 538[system.physmem] 539type=SimpleDRAM 540addr_mapping=openmap 541banks_per_rank=8 542clock=1000 543conf_table_reported=false 544in_addr_map=true 545lines_per_rowbuffer=64 546mem_sched_policy=fcfs 547null=false 548page_policy=open 549range=0:268435455 550ranks_per_channel=2 551read_buffer_size=32 552tBURST=4000 553tCL=14000 554tRCD=14000 555tREFI=7800000 556tRFC=300000 557tRP=14000 558tWTR=1000 559write_buffer_size=32 560write_thresh_perc=70 561zero=false 562port=system.membus.master[0] 563 564