stats.txt revision 9265:8fe936e937bd
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.028506 # Number of seconds simulated 4sim_ticks 28505597000 # Number of ticks simulated 5final_tick 28505597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 145688 # Simulator instruction rate (inst/s) 8host_op_rate 146734 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45838175 # Simulator tick rate (ticks/s) 10host_mem_usage 362080 # Number of bytes of host memory used 11host_seconds 621.87 # Real time elapsed on the host 12sim_insts 90599368 # Number of instructions simulated 13sim_ops 91249921 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 45568 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory 16system.physmem.bytes_read::total 993216 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 45568 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 45568 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 712 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15519 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1598563 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 33244278 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 34842842 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1598563 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1598563 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1598563 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 33244278 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 34842842 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 41system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 42system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 43system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 44system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 45system.cpu.dtb.read_accesses 0 # DTB read accesses 46system.cpu.dtb.write_accesses 0 # DTB write accesses 47system.cpu.dtb.inst_accesses 0 # ITB inst accesses 48system.cpu.dtb.hits 0 # DTB hits 49system.cpu.dtb.misses 0 # DTB misses 50system.cpu.dtb.accesses 0 # DTB accesses 51system.cpu.itb.inst_hits 0 # ITB inst hits 52system.cpu.itb.inst_misses 0 # ITB inst misses 53system.cpu.itb.read_hits 0 # DTB read hits 54system.cpu.itb.read_misses 0 # DTB read misses 55system.cpu.itb.write_hits 0 # DTB write hits 56system.cpu.itb.write_misses 0 # DTB write misses 57system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 442 # Number of system calls 73system.cpu.numCycles 57011195 # number of cpu cycles simulated 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.BPredUnit.lookups 27014403 # Number of BP lookups 77system.cpu.BPredUnit.condPredicted 22277078 # Number of conditional branches predicted 78system.cpu.BPredUnit.condIncorrect 889929 # Number of conditional branches incorrect 79system.cpu.BPredUnit.BTBLookups 11548760 # Number of BTB lookups 80system.cpu.BPredUnit.BTBHits 11430884 # Number of BTB hits 81system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 82system.cpu.BPredUnit.usedRAS 73122 # Number of times the RAS was used to get a target. 83system.cpu.BPredUnit.RASInCorrect 372 # Number of incorrect RAS predictions. 84system.cpu.fetch.icacheStallCycles 14508892 # Number of cycles fetch is stalled on an Icache miss 85system.cpu.fetch.Insts 129672886 # Number of instructions fetch has processed 86system.cpu.fetch.Branches 27014403 # Number of branches that fetch encountered 87system.cpu.fetch.predictedBranches 11504006 # Number of branches that fetch has predicted taken 88system.cpu.fetch.Cycles 24367767 # Number of cycles fetch has run and was not squashing or blocked 89system.cpu.fetch.SquashCycles 4991272 # Number of cycles fetch has spent squashing 90system.cpu.fetch.BlockedCycles 14021743 # Number of cycles fetch has spent blocked 91system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 92system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps 93system.cpu.fetch.CacheLines 14122126 # Number of cache lines fetched 94system.cpu.fetch.IcacheSquashes 347107 # Number of outstanding Icache misses that were squashed 95system.cpu.fetch.rateDist::samples 56945823 # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::mean 2.293943 # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::stdev 3.179113 # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::0 32616008 57.28% 57.28% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::1 3437208 6.04% 63.31% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::2 2033940 3.57% 66.88% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::3 1577922 2.77% 69.65% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::4 1684600 2.96% 72.61% # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::5 3016320 5.30% 77.91% # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::6 1478308 2.60% 80.51% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::7 1110359 1.95% 82.45% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::8 9991158 17.55% 100.00% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::total 56945823 # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.branchRate 0.473844 # Number of branch fetches per cycle 113system.cpu.fetch.rate 2.274516 # Number of inst fetches per cycle 114system.cpu.decode.IdleCycles 17727827 # Number of cycles decode is idle 115system.cpu.decode.BlockedCycles 11442534 # Number of cycles decode is blocked 116system.cpu.decode.RunCycles 22314035 # Number of cycles decode is running 117system.cpu.decode.UnblockCycles 1422886 # Number of cycles decode is unblocking 118system.cpu.decode.SquashCycles 4038541 # Number of cycles decode is squashing 119system.cpu.decode.BranchResolved 4486849 # Number of times decode resolved a branch 120system.cpu.decode.BranchMispred 8989 # Number of times decode detected a branch misprediction 121system.cpu.decode.DecodedInsts 127753929 # Number of instructions handled by decode 122system.cpu.decode.SquashedInsts 42812 # Number of squashed instructions handled by decode 123system.cpu.rename.SquashCycles 4038541 # Number of cycles rename is squashing 124system.cpu.rename.IdleCycles 19463622 # Number of cycles rename is idle 125system.cpu.rename.BlockCycles 5507295 # Number of cycles rename is blocking 126system.cpu.rename.serializeStallCycles 178125 # count of cycles rename stalled for serializing inst 127system.cpu.rename.RunCycles 21532560 # Number of cycles rename is running 128system.cpu.rename.UnblockCycles 6225680 # Number of cycles rename is unblocking 129system.cpu.rename.RenamedInsts 124585344 # Number of instructions processed by rename 130system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full 131system.cpu.rename.IQFullEvents 540744 # Number of times rename has blocked due to IQ full 132system.cpu.rename.LSQFullEvents 4833961 # Number of times rename has blocked due to LSQ full 133system.cpu.rename.FullRegisterEvents 11275 # Number of times there has been no free registers 134system.cpu.rename.RenamedOperands 145162652 # Number of destination operands rename has renamed 135system.cpu.rename.RenameLookups 542774349 # Number of register rename lookups that rename has made 136system.cpu.rename.int_rename_lookups 542766580 # Number of integer rename lookups 137system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups 138system.cpu.rename.CommittedMaps 107429498 # Number of HB maps that are committed 139system.cpu.rename.UndoneMaps 37733154 # Number of HB maps that are undone due to squashing 140system.cpu.rename.serializingInsts 6541 # count of serializing insts renamed 141system.cpu.rename.tempSerializingInsts 6539 # count of temporary serializing insts renamed 142system.cpu.rename.skidInsts 14204519 # count of insts added to the skid buffer 143system.cpu.memDep0.insertedLoads 29836795 # Number of loads inserted to the mem dependence unit. 144system.cpu.memDep0.insertedStores 5560829 # Number of stores inserted to the mem dependence unit. 145system.cpu.memDep0.conflictingLoads 2097523 # Number of conflicting loads. 146system.cpu.memDep0.conflictingStores 1243222 # Number of conflicting stores. 147system.cpu.iq.iqInstsAdded 119152184 # Number of instructions added to the IQ (excludes non-spec) 148system.cpu.iq.iqNonSpecInstsAdded 10385 # Number of non-speculative instructions added to the IQ 149system.cpu.iq.iqInstsIssued 105702713 # Number of instructions issued 150system.cpu.iq.iqSquashedInstsIssued 79311 # Number of squashed instructions issued 151system.cpu.iq.iqSquashedInstsExamined 27697349 # Number of squashed instructions iterated over during squash; mainly for profiling 152system.cpu.iq.iqSquashedOperandsExamined 68611569 # Number of squashed operands that are examined and possibly removed from graph 153system.cpu.iq.iqSquashedNonSpecRemoved 253 # Number of squashed non-spec instructions that were removed 154system.cpu.iq.issued_per_cycle::samples 56945823 # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::mean 1.856198 # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::stdev 1.856170 # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::0 17311609 30.40% 30.40% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::1 13029602 22.88% 53.28% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::2 8527913 14.98% 68.26% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::3 6948954 12.20% 80.46% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::4 5271164 9.26% 89.72% # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::5 2793517 4.91% 94.62% # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::6 2152448 3.78% 98.40% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::7 481434 0.85% 99.25% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::8 429182 0.75% 100.00% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::total 56945823 # Number of insts issued each cycle 171system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 172system.cpu.iq.fu_full::IntAlu 40477 6.05% 6.05% # attempts to use FU when none available 173system.cpu.iq.fu_full::IntMult 27 0.00% 6.06% # attempts to use FU when none available 174system.cpu.iq.fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available 175system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available 176system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available 177system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available 178system.cpu.iq.fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available 179system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available 180system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available 201system.cpu.iq.fu_full::MemRead 349114 52.21% 58.26% # attempts to use FU when none available 202system.cpu.iq.fu_full::MemWrite 279085 41.74% 100.00% # attempts to use FU when none available 203system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 204system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 205system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 206system.cpu.iq.FU_type_0::IntAlu 74715129 70.68% 70.68% # Type of FU issued 207system.cpu.iq.FU_type_0::IntMult 10969 0.01% 70.69% # Type of FU issued 208system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.69% # Type of FU issued 209system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.69% # Type of FU issued 210system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.69% # Type of FU issued 211system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.69% # Type of FU issued 212system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.69% # Type of FU issued 213system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.69% # Type of FU issued 214system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.69% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.69% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.69% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.69% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.69% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.69% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.69% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.69% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.69% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.69% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.69% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.69% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.69% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.69% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.69% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdFloatCvt 226 0.00% 70.69% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.69% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdFloatMisc 287 0.00% 70.70% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 70.70% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued 235system.cpu.iq.FU_type_0::MemRead 25832645 24.44% 95.13% # Type of FU issued 236system.cpu.iq.FU_type_0::MemWrite 5143450 4.87% 100.00% # Type of FU issued 237system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 238system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 239system.cpu.iq.FU_type_0::total 105702713 # Type of FU issued 240system.cpu.iq.rate 1.854069 # Inst issue rate 241system.cpu.iq.fu_busy_cnt 668703 # FU busy when requested 242system.cpu.iq.fu_busy_rate 0.006326 # FU busy rate (busy events/executed inst) 243system.cpu.iq.int_inst_queue_reads 269098152 # Number of integer instruction queue reads 244system.cpu.iq.int_inst_queue_writes 146861999 # Number of integer instruction queue writes 245system.cpu.iq.int_inst_queue_wakeup_accesses 102960296 # Number of integer instruction queue wakeup accesses 246system.cpu.iq.fp_inst_queue_reads 1111 # Number of floating instruction queue reads 247system.cpu.iq.fp_inst_queue_writes 1652 # Number of floating instruction queue writes 248system.cpu.iq.fp_inst_queue_wakeup_accesses 475 # Number of floating instruction queue wakeup accesses 249system.cpu.iq.int_alu_accesses 106370866 # Number of integer alu accesses 250system.cpu.iq.fp_alu_accesses 550 # Number of floating point alu accesses 251system.cpu.iew.lsq.thread0.forwLoads 430808 # Number of loads that had data forwarded from stores 252system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 253system.cpu.iew.lsq.thread0.squashedLoads 7260915 # Number of loads squashed 254system.cpu.iew.lsq.thread0.ignoredResponses 7599 # Number of memory responses ignored because the instruction is squashed 255system.cpu.iew.lsq.thread0.memOrderViolation 4486 # Number of memory ordering violations 256system.cpu.iew.lsq.thread0.squashedStores 814071 # Number of stores squashed 257system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 258system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 259system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled 260system.cpu.iew.lsq.thread0.cacheBlocked 165011 # Number of times an access to memory failed due to the cache being blocked 261system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 262system.cpu.iew.iewSquashCycles 4038541 # Number of cycles IEW is squashing 263system.cpu.iew.iewBlockCycles 891747 # Number of cycles IEW is blocking 264system.cpu.iew.iewUnblockCycles 116973 # Number of cycles IEW is unblocking 265system.cpu.iew.iewDispatchedInsts 119175285 # Number of instructions dispatched to IQ 266system.cpu.iew.iewDispSquashedInsts 342275 # Number of squashed instructions skipped by dispatch 267system.cpu.iew.iewDispLoadInsts 29836795 # Number of dispatched load instructions 268system.cpu.iew.iewDispStoreInsts 5560829 # Number of dispatched store instructions 269system.cpu.iew.iewDispNonSpecInsts 6480 # Number of dispatched non-speculative instructions 270system.cpu.iew.iewIQFullEvents 49074 # Number of times the IQ has become full, causing a stall 271system.cpu.iew.iewLSQFullEvents 15714 # Number of times the LSQ has become full, causing a stall 272system.cpu.iew.memOrderViolationEvents 4486 # Number of memory order violations 273system.cpu.iew.predictedTakenIncorrect 478618 # Number of branches that were predicted taken incorrectly 274system.cpu.iew.predictedNotTakenIncorrect 473981 # Number of branches that were predicted not taken incorrectly 275system.cpu.iew.branchMispredicts 952599 # Number of branch mispredicts detected at execute 276system.cpu.iew.iewExecutedInsts 104642381 # Number of executed instructions 277system.cpu.iew.iewExecLoadInsts 25500898 # Number of load instructions executed 278system.cpu.iew.iewExecSquashedInsts 1060332 # Number of squashed instructions skipped in execute 279system.cpu.iew.exec_swp 0 # number of swp insts executed 280system.cpu.iew.exec_nop 12716 # number of nop insts executed 281system.cpu.iew.exec_refs 30579562 # number of memory reference insts executed 282system.cpu.iew.exec_branches 21366362 # Number of branches executed 283system.cpu.iew.exec_stores 5078664 # Number of stores executed 284system.cpu.iew.exec_rate 1.835471 # Inst execution rate 285system.cpu.iew.wb_sent 103249709 # cumulative count of insts sent to commit 286system.cpu.iew.wb_count 102960771 # cumulative count of insts written-back 287system.cpu.iew.wb_producers 61941288 # num instructions producing a value 288system.cpu.iew.wb_consumers 102916553 # num instructions consuming a value 289system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 290system.cpu.iew.wb_rate 1.805975 # insts written-back per cycle 291system.cpu.iew.wb_fanout 0.601859 # average fanout of values written-back 292system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 293system.cpu.commit.commitSquashedInsts 27915285 # The number of squashed insts skipped by commit 294system.cpu.commit.commitNonSpecStalls 10132 # The number of times commit has been forced to stall to communicate backwards 295system.cpu.commit.branchMispredicts 881077 # The number of times a branch was mispredicted 296system.cpu.commit.committed_per_cycle::samples 52907283 # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::mean 1.724952 # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::stdev 2.476924 # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::0 22917585 43.32% 43.32% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::1 13525297 25.56% 68.88% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::2 4253401 8.04% 76.92% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::3 3602316 6.81% 83.73% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::4 1554565 2.94% 86.67% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::5 724715 1.37% 88.04% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::6 894547 1.69% 89.73% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::7 264490 0.50% 90.23% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::8 5170367 9.77% 100.00% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::total 52907283 # Number of insts commited each cycle 313system.cpu.commit.committedInsts 90611977 # Number of instructions committed 314system.cpu.commit.committedOps 91262530 # Number of ops (including micro ops) committed 315system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 316system.cpu.commit.refs 27322638 # Number of memory references committed 317system.cpu.commit.loads 22575880 # Number of loads committed 318system.cpu.commit.membars 3888 # Number of memory barriers committed 319system.cpu.commit.branches 18734218 # Number of branches committed 320system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 321system.cpu.commit.int_insts 72533330 # Number of committed integer instructions. 322system.cpu.commit.function_calls 56148 # Number of function calls committed. 323system.cpu.commit.bw_lim_events 5170367 # number cycles where commit BW limit reached 324system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 325system.cpu.rob.rob_reads 166908997 # The number of ROB reads 326system.cpu.rob.rob_writes 242415249 # The number of ROB writes 327system.cpu.timesIdled 17140 # Number of times that the entire CPU went into an idle state and unscheduled itself 328system.cpu.idleCycles 65372 # Total number of cycles that the CPU has spent unscheduled due to idling 329system.cpu.committedInsts 90599368 # Number of Instructions Simulated 330system.cpu.committedOps 91249921 # Number of Ops (including micro ops) Simulated 331system.cpu.committedInsts_total 90599368 # Number of Instructions Simulated 332system.cpu.cpi 0.629267 # CPI: Cycles Per Instruction 333system.cpu.cpi_total 0.629267 # CPI: Total CPI of All Threads 334system.cpu.ipc 1.589150 # IPC: Instructions Per Cycle 335system.cpu.ipc_total 1.589150 # IPC: Total IPC of All Threads 336system.cpu.int_regfile_reads 497539806 # number of integer regfile reads 337system.cpu.int_regfile_writes 120848373 # number of integer regfile writes 338system.cpu.fp_regfile_reads 239 # number of floating regfile reads 339system.cpu.fp_regfile_writes 624 # number of floating regfile writes 340system.cpu.misc_regfile_reads 183493284 # number of misc regfile reads 341system.cpu.misc_regfile_writes 11612 # number of misc regfile writes 342system.cpu.icache.replacements 3 # number of replacements 343system.cpu.icache.tagsinuse 636.231301 # Cycle average of tags in use 344system.cpu.icache.total_refs 14121140 # Total number of references to valid blocks. 345system.cpu.icache.sampled_refs 738 # Sample count of references to valid blocks. 346system.cpu.icache.avg_refs 19134.336043 # Average number of references to valid blocks. 347system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 348system.cpu.icache.occ_blocks::cpu.inst 636.231301 # Average occupied blocks per requestor 349system.cpu.icache.occ_percent::cpu.inst 0.310660 # Average percentage of cache occupancy 350system.cpu.icache.occ_percent::total 0.310660 # Average percentage of cache occupancy 351system.cpu.icache.ReadReq_hits::cpu.inst 14121140 # number of ReadReq hits 352system.cpu.icache.ReadReq_hits::total 14121140 # number of ReadReq hits 353system.cpu.icache.demand_hits::cpu.inst 14121140 # number of demand (read+write) hits 354system.cpu.icache.demand_hits::total 14121140 # number of demand (read+write) hits 355system.cpu.icache.overall_hits::cpu.inst 14121140 # number of overall hits 356system.cpu.icache.overall_hits::total 14121140 # number of overall hits 357system.cpu.icache.ReadReq_misses::cpu.inst 986 # number of ReadReq misses 358system.cpu.icache.ReadReq_misses::total 986 # number of ReadReq misses 359system.cpu.icache.demand_misses::cpu.inst 986 # number of demand (read+write) misses 360system.cpu.icache.demand_misses::total 986 # number of demand (read+write) misses 361system.cpu.icache.overall_misses::cpu.inst 986 # number of overall misses 362system.cpu.icache.overall_misses::total 986 # number of overall misses 363system.cpu.icache.ReadReq_miss_latency::cpu.inst 35670500 # number of ReadReq miss cycles 364system.cpu.icache.ReadReq_miss_latency::total 35670500 # number of ReadReq miss cycles 365system.cpu.icache.demand_miss_latency::cpu.inst 35670500 # number of demand (read+write) miss cycles 366system.cpu.icache.demand_miss_latency::total 35670500 # number of demand (read+write) miss cycles 367system.cpu.icache.overall_miss_latency::cpu.inst 35670500 # number of overall miss cycles 368system.cpu.icache.overall_miss_latency::total 35670500 # number of overall miss cycles 369system.cpu.icache.ReadReq_accesses::cpu.inst 14122126 # number of ReadReq accesses(hits+misses) 370system.cpu.icache.ReadReq_accesses::total 14122126 # number of ReadReq accesses(hits+misses) 371system.cpu.icache.demand_accesses::cpu.inst 14122126 # number of demand (read+write) accesses 372system.cpu.icache.demand_accesses::total 14122126 # number of demand (read+write) accesses 373system.cpu.icache.overall_accesses::cpu.inst 14122126 # number of overall (read+write) accesses 374system.cpu.icache.overall_accesses::total 14122126 # number of overall (read+write) accesses 375system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses 376system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses 377system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses 378system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses 379system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses 380system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses 381system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36176.977688 # average ReadReq miss latency 382system.cpu.icache.ReadReq_avg_miss_latency::total 36176.977688 # average ReadReq miss latency 383system.cpu.icache.demand_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency 384system.cpu.icache.demand_avg_miss_latency::total 36176.977688 # average overall miss latency 385system.cpu.icache.overall_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency 386system.cpu.icache.overall_avg_miss_latency::total 36176.977688 # average overall miss latency 387system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 388system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 389system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 390system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 391system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 392system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 393system.cpu.icache.fast_writes 0 # number of fast writes performed 394system.cpu.icache.cache_copies 0 # number of cache copies performed 395system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits 396system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits 397system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits 398system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 399system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits 400system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits 401system.cpu.icache.ReadReq_mshr_misses::cpu.inst 738 # number of ReadReq MSHR misses 402system.cpu.icache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses 403system.cpu.icache.demand_mshr_misses::cpu.inst 738 # number of demand (read+write) MSHR misses 404system.cpu.icache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses 405system.cpu.icache.overall_mshr_misses::cpu.inst 738 # number of overall MSHR misses 406system.cpu.icache.overall_mshr_misses::total 738 # number of overall MSHR misses 407system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26658000 # number of ReadReq MSHR miss cycles 408system.cpu.icache.ReadReq_mshr_miss_latency::total 26658000 # number of ReadReq MSHR miss cycles 409system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26658000 # number of demand (read+write) MSHR miss cycles 410system.cpu.icache.demand_mshr_miss_latency::total 26658000 # number of demand (read+write) MSHR miss cycles 411system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26658000 # number of overall MSHR miss cycles 412system.cpu.icache.overall_mshr_miss_latency::total 26658000 # number of overall MSHR miss cycles 413system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses 414system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses 415system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses 416system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses 417system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses 418system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses 419system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36121.951220 # average ReadReq mshr miss latency 420system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36121.951220 # average ReadReq mshr miss latency 421system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency 422system.cpu.icache.demand_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency 423system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency 424system.cpu.icache.overall_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency 425system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 426system.cpu.dcache.replacements 943542 # number of replacements 427system.cpu.dcache.tagsinuse 3691.655008 # Cycle average of tags in use 428system.cpu.dcache.total_refs 28378395 # Total number of references to valid blocks. 429system.cpu.dcache.sampled_refs 947638 # Sample count of references to valid blocks. 430system.cpu.dcache.avg_refs 29.946451 # Average number of references to valid blocks. 431system.cpu.dcache.warmup_cycle 8118725000 # Cycle when the warmup percentage was hit. 432system.cpu.dcache.occ_blocks::cpu.data 3691.655008 # Average occupied blocks per requestor 433system.cpu.dcache.occ_percent::cpu.data 0.901283 # Average percentage of cache occupancy 434system.cpu.dcache.occ_percent::total 0.901283 # Average percentage of cache occupancy 435system.cpu.dcache.ReadReq_hits::cpu.data 23798260 # number of ReadReq hits 436system.cpu.dcache.ReadReq_hits::total 23798260 # number of ReadReq hits 437system.cpu.dcache.WriteReq_hits::cpu.data 4568472 # number of WriteReq hits 438system.cpu.dcache.WriteReq_hits::total 4568472 # number of WriteReq hits 439system.cpu.dcache.LoadLockedReq_hits::cpu.data 5862 # number of LoadLockedReq hits 440system.cpu.dcache.LoadLockedReq_hits::total 5862 # number of LoadLockedReq hits 441system.cpu.dcache.StoreCondReq_hits::cpu.data 5801 # number of StoreCondReq hits 442system.cpu.dcache.StoreCondReq_hits::total 5801 # number of StoreCondReq hits 443system.cpu.dcache.demand_hits::cpu.data 28366732 # number of demand (read+write) hits 444system.cpu.dcache.demand_hits::total 28366732 # number of demand (read+write) hits 445system.cpu.dcache.overall_hits::cpu.data 28366732 # number of overall hits 446system.cpu.dcache.overall_hits::total 28366732 # number of overall hits 447system.cpu.dcache.ReadReq_misses::cpu.data 1060889 # number of ReadReq misses 448system.cpu.dcache.ReadReq_misses::total 1060889 # number of ReadReq misses 449system.cpu.dcache.WriteReq_misses::cpu.data 166509 # number of WriteReq misses 450system.cpu.dcache.WriteReq_misses::total 166509 # number of WriteReq misses 451system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses 452system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses 453system.cpu.dcache.demand_misses::cpu.data 1227398 # number of demand (read+write) misses 454system.cpu.dcache.demand_misses::total 1227398 # number of demand (read+write) misses 455system.cpu.dcache.overall_misses::cpu.data 1227398 # number of overall misses 456system.cpu.dcache.overall_misses::total 1227398 # number of overall misses 457system.cpu.dcache.ReadReq_miss_latency::cpu.data 21973475500 # number of ReadReq miss cycles 458system.cpu.dcache.ReadReq_miss_latency::total 21973475500 # number of ReadReq miss cycles 459system.cpu.dcache.WriteReq_miss_latency::cpu.data 6211010261 # number of WriteReq miss cycles 460system.cpu.dcache.WriteReq_miss_latency::total 6211010261 # number of WriteReq miss cycles 461system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 161000 # number of LoadLockedReq miss cycles 462system.cpu.dcache.LoadLockedReq_miss_latency::total 161000 # number of LoadLockedReq miss cycles 463system.cpu.dcache.demand_miss_latency::cpu.data 28184485761 # number of demand (read+write) miss cycles 464system.cpu.dcache.demand_miss_latency::total 28184485761 # number of demand (read+write) miss cycles 465system.cpu.dcache.overall_miss_latency::cpu.data 28184485761 # number of overall miss cycles 466system.cpu.dcache.overall_miss_latency::total 28184485761 # number of overall miss cycles 467system.cpu.dcache.ReadReq_accesses::cpu.data 24859149 # number of ReadReq accesses(hits+misses) 468system.cpu.dcache.ReadReq_accesses::total 24859149 # number of ReadReq accesses(hits+misses) 469system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 470system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 471system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5870 # number of LoadLockedReq accesses(hits+misses) 472system.cpu.dcache.LoadLockedReq_accesses::total 5870 # number of LoadLockedReq accesses(hits+misses) 473system.cpu.dcache.StoreCondReq_accesses::cpu.data 5801 # number of StoreCondReq accesses(hits+misses) 474system.cpu.dcache.StoreCondReq_accesses::total 5801 # number of StoreCondReq accesses(hits+misses) 475system.cpu.dcache.demand_accesses::cpu.data 29594130 # number of demand (read+write) accesses 476system.cpu.dcache.demand_accesses::total 29594130 # number of demand (read+write) accesses 477system.cpu.dcache.overall_accesses::cpu.data 29594130 # number of overall (read+write) accesses 478system.cpu.dcache.overall_accesses::total 29594130 # number of overall (read+write) accesses 479system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042676 # miss rate for ReadReq accesses 480system.cpu.dcache.ReadReq_miss_rate::total 0.042676 # miss rate for ReadReq accesses 481system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.035166 # miss rate for WriteReq accesses 482system.cpu.dcache.WriteReq_miss_rate::total 0.035166 # miss rate for WriteReq accesses 483system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001363 # miss rate for LoadLockedReq accesses 484system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001363 # miss rate for LoadLockedReq accesses 485system.cpu.dcache.demand_miss_rate::cpu.data 0.041474 # miss rate for demand accesses 486system.cpu.dcache.demand_miss_rate::total 0.041474 # miss rate for demand accesses 487system.cpu.dcache.overall_miss_rate::cpu.data 0.041474 # miss rate for overall accesses 488system.cpu.dcache.overall_miss_rate::total 0.041474 # miss rate for overall accesses 489system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20712.322873 # average ReadReq miss latency 490system.cpu.dcache.ReadReq_avg_miss_latency::total 20712.322873 # average ReadReq miss latency 491system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37301.348642 # average WriteReq miss latency 492system.cpu.dcache.WriteReq_avg_miss_latency::total 37301.348642 # average WriteReq miss latency 493system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20125 # average LoadLockedReq miss latency 494system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20125 # average LoadLockedReq miss latency 495system.cpu.dcache.demand_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency 496system.cpu.dcache.demand_avg_miss_latency::total 22962.792640 # average overall miss latency 497system.cpu.dcache.overall_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency 498system.cpu.dcache.overall_avg_miss_latency::total 22962.792640 # average overall miss latency 499system.cpu.dcache.blocked_cycles::no_mshrs 78891432 # number of cycles access was blocked 500system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 501system.cpu.dcache.blocked::no_mshrs 9153 # number of cycles access was blocked 502system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 503system.cpu.dcache.avg_blocked_cycles::no_mshrs 8619.188463 # average number of cycles each access was blocked 504system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 505system.cpu.dcache.fast_writes 0 # number of fast writes performed 506system.cpu.dcache.cache_copies 0 # number of cache copies performed 507system.cpu.dcache.writebacks::writebacks 942894 # number of writebacks 508system.cpu.dcache.writebacks::total 942894 # number of writebacks 509system.cpu.dcache.ReadReq_mshr_hits::cpu.data 148366 # number of ReadReq MSHR hits 510system.cpu.dcache.ReadReq_mshr_hits::total 148366 # number of ReadReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131394 # number of WriteReq MSHR hits 512system.cpu.dcache.WriteReq_mshr_hits::total 131394 # number of WriteReq MSHR hits 513system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits 514system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits 515system.cpu.dcache.demand_mshr_hits::cpu.data 279760 # number of demand (read+write) MSHR hits 516system.cpu.dcache.demand_mshr_hits::total 279760 # number of demand (read+write) MSHR hits 517system.cpu.dcache.overall_mshr_hits::cpu.data 279760 # number of overall MSHR hits 518system.cpu.dcache.overall_mshr_hits::total 279760 # number of overall MSHR hits 519system.cpu.dcache.ReadReq_mshr_misses::cpu.data 912523 # number of ReadReq MSHR misses 520system.cpu.dcache.ReadReq_mshr_misses::total 912523 # number of ReadReq MSHR misses 521system.cpu.dcache.WriteReq_mshr_misses::cpu.data 35115 # number of WriteReq MSHR misses 522system.cpu.dcache.WriteReq_mshr_misses::total 35115 # number of WriteReq MSHR misses 523system.cpu.dcache.demand_mshr_misses::cpu.data 947638 # number of demand (read+write) MSHR misses 524system.cpu.dcache.demand_mshr_misses::total 947638 # number of demand (read+write) MSHR misses 525system.cpu.dcache.overall_mshr_misses::cpu.data 947638 # number of overall MSHR misses 526system.cpu.dcache.overall_mshr_misses::total 947638 # number of overall MSHR misses 527system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16758552000 # number of ReadReq MSHR miss cycles 528system.cpu.dcache.ReadReq_mshr_miss_latency::total 16758552000 # number of ReadReq MSHR miss cycles 529system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1752488893 # number of WriteReq MSHR miss cycles 530system.cpu.dcache.WriteReq_mshr_miss_latency::total 1752488893 # number of WriteReq MSHR miss cycles 531system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18511040893 # number of demand (read+write) MSHR miss cycles 532system.cpu.dcache.demand_mshr_miss_latency::total 18511040893 # number of demand (read+write) MSHR miss cycles 533system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18511040893 # number of overall MSHR miss cycles 534system.cpu.dcache.overall_mshr_miss_latency::total 18511040893 # number of overall MSHR miss cycles 535system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036708 # mshr miss rate for ReadReq accesses 536system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036708 # mshr miss rate for ReadReq accesses 537system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007416 # mshr miss rate for WriteReq accesses 538system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007416 # mshr miss rate for WriteReq accesses 539system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for demand accesses 540system.cpu.dcache.demand_mshr_miss_rate::total 0.032021 # mshr miss rate for demand accesses 541system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for overall accesses 542system.cpu.dcache.overall_mshr_miss_rate::total 0.032021 # mshr miss rate for overall accesses 543system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18365.073538 # average ReadReq mshr miss latency 544system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18365.073538 # average ReadReq mshr miss latency 545system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49907.130656 # average WriteReq mshr miss latency 546system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49907.130656 # average WriteReq mshr miss latency 547system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.873581 # average overall mshr miss latency 548system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.873581 # average overall mshr miss latency 549system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.873581 # average overall mshr miss latency 550system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.873581 # average overall mshr miss latency 551system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 552system.cpu.l2cache.replacements 0 # number of replacements 553system.cpu.l2cache.tagsinuse 10969.237336 # Cycle average of tags in use 554system.cpu.l2cache.total_refs 1839897 # Total number of references to valid blocks. 555system.cpu.l2cache.sampled_refs 15502 # Sample count of references to valid blocks. 556system.cpu.l2cache.avg_refs 118.687718 # Average number of references to valid blocks. 557system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 558system.cpu.l2cache.occ_blocks::writebacks 10112.492667 # Average occupied blocks per requestor 559system.cpu.l2cache.occ_blocks::cpu.inst 621.566782 # Average occupied blocks per requestor 560system.cpu.l2cache.occ_blocks::cpu.data 235.177887 # Average occupied blocks per requestor 561system.cpu.l2cache.occ_percent::writebacks 0.308609 # Average percentage of cache occupancy 562system.cpu.l2cache.occ_percent::cpu.inst 0.018969 # Average percentage of cache occupancy 563system.cpu.l2cache.occ_percent::cpu.data 0.007177 # Average percentage of cache occupancy 564system.cpu.l2cache.occ_percent::total 0.334755 # Average percentage of cache occupancy 565system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits 566system.cpu.l2cache.ReadReq_hits::cpu.data 912096 # number of ReadReq hits 567system.cpu.l2cache.ReadReq_hits::total 912120 # number of ReadReq hits 568system.cpu.l2cache.Writeback_hits::writebacks 942894 # number of Writeback hits 569system.cpu.l2cache.Writeback_hits::total 942894 # number of Writeback hits 570system.cpu.l2cache.ReadExReq_hits::cpu.data 20725 # number of ReadExReq hits 571system.cpu.l2cache.ReadExReq_hits::total 20725 # number of ReadExReq hits 572system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits 573system.cpu.l2cache.demand_hits::cpu.data 932821 # number of demand (read+write) hits 574system.cpu.l2cache.demand_hits::total 932845 # number of demand (read+write) hits 575system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits 576system.cpu.l2cache.overall_hits::cpu.data 932821 # number of overall hits 577system.cpu.l2cache.overall_hits::total 932845 # number of overall hits 578system.cpu.l2cache.ReadReq_misses::cpu.inst 714 # number of ReadReq misses 579system.cpu.l2cache.ReadReq_misses::cpu.data 282 # number of ReadReq misses 580system.cpu.l2cache.ReadReq_misses::total 996 # number of ReadReq misses 581system.cpu.l2cache.ReadExReq_misses::cpu.data 14535 # number of ReadExReq misses 582system.cpu.l2cache.ReadExReq_misses::total 14535 # number of ReadExReq misses 583system.cpu.l2cache.demand_misses::cpu.inst 714 # number of demand (read+write) misses 584system.cpu.l2cache.demand_misses::cpu.data 14817 # number of demand (read+write) misses 585system.cpu.l2cache.demand_misses::total 15531 # number of demand (read+write) misses 586system.cpu.l2cache.overall_misses::cpu.inst 714 # number of overall misses 587system.cpu.l2cache.overall_misses::cpu.data 14817 # number of overall misses 588system.cpu.l2cache.overall_misses::total 15531 # number of overall misses 589system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25532000 # number of ReadReq miss cycles 590system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10374000 # number of ReadReq miss cycles 591system.cpu.l2cache.ReadReq_miss_latency::total 35906000 # number of ReadReq miss cycles 592system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499788500 # number of ReadExReq miss cycles 593system.cpu.l2cache.ReadExReq_miss_latency::total 499788500 # number of ReadExReq miss cycles 594system.cpu.l2cache.demand_miss_latency::cpu.inst 25532000 # number of demand (read+write) miss cycles 595system.cpu.l2cache.demand_miss_latency::cpu.data 510162500 # number of demand (read+write) miss cycles 596system.cpu.l2cache.demand_miss_latency::total 535694500 # number of demand (read+write) miss cycles 597system.cpu.l2cache.overall_miss_latency::cpu.inst 25532000 # number of overall miss cycles 598system.cpu.l2cache.overall_miss_latency::cpu.data 510162500 # number of overall miss cycles 599system.cpu.l2cache.overall_miss_latency::total 535694500 # number of overall miss cycles 600system.cpu.l2cache.ReadReq_accesses::cpu.inst 738 # number of ReadReq accesses(hits+misses) 601system.cpu.l2cache.ReadReq_accesses::cpu.data 912378 # number of ReadReq accesses(hits+misses) 602system.cpu.l2cache.ReadReq_accesses::total 913116 # number of ReadReq accesses(hits+misses) 603system.cpu.l2cache.Writeback_accesses::writebacks 942894 # number of Writeback accesses(hits+misses) 604system.cpu.l2cache.Writeback_accesses::total 942894 # number of Writeback accesses(hits+misses) 605system.cpu.l2cache.ReadExReq_accesses::cpu.data 35260 # number of ReadExReq accesses(hits+misses) 606system.cpu.l2cache.ReadExReq_accesses::total 35260 # number of ReadExReq accesses(hits+misses) 607system.cpu.l2cache.demand_accesses::cpu.inst 738 # number of demand (read+write) accesses 608system.cpu.l2cache.demand_accesses::cpu.data 947638 # number of demand (read+write) accesses 609system.cpu.l2cache.demand_accesses::total 948376 # number of demand (read+write) accesses 610system.cpu.l2cache.overall_accesses::cpu.inst 738 # number of overall (read+write) accesses 611system.cpu.l2cache.overall_accesses::cpu.data 947638 # number of overall (read+write) accesses 612system.cpu.l2cache.overall_accesses::total 948376 # number of overall (read+write) accesses 613system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967480 # miss rate for ReadReq accesses 614system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses 615system.cpu.l2cache.ReadReq_miss_rate::total 0.001091 # miss rate for ReadReq accesses 616system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.412223 # miss rate for ReadExReq accesses 617system.cpu.l2cache.ReadExReq_miss_rate::total 0.412223 # miss rate for ReadExReq accesses 618system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967480 # miss rate for demand accesses 619system.cpu.l2cache.demand_miss_rate::cpu.data 0.015636 # miss rate for demand accesses 620system.cpu.l2cache.demand_miss_rate::total 0.016376 # miss rate for demand accesses 621system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967480 # miss rate for overall accesses 622system.cpu.l2cache.overall_miss_rate::cpu.data 0.015636 # miss rate for overall accesses 623system.cpu.l2cache.overall_miss_rate::total 0.016376 # miss rate for overall accesses 624system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35759.103641 # average ReadReq miss latency 625system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36787.234043 # average ReadReq miss latency 626system.cpu.l2cache.ReadReq_avg_miss_latency::total 36050.200803 # average ReadReq miss latency 627system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34385.173719 # average ReadExReq miss latency 628system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34385.173719 # average ReadExReq miss latency 629system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35759.103641 # average overall miss latency 630system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.890194 # average overall miss latency 631system.cpu.l2cache.demand_avg_miss_latency::total 34491.951581 # average overall miss latency 632system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35759.103641 # average overall miss latency 633system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.890194 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::total 34491.951581 # average overall miss latency 635system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 636system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 637system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 639system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 640system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 641system.cpu.l2cache.fast_writes 0 # number of fast writes performed 642system.cpu.l2cache.cache_copies 0 # number of cache copies performed 643system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 644system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits 645system.cpu.l2cache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits 646system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 647system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits 648system.cpu.l2cache.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits 649system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 650system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits 651system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits 652system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 712 # number of ReadReq MSHR misses 653system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272 # number of ReadReq MSHR misses 654system.cpu.l2cache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses 655system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14535 # number of ReadExReq MSHR misses 656system.cpu.l2cache.ReadExReq_mshr_misses::total 14535 # number of ReadExReq MSHR misses 657system.cpu.l2cache.demand_mshr_misses::cpu.inst 712 # number of demand (read+write) MSHR misses 658system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses 659system.cpu.l2cache.demand_mshr_misses::total 15519 # number of demand (read+write) MSHR misses 660system.cpu.l2cache.overall_mshr_misses::cpu.inst 712 # number of overall MSHR misses 661system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses 662system.cpu.l2cache.overall_mshr_misses::total 15519 # number of overall MSHR misses 663system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23240000 # number of ReadReq MSHR miss cycles 664system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9198500 # number of ReadReq MSHR miss cycles 665system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32438500 # number of ReadReq MSHR miss cycles 666system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 453435000 # number of ReadExReq MSHR miss cycles 667system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 453435000 # number of ReadExReq MSHR miss cycles 668system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23240000 # number of demand (read+write) MSHR miss cycles 669system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462633500 # number of demand (read+write) MSHR miss cycles 670system.cpu.l2cache.demand_mshr_miss_latency::total 485873500 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23240000 # number of overall MSHR miss cycles 672system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462633500 # number of overall MSHR miss cycles 673system.cpu.l2cache.overall_mshr_miss_latency::total 485873500 # number of overall MSHR miss cycles 674system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for ReadReq accesses 675system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses 676system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001078 # mshr miss rate for ReadReq accesses 677system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412223 # mshr miss rate for ReadExReq accesses 678system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412223 # mshr miss rate for ReadExReq accesses 679system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for demand accesses 680system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses 681system.cpu.l2cache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses 682system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for overall accesses 683system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses 684system.cpu.l2cache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses 685system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.449438 # average ReadReq mshr miss latency 686system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33818.014706 # average ReadReq mshr miss latency 687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32965.955285 # average ReadReq mshr miss latency 688system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.078431 # average ReadExReq mshr miss latency 689system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.078431 # average ReadExReq mshr miss latency 690system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency 691system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency 693system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency 694system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency 696system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 697 698---------- End Simulation Statistics ---------- 699