stats.txt revision 9079:9a244ebdc3c9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.025879 # Number of seconds simulated 4sim_ticks 25878583500 # Number of ticks simulated 5final_tick 25878583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 220420 # Simulator instruction rate (inst/s) 8host_op_rate 222002 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 62960153 # Simulator tick rate (ticks/s) 10host_mem_usage 367872 # Number of bytes of host memory used 11host_seconds 411.03 # Real time elapsed on the host 12sim_insts 90599358 # Number of instructions simulated 13sim_ops 91249911 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 45504 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 947456 # Number of bytes read from this memory 16system.physmem.bytes_read::total 992960 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 45504 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 45504 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 711 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 14804 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 15515 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1758365 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 36611587 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 38369952 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1758365 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1758365 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1758365 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 36611587 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 38369952 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 41system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 42system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 43system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 44system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 45system.cpu.dtb.read_accesses 0 # DTB read accesses 46system.cpu.dtb.write_accesses 0 # DTB write accesses 47system.cpu.dtb.inst_accesses 0 # ITB inst accesses 48system.cpu.dtb.hits 0 # DTB hits 49system.cpu.dtb.misses 0 # DTB misses 50system.cpu.dtb.accesses 0 # DTB accesses 51system.cpu.itb.inst_hits 0 # ITB inst hits 52system.cpu.itb.inst_misses 0 # ITB inst misses 53system.cpu.itb.read_hits 0 # DTB read hits 54system.cpu.itb.read_misses 0 # DTB read misses 55system.cpu.itb.write_hits 0 # DTB write hits 56system.cpu.itb.write_misses 0 # DTB write misses 57system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 442 # Number of system calls 73system.cpu.numCycles 51757168 # number of cpu cycles simulated 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.BPredUnit.lookups 26984015 # Number of BP lookups 77system.cpu.BPredUnit.condPredicted 22232491 # Number of conditional branches predicted 78system.cpu.BPredUnit.condIncorrect 888214 # Number of conditional branches incorrect 79system.cpu.BPredUnit.BTBLookups 11580024 # Number of BTB lookups 80system.cpu.BPredUnit.BTBHits 11447482 # Number of BTB hits 81system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 82system.cpu.BPredUnit.usedRAS 71474 # Number of times the RAS was used to get a target. 83system.cpu.BPredUnit.RASInCorrect 416 # Number of incorrect RAS predictions. 84system.cpu.fetch.icacheStallCycles 14414928 # Number of cycles fetch is stalled on an Icache miss 85system.cpu.fetch.Insts 129560918 # Number of instructions fetch has processed 86system.cpu.fetch.Branches 26984015 # Number of branches that fetch encountered 87system.cpu.fetch.predictedBranches 11518956 # Number of branches that fetch has predicted taken 88system.cpu.fetch.Cycles 24378433 # Number of cycles fetch has run and was not squashing or blocked 89system.cpu.fetch.SquashCycles 4928329 # Number of cycles fetch has spent squashing 90system.cpu.fetch.BlockedCycles 8911472 # Number of cycles fetch has spent blocked 91system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 92system.cpu.fetch.PendingTrapStallCycles 24 # Number of stall cycles due to pending traps 93system.cpu.fetch.CacheLines 14076190 # Number of cache lines fetched 94system.cpu.fetch.IcacheSquashes 379999 # Number of outstanding Icache misses that were squashed 95system.cpu.fetch.rateDist::samples 51715551 # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::mean 2.525564 # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::stdev 3.245999 # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::0 27375149 52.93% 52.93% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::1 3448740 6.67% 59.60% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::2 2025913 3.92% 63.52% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::3 1592010 3.08% 66.60% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::4 1693129 3.27% 69.87% # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::5 2969374 5.74% 75.61% # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::6 1533811 2.97% 78.58% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::7 1107315 2.14% 80.72% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::8 9970110 19.28% 100.00% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::total 51715551 # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.branchRate 0.521358 # Number of branch fetches per cycle 113system.cpu.fetch.rate 2.503246 # Number of inst fetches per cycle 114system.cpu.decode.IdleCycles 17151536 # Number of cycles decode is idle 115system.cpu.decode.BlockedCycles 6845661 # Number of cycles decode is blocked 116system.cpu.decode.RunCycles 22836822 # Number of cycles decode is running 117system.cpu.decode.UnblockCycles 879705 # Number of cycles decode is unblocking 118system.cpu.decode.SquashCycles 4001827 # Number of cycles decode is squashing 119system.cpu.decode.BranchResolved 4473928 # Number of times decode resolved a branch 120system.cpu.decode.BranchMispred 9005 # Number of times decode detected a branch misprediction 121system.cpu.decode.DecodedInsts 127743952 # Number of instructions handled by decode 122system.cpu.decode.SquashedInsts 42919 # Number of squashed instructions handled by decode 123system.cpu.rename.SquashCycles 4001827 # Number of cycles rename is squashing 124system.cpu.rename.IdleCycles 18918146 # Number of cycles rename is idle 125system.cpu.rename.BlockCycles 2041479 # Number of cycles rename is blocking 126system.cpu.rename.serializeStallCycles 194552 # count of cycles rename stalled for serializing inst 127system.cpu.rename.RunCycles 21908799 # Number of cycles rename is running 128system.cpu.rename.UnblockCycles 4650748 # Number of cycles rename is unblocking 129system.cpu.rename.RenamedInsts 124387508 # Number of instructions processed by rename 130system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full 131system.cpu.rename.IQFullEvents 285864 # Number of times rename has blocked due to IQ full 132system.cpu.rename.LSQFullEvents 3910791 # Number of times rename has blocked due to LSQ full 133system.cpu.rename.FullRegisterEvents 369 # Number of times there has been no free registers 134system.cpu.rename.RenamedOperands 145115578 # Number of destination operands rename has renamed 135system.cpu.rename.RenameLookups 541729246 # Number of register rename lookups that rename has made 136system.cpu.rename.int_rename_lookups 541723014 # Number of integer rename lookups 137system.cpu.rename.fp_rename_lookups 6232 # Number of floating rename lookups 138system.cpu.rename.CommittedMaps 107429482 # Number of HB maps that are committed 139system.cpu.rename.UndoneMaps 37686096 # Number of HB maps that are undone due to squashing 140system.cpu.rename.serializingInsts 18180 # count of serializing insts renamed 141system.cpu.rename.tempSerializingInsts 18178 # count of temporary serializing insts renamed 142system.cpu.rename.skidInsts 11273342 # count of insts added to the skid buffer 143system.cpu.memDep0.insertedLoads 29662115 # Number of loads inserted to the mem dependence unit. 144system.cpu.memDep0.insertedStores 5564551 # Number of stores inserted to the mem dependence unit. 145system.cpu.memDep0.conflictingLoads 2120620 # Number of conflicting loads. 146system.cpu.memDep0.conflictingStores 1233720 # Number of conflicting stores. 147system.cpu.iq.iqInstsAdded 118944023 # Number of instructions added to the IQ (excludes non-spec) 148system.cpu.iq.iqNonSpecInstsAdded 22020 # Number of non-speculative instructions added to the IQ 149system.cpu.iq.iqInstsIssued 105456921 # Number of instructions issued 150system.cpu.iq.iqSquashedInstsIssued 87203 # Number of squashed instructions issued 151system.cpu.iq.iqSquashedInstsExamined 27512358 # Number of squashed instructions iterated over during squash; mainly for profiling 152system.cpu.iq.iqSquashedOperandsExamined 68343356 # Number of squashed operands that are examined and possibly removed from graph 153system.cpu.iq.iqSquashedNonSpecRemoved 11890 # Number of squashed non-spec instructions that were removed 154system.cpu.iq.issued_per_cycle::samples 51715551 # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::mean 2.039172 # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::stdev 1.917652 # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::0 13904878 26.89% 26.89% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::1 11456546 22.15% 49.04% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::2 7969137 15.41% 64.45% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::3 6724396 13.00% 77.45% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::4 5314058 10.28% 87.73% # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::5 2865211 5.54% 93.27% # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::6 2534987 4.90% 98.17% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::7 474000 0.92% 99.09% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::8 472338 0.91% 100.00% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::total 51715551 # Number of insts issued each cycle 171system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 172system.cpu.iq.fu_full::IntAlu 33403 5.02% 5.02% # attempts to use FU when none available 173system.cpu.iq.fu_full::IntMult 27 0.00% 5.02% # attempts to use FU when none available 174system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available 175system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available 176system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available 177system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available 178system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available 179system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available 180system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available 201system.cpu.iq.fu_full::MemRead 354808 53.31% 58.33% # attempts to use FU when none available 202system.cpu.iq.fu_full::MemWrite 277311 41.67% 100.00% # attempts to use FU when none available 203system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 204system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 205system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 206system.cpu.iq.FU_type_0::IntAlu 74629419 70.77% 70.77% # Type of FU issued 207system.cpu.iq.FU_type_0::IntMult 10524 0.01% 70.78% # Type of FU issued 208system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued 209system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued 210system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued 211system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued 212system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued 213system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued 214system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.78% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdFloatCvt 188 0.00% 70.78% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdFloatMisc 232 0.00% 70.78% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued 235system.cpu.iq.FU_type_0::MemRead 25677872 24.35% 95.13% # Type of FU issued 236system.cpu.iq.FU_type_0::MemWrite 5138682 4.87% 100.00% # Type of FU issued 237system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 238system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 239system.cpu.iq.FU_type_0::total 105456921 # Type of FU issued 240system.cpu.iq.rate 2.037533 # Inst issue rate 241system.cpu.iq.fu_busy_cnt 665549 # FU busy when requested 242system.cpu.iq.fu_busy_rate 0.006311 # FU busy rate (busy events/executed inst) 243system.cpu.iq.int_inst_queue_reads 263381228 # Number of integer instruction queue reads 244system.cpu.iq.int_inst_queue_writes 146480266 # Number of integer instruction queue writes 245system.cpu.iq.int_inst_queue_wakeup_accesses 102833498 # Number of integer instruction queue wakeup accesses 246system.cpu.iq.fp_inst_queue_reads 917 # Number of floating instruction queue reads 247system.cpu.iq.fp_inst_queue_writes 1333 # Number of floating instruction queue writes 248system.cpu.iq.fp_inst_queue_wakeup_accesses 399 # Number of floating instruction queue wakeup accesses 249system.cpu.iq.int_alu_accesses 106122017 # Number of integer alu accesses 250system.cpu.iq.fp_alu_accesses 453 # Number of floating point alu accesses 251system.cpu.iew.lsq.thread0.forwLoads 424644 # Number of loads that had data forwarded from stores 252system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 253system.cpu.iew.lsq.thread0.squashedLoads 7086237 # Number of loads squashed 254system.cpu.iew.lsq.thread0.ignoredResponses 8981 # Number of memory responses ignored because the instruction is squashed 255system.cpu.iew.lsq.thread0.memOrderViolation 4129 # Number of memory ordering violations 256system.cpu.iew.lsq.thread0.squashedStores 817795 # Number of stores squashed 257system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 258system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 259system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled 260system.cpu.iew.lsq.thread0.cacheBlocked 39333 # Number of times an access to memory failed due to the cache being blocked 261system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 262system.cpu.iew.iewSquashCycles 4001827 # Number of cycles IEW is squashing 263system.cpu.iew.iewBlockCycles 198669 # Number of cycles IEW is blocking 264system.cpu.iew.iewUnblockCycles 33921 # Number of cycles IEW is unblocking 265system.cpu.iew.iewDispatchedInsts 119002430 # Number of instructions dispatched to IQ 266system.cpu.iew.iewDispSquashedInsts 339181 # Number of squashed instructions skipped by dispatch 267system.cpu.iew.iewDispLoadInsts 29662115 # Number of dispatched load instructions 268system.cpu.iew.iewDispStoreInsts 5564551 # Number of dispatched store instructions 269system.cpu.iew.iewDispNonSpecInsts 18117 # Number of dispatched non-speculative instructions 270system.cpu.iew.iewIQFullEvents 13618 # Number of times the IQ has become full, causing a stall 271system.cpu.iew.iewLSQFullEvents 1230 # Number of times the LSQ has become full, causing a stall 272system.cpu.iew.memOrderViolationEvents 4129 # Number of memory order violations 273system.cpu.iew.predictedTakenIncorrect 473445 # Number of branches that were predicted taken incorrectly 274system.cpu.iew.predictedNotTakenIncorrect 489320 # Number of branches that were predicted not taken incorrectly 275system.cpu.iew.branchMispredicts 962765 # Number of branch mispredicts detected at execute 276system.cpu.iew.iewExecutedInsts 104433557 # Number of executed instructions 277system.cpu.iew.iewExecLoadInsts 25350982 # Number of load instructions executed 278system.cpu.iew.iewExecSquashedInsts 1023364 # Number of squashed instructions skipped in execute 279system.cpu.iew.exec_swp 0 # number of swp insts executed 280system.cpu.iew.exec_nop 36387 # number of nop insts executed 281system.cpu.iew.exec_refs 30425523 # number of memory reference insts executed 282system.cpu.iew.exec_branches 21334984 # Number of branches executed 283system.cpu.iew.exec_stores 5074541 # Number of stores executed 284system.cpu.iew.exec_rate 2.017760 # Inst execution rate 285system.cpu.iew.wb_sent 103141450 # cumulative count of insts sent to commit 286system.cpu.iew.wb_count 102833897 # cumulative count of insts written-back 287system.cpu.iew.wb_producers 62142858 # num instructions producing a value 288system.cpu.iew.wb_consumers 103855994 # num instructions consuming a value 289system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 290system.cpu.iew.wb_rate 1.986853 # insts written-back per cycle 291system.cpu.iew.wb_fanout 0.598356 # average fanout of values written-back 292system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 293system.cpu.commit.commitCommittedInsts 90611967 # The number of committed instructions 294system.cpu.commit.commitCommittedOps 91262520 # The number of committed instructions 295system.cpu.commit.commitSquashedInsts 27741223 # The number of squashed insts skipped by commit 296system.cpu.commit.commitNonSpecStalls 10130 # The number of times commit has been forced to stall to communicate backwards 297system.cpu.commit.branchMispredicts 891236 # The number of times a branch was mispredicted 298system.cpu.commit.committed_per_cycle::samples 47713725 # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::mean 1.912710 # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::stdev 2.511102 # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::0 17393373 36.45% 36.45% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::1 13510296 28.32% 64.77% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::2 4501215 9.43% 74.20% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::3 3866271 8.10% 82.31% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::4 1517173 3.18% 85.49% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::5 785983 1.65% 87.13% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::6 854820 1.79% 88.92% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::7 253298 0.53% 89.46% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::8 5031296 10.54% 100.00% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::total 47713725 # Number of insts commited each cycle 315system.cpu.commit.committedInsts 90611967 # Number of instructions committed 316system.cpu.commit.committedOps 91262520 # Number of ops (including micro ops) committed 317system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 318system.cpu.commit.refs 27322634 # Number of memory references committed 319system.cpu.commit.loads 22575878 # Number of loads committed 320system.cpu.commit.membars 3888 # Number of memory barriers committed 321system.cpu.commit.branches 18722472 # Number of branches committed 322system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 323system.cpu.commit.int_insts 72533322 # Number of committed integer instructions. 324system.cpu.commit.function_calls 56148 # Number of function calls committed. 325system.cpu.commit.bw_lim_events 5031296 # number cycles where commit BW limit reached 326system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 327system.cpu.rob.rob_reads 161680438 # The number of ROB reads 328system.cpu.rob.rob_writes 242031234 # The number of ROB writes 329system.cpu.timesIdled 1832 # Number of times that the entire CPU went into an idle state and unscheduled itself 330system.cpu.idleCycles 41617 # Total number of cycles that the CPU has spent unscheduled due to idling 331system.cpu.committedInsts 90599358 # Number of Instructions Simulated 332system.cpu.committedOps 91249911 # Number of Ops (including micro ops) Simulated 333system.cpu.committedInsts_total 90599358 # Number of Instructions Simulated 334system.cpu.cpi 0.571275 # CPI: Cycles Per Instruction 335system.cpu.cpi_total 0.571275 # CPI: Total CPI of All Threads 336system.cpu.ipc 1.750470 # IPC: Instructions Per Cycle 337system.cpu.ipc_total 1.750470 # IPC: Total IPC of All Threads 338system.cpu.int_regfile_reads 496537855 # number of integer regfile reads 339system.cpu.int_regfile_writes 120784900 # number of integer regfile writes 340system.cpu.fp_regfile_reads 199 # number of floating regfile reads 341system.cpu.fp_regfile_writes 517 # number of floating regfile writes 342system.cpu.misc_regfile_reads 183129525 # number of misc regfile reads 343system.cpu.misc_regfile_writes 11608 # number of misc regfile writes 344system.cpu.icache.replacements 2 # number of replacements 345system.cpu.icache.tagsinuse 635.708091 # Cycle average of tags in use 346system.cpu.icache.total_refs 14075225 # Total number of references to valid blocks. 347system.cpu.icache.sampled_refs 737 # Sample count of references to valid blocks. 348system.cpu.icache.avg_refs 19097.998643 # Average number of references to valid blocks. 349system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 350system.cpu.icache.occ_blocks::cpu.inst 635.708091 # Average occupied blocks per requestor 351system.cpu.icache.occ_percent::cpu.inst 0.310404 # Average percentage of cache occupancy 352system.cpu.icache.occ_percent::total 0.310404 # Average percentage of cache occupancy 353system.cpu.icache.ReadReq_hits::cpu.inst 14075225 # number of ReadReq hits 354system.cpu.icache.ReadReq_hits::total 14075225 # number of ReadReq hits 355system.cpu.icache.demand_hits::cpu.inst 14075225 # number of demand (read+write) hits 356system.cpu.icache.demand_hits::total 14075225 # number of demand (read+write) hits 357system.cpu.icache.overall_hits::cpu.inst 14075225 # number of overall hits 358system.cpu.icache.overall_hits::total 14075225 # number of overall hits 359system.cpu.icache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses 360system.cpu.icache.ReadReq_misses::total 965 # number of ReadReq misses 361system.cpu.icache.demand_misses::cpu.inst 965 # number of demand (read+write) misses 362system.cpu.icache.demand_misses::total 965 # number of demand (read+write) misses 363system.cpu.icache.overall_misses::cpu.inst 965 # number of overall misses 364system.cpu.icache.overall_misses::total 965 # number of overall misses 365system.cpu.icache.ReadReq_miss_latency::cpu.inst 33626500 # number of ReadReq miss cycles 366system.cpu.icache.ReadReq_miss_latency::total 33626500 # number of ReadReq miss cycles 367system.cpu.icache.demand_miss_latency::cpu.inst 33626500 # number of demand (read+write) miss cycles 368system.cpu.icache.demand_miss_latency::total 33626500 # number of demand (read+write) miss cycles 369system.cpu.icache.overall_miss_latency::cpu.inst 33626500 # number of overall miss cycles 370system.cpu.icache.overall_miss_latency::total 33626500 # number of overall miss cycles 371system.cpu.icache.ReadReq_accesses::cpu.inst 14076190 # number of ReadReq accesses(hits+misses) 372system.cpu.icache.ReadReq_accesses::total 14076190 # number of ReadReq accesses(hits+misses) 373system.cpu.icache.demand_accesses::cpu.inst 14076190 # number of demand (read+write) accesses 374system.cpu.icache.demand_accesses::total 14076190 # number of demand (read+write) accesses 375system.cpu.icache.overall_accesses::cpu.inst 14076190 # number of overall (read+write) accesses 376system.cpu.icache.overall_accesses::total 14076190 # number of overall (read+write) accesses 377system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000069 # miss rate for ReadReq accesses 378system.cpu.icache.ReadReq_miss_rate::total 0.000069 # miss rate for ReadReq accesses 379system.cpu.icache.demand_miss_rate::cpu.inst 0.000069 # miss rate for demand accesses 380system.cpu.icache.demand_miss_rate::total 0.000069 # miss rate for demand accesses 381system.cpu.icache.overall_miss_rate::cpu.inst 0.000069 # miss rate for overall accesses 382system.cpu.icache.overall_miss_rate::total 0.000069 # miss rate for overall accesses 383system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34846.113990 # average ReadReq miss latency 384system.cpu.icache.ReadReq_avg_miss_latency::total 34846.113990 # average ReadReq miss latency 385system.cpu.icache.demand_avg_miss_latency::cpu.inst 34846.113990 # average overall miss latency 386system.cpu.icache.demand_avg_miss_latency::total 34846.113990 # average overall miss latency 387system.cpu.icache.overall_avg_miss_latency::cpu.inst 34846.113990 # average overall miss latency 388system.cpu.icache.overall_avg_miss_latency::total 34846.113990 # average overall miss latency 389system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.icache.fast_writes 0 # number of fast writes performed 396system.cpu.icache.cache_copies 0 # number of cache copies performed 397system.cpu.icache.ReadReq_mshr_hits::cpu.inst 228 # number of ReadReq MSHR hits 398system.cpu.icache.ReadReq_mshr_hits::total 228 # number of ReadReq MSHR hits 399system.cpu.icache.demand_mshr_hits::cpu.inst 228 # number of demand (read+write) MSHR hits 400system.cpu.icache.demand_mshr_hits::total 228 # number of demand (read+write) MSHR hits 401system.cpu.icache.overall_mshr_hits::cpu.inst 228 # number of overall MSHR hits 402system.cpu.icache.overall_mshr_hits::total 228 # number of overall MSHR hits 403system.cpu.icache.ReadReq_mshr_misses::cpu.inst 737 # number of ReadReq MSHR misses 404system.cpu.icache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses 405system.cpu.icache.demand_mshr_misses::cpu.inst 737 # number of demand (read+write) MSHR misses 406system.cpu.icache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses 407system.cpu.icache.overall_mshr_misses::cpu.inst 737 # number of overall MSHR misses 408system.cpu.icache.overall_mshr_misses::total 737 # number of overall MSHR misses 409system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25265000 # number of ReadReq MSHR miss cycles 410system.cpu.icache.ReadReq_mshr_miss_latency::total 25265000 # number of ReadReq MSHR miss cycles 411system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25265000 # number of demand (read+write) MSHR miss cycles 412system.cpu.icache.demand_mshr_miss_latency::total 25265000 # number of demand (read+write) MSHR miss cycles 413system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25265000 # number of overall MSHR miss cycles 414system.cpu.icache.overall_mshr_miss_latency::total 25265000 # number of overall MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses 416system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses 417system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses 418system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses 419system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses 420system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses 421system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34280.868385 # average ReadReq mshr miss latency 422system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34280.868385 # average ReadReq mshr miss latency 423system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34280.868385 # average overall mshr miss latency 424system.cpu.icache.demand_avg_mshr_miss_latency::total 34280.868385 # average overall mshr miss latency 425system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34280.868385 # average overall mshr miss latency 426system.cpu.icache.overall_avg_mshr_miss_latency::total 34280.868385 # average overall mshr miss latency 427system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 428system.cpu.dcache.replacements 943587 # number of replacements 429system.cpu.dcache.tagsinuse 3648.438272 # Cycle average of tags in use 430system.cpu.dcache.total_refs 28413602 # Total number of references to valid blocks. 431system.cpu.dcache.sampled_refs 947683 # Sample count of references to valid blocks. 432system.cpu.dcache.avg_refs 29.982180 # Average number of references to valid blocks. 433system.cpu.dcache.warmup_cycle 8139620000 # Cycle when the warmup percentage was hit. 434system.cpu.dcache.occ_blocks::cpu.data 3648.438272 # Average occupied blocks per requestor 435system.cpu.dcache.occ_percent::cpu.data 0.890732 # Average percentage of cache occupancy 436system.cpu.dcache.occ_percent::total 0.890732 # Average percentage of cache occupancy 437system.cpu.dcache.ReadReq_hits::cpu.data 23842486 # number of ReadReq hits 438system.cpu.dcache.ReadReq_hits::total 23842486 # number of ReadReq hits 439system.cpu.dcache.WriteReq_hits::cpu.data 4559459 # number of WriteReq hits 440system.cpu.dcache.WriteReq_hits::total 4559459 # number of WriteReq hits 441system.cpu.dcache.LoadLockedReq_hits::cpu.data 5858 # number of LoadLockedReq hits 442system.cpu.dcache.LoadLockedReq_hits::total 5858 # number of LoadLockedReq hits 443system.cpu.dcache.StoreCondReq_hits::cpu.data 5799 # number of StoreCondReq hits 444system.cpu.dcache.StoreCondReq_hits::total 5799 # number of StoreCondReq hits 445system.cpu.dcache.demand_hits::cpu.data 28401945 # number of demand (read+write) hits 446system.cpu.dcache.demand_hits::total 28401945 # number of demand (read+write) hits 447system.cpu.dcache.overall_hits::cpu.data 28401945 # number of overall hits 448system.cpu.dcache.overall_hits::total 28401945 # number of overall hits 449system.cpu.dcache.ReadReq_misses::cpu.data 1005618 # number of ReadReq misses 450system.cpu.dcache.ReadReq_misses::total 1005618 # number of ReadReq misses 451system.cpu.dcache.WriteReq_misses::cpu.data 175522 # number of WriteReq misses 452system.cpu.dcache.WriteReq_misses::total 175522 # number of WriteReq misses 453system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses 454system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses 455system.cpu.dcache.demand_misses::cpu.data 1181140 # number of demand (read+write) misses 456system.cpu.dcache.demand_misses::total 1181140 # number of demand (read+write) misses 457system.cpu.dcache.overall_misses::cpu.data 1181140 # number of overall misses 458system.cpu.dcache.overall_misses::total 1181140 # number of overall misses 459system.cpu.dcache.ReadReq_miss_latency::cpu.data 5786835500 # number of ReadReq miss cycles 460system.cpu.dcache.ReadReq_miss_latency::total 5786835500 # number of ReadReq miss cycles 461system.cpu.dcache.WriteReq_miss_latency::cpu.data 4609409990 # number of WriteReq miss cycles 462system.cpu.dcache.WriteReq_miss_latency::total 4609409990 # number of WriteReq miss cycles 463system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130000 # number of LoadLockedReq miss cycles 464system.cpu.dcache.LoadLockedReq_miss_latency::total 130000 # number of LoadLockedReq miss cycles 465system.cpu.dcache.demand_miss_latency::cpu.data 10396245490 # number of demand (read+write) miss cycles 466system.cpu.dcache.demand_miss_latency::total 10396245490 # number of demand (read+write) miss cycles 467system.cpu.dcache.overall_miss_latency::cpu.data 10396245490 # number of overall miss cycles 468system.cpu.dcache.overall_miss_latency::total 10396245490 # number of overall miss cycles 469system.cpu.dcache.ReadReq_accesses::cpu.data 24848104 # number of ReadReq accesses(hits+misses) 470system.cpu.dcache.ReadReq_accesses::total 24848104 # number of ReadReq accesses(hits+misses) 471system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 472system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 473system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5865 # number of LoadLockedReq accesses(hits+misses) 474system.cpu.dcache.LoadLockedReq_accesses::total 5865 # number of LoadLockedReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::cpu.data 5799 # number of StoreCondReq accesses(hits+misses) 476system.cpu.dcache.StoreCondReq_accesses::total 5799 # number of StoreCondReq accesses(hits+misses) 477system.cpu.dcache.demand_accesses::cpu.data 29583085 # number of demand (read+write) accesses 478system.cpu.dcache.demand_accesses::total 29583085 # number of demand (read+write) accesses 479system.cpu.dcache.overall_accesses::cpu.data 29583085 # number of overall (read+write) accesses 480system.cpu.dcache.overall_accesses::total 29583085 # number of overall (read+write) accesses 481system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040471 # miss rate for ReadReq accesses 482system.cpu.dcache.ReadReq_miss_rate::total 0.040471 # miss rate for ReadReq accesses 483system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037069 # miss rate for WriteReq accesses 484system.cpu.dcache.WriteReq_miss_rate::total 0.037069 # miss rate for WriteReq accesses 485system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001194 # miss rate for LoadLockedReq accesses 486system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001194 # miss rate for LoadLockedReq accesses 487system.cpu.dcache.demand_miss_rate::cpu.data 0.039926 # miss rate for demand accesses 488system.cpu.dcache.demand_miss_rate::total 0.039926 # miss rate for demand accesses 489system.cpu.dcache.overall_miss_rate::cpu.data 0.039926 # miss rate for overall accesses 490system.cpu.dcache.overall_miss_rate::total 0.039926 # miss rate for overall accesses 491system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 5754.506681 # average ReadReq miss latency 492system.cpu.dcache.ReadReq_avg_miss_latency::total 5754.506681 # average ReadReq miss latency 493system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26261.152391 # average WriteReq miss latency 494system.cpu.dcache.WriteReq_avg_miss_latency::total 26261.152391 # average WriteReq miss latency 495system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18571.428571 # average LoadLockedReq miss latency 496system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18571.428571 # average LoadLockedReq miss latency 497system.cpu.dcache.demand_avg_miss_latency::cpu.data 8801.874028 # average overall miss latency 498system.cpu.dcache.demand_avg_miss_latency::total 8801.874028 # average overall miss latency 499system.cpu.dcache.overall_avg_miss_latency::cpu.data 8801.874028 # average overall miss latency 500system.cpu.dcache.overall_avg_miss_latency::total 8801.874028 # average overall miss latency 501system.cpu.dcache.blocked_cycles::no_mshrs 23117548 # number of cycles access was blocked 502system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_mshrs 8084 # number of cycles access was blocked 504system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_mshrs 2859.666997 # average number of cycles each access was blocked 506system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 507system.cpu.dcache.fast_writes 0 # number of fast writes performed 508system.cpu.dcache.cache_copies 0 # number of cache copies performed 509system.cpu.dcache.writebacks::writebacks 942950 # number of writebacks 510system.cpu.dcache.writebacks::total 942950 # number of writebacks 511system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101118 # number of ReadReq MSHR hits 512system.cpu.dcache.ReadReq_mshr_hits::total 101118 # number of ReadReq MSHR hits 513system.cpu.dcache.WriteReq_mshr_hits::cpu.data 132339 # number of WriteReq MSHR hits 514system.cpu.dcache.WriteReq_mshr_hits::total 132339 # number of WriteReq MSHR hits 515system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits 516system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits 517system.cpu.dcache.demand_mshr_hits::cpu.data 233457 # number of demand (read+write) MSHR hits 518system.cpu.dcache.demand_mshr_hits::total 233457 # number of demand (read+write) MSHR hits 519system.cpu.dcache.overall_mshr_hits::cpu.data 233457 # number of overall MSHR hits 520system.cpu.dcache.overall_mshr_hits::total 233457 # number of overall MSHR hits 521system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904500 # number of ReadReq MSHR misses 522system.cpu.dcache.ReadReq_mshr_misses::total 904500 # number of ReadReq MSHR misses 523system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43183 # number of WriteReq MSHR misses 524system.cpu.dcache.WriteReq_mshr_misses::total 43183 # number of WriteReq MSHR misses 525system.cpu.dcache.demand_mshr_misses::cpu.data 947683 # number of demand (read+write) MSHR misses 526system.cpu.dcache.demand_mshr_misses::total 947683 # number of demand (read+write) MSHR misses 527system.cpu.dcache.overall_mshr_misses::cpu.data 947683 # number of overall MSHR misses 528system.cpu.dcache.overall_mshr_misses::total 947683 # number of overall MSHR misses 529system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2400819500 # number of ReadReq MSHR miss cycles 530system.cpu.dcache.ReadReq_mshr_miss_latency::total 2400819500 # number of ReadReq MSHR miss cycles 531system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1075610609 # number of WriteReq MSHR miss cycles 532system.cpu.dcache.WriteReq_mshr_miss_latency::total 1075610609 # number of WriteReq MSHR miss cycles 533system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3476430109 # number of demand (read+write) MSHR miss cycles 534system.cpu.dcache.demand_mshr_miss_latency::total 3476430109 # number of demand (read+write) MSHR miss cycles 535system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3476430109 # number of overall MSHR miss cycles 536system.cpu.dcache.overall_mshr_miss_latency::total 3476430109 # number of overall MSHR miss cycles 537system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036401 # mshr miss rate for ReadReq accesses 538system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036401 # mshr miss rate for ReadReq accesses 539system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009120 # mshr miss rate for WriteReq accesses 540system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009120 # mshr miss rate for WriteReq accesses 541system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032035 # mshr miss rate for demand accesses 542system.cpu.dcache.demand_mshr_miss_rate::total 0.032035 # mshr miss rate for demand accesses 543system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032035 # mshr miss rate for overall accesses 544system.cpu.dcache.overall_mshr_miss_rate::total 0.032035 # mshr miss rate for overall accesses 545system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 2654.305694 # average ReadReq mshr miss latency 546system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 2654.305694 # average ReadReq mshr miss latency 547system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24908.195563 # average WriteReq mshr miss latency 548system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24908.195563 # average WriteReq mshr miss latency 549system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 3668.347020 # average overall mshr miss latency 550system.cpu.dcache.demand_avg_mshr_miss_latency::total 3668.347020 # average overall mshr miss latency 551system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3668.347020 # average overall mshr miss latency 552system.cpu.dcache.overall_avg_mshr_miss_latency::total 3668.347020 # average overall mshr miss latency 553system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 554system.cpu.l2cache.replacements 0 # number of replacements 555system.cpu.l2cache.tagsinuse 10511.051990 # Cycle average of tags in use 556system.cpu.l2cache.total_refs 1830916 # Total number of references to valid blocks. 557system.cpu.l2cache.sampled_refs 15498 # Sample count of references to valid blocks. 558system.cpu.l2cache.avg_refs 118.138857 # Average number of references to valid blocks. 559system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 560system.cpu.l2cache.occ_blocks::writebacks 9660.066682 # Average occupied blocks per requestor 561system.cpu.l2cache.occ_blocks::cpu.inst 620.063738 # Average occupied blocks per requestor 562system.cpu.l2cache.occ_blocks::cpu.data 230.921571 # Average occupied blocks per requestor 563system.cpu.l2cache.occ_percent::writebacks 0.294802 # Average percentage of cache occupancy 564system.cpu.l2cache.occ_percent::cpu.inst 0.018923 # Average percentage of cache occupancy 565system.cpu.l2cache.occ_percent::cpu.data 0.007047 # Average percentage of cache occupancy 566system.cpu.l2cache.occ_percent::total 0.320772 # Average percentage of cache occupancy 567system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits 568system.cpu.l2cache.ReadReq_hits::cpu.data 903058 # number of ReadReq hits 569system.cpu.l2cache.ReadReq_hits::total 903083 # number of ReadReq hits 570system.cpu.l2cache.Writeback_hits::writebacks 942950 # number of Writeback hits 571system.cpu.l2cache.Writeback_hits::total 942950 # number of Writeback hits 572system.cpu.l2cache.ReadExReq_hits::cpu.data 29811 # number of ReadExReq hits 573system.cpu.l2cache.ReadExReq_hits::total 29811 # number of ReadExReq hits 574system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits 575system.cpu.l2cache.demand_hits::cpu.data 932869 # number of demand (read+write) hits 576system.cpu.l2cache.demand_hits::total 932894 # number of demand (read+write) hits 577system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits 578system.cpu.l2cache.overall_hits::cpu.data 932869 # number of overall hits 579system.cpu.l2cache.overall_hits::total 932894 # number of overall hits 580system.cpu.l2cache.ReadReq_misses::cpu.inst 712 # number of ReadReq misses 581system.cpu.l2cache.ReadReq_misses::cpu.data 278 # number of ReadReq misses 582system.cpu.l2cache.ReadReq_misses::total 990 # number of ReadReq misses 583system.cpu.l2cache.ReadExReq_misses::cpu.data 14536 # number of ReadExReq misses 584system.cpu.l2cache.ReadExReq_misses::total 14536 # number of ReadExReq misses 585system.cpu.l2cache.demand_misses::cpu.inst 712 # number of demand (read+write) misses 586system.cpu.l2cache.demand_misses::cpu.data 14814 # number of demand (read+write) misses 587system.cpu.l2cache.demand_misses::total 15526 # number of demand (read+write) misses 588system.cpu.l2cache.overall_misses::cpu.inst 712 # number of overall misses 589system.cpu.l2cache.overall_misses::cpu.data 14814 # number of overall misses 590system.cpu.l2cache.overall_misses::total 15526 # number of overall misses 591system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24404500 # number of ReadReq miss cycles 592system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9520000 # number of ReadReq miss cycles 593system.cpu.l2cache.ReadReq_miss_latency::total 33924500 # number of ReadReq miss cycles 594system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 499194500 # number of ReadExReq miss cycles 595system.cpu.l2cache.ReadExReq_miss_latency::total 499194500 # number of ReadExReq miss cycles 596system.cpu.l2cache.demand_miss_latency::cpu.inst 24404500 # number of demand (read+write) miss cycles 597system.cpu.l2cache.demand_miss_latency::cpu.data 508714500 # number of demand (read+write) miss cycles 598system.cpu.l2cache.demand_miss_latency::total 533119000 # number of demand (read+write) miss cycles 599system.cpu.l2cache.overall_miss_latency::cpu.inst 24404500 # number of overall miss cycles 600system.cpu.l2cache.overall_miss_latency::cpu.data 508714500 # number of overall miss cycles 601system.cpu.l2cache.overall_miss_latency::total 533119000 # number of overall miss cycles 602system.cpu.l2cache.ReadReq_accesses::cpu.inst 737 # number of ReadReq accesses(hits+misses) 603system.cpu.l2cache.ReadReq_accesses::cpu.data 903336 # number of ReadReq accesses(hits+misses) 604system.cpu.l2cache.ReadReq_accesses::total 904073 # number of ReadReq accesses(hits+misses) 605system.cpu.l2cache.Writeback_accesses::writebacks 942950 # number of Writeback accesses(hits+misses) 606system.cpu.l2cache.Writeback_accesses::total 942950 # number of Writeback accesses(hits+misses) 607system.cpu.l2cache.ReadExReq_accesses::cpu.data 44347 # number of ReadExReq accesses(hits+misses) 608system.cpu.l2cache.ReadExReq_accesses::total 44347 # number of ReadExReq accesses(hits+misses) 609system.cpu.l2cache.demand_accesses::cpu.inst 737 # number of demand (read+write) accesses 610system.cpu.l2cache.demand_accesses::cpu.data 947683 # number of demand (read+write) accesses 611system.cpu.l2cache.demand_accesses::total 948420 # number of demand (read+write) accesses 612system.cpu.l2cache.overall_accesses::cpu.inst 737 # number of overall (read+write) accesses 613system.cpu.l2cache.overall_accesses::cpu.data 947683 # number of overall (read+write) accesses 614system.cpu.l2cache.overall_accesses::total 948420 # number of overall (read+write) accesses 615system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.966079 # miss rate for ReadReq accesses 616system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000308 # miss rate for ReadReq accesses 617system.cpu.l2cache.ReadReq_miss_rate::total 0.001095 # miss rate for ReadReq accesses 618system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.327779 # miss rate for ReadExReq accesses 619system.cpu.l2cache.ReadExReq_miss_rate::total 0.327779 # miss rate for ReadExReq accesses 620system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966079 # miss rate for demand accesses 621system.cpu.l2cache.demand_miss_rate::cpu.data 0.015632 # miss rate for demand accesses 622system.cpu.l2cache.demand_miss_rate::total 0.016370 # miss rate for demand accesses 623system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966079 # miss rate for overall accesses 624system.cpu.l2cache.overall_miss_rate::cpu.data 0.015632 # miss rate for overall accesses 625system.cpu.l2cache.overall_miss_rate::total 0.016370 # miss rate for overall accesses 626system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34275.983146 # average ReadReq miss latency 627system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34244.604317 # average ReadReq miss latency 628system.cpu.l2cache.ReadReq_avg_miss_latency::total 34267.171717 # average ReadReq miss latency 629system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34341.944139 # average ReadExReq miss latency 630system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34341.944139 # average ReadExReq miss latency 631system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34275.983146 # average overall miss latency 632system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34340.117456 # average overall miss latency 633system.cpu.l2cache.demand_avg_miss_latency::total 34337.176349 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34275.983146 # average overall miss latency 635system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34340.117456 # average overall miss latency 636system.cpu.l2cache.overall_avg_miss_latency::total 34337.176349 # average overall miss latency 637system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 640system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 641system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 642system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.l2cache.fast_writes 0 # number of fast writes performed 644system.cpu.l2cache.cache_copies 0 # number of cache copies performed 645system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 646system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits 647system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 648system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 649system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits 650system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 651system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 652system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits 653system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits 654system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 711 # number of ReadReq MSHR misses 655system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 268 # number of ReadReq MSHR misses 656system.cpu.l2cache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses 657system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14536 # number of ReadExReq MSHR misses 658system.cpu.l2cache.ReadExReq_mshr_misses::total 14536 # number of ReadExReq MSHR misses 659system.cpu.l2cache.demand_mshr_misses::cpu.inst 711 # number of demand (read+write) MSHR misses 660system.cpu.l2cache.demand_mshr_misses::cpu.data 14804 # number of demand (read+write) MSHR misses 661system.cpu.l2cache.demand_mshr_misses::total 15515 # number of demand (read+write) MSHR misses 662system.cpu.l2cache.overall_mshr_misses::cpu.inst 711 # number of overall MSHR misses 663system.cpu.l2cache.overall_mshr_misses::cpu.data 14804 # number of overall MSHR misses 664system.cpu.l2cache.overall_mshr_misses::total 15515 # number of overall MSHR misses 665system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22107000 # number of ReadReq MSHR miss cycles 666system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8364000 # number of ReadReq MSHR miss cycles 667system.cpu.l2cache.ReadReq_mshr_miss_latency::total 30471000 # number of ReadReq MSHR miss cycles 668system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 452118500 # number of ReadExReq MSHR miss cycles 669system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 452118500 # number of ReadExReq MSHR miss cycles 670system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22107000 # number of demand (read+write) MSHR miss cycles 671system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 460482500 # number of demand (read+write) MSHR miss cycles 672system.cpu.l2cache.demand_mshr_miss_latency::total 482589500 # number of demand (read+write) MSHR miss cycles 673system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22107000 # number of overall MSHR miss cycles 674system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 460482500 # number of overall MSHR miss cycles 675system.cpu.l2cache.overall_mshr_miss_latency::total 482589500 # number of overall MSHR miss cycles 676system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for ReadReq accesses 677system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000297 # mshr miss rate for ReadReq accesses 678system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001083 # mshr miss rate for ReadReq accesses 679system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.327779 # mshr miss rate for ReadExReq accesses 680system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.327779 # mshr miss rate for ReadExReq accesses 681system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for demand accesses 682system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for demand accesses 683system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses 684system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964722 # mshr miss rate for overall accesses 685system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for overall accesses 686system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses 687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31092.827004 # average ReadReq mshr miss latency 688system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31208.955224 # average ReadReq mshr miss latency 689system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31124.616956 # average ReadReq mshr miss latency 690system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31103.364062 # average ReadExReq mshr miss latency 691system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31103.364062 # average ReadExReq mshr miss latency 692system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency 694system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency 695system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31092.827004 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31105.275601 # average overall mshr miss latency 697system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31104.705124 # average overall mshr miss latency 698system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 699 700---------- End Simulation Statistics ---------- 701