stats.txt revision 11687:b3d5f0e9e258
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058675 # Number of seconds simulated 4sim_ticks 58675371500 # Number of ticks simulated 5final_tick 58675371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 241655 # Simulator instruction rate (inst/s) 8host_op_rate 242858 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 156520643 # Simulator tick rate (ticks/s) 10host_mem_usage 492304 # Number of bytes of host memory used 11host_seconds 374.87 # Real time elapsed on the host 12sim_insts 90589799 # Number of instructions simulated 13sim_ops 91041030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 218240 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 923072 # Number of bytes read from this memory 20system.physmem.bytes_read::total 1186048 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6656 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 3410 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 14423 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 18532 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 104 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 762432 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 3719448 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 15731848 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 20213728 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 762432 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 762432 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 113438 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 113438 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 113438 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 762432 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 3719448 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 15731848 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 20327166 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 18533 # Number of read requests accepted 45system.physmem.writeReqs 104 # Number of write requests accepted 46system.physmem.readBursts 18533 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 104 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 1180480 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue 50system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 1186112 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 6656 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 56system.physmem.perBankRdBursts::0 3245 # Per bank write bursts 57system.physmem.perBankRdBursts::1 921 # Per bank write bursts 58system.physmem.perBankRdBursts::2 952 # Per bank write bursts 59system.physmem.perBankRdBursts::3 1031 # Per bank write bursts 60system.physmem.perBankRdBursts::4 1065 # Per bank write bursts 61system.physmem.perBankRdBursts::5 1118 # Per bank write bursts 62system.physmem.perBankRdBursts::6 1097 # Per bank write bursts 63system.physmem.perBankRdBursts::7 1096 # Per bank write bursts 64system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 65system.physmem.perBankRdBursts::9 962 # Per bank write bursts 66system.physmem.perBankRdBursts::10 932 # Per bank write bursts 67system.physmem.perBankRdBursts::11 899 # Per bank write bursts 68system.physmem.perBankRdBursts::12 904 # Per bank write bursts 69system.physmem.perBankRdBursts::13 895 # Per bank write bursts 70system.physmem.perBankRdBursts::14 1401 # Per bank write bursts 71system.physmem.perBankRdBursts::15 903 # Per bank write bursts 72system.physmem.perBankWrBursts::0 0 # Per bank write bursts 73system.physmem.perBankWrBursts::1 0 # Per bank write bursts 74system.physmem.perBankWrBursts::2 3 # Per bank write bursts 75system.physmem.perBankWrBursts::3 3 # Per bank write bursts 76system.physmem.perBankWrBursts::4 12 # Per bank write bursts 77system.physmem.perBankWrBursts::5 10 # Per bank write bursts 78system.physmem.perBankWrBursts::6 15 # Per bank write bursts 79system.physmem.perBankWrBursts::7 0 # Per bank write bursts 80system.physmem.perBankWrBursts::8 1 # Per bank write bursts 81system.physmem.perBankWrBursts::9 0 # Per bank write bursts 82system.physmem.perBankWrBursts::10 1 # Per bank write bursts 83system.physmem.perBankWrBursts::11 3 # Per bank write bursts 84system.physmem.perBankWrBursts::12 5 # Per bank write bursts 85system.physmem.perBankWrBursts::13 12 # Per bank write bursts 86system.physmem.perBankWrBursts::14 7 # Per bank write bursts 87system.physmem.perBankWrBursts::15 0 # Per bank write bursts 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 90system.physmem.totGap 58675363000 # Total gap between requests 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) 97system.physmem.readPktSize::6 18533 # Read request sizes (log2) 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) 104system.physmem.writePktSize::6 104 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 12556 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 3396 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 314 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 300 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 296 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 280 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 99 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 137system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 5 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 5 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 5 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 5 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 5 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 5 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 201system.physmem.bytesPerActivate::samples 2974 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 397.815736 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 217.392167 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 406.651837 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 841 28.28% 28.28% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 992 33.36% 61.63% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 92 3.09% 64.73% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 59 1.98% 66.71% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 59 1.98% 68.70% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 62 2.08% 70.78% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 53 1.78% 72.56% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 59 1.98% 74.55% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 757 25.45% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 2974 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 4542 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::gmean 1434.998534 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::stdev 7438.956513 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads 228system.physmem.totQLat 819558662 # Total ticks spent queuing 229system.physmem.totMemAccLat 1165402412 # Total ticks spent from burst creation until serviced by the DRAM 230system.physmem.totBusLat 92225000 # Total ticks spent in databus transfers 231system.physmem.avgQLat 44432.57 # Average queueing delay per DRAM burst 232system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 233system.physmem.avgMemAccLat 63182.57 # Average memory access latency per DRAM burst 234system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s 235system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s 236system.physmem.avgRdBWSys 20.21 # Average system read bandwidth in MiByte/s 237system.physmem.avgWrBWSys 0.11 # Average system write bandwidth in MiByte/s 238system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 239system.physmem.busUtil 0.16 # Data bus utilization in percentage 240system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads 241system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 242system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing 243system.physmem.avgWrQLen 17.01 # Average write queue length when enqueuing 244system.physmem.readRowHits 15523 # Number of row buffer hits during reads 245system.physmem.writeRowHits 12 # Number of row buffer hits during writes 246system.physmem.readRowHitRate 84.16 # Row buffer hit rate for reads 247system.physmem.writeRowHitRate 11.88 # Row buffer hit rate for writes 248system.physmem.avgGap 3148326.61 # Average gap between requests 249system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined 250system.physmem_0.actEnergy 15986460 # Energy for activate commands per rank (pJ) 251system.physmem_0.preEnergy 8481825 # Energy for precharge commands per rank (pJ) 252system.physmem_0.readEnergy 75141360 # Energy for read commands per rank (pJ) 253system.physmem_0.writeEnergy 224460 # Energy for write commands per rank (pJ) 254system.physmem_0.refreshEnergy 1848222480.000000 # Energy for refresh commands per rank (pJ) 255system.physmem_0.actBackEnergy 457291620 # Energy for active background per rank (pJ) 256system.physmem_0.preBackEnergy 99494880 # Energy for precharge background per rank (pJ) 257system.physmem_0.actPowerDownEnergy 3995273070 # Energy for active power-down per rank (pJ) 258system.physmem_0.prePowerDownEnergy 3179264640 # Energy for precharge power-down per rank (pJ) 259system.physmem_0.selfRefreshEnergy 10079734425 # Energy for self refresh per rank (pJ) 260system.physmem_0.totalEnergy 19762775190 # Total energy per rank (pJ) 261system.physmem_0.averagePower 336.815504 # Core power per rank (mW) 262system.physmem_0.totalIdleTime 57405272063 # Total Idle time Per DRAM Rank 263system.physmem_0.memoryStateTime::IDLE 196297250 # Time in different power states 264system.physmem_0.memoryStateTime::REF 786242000 # Time in different power states 265system.physmem_0.memoryStateTime::SREF 40364411250 # Time in different power states 266system.physmem_0.memoryStateTime::PRE_PDN 8279321820 # Time in different power states 267system.physmem_0.memoryStateTime::ACT 287560187 # Time in different power states 268system.physmem_0.memoryStateTime::ACT_PDN 8761538993 # Time in different power states 269system.physmem_1.actEnergy 5305020 # Energy for activate commands per rank (pJ) 270system.physmem_1.preEnergy 2804505 # Energy for precharge commands per rank (pJ) 271system.physmem_1.readEnergy 56548800 # Energy for read commands per rank (pJ) 272system.physmem_1.writeEnergy 151380 # Energy for write commands per rank (pJ) 273system.physmem_1.refreshEnergy 250773120.000000 # Energy for refresh commands per rank (pJ) 274system.physmem_1.actBackEnergy 129702360 # Energy for active background per rank (pJ) 275system.physmem_1.preBackEnergy 13640160 # Energy for precharge background per rank (pJ) 276system.physmem_1.actPowerDownEnergy 769421340 # Energy for active power-down per rank (pJ) 277system.physmem_1.prePowerDownEnergy 250623360 # Energy for precharge power-down per rank (pJ) 278system.physmem_1.selfRefreshEnergy 13483521390 # Energy for self refresh per rank (pJ) 279system.physmem_1.totalEnergy 14962606875 # Total energy per rank (pJ) 280system.physmem_1.averagePower 255.006594 # Core power per rank (mW) 281system.physmem_1.totalIdleTime 58353889098 # Total Idle time Per DRAM Rank 282system.physmem_1.memoryStateTime::IDLE 22210250 # Time in different power states 283system.physmem_1.memoryStateTime::REF 106530000 # Time in different power states 284system.physmem_1.memoryStateTime::SREF 56015166500 # Time in different power states 285system.physmem_1.memoryStateTime::PRE_PDN 652672389 # Time in different power states 286system.physmem_1.memoryStateTime::ACT 191421152 # Time in different power states 287system.physmem_1.memoryStateTime::ACT_PDN 1687371209 # Time in different power states 288system.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 289system.cpu.branchPred.lookups 28234010 # Number of BP lookups 290system.cpu.branchPred.condPredicted 23266490 # Number of conditional branches predicted 291system.cpu.branchPred.condIncorrect 835433 # Number of conditional branches incorrect 292system.cpu.branchPred.BTBLookups 11829728 # Number of BTB lookups 293system.cpu.branchPred.BTBHits 11748003 # Number of BTB hits 294system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 295system.cpu.branchPred.BTBHitPct 99.309156 # BTB Hit Percentage 296system.cpu.branchPred.usedRAS 74546 # Number of times the RAS was used to get a target. 297system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. 298system.cpu.branchPred.indirectLookups 27219 # Number of indirect predictor lookups. 299system.cpu.branchPred.indirectHits 25475 # Number of indirect target hits. 300system.cpu.branchPred.indirectMisses 1744 # Number of indirect misses. 301system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. 302system.cpu_clk_domain.clock 500 # Clock period in ticks 303system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 304system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 313system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 314system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 315system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 316system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 317system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 322system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 323system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 324system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 333system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 334system.cpu.dtb.walker.walks 0 # Table walker walks requested 335system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.inst_hits 0 # ITB inst hits 343system.cpu.dtb.inst_misses 0 # ITB inst misses 344system.cpu.dtb.read_hits 0 # DTB read hits 345system.cpu.dtb.read_misses 0 # DTB read misses 346system.cpu.dtb.write_hits 0 # DTB write hits 347system.cpu.dtb.write_misses 0 # DTB write misses 348system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 349system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 350system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 351system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 352system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 353system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 354system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 355system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.dtb.read_accesses 0 # DTB read accesses 358system.cpu.dtb.write_accesses 0 # DTB write accesses 359system.cpu.dtb.inst_accesses 0 # ITB inst accesses 360system.cpu.dtb.hits 0 # DTB hits 361system.cpu.dtb.misses 0 # DTB misses 362system.cpu.dtb.accesses 0 # DTB accesses 363system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 364system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 373system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 374system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 375system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 376system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 377system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 378system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 379system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 380system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 381system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 382system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 383system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 384system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 385system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 386system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 388system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 389system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 390system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 391system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 392system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 393system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 394system.cpu.itb.walker.walks 0 # Table walker walks requested 395system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.inst_hits 0 # ITB inst hits 403system.cpu.itb.inst_misses 0 # ITB inst misses 404system.cpu.itb.read_hits 0 # DTB read hits 405system.cpu.itb.read_misses 0 # DTB read misses 406system.cpu.itb.write_hits 0 # DTB write hits 407system.cpu.itb.write_misses 0 # DTB write misses 408system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 409system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 410system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 411system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 412system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 413system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 414system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 415system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 416system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 417system.cpu.itb.read_accesses 0 # DTB read accesses 418system.cpu.itb.write_accesses 0 # DTB write accesses 419system.cpu.itb.inst_accesses 0 # ITB inst accesses 420system.cpu.itb.hits 0 # DTB hits 421system.cpu.itb.misses 0 # DTB misses 422system.cpu.itb.accesses 0 # DTB accesses 423system.cpu.workload.num_syscalls 442 # Number of system calls 424system.cpu.pwrStateResidencyTicks::ON 58675371500 # Cumulative time (in ticks) in various power states 425system.cpu.numCycles 117350744 # number of cpu cycles simulated 426system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 427system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 428system.cpu.fetch.icacheStallCycles 746331 # Number of cycles fetch is stalled on an Icache miss 429system.cpu.fetch.Insts 134908246 # Number of instructions fetch has processed 430system.cpu.fetch.Branches 28234010 # Number of branches that fetch encountered 431system.cpu.fetch.predictedBranches 11848024 # Number of branches that fetch has predicted taken 432system.cpu.fetch.Cycles 115699810 # Number of cycles fetch has run and was not squashing or blocked 433system.cpu.fetch.SquashCycles 1674291 # Number of cycles fetch has spent squashing 434system.cpu.fetch.MiscStallCycles 849 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 435system.cpu.fetch.IcacheWaitRetryStallCycles 926 # Number of stall cycles due to full MSHR 436system.cpu.fetch.CacheLines 32275670 # Number of cache lines fetched 437system.cpu.fetch.IcacheSquashes 568 # Number of outstanding Icache misses that were squashed 438system.cpu.fetch.rateDist::samples 117285061 # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::mean 1.155401 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::stdev 1.317679 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::0 59749210 50.94% 50.94% # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::1 13933958 11.88% 62.82% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::2 9228354 7.87% 70.69% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::3 34373539 29.31% 100.00% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::total 117285061 # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.branchRate 0.240595 # Number of branch fetches per cycle 451system.cpu.fetch.rate 1.149616 # Number of inst fetches per cycle 452system.cpu.decode.IdleCycles 8835265 # Number of cycles decode is idle 453system.cpu.decode.BlockedCycles 65049836 # Number of cycles decode is blocked 454system.cpu.decode.RunCycles 33012809 # Number of cycles decode is running 455system.cpu.decode.UnblockCycles 9561722 # Number of cycles decode is unblocking 456system.cpu.decode.SquashCycles 825429 # Number of cycles decode is squashing 457system.cpu.decode.BranchResolved 4097911 # Number of times decode resolved a branch 458system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction 459system.cpu.decode.DecodedInsts 114395758 # Number of instructions handled by decode 460system.cpu.decode.SquashedInsts 1985288 # Number of squashed instructions handled by decode 461system.cpu.rename.SquashCycles 825429 # Number of cycles rename is squashing 462system.cpu.rename.IdleCycles 15272092 # Number of cycles rename is idle 463system.cpu.rename.BlockCycles 50298480 # Number of cycles rename is blocking 464system.cpu.rename.serializeStallCycles 112986 # count of cycles rename stalled for serializing inst 465system.cpu.rename.RunCycles 35409562 # Number of cycles rename is running 466system.cpu.rename.UnblockCycles 15366512 # Number of cycles rename is unblocking 467system.cpu.rename.RenamedInsts 110872789 # Number of instructions processed by rename 468system.cpu.rename.SquashedInsts 1412207 # Number of squashed instructions processed by rename 469system.cpu.rename.ROBFullEvents 11133815 # Number of times rename has blocked due to ROB full 470system.cpu.rename.IQFullEvents 1555614 # Number of times rename has blocked due to IQ full 471system.cpu.rename.LQFullEvents 2094363 # Number of times rename has blocked due to LQ full 472system.cpu.rename.SQFullEvents 506230 # Number of times rename has blocked due to SQ full 473system.cpu.rename.RenamedOperands 129945991 # Number of destination operands rename has renamed 474system.cpu.rename.RenameLookups 483154289 # Number of register rename lookups that rename has made 475system.cpu.rename.int_rename_lookups 119447702 # Number of integer rename lookups 476system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups 477system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed 478system.cpu.rename.UndoneMaps 22633072 # Number of HB maps that are undone due to squashing 479system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed 480system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed 481system.cpu.rename.skidInsts 21514760 # count of insts added to the skid buffer 482system.cpu.memDep0.insertedLoads 26805262 # Number of loads inserted to the mem dependence unit. 483system.cpu.memDep0.insertedStores 5347320 # Number of stores inserted to the mem dependence unit. 484system.cpu.memDep0.conflictingLoads 521988 # Number of conflicting loads. 485system.cpu.memDep0.conflictingStores 256188 # Number of conflicting stores. 486system.cpu.iq.iqInstsAdded 109667585 # Number of instructions added to the IQ (excludes non-spec) 487system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ 488system.cpu.iq.iqInstsIssued 101366888 # Number of instructions issued 489system.cpu.iq.iqSquashedInstsIssued 1074694 # Number of squashed instructions issued 490system.cpu.iq.iqSquashedInstsExamined 18634838 # Number of squashed instructions iterated over during squash; mainly for profiling 491system.cpu.iq.iqSquashedOperandsExamined 41670017 # Number of squashed operands that are examined and possibly removed from graph 492system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed 493system.cpu.iq.issued_per_cycle::samples 117285061 # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::mean 0.864278 # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::stdev 0.988233 # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::0 55650042 47.45% 47.45% # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::1 31364266 26.74% 74.19% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::2 22008003 18.76% 92.95% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::3 7064697 6.02% 98.98% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::4 1197740 1.02% 100.00% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::total 117285061 # Number of insts issued each cycle 510system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 511system.cpu.iq.fu_full::IntAlu 9783493 48.67% 48.67% # attempts to use FU when none available 512system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available 513system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available 514system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available 515system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available 516system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available 517system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available 518system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.67% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available 542system.cpu.iq.fu_full::MemRead 9615891 47.83% 96.50% # attempts to use FU when none available 543system.cpu.iq.fu_full::MemWrite 702910 3.50% 100.00% # attempts to use FU when none available 544system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available 545system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available 546system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 547system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 548system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 549system.cpu.iq.FU_type_0::IntAlu 71970995 71.00% 71.00% # Type of FU issued 550system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued 551system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued 552system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued 553system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 71.01% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 71.01% # Type of FU issued 559system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued 580system.cpu.iq.FU_type_0::MemRead 24337764 24.01% 95.02% # Type of FU issued 581system.cpu.iq.FU_type_0::MemWrite 5047220 4.98% 100.00% # Type of FU issued 582system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued 583system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued 584system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 585system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 586system.cpu.iq.FU_type_0::total 101366888 # Type of FU issued 587system.cpu.iq.rate 0.863794 # Inst issue rate 588system.cpu.iq.fu_busy_cnt 20102384 # FU busy when requested 589system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) 590system.cpu.iq.int_inst_queue_reads 341195448 # Number of integer instruction queue reads 591system.cpu.iq.int_inst_queue_writes 128311397 # Number of integer instruction queue writes 592system.cpu.iq.int_inst_queue_wakeup_accesses 99608403 # Number of integer instruction queue wakeup accesses 593system.cpu.iq.fp_inst_queue_reads 467 # Number of floating instruction queue reads 594system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes 595system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses 596system.cpu.iq.int_alu_accesses 121469025 # Number of integer alu accesses 597system.cpu.iq.fp_alu_accesses 247 # Number of floating point alu accesses 598system.cpu.iew.lsq.thread0.forwLoads 288057 # Number of loads that had data forwarded from stores 599system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 600system.cpu.iew.lsq.thread0.squashedLoads 4329351 # Number of loads squashed 601system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed 602system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations 603system.cpu.iew.lsq.thread0.squashedStores 602476 # Number of stores squashed 604system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 605system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 606system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled 607system.cpu.iew.lsq.thread0.cacheBlocked 130798 # Number of times an access to memory failed due to the cache being blocked 608system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 609system.cpu.iew.iewSquashCycles 825429 # Number of cycles IEW is squashing 610system.cpu.iew.iewBlockCycles 8290686 # Number of cycles IEW is blocking 611system.cpu.iew.iewUnblockCycles 768265 # Number of cycles IEW is unblocking 612system.cpu.iew.iewDispatchedInsts 109688691 # Number of instructions dispatched to IQ 613system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 614system.cpu.iew.iewDispLoadInsts 26805262 # Number of dispatched load instructions 615system.cpu.iew.iewDispStoreInsts 5347320 # Number of dispatched store instructions 616system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions 617system.cpu.iew.iewIQFullEvents 180386 # Number of times the IQ has become full, causing a stall 618system.cpu.iew.iewLSQFullEvents 424316 # Number of times the LSQ has become full, causing a stall 619system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations 620system.cpu.iew.predictedTakenIncorrect 435090 # Number of branches that were predicted taken incorrectly 621system.cpu.iew.predictedNotTakenIncorrect 412415 # Number of branches that were predicted not taken incorrectly 622system.cpu.iew.branchMispredicts 847505 # Number of branch mispredicts detected at execute 623system.cpu.iew.iewExecutedInsts 100109953 # Number of executed instructions 624system.cpu.iew.iewExecLoadInsts 23803133 # Number of load instructions executed 625system.cpu.iew.iewExecSquashedInsts 1256935 # Number of squashed instructions skipped in execute 626system.cpu.iew.exec_swp 0 # number of swp insts executed 627system.cpu.iew.exec_nop 12823 # number of nop insts executed 628system.cpu.iew.exec_refs 28718801 # number of memory reference insts executed 629system.cpu.iew.exec_branches 20621332 # Number of branches executed 630system.cpu.iew.exec_stores 4915668 # Number of stores executed 631system.cpu.iew.exec_rate 0.853083 # Inst execution rate 632system.cpu.iew.wb_sent 99693665 # cumulative count of insts sent to commit 633system.cpu.iew.wb_count 99608516 # cumulative count of insts written-back 634system.cpu.iew.wb_producers 59691499 # num instructions producing a value 635system.cpu.iew.wb_consumers 95528314 # num instructions consuming a value 636system.cpu.iew.wb_rate 0.848810 # insts written-back per cycle 637system.cpu.iew.wb_fanout 0.624857 # average fanout of values written-back 638system.cpu.commit.commitSquashedInsts 17363350 # The number of squashed insts skipped by commit 639system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 640system.cpu.commit.branchMispredicts 823717 # The number of times a branch was mispredicted 641system.cpu.commit.committed_per_cycle::samples 114597116 # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::mean 0.794554 # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::stdev 1.732042 # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::0 78173194 68.22% 68.22% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::1 18611100 16.24% 84.46% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::2 7154015 6.24% 90.70% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::3 3469592 3.03% 93.73% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::4 1644807 1.44% 95.16% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::5 541237 0.47% 95.63% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::6 703127 0.61% 96.25% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::7 178794 0.16% 96.40% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::8 4121250 3.60% 100.00% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::total 114597116 # Number of insts commited each cycle 658system.cpu.commit.committedInsts 90602408 # Number of instructions committed 659system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed 660system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 661system.cpu.commit.refs 27220755 # Number of memory references committed 662system.cpu.commit.loads 22475911 # Number of loads committed 663system.cpu.commit.membars 3888 # Number of memory barriers committed 664system.cpu.commit.branches 18732305 # Number of branches committed 665system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 666system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. 667system.cpu.commit.function_calls 56148 # Number of function calls committed. 668system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 669system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction 670system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 671system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 673system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 676system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction 677system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 678system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction 679system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 696system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 697system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 698system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 699system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 700system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction 701system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction 702system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction 703system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction 704system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 705system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 706system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction 707system.cpu.commit.bw_lim_events 4121250 # number cycles where commit BW limit reached 708system.cpu.rob.rob_reads 218887121 # The number of ROB reads 709system.cpu.rob.rob_writes 219522508 # The number of ROB writes 710system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself 711system.cpu.idleCycles 65683 # Total number of cycles that the CPU has spent unscheduled due to idling 712system.cpu.committedInsts 90589799 # Number of Instructions Simulated 713system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated 714system.cpu.cpi 1.295408 # CPI: Cycles Per Instruction 715system.cpu.cpi_total 1.295408 # CPI: Total CPI of All Threads 716system.cpu.ipc 0.771958 # IPC: Instructions Per Cycle 717system.cpu.ipc_total 0.771958 # IPC: Total IPC of All Threads 718system.cpu.int_regfile_reads 108097860 # number of integer regfile reads 719system.cpu.int_regfile_writes 58692141 # number of integer regfile writes 720system.cpu.fp_regfile_reads 58 # number of floating regfile reads 721system.cpu.fp_regfile_writes 93 # number of floating regfile writes 722system.cpu.cc_regfile_reads 369004584 # number of cc regfile reads 723system.cpu.cc_regfile_writes 58686965 # number of cc regfile writes 724system.cpu.misc_regfile_reads 28409767 # number of misc regfile reads 725system.cpu.misc_regfile_writes 7784 # number of misc regfile writes 726system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 727system.cpu.dcache.tags.replacements 5470621 # number of replacements 728system.cpu.dcache.tags.tagsinuse 511.769293 # Cycle average of tags in use 729system.cpu.dcache.tags.total_refs 18249382 # Total number of references to valid blocks. 730system.cpu.dcache.tags.sampled_refs 5471133 # Sample count of references to valid blocks. 731system.cpu.dcache.tags.avg_refs 3.335576 # Average number of references to valid blocks. 732system.cpu.dcache.tags.warmup_cycle 38111500 # Cycle when the warmup percentage was hit. 733system.cpu.dcache.tags.occ_blocks::cpu.data 511.769293 # Average occupied blocks per requestor 734system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy 735system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy 736system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 737system.cpu.dcache.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id 738system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id 739system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 740system.cpu.dcache.tags.tag_accesses 61907171 # Number of tag accesses 741system.cpu.dcache.tags.data_accesses 61907171 # Number of data accesses 742system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 743system.cpu.dcache.ReadReq_hits::cpu.data 13887260 # number of ReadReq hits 744system.cpu.dcache.ReadReq_hits::total 13887260 # number of ReadReq hits 745system.cpu.dcache.WriteReq_hits::cpu.data 4353834 # number of WriteReq hits 746system.cpu.dcache.WriteReq_hits::total 4353834 # number of WriteReq hits 747system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 748system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 749system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits 750system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits 751system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 752system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 753system.cpu.dcache.demand_hits::cpu.data 18241094 # number of demand (read+write) hits 754system.cpu.dcache.demand_hits::total 18241094 # number of demand (read+write) hits 755system.cpu.dcache.overall_hits::cpu.data 18241616 # number of overall hits 756system.cpu.dcache.overall_hits::total 18241616 # number of overall hits 757system.cpu.dcache.ReadReq_misses::cpu.data 9587475 # number of ReadReq misses 758system.cpu.dcache.ReadReq_misses::total 9587475 # number of ReadReq misses 759system.cpu.dcache.WriteReq_misses::cpu.data 381147 # number of WriteReq misses 760system.cpu.dcache.WriteReq_misses::total 381147 # number of WriteReq misses 761system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses 762system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses 763system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses 764system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses 765system.cpu.dcache.demand_misses::cpu.data 9968622 # number of demand (read+write) misses 766system.cpu.dcache.demand_misses::total 9968622 # number of demand (read+write) misses 767system.cpu.dcache.overall_misses::cpu.data 9968629 # number of overall misses 768system.cpu.dcache.overall_misses::total 9968629 # number of overall misses 769system.cpu.dcache.ReadReq_miss_latency::cpu.data 89371349000 # number of ReadReq miss cycles 770system.cpu.dcache.ReadReq_miss_latency::total 89371349000 # number of ReadReq miss cycles 771system.cpu.dcache.WriteReq_miss_latency::cpu.data 4092576700 # number of WriteReq miss cycles 772system.cpu.dcache.WriteReq_miss_latency::total 4092576700 # number of WriteReq miss cycles 773system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles 774system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles 775system.cpu.dcache.demand_miss_latency::cpu.data 93463925700 # number of demand (read+write) miss cycles 776system.cpu.dcache.demand_miss_latency::total 93463925700 # number of demand (read+write) miss cycles 777system.cpu.dcache.overall_miss_latency::cpu.data 93463925700 # number of overall miss cycles 778system.cpu.dcache.overall_miss_latency::total 93463925700 # number of overall miss cycles 779system.cpu.dcache.ReadReq_accesses::cpu.data 23474735 # number of ReadReq accesses(hits+misses) 780system.cpu.dcache.ReadReq_accesses::total 23474735 # number of ReadReq accesses(hits+misses) 781system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 782system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 783system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) 784system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) 785system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 786system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 787system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 788system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 789system.cpu.dcache.demand_accesses::cpu.data 28209716 # number of demand (read+write) accesses 790system.cpu.dcache.demand_accesses::total 28209716 # number of demand (read+write) accesses 791system.cpu.dcache.overall_accesses::cpu.data 28210245 # number of overall (read+write) accesses 792system.cpu.dcache.overall_accesses::total 28210245 # number of overall (read+write) accesses 793system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408417 # miss rate for ReadReq accesses 794system.cpu.dcache.ReadReq_miss_rate::total 0.408417 # miss rate for ReadReq accesses 795system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses 796system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses 797system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses 798system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses 799system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses 800system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses 801system.cpu.dcache.demand_miss_rate::cpu.data 0.353375 # miss rate for demand accesses 802system.cpu.dcache.demand_miss_rate::total 0.353375 # miss rate for demand accesses 803system.cpu.dcache.overall_miss_rate::cpu.data 0.353369 # miss rate for overall accesses 804system.cpu.dcache.overall_miss_rate::total 0.353369 # miss rate for overall accesses 805system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9321.677397 # average ReadReq miss latency 806system.cpu.dcache.ReadReq_avg_miss_latency::total 9321.677397 # average ReadReq miss latency 807system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10737.528303 # average WriteReq miss latency 808system.cpu.dcache.WriteReq_avg_miss_latency::total 10737.528303 # average WriteReq miss latency 809system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency 810system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency 811system.cpu.dcache.demand_avg_miss_latency::cpu.data 9375.811993 # average overall miss latency 812system.cpu.dcache.demand_avg_miss_latency::total 9375.811993 # average overall miss latency 813system.cpu.dcache.overall_avg_miss_latency::cpu.data 9375.805409 # average overall miss latency 814system.cpu.dcache.overall_avg_miss_latency::total 9375.805409 # average overall miss latency 815system.cpu.dcache.blocked_cycles::no_mshrs 331977 # number of cycles access was blocked 816system.cpu.dcache.blocked_cycles::no_targets 129797 # number of cycles access was blocked 817system.cpu.dcache.blocked::no_mshrs 121610 # number of cycles access was blocked 818system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked 819system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.729850 # average number of cycles each access was blocked 820system.cpu.dcache.avg_blocked_cycles::no_targets 10.108801 # average number of cycles each access was blocked 821system.cpu.dcache.writebacks::writebacks 5470621 # number of writebacks 822system.cpu.dcache.writebacks::total 5470621 # number of writebacks 823system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338830 # number of ReadReq MSHR hits 824system.cpu.dcache.ReadReq_mshr_hits::total 4338830 # number of ReadReq MSHR hits 825system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158660 # number of WriteReq MSHR hits 826system.cpu.dcache.WriteReq_mshr_hits::total 158660 # number of WriteReq MSHR hits 827system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits 828system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits 829system.cpu.dcache.demand_mshr_hits::cpu.data 4497490 # number of demand (read+write) MSHR hits 830system.cpu.dcache.demand_mshr_hits::total 4497490 # number of demand (read+write) MSHR hits 831system.cpu.dcache.overall_mshr_hits::cpu.data 4497490 # number of overall MSHR hits 832system.cpu.dcache.overall_mshr_hits::total 4497490 # number of overall MSHR hits 833system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248645 # number of ReadReq MSHR misses 834system.cpu.dcache.ReadReq_mshr_misses::total 5248645 # number of ReadReq MSHR misses 835system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses 836system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses 837system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses 838system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses 839system.cpu.dcache.demand_mshr_misses::cpu.data 5471132 # number of demand (read+write) MSHR misses 840system.cpu.dcache.demand_mshr_misses::total 5471132 # number of demand (read+write) MSHR misses 841system.cpu.dcache.overall_mshr_misses::cpu.data 5471136 # number of overall MSHR misses 842system.cpu.dcache.overall_mshr_misses::total 5471136 # number of overall MSHR misses 843system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817219500 # number of ReadReq MSHR miss cycles 844system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817219500 # number of ReadReq MSHR miss cycles 845system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2296823105 # number of WriteReq MSHR miss cycles 846system.cpu.dcache.WriteReq_mshr_miss_latency::total 2296823105 # number of WriteReq MSHR miss cycles 847system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles 848system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles 849system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46114042605 # number of demand (read+write) MSHR miss cycles 850system.cpu.dcache.demand_mshr_miss_latency::total 46114042605 # number of demand (read+write) MSHR miss cycles 851system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46114278105 # number of overall MSHR miss cycles 852system.cpu.dcache.overall_mshr_miss_latency::total 46114278105 # number of overall MSHR miss cycles 853system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223587 # mshr miss rate for ReadReq accesses 854system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223587 # mshr miss rate for ReadReq accesses 855system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses 856system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses 857system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses 858system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses 859system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193945 # mshr miss rate for demand accesses 860system.cpu.dcache.demand_mshr_miss_rate::total 0.193945 # mshr miss rate for demand accesses 861system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193941 # mshr miss rate for overall accesses 862system.cpu.dcache.overall_mshr_miss_rate::total 0.193941 # mshr miss rate for overall accesses 863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.291702 # average ReadReq mshr miss latency 864system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.291702 # average ReadReq mshr miss latency 865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10323.403637 # average WriteReq mshr miss latency 866system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10323.403637 # average WriteReq mshr miss latency 867system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency 868system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency 869system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8428.610862 # average overall mshr miss latency 870system.cpu.dcache.demand_avg_mshr_miss_latency::total 8428.610862 # average overall mshr miss latency 871system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8428.647744 # average overall mshr miss latency 872system.cpu.dcache.overall_avg_mshr_miss_latency::total 8428.647744 # average overall mshr miss latency 873system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 874system.cpu.icache.tags.replacements 448 # number of replacements 875system.cpu.icache.tags.tagsinuse 427.600534 # Cycle average of tags in use 876system.cpu.icache.tags.total_refs 32274508 # Total number of references to valid blocks. 877system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. 878system.cpu.icache.tags.avg_refs 35623.077263 # Average number of references to valid blocks. 879system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 880system.cpu.icache.tags.occ_blocks::cpu.inst 427.600534 # Average occupied blocks per requestor 881system.cpu.icache.tags.occ_percent::cpu.inst 0.835157 # Average percentage of cache occupancy 882system.cpu.icache.tags.occ_percent::total 0.835157 # Average percentage of cache occupancy 883system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id 884system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 885system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 886system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id 887system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id 888system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id 889system.cpu.icache.tags.tag_accesses 64552224 # Number of tag accesses 890system.cpu.icache.tags.data_accesses 64552224 # Number of data accesses 891system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 892system.cpu.icache.ReadReq_hits::cpu.inst 32274508 # number of ReadReq hits 893system.cpu.icache.ReadReq_hits::total 32274508 # number of ReadReq hits 894system.cpu.icache.demand_hits::cpu.inst 32274508 # number of demand (read+write) hits 895system.cpu.icache.demand_hits::total 32274508 # number of demand (read+write) hits 896system.cpu.icache.overall_hits::cpu.inst 32274508 # number of overall hits 897system.cpu.icache.overall_hits::total 32274508 # number of overall hits 898system.cpu.icache.ReadReq_misses::cpu.inst 1151 # number of ReadReq misses 899system.cpu.icache.ReadReq_misses::total 1151 # number of ReadReq misses 900system.cpu.icache.demand_misses::cpu.inst 1151 # number of demand (read+write) misses 901system.cpu.icache.demand_misses::total 1151 # number of demand (read+write) misses 902system.cpu.icache.overall_misses::cpu.inst 1151 # number of overall misses 903system.cpu.icache.overall_misses::total 1151 # number of overall misses 904system.cpu.icache.ReadReq_miss_latency::cpu.inst 79113980 # number of ReadReq miss cycles 905system.cpu.icache.ReadReq_miss_latency::total 79113980 # number of ReadReq miss cycles 906system.cpu.icache.demand_miss_latency::cpu.inst 79113980 # number of demand (read+write) miss cycles 907system.cpu.icache.demand_miss_latency::total 79113980 # number of demand (read+write) miss cycles 908system.cpu.icache.overall_miss_latency::cpu.inst 79113980 # number of overall miss cycles 909system.cpu.icache.overall_miss_latency::total 79113980 # number of overall miss cycles 910system.cpu.icache.ReadReq_accesses::cpu.inst 32275659 # number of ReadReq accesses(hits+misses) 911system.cpu.icache.ReadReq_accesses::total 32275659 # number of ReadReq accesses(hits+misses) 912system.cpu.icache.demand_accesses::cpu.inst 32275659 # number of demand (read+write) accesses 913system.cpu.icache.demand_accesses::total 32275659 # number of demand (read+write) accesses 914system.cpu.icache.overall_accesses::cpu.inst 32275659 # number of overall (read+write) accesses 915system.cpu.icache.overall_accesses::total 32275659 # number of overall (read+write) accesses 916system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses 917system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses 918system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses 919system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses 920system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses 921system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses 922system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68734.995656 # average ReadReq miss latency 923system.cpu.icache.ReadReq_avg_miss_latency::total 68734.995656 # average ReadReq miss latency 924system.cpu.icache.demand_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency 925system.cpu.icache.demand_avg_miss_latency::total 68734.995656 # average overall miss latency 926system.cpu.icache.overall_avg_miss_latency::cpu.inst 68734.995656 # average overall miss latency 927system.cpu.icache.overall_avg_miss_latency::total 68734.995656 # average overall miss latency 928system.cpu.icache.blocked_cycles::no_mshrs 21173 # number of cycles access was blocked 929system.cpu.icache.blocked_cycles::no_targets 759 # number of cycles access was blocked 930system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked 931system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked 932system.cpu.icache.avg_blocked_cycles::no_mshrs 94.102222 # average number of cycles each access was blocked 933system.cpu.icache.avg_blocked_cycles::no_targets 126.500000 # average number of cycles each access was blocked 934system.cpu.icache.writebacks::writebacks 448 # number of writebacks 935system.cpu.icache.writebacks::total 448 # number of writebacks 936system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits 937system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits 938system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits 939system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits 940system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits 941system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits 942system.cpu.icache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses 943system.cpu.icache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses 944system.cpu.icache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses 945system.cpu.icache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses 946system.cpu.icache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses 947system.cpu.icache.overall_mshr_misses::total 907 # number of overall MSHR misses 948system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60405484 # number of ReadReq MSHR miss cycles 949system.cpu.icache.ReadReq_mshr_miss_latency::total 60405484 # number of ReadReq MSHR miss cycles 950system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60405484 # number of demand (read+write) MSHR miss cycles 951system.cpu.icache.demand_mshr_miss_latency::total 60405484 # number of demand (read+write) MSHR miss cycles 952system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60405484 # number of overall MSHR miss cycles 953system.cpu.icache.overall_mshr_miss_latency::total 60405484 # number of overall MSHR miss cycles 954system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 955system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 956system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 957system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 958system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 959system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 960system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66599.210584 # average ReadReq mshr miss latency 961system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66599.210584 # average ReadReq mshr miss latency 962system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency 963system.cpu.icache.demand_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency 964system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66599.210584 # average overall mshr miss latency 965system.cpu.icache.overall_avg_mshr_miss_latency::total 66599.210584 # average overall mshr miss latency 966system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 967system.cpu.l2cache.prefetcher.num_hwpf_issued 4988856 # number of hwpf issued 968system.cpu.l2cache.prefetcher.pfIdentified 5295771 # number of prefetch candidates identified 969system.cpu.l2cache.prefetcher.pfBufferHit 266816 # number of redundant prefetches already in prefetch queue 970system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 971system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 972system.cpu.l2cache.prefetcher.pfSpanPage 14074045 # number of prefetches not generated due to page crossing 973system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 974system.cpu.l2cache.tags.replacements 140 # number of replacements 975system.cpu.l2cache.tags.tagsinuse 11212.925557 # Cycle average of tags in use 976system.cpu.l2cache.tags.total_refs 5291618 # Total number of references to valid blocks. 977system.cpu.l2cache.tags.sampled_refs 14696 # Sample count of references to valid blocks. 978system.cpu.l2cache.tags.avg_refs 360.071992 # Average number of references to valid blocks. 979system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 980system.cpu.l2cache.tags.occ_blocks::writebacks 11154.278216 # Average occupied blocks per requestor 981system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 58.647341 # Average occupied blocks per requestor 982system.cpu.l2cache.tags.occ_percent::writebacks 0.680803 # Average percentage of cache occupancy 983system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003580 # Average percentage of cache occupancy 984system.cpu.l2cache.tags.occ_percent::total 0.684383 # Average percentage of cache occupancy 985system.cpu.l2cache.tags.occ_task_id_blocks::1022 60 # Occupied blocks per task id 986system.cpu.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id 987system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 988system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 989system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1024::0 477 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3389 # Occupied blocks per task id 992system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9672 # Occupied blocks per task id 993system.cpu.l2cache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id 994system.cpu.l2cache.tags.age_task_id_blocks_1024::4 839 # Occupied blocks per task id 995system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003662 # Percentage of cache occupancy per task id 996system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id 997system.cpu.l2cache.tags.tag_accesses 180525801 # Number of tag accesses 998system.cpu.l2cache.tags.data_accesses 180525801 # Number of data accesses 999system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 1000system.cpu.l2cache.WritebackDirty_hits::writebacks 5457281 # number of WritebackDirty hits 1001system.cpu.l2cache.WritebackDirty_hits::total 5457281 # number of WritebackDirty hits 1002system.cpu.l2cache.WritebackClean_hits::writebacks 10913 # number of WritebackClean hits 1003system.cpu.l2cache.WritebackClean_hits::total 10913 # number of WritebackClean hits 1004system.cpu.l2cache.ReadExReq_hits::cpu.data 226015 # number of ReadExReq hits 1005system.cpu.l2cache.ReadExReq_hits::total 226015 # number of ReadExReq hits 1006system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 206 # number of ReadCleanReq hits 1007system.cpu.l2cache.ReadCleanReq_hits::total 206 # number of ReadCleanReq hits 1008system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5241513 # number of ReadSharedReq hits 1009system.cpu.l2cache.ReadSharedReq_hits::total 5241513 # number of ReadSharedReq hits 1010system.cpu.l2cache.demand_hits::cpu.inst 206 # number of demand (read+write) hits 1011system.cpu.l2cache.demand_hits::cpu.data 5467528 # number of demand (read+write) hits 1012system.cpu.l2cache.demand_hits::total 5467734 # number of demand (read+write) hits 1013system.cpu.l2cache.overall_hits::cpu.inst 206 # number of overall hits 1014system.cpu.l2cache.overall_hits::cpu.data 5467528 # number of overall hits 1015system.cpu.l2cache.overall_hits::total 5467734 # number of overall hits 1016system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses 1017system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses 1018system.cpu.l2cache.ReadExReq_misses::cpu.data 505 # number of ReadExReq misses 1019system.cpu.l2cache.ReadExReq_misses::total 505 # number of ReadExReq misses 1020system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses 1021system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses 1022system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3100 # number of ReadSharedReq misses 1023system.cpu.l2cache.ReadSharedReq_misses::total 3100 # number of ReadSharedReq misses 1024system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses 1025system.cpu.l2cache.demand_misses::cpu.data 3605 # number of demand (read+write) misses 1026system.cpu.l2cache.demand_misses::total 4306 # number of demand (read+write) misses 1027system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses 1028system.cpu.l2cache.overall_misses::cpu.data 3605 # number of overall misses 1029system.cpu.l2cache.overall_misses::total 4306 # number of overall misses 1030system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 63500 # number of UpgradeReq miss cycles 1031system.cpu.l2cache.UpgradeReq_miss_latency::total 63500 # number of UpgradeReq miss cycles 1032system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64129500 # number of ReadExReq miss cycles 1033system.cpu.l2cache.ReadExReq_miss_latency::total 64129500 # number of ReadExReq miss cycles 1034system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58109500 # number of ReadCleanReq miss cycles 1035system.cpu.l2cache.ReadCleanReq_miss_latency::total 58109500 # number of ReadCleanReq miss cycles 1036system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 616309000 # number of ReadSharedReq miss cycles 1037system.cpu.l2cache.ReadSharedReq_miss_latency::total 616309000 # number of ReadSharedReq miss cycles 1038system.cpu.l2cache.demand_miss_latency::cpu.inst 58109500 # number of demand (read+write) miss cycles 1039system.cpu.l2cache.demand_miss_latency::cpu.data 680438500 # number of demand (read+write) miss cycles 1040system.cpu.l2cache.demand_miss_latency::total 738548000 # number of demand (read+write) miss cycles 1041system.cpu.l2cache.overall_miss_latency::cpu.inst 58109500 # number of overall miss cycles 1042system.cpu.l2cache.overall_miss_latency::cpu.data 680438500 # number of overall miss cycles 1043system.cpu.l2cache.overall_miss_latency::total 738548000 # number of overall miss cycles 1044system.cpu.l2cache.WritebackDirty_accesses::writebacks 5457281 # number of WritebackDirty accesses(hits+misses) 1045system.cpu.l2cache.WritebackDirty_accesses::total 5457281 # number of WritebackDirty accesses(hits+misses) 1046system.cpu.l2cache.WritebackClean_accesses::writebacks 10913 # number of WritebackClean accesses(hits+misses) 1047system.cpu.l2cache.WritebackClean_accesses::total 10913 # number of WritebackClean accesses(hits+misses) 1048system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) 1049system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) 1050system.cpu.l2cache.ReadExReq_accesses::cpu.data 226520 # number of ReadExReq accesses(hits+misses) 1051system.cpu.l2cache.ReadExReq_accesses::total 226520 # number of ReadExReq accesses(hits+misses) 1052system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 907 # number of ReadCleanReq accesses(hits+misses) 1053system.cpu.l2cache.ReadCleanReq_accesses::total 907 # number of ReadCleanReq accesses(hits+misses) 1054system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244613 # number of ReadSharedReq accesses(hits+misses) 1055system.cpu.l2cache.ReadSharedReq_accesses::total 5244613 # number of ReadSharedReq accesses(hits+misses) 1056system.cpu.l2cache.demand_accesses::cpu.inst 907 # number of demand (read+write) accesses 1057system.cpu.l2cache.demand_accesses::cpu.data 5471133 # number of demand (read+write) accesses 1058system.cpu.l2cache.demand_accesses::total 5472040 # number of demand (read+write) accesses 1059system.cpu.l2cache.overall_accesses::cpu.inst 907 # number of overall (read+write) accesses 1060system.cpu.l2cache.overall_accesses::cpu.data 5471133 # number of overall (read+write) accesses 1061system.cpu.l2cache.overall_accesses::total 5472040 # number of overall (read+write) accesses 1062system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1063system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1064system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002229 # miss rate for ReadExReq accesses 1065system.cpu.l2cache.ReadExReq_miss_rate::total 0.002229 # miss rate for ReadExReq accesses 1066system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.772878 # miss rate for ReadCleanReq accesses 1067system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.772878 # miss rate for ReadCleanReq accesses 1068system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000591 # miss rate for ReadSharedReq accesses 1069system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000591 # miss rate for ReadSharedReq accesses 1070system.cpu.l2cache.demand_miss_rate::cpu.inst 0.772878 # miss rate for demand accesses 1071system.cpu.l2cache.demand_miss_rate::cpu.data 0.000659 # miss rate for demand accesses 1072system.cpu.l2cache.demand_miss_rate::total 0.000787 # miss rate for demand accesses 1073system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772878 # miss rate for overall accesses 1074system.cpu.l2cache.overall_miss_rate::cpu.data 0.000659 # miss rate for overall accesses 1075system.cpu.l2cache.overall_miss_rate::total 0.000787 # miss rate for overall accesses 1076system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21166.666667 # average UpgradeReq miss latency 1077system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21166.666667 # average UpgradeReq miss latency 1078system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 126989.108911 # average ReadExReq miss latency 1079system.cpu.l2cache.ReadExReq_avg_miss_latency::total 126989.108911 # average ReadExReq miss latency 1080system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82895.149786 # average ReadCleanReq miss latency 1081system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82895.149786 # average ReadCleanReq miss latency 1082system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198809.354839 # average ReadSharedReq miss latency 1083system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198809.354839 # average ReadSharedReq miss latency 1084system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency 1085system.cpu.l2cache.demand_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency 1086system.cpu.l2cache.demand_avg_miss_latency::total 171516.024152 # average overall miss latency 1087system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82895.149786 # average overall miss latency 1088system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188748.543689 # average overall miss latency 1089system.cpu.l2cache.overall_avg_miss_latency::total 171516.024152 # average overall miss latency 1090system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1091system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1092system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1093system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1094system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1095system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1096system.cpu.l2cache.unused_prefetches 3 # number of HardPF blocks evicted w/o reference 1097system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks 1098system.cpu.l2cache.writebacks::total 104 # number of writebacks 1099system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits 1100system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits 1101system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1102system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1103system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits 1104system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits 1105system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1106system.cpu.l2cache.demand_mshr_hits::cpu.data 194 # number of demand (read+write) MSHR hits 1107system.cpu.l2cache.demand_mshr_hits::total 195 # number of demand (read+write) MSHR hits 1108system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1109system.cpu.l2cache.overall_mshr_hits::cpu.data 194 # number of overall MSHR hits 1110system.cpu.l2cache.overall_mshr_hits::total 195 # number of overall MSHR hits 1111system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316848 # number of HardPFReq MSHR misses 1112system.cpu.l2cache.HardPFReq_mshr_misses::total 316848 # number of HardPFReq MSHR misses 1113system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses 1114system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses 1115system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 343 # number of ReadExReq MSHR misses 1116system.cpu.l2cache.ReadExReq_mshr_misses::total 343 # number of ReadExReq MSHR misses 1117system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses 1118system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses 1119system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3068 # number of ReadSharedReq MSHR misses 1120system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3068 # number of ReadSharedReq MSHR misses 1121system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses 1122system.cpu.l2cache.demand_mshr_misses::cpu.data 3411 # number of demand (read+write) MSHR misses 1123system.cpu.l2cache.demand_mshr_misses::total 4111 # number of demand (read+write) MSHR misses 1124system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses 1125system.cpu.l2cache.overall_mshr_misses::cpu.data 3411 # number of overall MSHR misses 1126system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316848 # number of overall MSHR misses 1127system.cpu.l2cache.overall_mshr_misses::total 320959 # number of overall MSHR misses 1128system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of HardPFReq MSHR miss cycles 1129system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1079223443 # number of HardPFReq MSHR miss cycles 1130system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 45500 # number of UpgradeReq MSHR miss cycles 1131system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 45500 # number of UpgradeReq MSHR miss cycles 1132system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 45646000 # number of ReadExReq MSHR miss cycles 1133system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 45646000 # number of ReadExReq MSHR miss cycles 1134system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53848500 # number of ReadCleanReq MSHR miss cycles 1135system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53848500 # number of ReadCleanReq MSHR miss cycles 1136system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 589212500 # number of ReadSharedReq MSHR miss cycles 1137system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 589212500 # number of ReadSharedReq MSHR miss cycles 1138system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53848500 # number of demand (read+write) MSHR miss cycles 1139system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 634858500 # number of demand (read+write) MSHR miss cycles 1140system.cpu.l2cache.demand_mshr_miss_latency::total 688707000 # number of demand (read+write) MSHR miss cycles 1141system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53848500 # number of overall MSHR miss cycles 1142system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 634858500 # number of overall MSHR miss cycles 1143system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1079223443 # number of overall MSHR miss cycles 1144system.cpu.l2cache.overall_mshr_miss_latency::total 1767930443 # number of overall MSHR miss cycles 1145system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1146system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1147system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1148system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1149system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses 1150system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses 1151system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for ReadCleanReq accesses 1152system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.771775 # mshr miss rate for ReadCleanReq accesses 1153system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000585 # mshr miss rate for ReadSharedReq accesses 1154system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000585 # mshr miss rate for ReadSharedReq accesses 1155system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for demand accesses 1156system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for demand accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::total 0.000751 # mshr miss rate for demand accesses 1158system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.771775 # mshr miss rate for overall accesses 1159system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000623 # mshr miss rate for overall accesses 1160system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1161system.cpu.l2cache.overall_mshr_miss_rate::total 0.058654 # mshr miss rate for overall accesses 1162system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average HardPFReq mshr miss latency 1163system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3406.123577 # average HardPFReq mshr miss latency 1164system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15166.666667 # average UpgradeReq mshr miss latency 1165system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15166.666667 # average UpgradeReq mshr miss latency 1166system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 133078.717201 # average ReadExReq mshr miss latency 1167system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 133078.717201 # average ReadExReq mshr miss latency 1168system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76926.428571 # average ReadCleanReq mshr miss latency 1169system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76926.428571 # average ReadCleanReq mshr miss latency 1170system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192051.010430 # average ReadSharedReq mshr miss latency 1171system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192051.010430 # average ReadSharedReq mshr miss latency 1172system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency 1173system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency 1174system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167527.852104 # average overall mshr miss latency 1175system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76926.428571 # average overall mshr miss latency 1176system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 186120.932278 # average overall mshr miss latency 1177system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3406.123577 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5508.275023 # average overall mshr miss latency 1179system.cpu.toL2Bus.snoop_filter.tot_requests 10943112 # Total number of requests made to the snoop filter. 1180system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471085 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1181system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1182system.cpu.toL2Bus.snoop_filter.tot_snoops 302425 # Total number of snoops made to the snoop filter. 1183system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302424 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1184system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1185system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 1186system.cpu.toL2Bus.trans_dist::ReadResp 5245519 # Transaction distribution 1187system.cpu.toL2Bus.trans_dist::WritebackDirty 5457385 # Transaction distribution 1188system.cpu.toL2Bus.trans_dist::WritebackClean 13788 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::CleanEvict 36 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::HardPFReq 318720 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::ReadExReq 226520 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::ReadExResp 226520 # Transaction distribution 1196system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244613 # Transaction distribution 1198system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes) 1199system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412897 # Packet count per connected master and slave (bytes) 1200system.cpu.toL2Bus.pkt_count::total 16415158 # Packet count per connected master and slave (bytes) 1201system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes) 1202system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700272512 # Cumulative packet size per connected master and slave (bytes) 1203system.cpu.toL2Bus.pkt_size::total 700359168 # Cumulative packet size per connected master and slave (bytes) 1204system.cpu.toL2Bus.snoops 318864 # Total snoops (count) 1205system.cpu.toL2Bus.snoopTraffic 6912 # Total snoop traffic (bytes) 1206system.cpu.toL2Bus.snoop_fanout::samples 5790903 # Request fanout histogram 1207system.cpu.toL2Bus.snoop_fanout::mean 0.052723 # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::stdev 0.223481 # Request fanout histogram 1209system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1210system.cpu.toL2Bus.snoop_fanout::0 5485590 94.73% 94.73% # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::1 305312 5.27% 100.00% # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1213system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1214system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1215system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1216system.cpu.toL2Bus.snoop_fanout::total 5790903 # Request fanout histogram 1217system.cpu.toL2Bus.reqLayer0.occupancy 10942625015 # Layer occupancy (ticks) 1218system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%) 1219system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) 1220system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1221system.cpu.toL2Bus.respLayer0.occupancy 1360996 # Layer occupancy (ticks) 1222system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1223system.cpu.toL2Bus.respLayer1.occupancy 8206704493 # Layer occupancy (ticks) 1224system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) 1225system.membus.snoop_filter.tot_requests 18677 # Total number of requests made to the snoop filter. 1226system.membus.snoop_filter.hit_single_requests 3023 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1227system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1228system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1229system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1230system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1231system.membus.pwrStateResidencyTicks::UNDEFINED 58675371500 # Cumulative time (in ticks) in various power states 1232system.membus.trans_dist::ReadResp 18190 # Transaction distribution 1233system.membus.trans_dist::WritebackDirty 104 # Transaction distribution 1234system.membus.trans_dist::CleanEvict 36 # Transaction distribution 1235system.membus.trans_dist::UpgradeReq 4 # Transaction distribution 1236system.membus.trans_dist::ReadExReq 342 # Transaction distribution 1237system.membus.trans_dist::ReadExResp 342 # Transaction distribution 1238system.membus.trans_dist::ReadSharedReq 18191 # Transaction distribution 1239system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37209 # Packet count per connected master and slave (bytes) 1240system.membus.pkt_count::total 37209 # Packet count per connected master and slave (bytes) 1241system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192704 # Cumulative packet size per connected master and slave (bytes) 1242system.membus.pkt_size::total 1192704 # Cumulative packet size per connected master and slave (bytes) 1243system.membus.snoops 0 # Total snoops (count) 1244system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1245system.membus.snoop_fanout::samples 18537 # Request fanout histogram 1246system.membus.snoop_fanout::mean 0 # Request fanout histogram 1247system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1248system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1249system.membus.snoop_fanout::0 18537 100.00% 100.00% # Request fanout histogram 1250system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1251system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1252system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1253system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1254system.membus.snoop_fanout::total 18537 # Request fanout histogram 1255system.membus.reqLayer0.occupancy 29625930 # Layer occupancy (ticks) 1256system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 1257system.membus.respLayer1.occupancy 97326818 # Layer occupancy (ticks) 1258system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1259 1260---------- End Simulation Statistics ---------- 1261