stats.txt revision 10352:5f1f92bf76ee
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026367 # Number of seconds simulated 4sim_ticks 26367385000 # Number of ticks simulated 5final_tick 26367385000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 125019 # Simulator instruction rate (inst/s) 8host_op_rate 125641 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36388385 # Simulator tick rate (ticks/s) 10host_mem_usage 387112 # Number of bytes of host memory used 11host_seconds 724.61 # Real time elapsed on the host 12sim_insts 90589798 # Number of instructions simulated 13sim_ops 91041029 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 44608 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 947840 # Number of bytes read from this memory 18system.physmem.bytes_read::total 992448 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 44608 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 44608 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 697 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14810 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1691787 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 35947440 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 37639227 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1691787 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1691787 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1691787 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 35947440 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 37639227 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 15507 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 15507 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 992448 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 992448 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 989 # Per bank write bursts 45system.physmem.perBankRdBursts::1 884 # Per bank write bursts 46system.physmem.perBankRdBursts::2 939 # Per bank write bursts 47system.physmem.perBankRdBursts::3 1031 # Per bank write bursts 48system.physmem.perBankRdBursts::4 1047 # Per bank write bursts 49system.physmem.perBankRdBursts::5 1105 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1078 # Per bank write bursts 51system.physmem.perBankRdBursts::7 1078 # Per bank write bursts 52system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 53system.physmem.perBankRdBursts::9 961 # Per bank write bursts 54system.physmem.perBankRdBursts::10 931 # Per bank write bursts 55system.physmem.perBankRdBursts::11 899 # Per bank write bursts 56system.physmem.perBankRdBursts::12 906 # Per bank write bursts 57system.physmem.perBankRdBursts::13 864 # Per bank write bursts 58system.physmem.perBankRdBursts::14 875 # Per bank write bursts 59system.physmem.perBankRdBursts::15 896 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 26367229500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 15507 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 9831 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 5064 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 594 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 734.553002 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 545.014262 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 382.702300 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 137 10.16% 10.16% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 142 10.53% 20.68% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 57 4.23% 24.91% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 62 4.60% 29.50% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 68 5.04% 34.54% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 37 2.74% 37.29% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 30 2.22% 39.51% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 28 2.08% 41.59% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 788 58.41% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation 203system.physmem.totQLat 76352250 # Total ticks spent queuing 204system.physmem.totMemAccLat 367108500 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 77535000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 4923.73 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 23673.73 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 37.64 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 37.64 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.29 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 14147 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 91.23 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 1700343.68 # Average gap between requests 224system.physmem.pageHitRate 91.23 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 23819655750 # Time in different power states 226system.physmem.memoryStateTime::REF 880360000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 1664500500 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 37639227 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 969 # Transaction distribution 232system.membus.trans_dist::ReadResp 969 # Transaction distribution 233system.membus.trans_dist::UpgradeReq 3 # Transaction distribution 234system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 235system.membus.trans_dist::ReadExReq 14538 # Transaction distribution 236system.membus.trans_dist::ReadExResp 14538 # Transaction distribution 237system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31020 # Packet count per connected master and slave (bytes) 238system.membus.pkt_count::total 31020 # Packet count per connected master and slave (bytes) 239system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992448 # Cumulative packet size per connected master and slave (bytes) 240system.membus.tot_pkt_size::total 992448 # Cumulative packet size per connected master and slave (bytes) 241system.membus.data_through_bus 992448 # Total data (bytes) 242system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 243system.membus.reqLayer0.occupancy 18431500 # Layer occupancy (ticks) 244system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 245system.membus.respLayer1.occupancy 144905497 # Layer occupancy (ticks) 246system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 247system.cpu_clk_domain.clock 500 # Clock period in ticks 248system.cpu.branchPred.lookups 29708806 # Number of BP lookups 249system.cpu.branchPred.condPredicted 24486950 # Number of conditional branches predicted 250system.cpu.branchPred.condIncorrect 848073 # Number of conditional branches incorrect 251system.cpu.branchPred.BTBLookups 12459505 # Number of BTB lookups 252system.cpu.branchPred.BTBHits 12380967 # Number of BTB hits 253system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 254system.cpu.branchPred.BTBHitPct 99.369654 # BTB Hit Percentage 255system.cpu.branchPred.usedRAS 77225 # Number of times the RAS was used to get a target. 256system.cpu.branchPred.RASInCorrect 105 # Number of incorrect RAS predictions. 257system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 258system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 259system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 260system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 261system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 262system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 263system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 264system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 265system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 266system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 267system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 268system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 269system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 270system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 271system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 272system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 273system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 274system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 275system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 276system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 277system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 278system.cpu.dtb.inst_hits 0 # ITB inst hits 279system.cpu.dtb.inst_misses 0 # ITB inst misses 280system.cpu.dtb.read_hits 0 # DTB read hits 281system.cpu.dtb.read_misses 0 # DTB read misses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 285system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 286system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 287system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 288system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 289system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 290system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 291system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dtb.read_accesses 0 # DTB read accesses 294system.cpu.dtb.write_accesses 0 # DTB write accesses 295system.cpu.dtb.inst_accesses 0 # ITB inst accesses 296system.cpu.dtb.hits 0 # DTB hits 297system.cpu.dtb.misses 0 # DTB misses 298system.cpu.dtb.accesses 0 # DTB accesses 299system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 300system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 301system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 302system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 303system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 304system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 305system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 306system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 307system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 308system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 309system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 310system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 311system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 312system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 313system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 314system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 315system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 316system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 317system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 318system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 319system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 320system.cpu.itb.inst_hits 0 # ITB inst hits 321system.cpu.itb.inst_misses 0 # ITB inst misses 322system.cpu.itb.read_hits 0 # DTB read hits 323system.cpu.itb.read_misses 0 # DTB read misses 324system.cpu.itb.write_hits 0 # DTB write hits 325system.cpu.itb.write_misses 0 # DTB write misses 326system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 327system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 328system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 329system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 330system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 331system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 332system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 333system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 334system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 335system.cpu.itb.read_accesses 0 # DTB read accesses 336system.cpu.itb.write_accesses 0 # DTB write accesses 337system.cpu.itb.inst_accesses 0 # ITB inst accesses 338system.cpu.itb.hits 0 # DTB hits 339system.cpu.itb.misses 0 # DTB misses 340system.cpu.itb.accesses 0 # DTB accesses 341system.cpu.workload.num_syscalls 442 # Number of system calls 342system.cpu.numCycles 52734771 # number of cpu cycles simulated 343system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 344system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 345system.cpu.fetch.icacheStallCycles 15504828 # Number of cycles fetch is stalled on an Icache miss 346system.cpu.fetch.Insts 141696019 # Number of instructions fetch has processed 347system.cpu.fetch.Branches 29708806 # Number of branches that fetch encountered 348system.cpu.fetch.predictedBranches 12458192 # Number of branches that fetch has predicted taken 349system.cpu.fetch.Cycles 36323119 # Number of cycles fetch has run and was not squashing or blocked 350system.cpu.fetch.SquashCycles 1712998 # Number of cycles fetch has spent squashing 351system.cpu.fetch.MiscStallCycles 10 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 352system.cpu.fetch.PendingTrapStallCycles 5 # Number of stall cycles due to pending traps 353system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR 354system.cpu.fetch.CacheLines 15157439 # Number of cache lines fetched 355system.cpu.fetch.IcacheSquashes 317484 # Number of outstanding Icache misses that were squashed 356system.cpu.fetch.rateDist::samples 52684513 # Number of instructions fetched each cycle (Total) 357system.cpu.fetch.rateDist::mean 2.702798 # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::stdev 3.249702 # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::0 25447326 48.30% 48.30% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::1 3927834 7.46% 55.76% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::2 2643597 5.02% 60.77% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::3 1975703 3.75% 64.52% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::4 2124397 4.03% 68.56% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::5 2942984 5.59% 74.14% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::6 1825722 3.47% 77.61% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::7 1288988 2.45% 80.05% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::8 10507962 19.95% 100.00% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::total 52684513 # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.branchRate 0.563363 # Number of branch fetches per cycle 374system.cpu.fetch.rate 2.686956 # Number of inst fetches per cycle 375system.cpu.decode.IdleCycles 11541183 # Number of cycles decode is idle 376system.cpu.decode.BlockedCycles 18148303 # Number of cycles decode is blocked 377system.cpu.decode.RunCycles 18363246 # Number of cycles decode is running 378system.cpu.decode.UnblockCycles 3783966 # Number of cycles decode is unblocking 379system.cpu.decode.SquashCycles 847815 # Number of cycles decode is squashing 380system.cpu.decode.BranchResolved 4787740 # Number of times decode resolved a branch 381system.cpu.decode.BranchMispred 8797 # Number of times decode detected a branch misprediction 382system.cpu.decode.DecodedInsts 133953704 # Number of instructions handled by decode 383system.cpu.decode.SquashedInsts 39951 # Number of squashed instructions handled by decode 384system.cpu.rename.SquashCycles 847815 # Number of cycles rename is squashing 385system.cpu.rename.IdleCycles 13130783 # Number of cycles rename is idle 386system.cpu.rename.BlockCycles 7261973 # Number of cycles rename is blocking 387system.cpu.rename.serializeStallCycles 198650 # count of cycles rename stalled for serializing inst 388system.cpu.rename.RunCycles 20259912 # Number of cycles rename is running 389system.cpu.rename.UnblockCycles 10985380 # Number of cycles rename is unblocking 390system.cpu.rename.RenamedInsts 130534992 # Number of instructions processed by rename 391system.cpu.rename.ROBFullEvents 3194 # Number of times rename has blocked due to ROB full 392system.cpu.rename.IQFullEvents 4661957 # Number of times rename has blocked due to IQ full 393system.cpu.rename.LQFullEvents 5208173 # Number of times rename has blocked due to LQ full 394system.cpu.rename.SQFullEvents 864876 # Number of times rename has blocked due to SQ full 395system.cpu.rename.RenamedOperands 151632066 # Number of destination operands rename has renamed 396system.cpu.rename.RenameLookups 568616751 # Number of register rename lookups that rename has made 397system.cpu.rename.int_rename_lookups 140291234 # Number of integer rename lookups 398system.cpu.rename.fp_rename_lookups 824 # Number of floating rename lookups 399system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed 400system.cpu.rename.UndoneMaps 44319147 # Number of HB maps that are undone due to squashing 401system.cpu.rename.serializingInsts 4700 # count of serializing insts renamed 402system.cpu.rename.tempSerializingInsts 4700 # count of temporary serializing insts renamed 403system.cpu.rename.skidInsts 18678634 # count of insts added to the skid buffer 404system.cpu.memDep0.insertedLoads 31297749 # Number of loads inserted to the mem dependence unit. 405system.cpu.memDep0.insertedStores 5707560 # Number of stores inserted to the mem dependence unit. 406system.cpu.memDep0.conflictingLoads 2464961 # Number of conflicting loads. 407system.cpu.memDep0.conflictingStores 1558957 # Number of conflicting stores. 408system.cpu.iq.iqInstsAdded 125335435 # Number of instructions added to the IQ (excludes non-spec) 409system.cpu.iq.iqNonSpecInstsAdded 8504 # Number of non-speculative instructions added to the IQ 410system.cpu.iq.iqInstsIssued 107771373 # Number of instructions issued 411system.cpu.iq.iqSquashedInstsIssued 19311 # Number of squashed instructions issued 412system.cpu.iq.iqSquashedInstsExamined 34045700 # Number of squashed instructions iterated over during squash; mainly for profiling 413system.cpu.iq.iqSquashedOperandsExamined 86545264 # Number of squashed operands that are examined and possibly removed from graph 414system.cpu.iq.iqSquashedNonSpecRemoved 286 # Number of squashed non-spec instructions that were removed 415system.cpu.iq.issued_per_cycle::samples 52684513 # Number of insts issued each cycle 416system.cpu.iq.issued_per_cycle::mean 2.045599 # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::stdev 1.948200 # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::0 15278150 29.00% 29.00% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::1 10252049 19.46% 48.46% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::2 8069131 15.32% 63.77% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::3 6193349 11.76% 75.53% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::4 6619102 12.56% 88.09% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::5 3132844 5.95% 94.04% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::6 1926333 3.66% 97.70% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::7 606051 1.15% 98.85% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::8 607504 1.15% 100.00% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::total 52684513 # Number of insts issued each cycle 432system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 433system.cpu.iq.fu_full::IntAlu 313366 33.84% 33.84% # attempts to use FU when none available 434system.cpu.iq.fu_full::IntMult 27 0.00% 33.85% # attempts to use FU when none available 435system.cpu.iq.fu_full::IntDiv 0 0.00% 33.85% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.85% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.85% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.85% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatMult 0 0.00% 33.85% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.85% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.85% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.85% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.85% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.85% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.85% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.85% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.85% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdMult 0 0.00% 33.85% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.85% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdShift 0 0.00% 33.85% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.85% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.85% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.85% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.85% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.85% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.85% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.85% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.85% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.85% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.85% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.85% # attempts to use FU when none available 462system.cpu.iq.fu_full::MemRead 287772 31.08% 64.92% # attempts to use FU when none available 463system.cpu.iq.fu_full::MemWrite 324774 35.08% 100.00% # attempts to use FU when none available 464system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 465system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 466system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 467system.cpu.iq.FU_type_0::IntAlu 76600270 71.08% 71.08% # Type of FU issued 468system.cpu.iq.FU_type_0::IntMult 10764 0.01% 71.09% # Type of FU issued 469system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.09% # Type of FU issued 470system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.09% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.09% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.09% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.09% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.09% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.09% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.09% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.09% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.09% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.09% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.09% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.09% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.09% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.09% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.09% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.09% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.09% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.09% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.09% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 71.09% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatCvt 144 0.00% 71.09% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.09% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatMisc 193 0.00% 71.09% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.09% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 71.09% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.09% # Type of FU issued 496system.cpu.iq.FU_type_0::MemRead 25964378 24.09% 95.18% # Type of FU issued 497system.cpu.iq.FU_type_0::MemWrite 5195603 4.82% 100.00% # Type of FU issued 498system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 499system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 500system.cpu.iq.FU_type_0::total 107771373 # Type of FU issued 501system.cpu.iq.rate 2.043649 # Inst issue rate 502system.cpu.iq.fu_busy_cnt 925939 # FU busy when requested 503system.cpu.iq.fu_busy_rate 0.008592 # FU busy rate (busy events/executed inst) 504system.cpu.iq.int_inst_queue_reads 269171739 # Number of integer instruction queue reads 505system.cpu.iq.int_inst_queue_writes 159396970 # Number of integer instruction queue writes 506system.cpu.iq.int_inst_queue_wakeup_accesses 104914190 # Number of integer instruction queue wakeup accesses 507system.cpu.iq.fp_inst_queue_reads 770 # Number of floating instruction queue reads 508system.cpu.iq.fp_inst_queue_writes 1077 # Number of floating instruction queue writes 509system.cpu.iq.fp_inst_queue_wakeup_accesses 346 # Number of floating instruction queue wakeup accesses 510system.cpu.iq.int_alu_accesses 108696926 # Number of integer alu accesses 511system.cpu.iq.fp_alu_accesses 386 # Number of floating point alu accesses 512system.cpu.iew.lsq.thread0.forwLoads 461125 # Number of loads that had data forwarded from stores 513system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 514system.cpu.iew.lsq.thread0.squashedLoads 8821838 # Number of loads squashed 515system.cpu.iew.lsq.thread0.ignoredResponses 5647 # Number of memory responses ignored because the instruction is squashed 516system.cpu.iew.lsq.thread0.memOrderViolation 8949 # Number of memory ordering violations 517system.cpu.iew.lsq.thread0.squashedStores 962716 # Number of stores squashed 518system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 519system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 520system.cpu.iew.lsq.thread0.rescheduledLoads 15326 # Number of loads that were rescheduled 521system.cpu.iew.lsq.thread0.cacheBlocked 231326 # Number of times an access to memory failed due to the cache being blocked 522system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 523system.cpu.iew.iewSquashCycles 847815 # Number of cycles IEW is squashing 524system.cpu.iew.iewBlockCycles 5127616 # Number of cycles IEW is blocking 525system.cpu.iew.iewUnblockCycles 500104 # Number of cycles IEW is unblocking 526system.cpu.iew.iewDispatchedInsts 125356607 # Number of instructions dispatched to IQ 527system.cpu.iew.iewDispSquashedInsts 320162 # Number of squashed instructions skipped by dispatch 528system.cpu.iew.iewDispLoadInsts 31297749 # Number of dispatched load instructions 529system.cpu.iew.iewDispStoreInsts 5707560 # Number of dispatched store instructions 530system.cpu.iew.iewDispNonSpecInsts 4616 # Number of dispatched non-speculative instructions 531system.cpu.iew.iewIQFullEvents 66442 # Number of times the IQ has become full, causing a stall 532system.cpu.iew.iewLSQFullEvents 385113 # Number of times the LSQ has become full, causing a stall 533system.cpu.iew.memOrderViolationEvents 8949 # Number of memory order violations 534system.cpu.iew.predictedTakenIncorrect 454051 # Number of branches that were predicted taken incorrectly 535system.cpu.iew.predictedNotTakenIncorrect 452935 # Number of branches that were predicted not taken incorrectly 536system.cpu.iew.branchMispredicts 906986 # Number of branch mispredicts detected at execute 537system.cpu.iew.iewExecutedInsts 106740965 # Number of executed instructions 538system.cpu.iew.iewExecLoadInsts 25734173 # Number of load instructions executed 539system.cpu.iew.iewExecSquashedInsts 1030408 # Number of squashed instructions skipped in execute 540system.cpu.iew.exec_swp 0 # number of swp insts executed 541system.cpu.iew.exec_nop 12668 # number of nop insts executed 542system.cpu.iew.exec_refs 30844738 # number of memory reference insts executed 543system.cpu.iew.exec_branches 21924000 # Number of branches executed 544system.cpu.iew.exec_stores 5110565 # Number of stores executed 545system.cpu.iew.exec_rate 2.024110 # Inst execution rate 546system.cpu.iew.wb_sent 105227967 # cumulative count of insts sent to commit 547system.cpu.iew.wb_count 104914536 # cumulative count of insts written-back 548system.cpu.iew.wb_producers 63175597 # num instructions producing a value 549system.cpu.iew.wb_consumers 106448562 # num instructions consuming a value 550system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 551system.cpu.iew.wb_rate 1.989476 # insts written-back per cycle 552system.cpu.iew.wb_fanout 0.593485 # average fanout of values written-back 553system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 554system.cpu.commit.commitSquashedInsts 34317785 # The number of squashed insts skipped by commit 555system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 556system.cpu.commit.branchMispredicts 839389 # The number of times a branch was mispredicted 557system.cpu.commit.committed_per_cycle::samples 47813008 # Number of insts commited each cycle 558system.cpu.commit.committed_per_cycle::mean 1.904370 # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::stdev 2.590937 # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::0 19048029 39.84% 39.84% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::1 12579538 26.31% 66.15% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::2 4065916 8.50% 74.65% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::3 3224325 6.74% 81.40% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::4 1531590 3.20% 84.60% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::5 701376 1.47% 86.07% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::6 1004304 2.10% 88.17% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::7 253211 0.53% 88.70% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::8 5404719 11.30% 100.00% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::total 47813008 # Number of insts commited each cycle 574system.cpu.commit.committedInsts 90602407 # Number of instructions committed 575system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed 576system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 577system.cpu.commit.refs 27220755 # Number of memory references committed 578system.cpu.commit.loads 22475911 # Number of loads committed 579system.cpu.commit.membars 3888 # Number of memory barriers committed 580system.cpu.commit.branches 18732304 # Number of branches committed 581system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 582system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. 583system.cpu.commit.function_calls 56148 # Number of function calls committed. 584system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 585system.cpu.commit.op_class_0::IntAlu 63822386 70.09% 70.09% # Class of committed instruction 586system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 587system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 588system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 589system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 590system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 591system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 592system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 593system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 594system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 595system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 596system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 597system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 598system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 599system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 600system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 601system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 602system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 603system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 604system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 605system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 606system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 607system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 608system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 609system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 610system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 611system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 612system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 613system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 614system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 615system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 616system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 617system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 618system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction 619system.cpu.commit.bw_lim_events 5404719 # number cycles where commit BW limit reached 620system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 621system.cpu.rob.rob_reads 167773978 # The number of ROB reads 622system.cpu.rob.rob_writes 255639290 # The number of ROB writes 623system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself 624system.cpu.idleCycles 50258 # Total number of cycles that the CPU has spent unscheduled due to idling 625system.cpu.committedInsts 90589798 # Number of Instructions Simulated 626system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated 627system.cpu.cpi 0.582127 # CPI: Cycles Per Instruction 628system.cpu.cpi_total 0.582127 # CPI: Total CPI of All Threads 629system.cpu.ipc 1.717838 # IPC: Instructions Per Cycle 630system.cpu.ipc_total 1.717838 # IPC: Total IPC of All Threads 631system.cpu.int_regfile_reads 115515398 # number of integer regfile reads 632system.cpu.int_regfile_writes 62074294 # number of integer regfile writes 633system.cpu.fp_regfile_reads 287 # number of floating regfile reads 634system.cpu.fp_regfile_writes 460 # number of floating regfile writes 635system.cpu.cc_regfile_reads 391234324 # number of cc regfile reads 636system.cpu.cc_regfile_writes 61185455 # number of cc regfile writes 637system.cpu.misc_regfile_reads 29410043 # number of misc regfile reads 638system.cpu.misc_regfile_writes 7784 # number of misc regfile writes 639system.cpu.toL2Bus.throughput 4590653188 # Throughput (bytes/s) 640system.cpu.toL2Bus.trans_dist::ReadReq 911002 # Transaction distribution 641system.cpu.toL2Bus.trans_dist::ReadResp 911001 # Transaction distribution 642system.cpu.toL2Bus.trans_dist::Writeback 942911 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::ReadExReq 37393 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::ReadExResp 37393 # Transaction distribution 647system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1448 # Packet count per connected master and slave (bytes) 648system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838257 # Packet count per connected master and slave (bytes) 649system.cpu.toL2Bus.pkt_count::total 2839705 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46144 # Cumulative packet size per connected master and slave (bytes) 651system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120997056 # Cumulative packet size per connected master and slave (bytes) 652system.cpu.toL2Bus.tot_pkt_size::total 121043200 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.data_through_bus 121043200 # Total data (bytes) 654system.cpu.toL2Bus.snoop_data_through_bus 320 # Total snoop data (bytes) 655system.cpu.toL2Bus.reqLayer0.occupancy 1888566500 # Layer occupancy (ticks) 656system.cpu.toL2Bus.reqLayer0.utilization 7.2 # Layer utilization (%) 657system.cpu.toL2Bus.respLayer0.occupancy 1205249 # Layer occupancy (ticks) 658system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 659system.cpu.toL2Bus.respLayer1.occupancy 1424155994 # Layer occupancy (ticks) 660system.cpu.toL2Bus.respLayer1.utilization 5.4 # Layer utilization (%) 661system.cpu.icache.tags.replacements 2 # number of replacements 662system.cpu.icache.tags.tagsinuse 624.324849 # Cycle average of tags in use 663system.cpu.icache.tags.total_refs 15156433 # Total number of references to valid blocks. 664system.cpu.icache.tags.sampled_refs 721 # Sample count of references to valid blocks. 665system.cpu.icache.tags.avg_refs 21021.404993 # Average number of references to valid blocks. 666system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 667system.cpu.icache.tags.occ_blocks::cpu.inst 624.324849 # Average occupied blocks per requestor 668system.cpu.icache.tags.occ_percent::cpu.inst 0.304846 # Average percentage of cache occupancy 669system.cpu.icache.tags.occ_percent::total 0.304846 # Average percentage of cache occupancy 670system.cpu.icache.tags.occ_task_id_blocks::1024 719 # Occupied blocks per task id 671system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 672system.cpu.icache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id 673system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id 674system.cpu.icache.tags.age_task_id_blocks_1024::4 666 # Occupied blocks per task id 675system.cpu.icache.tags.occ_task_id_percent::1024 0.351074 # Percentage of cache occupancy per task id 676system.cpu.icache.tags.tag_accesses 30315604 # Number of tag accesses 677system.cpu.icache.tags.data_accesses 30315604 # Number of data accesses 678system.cpu.icache.ReadReq_hits::cpu.inst 15156433 # number of ReadReq hits 679system.cpu.icache.ReadReq_hits::total 15156433 # number of ReadReq hits 680system.cpu.icache.demand_hits::cpu.inst 15156433 # number of demand (read+write) hits 681system.cpu.icache.demand_hits::total 15156433 # number of demand (read+write) hits 682system.cpu.icache.overall_hits::cpu.inst 15156433 # number of overall hits 683system.cpu.icache.overall_hits::total 15156433 # number of overall hits 684system.cpu.icache.ReadReq_misses::cpu.inst 1006 # number of ReadReq misses 685system.cpu.icache.ReadReq_misses::total 1006 # number of ReadReq misses 686system.cpu.icache.demand_misses::cpu.inst 1006 # number of demand (read+write) misses 687system.cpu.icache.demand_misses::total 1006 # number of demand (read+write) misses 688system.cpu.icache.overall_misses::cpu.inst 1006 # number of overall misses 689system.cpu.icache.overall_misses::total 1006 # number of overall misses 690system.cpu.icache.ReadReq_miss_latency::cpu.inst 68127998 # number of ReadReq miss cycles 691system.cpu.icache.ReadReq_miss_latency::total 68127998 # number of ReadReq miss cycles 692system.cpu.icache.demand_miss_latency::cpu.inst 68127998 # number of demand (read+write) miss cycles 693system.cpu.icache.demand_miss_latency::total 68127998 # number of demand (read+write) miss cycles 694system.cpu.icache.overall_miss_latency::cpu.inst 68127998 # number of overall miss cycles 695system.cpu.icache.overall_miss_latency::total 68127998 # number of overall miss cycles 696system.cpu.icache.ReadReq_accesses::cpu.inst 15157439 # number of ReadReq accesses(hits+misses) 697system.cpu.icache.ReadReq_accesses::total 15157439 # number of ReadReq accesses(hits+misses) 698system.cpu.icache.demand_accesses::cpu.inst 15157439 # number of demand (read+write) accesses 699system.cpu.icache.demand_accesses::total 15157439 # number of demand (read+write) accesses 700system.cpu.icache.overall_accesses::cpu.inst 15157439 # number of overall (read+write) accesses 701system.cpu.icache.overall_accesses::total 15157439 # number of overall (read+write) accesses 702system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses 703system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses 704system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses 705system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses 706system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses 707system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses 708system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67721.667992 # average ReadReq miss latency 709system.cpu.icache.ReadReq_avg_miss_latency::total 67721.667992 # average ReadReq miss latency 710system.cpu.icache.demand_avg_miss_latency::cpu.inst 67721.667992 # average overall miss latency 711system.cpu.icache.demand_avg_miss_latency::total 67721.667992 # average overall miss latency 712system.cpu.icache.overall_avg_miss_latency::cpu.inst 67721.667992 # average overall miss latency 713system.cpu.icache.overall_avg_miss_latency::total 67721.667992 # average overall miss latency 714system.cpu.icache.blocked_cycles::no_mshrs 475 # number of cycles access was blocked 715system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 716system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked 717system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 718system.cpu.icache.avg_blocked_cycles::no_mshrs 43.181818 # average number of cycles each access was blocked 719system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 720system.cpu.icache.fast_writes 0 # number of fast writes performed 721system.cpu.icache.cache_copies 0 # number of cache copies performed 722system.cpu.icache.ReadReq_mshr_hits::cpu.inst 279 # number of ReadReq MSHR hits 723system.cpu.icache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits 724system.cpu.icache.demand_mshr_hits::cpu.inst 279 # number of demand (read+write) MSHR hits 725system.cpu.icache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits 726system.cpu.icache.overall_mshr_hits::cpu.inst 279 # number of overall MSHR hits 727system.cpu.icache.overall_mshr_hits::total 279 # number of overall MSHR hits 728system.cpu.icache.ReadReq_mshr_misses::cpu.inst 727 # number of ReadReq MSHR misses 729system.cpu.icache.ReadReq_mshr_misses::total 727 # number of ReadReq MSHR misses 730system.cpu.icache.demand_mshr_misses::cpu.inst 727 # number of demand (read+write) MSHR misses 731system.cpu.icache.demand_mshr_misses::total 727 # number of demand (read+write) MSHR misses 732system.cpu.icache.overall_mshr_misses::cpu.inst 727 # number of overall MSHR misses 733system.cpu.icache.overall_mshr_misses::total 727 # number of overall MSHR misses 734system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50452500 # number of ReadReq MSHR miss cycles 735system.cpu.icache.ReadReq_mshr_miss_latency::total 50452500 # number of ReadReq MSHR miss cycles 736system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50452500 # number of demand (read+write) MSHR miss cycles 737system.cpu.icache.demand_mshr_miss_latency::total 50452500 # number of demand (read+write) MSHR miss cycles 738system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50452500 # number of overall MSHR miss cycles 739system.cpu.icache.overall_mshr_miss_latency::total 50452500 # number of overall MSHR miss cycles 740system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for ReadReq accesses 741system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000048 # mshr miss rate for ReadReq accesses 742system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for demand accesses 743system.cpu.icache.demand_mshr_miss_rate::total 0.000048 # mshr miss rate for demand accesses 744system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000048 # mshr miss rate for overall accesses 745system.cpu.icache.overall_mshr_miss_rate::total 0.000048 # mshr miss rate for overall accesses 746system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69398.211829 # average ReadReq mshr miss latency 747system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69398.211829 # average ReadReq mshr miss latency 748system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69398.211829 # average overall mshr miss latency 749system.cpu.icache.demand_avg_mshr_miss_latency::total 69398.211829 # average overall mshr miss latency 750system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69398.211829 # average overall mshr miss latency 751system.cpu.icache.overall_avg_mshr_miss_latency::total 69398.211829 # average overall mshr miss latency 752system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 753system.cpu.l2cache.tags.replacements 0 # number of replacements 754system.cpu.l2cache.tags.tagsinuse 10760.665120 # Cycle average of tags in use 755system.cpu.l2cache.tags.total_refs 1837803 # Total number of references to valid blocks. 756system.cpu.l2cache.tags.sampled_refs 15490 # Sample count of references to valid blocks. 757system.cpu.l2cache.tags.avg_refs 118.644480 # Average number of references to valid blocks. 758system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 759system.cpu.l2cache.tags.occ_blocks::writebacks 9918.109380 # Average occupied blocks per requestor 760system.cpu.l2cache.tags.occ_blocks::cpu.inst 609.591474 # Average occupied blocks per requestor 761system.cpu.l2cache.tags.occ_blocks::cpu.data 232.964266 # Average occupied blocks per requestor 762system.cpu.l2cache.tags.occ_percent::writebacks 0.302677 # Average percentage of cache occupancy 763system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018603 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_percent::cpu.data 0.007110 # Average percentage of cache occupancy 765system.cpu.l2cache.tags.occ_percent::total 0.328389 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_task_id_blocks::1024 15490 # Occupied blocks per task id 767system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 768system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 769system.cpu.l2cache.tags.age_task_id_blocks_1024::2 502 # Occupied blocks per task id 770system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1303 # Occupied blocks per task id 771system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13612 # Occupied blocks per task id 772system.cpu.l2cache.tags.occ_task_id_percent::1024 0.472717 # Percentage of cache occupancy per task id 773system.cpu.l2cache.tags.tag_accesses 15183333 # Number of tag accesses 774system.cpu.l2cache.tags.data_accesses 15183333 # Number of data accesses 775system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits 776system.cpu.l2cache.ReadReq_hits::cpu.data 909994 # number of ReadReq hits 777system.cpu.l2cache.ReadReq_hits::total 910018 # number of ReadReq hits 778system.cpu.l2cache.Writeback_hits::writebacks 942911 # number of Writeback hits 779system.cpu.l2cache.Writeback_hits::total 942911 # number of Writeback hits 780system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits 781system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits 782system.cpu.l2cache.ReadExReq_hits::cpu.data 22855 # number of ReadExReq hits 783system.cpu.l2cache.ReadExReq_hits::total 22855 # number of ReadExReq hits 784system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits 785system.cpu.l2cache.demand_hits::cpu.data 932849 # number of demand (read+write) hits 786system.cpu.l2cache.demand_hits::total 932873 # number of demand (read+write) hits 787system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits 788system.cpu.l2cache.overall_hits::cpu.data 932849 # number of overall hits 789system.cpu.l2cache.overall_hits::total 932873 # number of overall hits 790system.cpu.l2cache.ReadReq_misses::cpu.inst 698 # number of ReadReq misses 791system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses 792system.cpu.l2cache.ReadReq_misses::total 979 # number of ReadReq misses 793system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses 794system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses 795system.cpu.l2cache.ReadExReq_misses::cpu.data 14538 # number of ReadExReq misses 796system.cpu.l2cache.ReadExReq_misses::total 14538 # number of ReadExReq misses 797system.cpu.l2cache.demand_misses::cpu.inst 698 # number of demand (read+write) misses 798system.cpu.l2cache.demand_misses::cpu.data 14819 # number of demand (read+write) misses 799system.cpu.l2cache.demand_misses::total 15517 # number of demand (read+write) misses 800system.cpu.l2cache.overall_misses::cpu.inst 698 # number of overall misses 801system.cpu.l2cache.overall_misses::cpu.data 14819 # number of overall misses 802system.cpu.l2cache.overall_misses::total 15517 # number of overall misses 803system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 49485750 # number of ReadReq miss cycles 804system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20358500 # number of ReadReq miss cycles 805system.cpu.l2cache.ReadReq_miss_latency::total 69844250 # number of ReadReq miss cycles 806system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 967191000 # number of ReadExReq miss cycles 807system.cpu.l2cache.ReadExReq_miss_latency::total 967191000 # number of ReadExReq miss cycles 808system.cpu.l2cache.demand_miss_latency::cpu.inst 49485750 # number of demand (read+write) miss cycles 809system.cpu.l2cache.demand_miss_latency::cpu.data 987549500 # number of demand (read+write) miss cycles 810system.cpu.l2cache.demand_miss_latency::total 1037035250 # number of demand (read+write) miss cycles 811system.cpu.l2cache.overall_miss_latency::cpu.inst 49485750 # number of overall miss cycles 812system.cpu.l2cache.overall_miss_latency::cpu.data 987549500 # number of overall miss cycles 813system.cpu.l2cache.overall_miss_latency::total 1037035250 # number of overall miss cycles 814system.cpu.l2cache.ReadReq_accesses::cpu.inst 722 # number of ReadReq accesses(hits+misses) 815system.cpu.l2cache.ReadReq_accesses::cpu.data 910275 # number of ReadReq accesses(hits+misses) 816system.cpu.l2cache.ReadReq_accesses::total 910997 # number of ReadReq accesses(hits+misses) 817system.cpu.l2cache.Writeback_accesses::writebacks 942911 # number of Writeback accesses(hits+misses) 818system.cpu.l2cache.Writeback_accesses::total 942911 # number of Writeback accesses(hits+misses) 819system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses) 820system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses) 821system.cpu.l2cache.ReadExReq_accesses::cpu.data 37393 # number of ReadExReq accesses(hits+misses) 822system.cpu.l2cache.ReadExReq_accesses::total 37393 # number of ReadExReq accesses(hits+misses) 823system.cpu.l2cache.demand_accesses::cpu.inst 722 # number of demand (read+write) accesses 824system.cpu.l2cache.demand_accesses::cpu.data 947668 # number of demand (read+write) accesses 825system.cpu.l2cache.demand_accesses::total 948390 # number of demand (read+write) accesses 826system.cpu.l2cache.overall_accesses::cpu.inst 722 # number of overall (read+write) accesses 827system.cpu.l2cache.overall_accesses::cpu.data 947668 # number of overall (read+write) accesses 828system.cpu.l2cache.overall_accesses::total 948390 # number of overall (read+write) accesses 829system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.966759 # miss rate for ReadReq accesses 830system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000309 # miss rate for ReadReq accesses 831system.cpu.l2cache.ReadReq_miss_rate::total 0.001075 # miss rate for ReadReq accesses 832system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for UpgradeReq accesses 833system.cpu.l2cache.UpgradeReq_miss_rate::total 0.600000 # miss rate for UpgradeReq accesses 834system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.388789 # miss rate for ReadExReq accesses 835system.cpu.l2cache.ReadExReq_miss_rate::total 0.388789 # miss rate for ReadExReq accesses 836system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966759 # miss rate for demand accesses 837system.cpu.l2cache.demand_miss_rate::cpu.data 0.015637 # miss rate for demand accesses 838system.cpu.l2cache.demand_miss_rate::total 0.016361 # miss rate for demand accesses 839system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966759 # miss rate for overall accesses 840system.cpu.l2cache.overall_miss_rate::cpu.data 0.015637 # miss rate for overall accesses 841system.cpu.l2cache.overall_miss_rate::total 0.016361 # miss rate for overall accesses 842system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70896.489971 # average ReadReq miss latency 843system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72450.177936 # average ReadReq miss latency 844system.cpu.l2cache.ReadReq_avg_miss_latency::total 71342.441267 # average ReadReq miss latency 845system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66528.477095 # average ReadExReq miss latency 846system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66528.477095 # average ReadExReq miss latency 847system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70896.489971 # average overall miss latency 848system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66640.765234 # average overall miss latency 849system.cpu.l2cache.demand_avg_miss_latency::total 66832.200168 # average overall miss latency 850system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70896.489971 # average overall miss latency 851system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66640.765234 # average overall miss latency 852system.cpu.l2cache.overall_avg_miss_latency::total 66832.200168 # average overall miss latency 853system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 854system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 855system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 856system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 857system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 858system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 859system.cpu.l2cache.fast_writes 0 # number of fast writes performed 860system.cpu.l2cache.cache_copies 0 # number of cache copies performed 861system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 862system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits 863system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits 864system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 865system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits 866system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits 867system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 868system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits 869system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits 870system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 697 # number of ReadReq MSHR misses 871system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272 # number of ReadReq MSHR misses 872system.cpu.l2cache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses 873system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses 874system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses 875system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14538 # number of ReadExReq MSHR misses 876system.cpu.l2cache.ReadExReq_mshr_misses::total 14538 # number of ReadExReq MSHR misses 877system.cpu.l2cache.demand_mshr_misses::cpu.inst 697 # number of demand (read+write) MSHR misses 878system.cpu.l2cache.demand_mshr_misses::cpu.data 14810 # number of demand (read+write) MSHR misses 879system.cpu.l2cache.demand_mshr_misses::total 15507 # number of demand (read+write) MSHR misses 880system.cpu.l2cache.overall_mshr_misses::cpu.inst 697 # number of overall MSHR misses 881system.cpu.l2cache.overall_mshr_misses::cpu.data 14810 # number of overall MSHR misses 882system.cpu.l2cache.overall_mshr_misses::total 15507 # number of overall MSHR misses 883system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40695500 # number of ReadReq MSHR miss cycles 884system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16451000 # number of ReadReq MSHR miss cycles 885system.cpu.l2cache.ReadReq_mshr_miss_latency::total 57146500 # number of ReadReq MSHR miss cycles 886system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 30003 # number of UpgradeReq MSHR miss cycles 887system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 30003 # number of UpgradeReq MSHR miss cycles 888system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 785057000 # number of ReadExReq MSHR miss cycles 889system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 785057000 # number of ReadExReq MSHR miss cycles 890system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40695500 # number of demand (read+write) MSHR miss cycles 891system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 801508000 # number of demand (read+write) MSHR miss cycles 892system.cpu.l2cache.demand_mshr_miss_latency::total 842203500 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40695500 # number of overall MSHR miss cycles 894system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 801508000 # number of overall MSHR miss cycles 895system.cpu.l2cache.overall_mshr_miss_latency::total 842203500 # number of overall MSHR miss cycles 896system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965374 # mshr miss rate for ReadReq accesses 897system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000299 # mshr miss rate for ReadReq accesses 898system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001064 # mshr miss rate for ReadReq accesses 899system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses 900system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses 901system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.388789 # mshr miss rate for ReadExReq accesses 902system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.388789 # mshr miss rate for ReadExReq accesses 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965374 # mshr miss rate for demand accesses 904system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for demand accesses 905system.cpu.l2cache.demand_mshr_miss_rate::total 0.016351 # mshr miss rate for demand accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965374 # mshr miss rate for overall accesses 907system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015628 # mshr miss rate for overall accesses 908system.cpu.l2cache.overall_mshr_miss_rate::total 0.016351 # mshr miss rate for overall accesses 909system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58386.657102 # average ReadReq mshr miss latency 910system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60481.617647 # average ReadReq mshr miss latency 911system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58974.716202 # average ReadReq mshr miss latency 912system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 913system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 914system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54000.343926 # average ReadExReq mshr miss latency 915system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54000.343926 # average ReadExReq mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58386.657102 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54119.378798 # average overall mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54311.182047 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58386.657102 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54119.378798 # average overall mshr miss latency 921system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54311.182047 # average overall mshr miss latency 922system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 923system.cpu.dcache.tags.replacements 943572 # number of replacements 924system.cpu.dcache.tags.tagsinuse 3673.474741 # Cycle average of tags in use 925system.cpu.dcache.tags.total_refs 28380480 # Total number of references to valid blocks. 926system.cpu.dcache.tags.sampled_refs 947668 # Sample count of references to valid blocks. 927system.cpu.dcache.tags.avg_refs 29.947703 # Average number of references to valid blocks. 928system.cpu.dcache.tags.warmup_cycle 7812548250 # Cycle when the warmup percentage was hit. 929system.cpu.dcache.tags.occ_blocks::cpu.data 3673.474741 # Average occupied blocks per requestor 930system.cpu.dcache.tags.occ_percent::cpu.data 0.896844 # Average percentage of cache occupancy 931system.cpu.dcache.tags.occ_percent::total 0.896844 # Average percentage of cache occupancy 932system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 933system.cpu.dcache.tags.age_task_id_blocks_1024::0 478 # Occupied blocks per task id 934system.cpu.dcache.tags.age_task_id_blocks_1024::1 3177 # Occupied blocks per task id 935system.cpu.dcache.tags.age_task_id_blocks_1024::2 441 # Occupied blocks per task id 936system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 937system.cpu.dcache.tags.tag_accesses 60432712 # Number of tag accesses 938system.cpu.dcache.tags.data_accesses 60432712 # Number of data accesses 939system.cpu.dcache.ReadReq_hits::cpu.data 23814120 # number of ReadReq hits 940system.cpu.dcache.ReadReq_hits::total 23814120 # number of ReadReq hits 941system.cpu.dcache.WriteReq_hits::cpu.data 4557910 # number of WriteReq hits 942system.cpu.dcache.WriteReq_hits::total 4557910 # number of WriteReq hits 943system.cpu.dcache.SoftPFReq_hits::cpu.data 634 # number of SoftPFReq hits 944system.cpu.dcache.SoftPFReq_hits::total 634 # number of SoftPFReq hits 945system.cpu.dcache.LoadLockedReq_hits::cpu.data 3911 # number of LoadLockedReq hits 946system.cpu.dcache.LoadLockedReq_hits::total 3911 # number of LoadLockedReq hits 947system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 948system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 949system.cpu.dcache.demand_hits::cpu.data 28372030 # number of demand (read+write) hits 950system.cpu.dcache.demand_hits::total 28372030 # number of demand (read+write) hits 951system.cpu.dcache.overall_hits::cpu.data 28372664 # number of overall hits 952system.cpu.dcache.overall_hits::total 28372664 # number of overall hits 953system.cpu.dcache.ReadReq_misses::cpu.data 1184948 # number of ReadReq misses 954system.cpu.dcache.ReadReq_misses::total 1184948 # number of ReadReq misses 955system.cpu.dcache.WriteReq_misses::cpu.data 177071 # number of WriteReq misses 956system.cpu.dcache.WriteReq_misses::total 177071 # number of WriteReq misses 957system.cpu.dcache.SoftPFReq_misses::cpu.data 33 # number of SoftPFReq misses 958system.cpu.dcache.SoftPFReq_misses::total 33 # number of SoftPFReq misses 959system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses 960system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses 961system.cpu.dcache.demand_misses::cpu.data 1362019 # number of demand (read+write) misses 962system.cpu.dcache.demand_misses::total 1362019 # number of demand (read+write) misses 963system.cpu.dcache.overall_misses::cpu.data 1362052 # number of overall misses 964system.cpu.dcache.overall_misses::total 1362052 # number of overall misses 965system.cpu.dcache.ReadReq_miss_latency::cpu.data 14093002232 # number of ReadReq miss cycles 966system.cpu.dcache.ReadReq_miss_latency::total 14093002232 # number of ReadReq miss cycles 967system.cpu.dcache.WriteReq_miss_latency::cpu.data 8425812922 # number of WriteReq miss cycles 968system.cpu.dcache.WriteReq_miss_latency::total 8425812922 # number of WriteReq miss cycles 969system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 265500 # number of LoadLockedReq miss cycles 970system.cpu.dcache.LoadLockedReq_miss_latency::total 265500 # number of LoadLockedReq miss cycles 971system.cpu.dcache.demand_miss_latency::cpu.data 22518815154 # number of demand (read+write) miss cycles 972system.cpu.dcache.demand_miss_latency::total 22518815154 # number of demand (read+write) miss cycles 973system.cpu.dcache.overall_miss_latency::cpu.data 22518815154 # number of overall miss cycles 974system.cpu.dcache.overall_miss_latency::total 22518815154 # number of overall miss cycles 975system.cpu.dcache.ReadReq_accesses::cpu.data 24999068 # number of ReadReq accesses(hits+misses) 976system.cpu.dcache.ReadReq_accesses::total 24999068 # number of ReadReq accesses(hits+misses) 977system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 978system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 979system.cpu.dcache.SoftPFReq_accesses::cpu.data 667 # number of SoftPFReq accesses(hits+misses) 980system.cpu.dcache.SoftPFReq_accesses::total 667 # number of SoftPFReq accesses(hits+misses) 981system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919 # number of LoadLockedReq accesses(hits+misses) 982system.cpu.dcache.LoadLockedReq_accesses::total 3919 # number of LoadLockedReq accesses(hits+misses) 983system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 984system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 985system.cpu.dcache.demand_accesses::cpu.data 29734049 # number of demand (read+write) accesses 986system.cpu.dcache.demand_accesses::total 29734049 # number of demand (read+write) accesses 987system.cpu.dcache.overall_accesses::cpu.data 29734716 # number of overall (read+write) accesses 988system.cpu.dcache.overall_accesses::total 29734716 # number of overall (read+write) accesses 989system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047400 # miss rate for ReadReq accesses 990system.cpu.dcache.ReadReq_miss_rate::total 0.047400 # miss rate for ReadReq accesses 991system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037396 # miss rate for WriteReq accesses 992system.cpu.dcache.WriteReq_miss_rate::total 0.037396 # miss rate for WriteReq accesses 993system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.049475 # miss rate for SoftPFReq accesses 994system.cpu.dcache.SoftPFReq_miss_rate::total 0.049475 # miss rate for SoftPFReq accesses 995system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002041 # miss rate for LoadLockedReq accesses 996system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002041 # miss rate for LoadLockedReq accesses 997system.cpu.dcache.demand_miss_rate::cpu.data 0.045807 # miss rate for demand accesses 998system.cpu.dcache.demand_miss_rate::total 0.045807 # miss rate for demand accesses 999system.cpu.dcache.overall_miss_rate::cpu.data 0.045807 # miss rate for overall accesses 1000system.cpu.dcache.overall_miss_rate::total 0.045807 # miss rate for overall accesses 1001system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11893.350790 # average ReadReq miss latency 1002system.cpu.dcache.ReadReq_avg_miss_latency::total 11893.350790 # average ReadReq miss latency 1003system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47584.375318 # average WriteReq miss latency 1004system.cpu.dcache.WriteReq_avg_miss_latency::total 47584.375318 # average WriteReq miss latency 1005system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33187.500000 # average LoadLockedReq miss latency 1006system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33187.500000 # average LoadLockedReq miss latency 1007system.cpu.dcache.demand_avg_miss_latency::cpu.data 16533.407503 # average overall miss latency 1008system.cpu.dcache.demand_avg_miss_latency::total 16533.407503 # average overall miss latency 1009system.cpu.dcache.overall_avg_miss_latency::cpu.data 16533.006929 # average overall miss latency 1010system.cpu.dcache.overall_avg_miss_latency::total 16533.006929 # average overall miss latency 1011system.cpu.dcache.blocked_cycles::no_mshrs 231027 # number of cycles access was blocked 1012system.cpu.dcache.blocked_cycles::no_targets 25 # number of cycles access was blocked 1013system.cpu.dcache.blocked::no_mshrs 44986 # number of cycles access was blocked 1014system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 1015system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.135531 # average number of cycles each access was blocked 1016system.cpu.dcache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked 1017system.cpu.dcache.fast_writes 0 # number of fast writes performed 1018system.cpu.dcache.cache_copies 0 # number of cache copies performed 1019system.cpu.dcache.writebacks::writebacks 942911 # number of writebacks 1020system.cpu.dcache.writebacks::total 942911 # number of writebacks 1021system.cpu.dcache.ReadReq_mshr_hits::cpu.data 274687 # number of ReadReq MSHR hits 1022system.cpu.dcache.ReadReq_mshr_hits::total 274687 # number of ReadReq MSHR hits 1023system.cpu.dcache.WriteReq_mshr_hits::cpu.data 139679 # number of WriteReq MSHR hits 1024system.cpu.dcache.WriteReq_mshr_hits::total 139679 # number of WriteReq MSHR hits 1025system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits 1026system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits 1027system.cpu.dcache.demand_mshr_hits::cpu.data 414366 # number of demand (read+write) MSHR hits 1028system.cpu.dcache.demand_mshr_hits::total 414366 # number of demand (read+write) MSHR hits 1029system.cpu.dcache.overall_mshr_hits::cpu.data 414366 # number of overall MSHR hits 1030system.cpu.dcache.overall_mshr_hits::total 414366 # number of overall MSHR hits 1031system.cpu.dcache.ReadReq_mshr_misses::cpu.data 910261 # number of ReadReq MSHR misses 1032system.cpu.dcache.ReadReq_mshr_misses::total 910261 # number of ReadReq MSHR misses 1033system.cpu.dcache.WriteReq_mshr_misses::cpu.data 37392 # number of WriteReq MSHR misses 1034system.cpu.dcache.WriteReq_mshr_misses::total 37392 # number of WriteReq MSHR misses 1035system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 20 # number of SoftPFReq MSHR misses 1036system.cpu.dcache.SoftPFReq_mshr_misses::total 20 # number of SoftPFReq MSHR misses 1037system.cpu.dcache.demand_mshr_misses::cpu.data 947653 # number of demand (read+write) MSHR misses 1038system.cpu.dcache.demand_mshr_misses::total 947653 # number of demand (read+write) MSHR misses 1039system.cpu.dcache.overall_mshr_misses::cpu.data 947673 # number of overall MSHR misses 1040system.cpu.dcache.overall_mshr_misses::total 947673 # number of overall MSHR misses 1041system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10074295509 # number of ReadReq MSHR miss cycles 1042system.cpu.dcache.ReadReq_mshr_miss_latency::total 10074295509 # number of ReadReq MSHR miss cycles 1043system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1254962842 # number of WriteReq MSHR miss cycles 1044system.cpu.dcache.WriteReq_mshr_miss_latency::total 1254962842 # number of WriteReq MSHR miss cycles 1045system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1219250 # number of SoftPFReq MSHR miss cycles 1046system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1219250 # number of SoftPFReq MSHR miss cycles 1047system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11329258351 # number of demand (read+write) MSHR miss cycles 1048system.cpu.dcache.demand_mshr_miss_latency::total 11329258351 # number of demand (read+write) MSHR miss cycles 1049system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11330477601 # number of overall MSHR miss cycles 1050system.cpu.dcache.overall_mshr_miss_latency::total 11330477601 # number of overall MSHR miss cycles 1051system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036412 # mshr miss rate for ReadReq accesses 1052system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036412 # mshr miss rate for ReadReq accesses 1053system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007897 # mshr miss rate for WriteReq accesses 1054system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007897 # mshr miss rate for WriteReq accesses 1055system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.029985 # mshr miss rate for SoftPFReq accesses 1056system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.029985 # mshr miss rate for SoftPFReq accesses 1057system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for demand accesses 1058system.cpu.dcache.demand_mshr_miss_rate::total 0.031871 # mshr miss rate for demand accesses 1059system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031871 # mshr miss rate for overall accesses 1060system.cpu.dcache.overall_mshr_miss_rate::total 0.031871 # mshr miss rate for overall accesses 1061system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11067.480106 # average ReadReq mshr miss latency 1062system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11067.480106 # average ReadReq mshr miss latency 1063system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33562.335312 # average WriteReq mshr miss latency 1064system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33562.335312 # average WriteReq mshr miss latency 1065system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 60962.500000 # average SoftPFReq mshr miss latency 1066system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 60962.500000 # average SoftPFReq mshr miss latency 1067system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11955.070422 # average overall mshr miss latency 1068system.cpu.dcache.demand_avg_mshr_miss_latency::total 11955.070422 # average overall mshr miss latency 1069system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11956.104691 # average overall mshr miss latency 1070system.cpu.dcache.overall_avg_mshr_miss_latency::total 11956.104691 # average overall mshr miss latency 1071system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1072 1073---------- End Simulation Statistics ---------- 1074