stats.txt revision 11441:0edcf757b6a2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.061235 # Number of seconds simulated 4sim_ticks 61234797500 # Number of ticks simulated 5final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 274685 # Simulator instruction rate (inst/s) 8host_op_rate 276053 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 185648704 # Simulator tick rate (ticks/s) 10host_mem_usage 404860 # Number of bytes of host memory used 11host_seconds 329.84 # Real time elapsed on the host 12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory 18system.physmem.bytes_read::total 996672 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 15573 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 807907 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 15468329 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 16276236 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 807907 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 807907 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 807907 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 15468329 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 16276236 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 15573 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 15573 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 996672 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 996672 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 993 # Per bank write bursts 45system.physmem.perBankRdBursts::1 890 # Per bank write bursts 46system.physmem.perBankRdBursts::2 949 # Per bank write bursts 47system.physmem.perBankRdBursts::3 1027 # Per bank write bursts 48system.physmem.perBankRdBursts::4 1050 # Per bank write bursts 49system.physmem.perBankRdBursts::5 1113 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1087 # Per bank write bursts 51system.physmem.perBankRdBursts::7 1088 # Per bank write bursts 52system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 53system.physmem.perBankRdBursts::9 962 # Per bank write bursts 54system.physmem.perBankRdBursts::10 938 # Per bank write bursts 55system.physmem.perBankRdBursts::11 899 # Per bank write bursts 56system.physmem.perBankRdBursts::12 904 # Per bank write bursts 57system.physmem.perBankRdBursts::13 867 # Per bank write bursts 58system.physmem.perBankRdBursts::14 876 # Per bank write bursts 59system.physmem.perBankRdBursts::15 906 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 61234703000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 15573 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 1535 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 648.213681 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 443.714701 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 401.012846 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 241 15.70% 15.70% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 186 12.12% 27.82% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 88 5.73% 33.55% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 73 4.76% 38.31% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 71 4.63% 42.93% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 84 5.47% 48.40% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 36 2.35% 50.75% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 51 3.32% 54.07% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 705 45.93% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 1535 # Bytes accessed per row activation 203system.physmem.totQLat 72594750 # Total ticks spent queuing 204system.physmem.totMemAccLat 364588500 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 77865000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 4661.58 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 23411.58 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 0.13 # Data bus utilization in percentage 215system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 14028 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 90.08 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 3932107.04 # Average gap between requests 224system.physmem.pageHitRate 90.08 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 63679200 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 2519893620 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 34528365000 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 41120963895 # Total energy per rank (pJ) 233system.physmem_0.averagePower 671.567381 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 57430990750 # Time in different power states 235system.physmem_0.memoryStateTime::REF 2044640000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 1755713000 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 2548962765 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 34502857500 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 41116813260 # Total energy per rank (pJ) 247system.physmem_1.averagePower 671.499745 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 57389143250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 2044640000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 20750031 # Number of BP lookups 254system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 8954908 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 8830467 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 98.610360 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 61988 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 26205 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 276system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 277system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 278system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 279system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 280system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 285system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 286system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 287system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 296system.cpu.dtb.walker.walks 0 # Table walker walks requested 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.inst_hits 0 # ITB inst hits 305system.cpu.dtb.inst_misses 0 # ITB inst misses 306system.cpu.dtb.read_hits 0 # DTB read hits 307system.cpu.dtb.read_misses 0 # DTB read misses 308system.cpu.dtb.write_hits 0 # DTB write hits 309system.cpu.dtb.write_misses 0 # DTB write misses 310system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 314system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 315system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 316system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dtb.read_accesses 0 # DTB read accesses 320system.cpu.dtb.write_accesses 0 # DTB write accesses 321system.cpu.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.dtb.hits 0 # DTB hits 323system.cpu.dtb.misses 0 # DTB misses 324system.cpu.dtb.accesses 0 # DTB accesses 325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 354system.cpu.itb.walker.walks 0 # Table walker walks requested 355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.inst_hits 0 # ITB inst hits 363system.cpu.itb.inst_misses 0 # ITB inst misses 364system.cpu.itb.read_hits 0 # DTB read hits 365system.cpu.itb.read_misses 0 # DTB read misses 366system.cpu.itb.write_hits 0 # DTB write hits 367system.cpu.itb.write_misses 0 # DTB write misses 368system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 369system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 370system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 371system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 372system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 373system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 374system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 375system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 442 # Number of system calls 384system.cpu.numCycles 122469595 # number of cpu cycles simulated 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 387system.cpu.committedInsts 90602850 # Number of instructions committed 388system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed 389system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit 390system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 391system.cpu.cpi 1.351719 # CPI: cycles per instruction 392system.cpu.ipc 0.739799 # IPC: instructions per cycle 393system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 394system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction 395system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 396system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 397system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 398system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 399system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 400system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 401system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 402system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 403system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 404system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 405system.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 406system.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 407system.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 408system.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 409system.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 410system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 411system.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 412system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 413system.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 414system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 415system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 416system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 417system.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 418system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 419system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 420system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 421system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 422system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 423system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 424system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 425system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 426system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 427system.cpu.op_class_0::total 91054081 # Class of committed instruction 428system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked 429system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped 430system.cpu.dcache.tags.replacements 946097 # number of replacements 431system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use 432system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks. 433system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. 434system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks. 435system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit. 436system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor 437system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy 438system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy 439system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 440system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id 441system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id 442system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id 443system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 444system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses 445system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses 446system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits 447system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits 448system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits 449system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits 450system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 451system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 452system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 453system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 454system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 455system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 456system.cpu.dcache.demand_hits::cpu.data 26254404 # number of demand (read+write) hits 457system.cpu.dcache.demand_hits::total 26254404 # number of demand (read+write) hits 458system.cpu.dcache.overall_hits::cpu.data 26254912 # number of overall hits 459system.cpu.dcache.overall_hits::total 26254912 # number of overall hits 460system.cpu.dcache.ReadReq_misses::cpu.data 914926 # number of ReadReq misses 461system.cpu.dcache.ReadReq_misses::total 914926 # number of ReadReq misses 462system.cpu.dcache.WriteReq_misses::cpu.data 74289 # number of WriteReq misses 463system.cpu.dcache.WriteReq_misses::total 74289 # number of WriteReq misses 464system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 465system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses 466system.cpu.dcache.demand_misses::cpu.data 989215 # number of demand (read+write) misses 467system.cpu.dcache.demand_misses::total 989215 # number of demand (read+write) misses 468system.cpu.dcache.overall_misses::cpu.data 989219 # number of overall misses 469system.cpu.dcache.overall_misses::total 989219 # number of overall misses 470system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919140000 # number of ReadReq miss cycles 471system.cpu.dcache.ReadReq_miss_latency::total 11919140000 # number of ReadReq miss cycles 472system.cpu.dcache.WriteReq_miss_latency::cpu.data 2539899500 # number of WriteReq miss cycles 473system.cpu.dcache.WriteReq_miss_latency::total 2539899500 # number of WriteReq miss cycles 474system.cpu.dcache.demand_miss_latency::cpu.data 14459039500 # number of demand (read+write) miss cycles 475system.cpu.dcache.demand_miss_latency::total 14459039500 # number of demand (read+write) miss cycles 476system.cpu.dcache.overall_miss_latency::cpu.data 14459039500 # number of overall miss cycles 477system.cpu.dcache.overall_miss_latency::total 14459039500 # number of overall miss cycles 478system.cpu.dcache.ReadReq_accesses::cpu.data 22508638 # number of ReadReq accesses(hits+misses) 479system.cpu.dcache.ReadReq_accesses::total 22508638 # number of ReadReq accesses(hits+misses) 480system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 481system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 482system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 483system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 484system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 485system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 486system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 487system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 488system.cpu.dcache.demand_accesses::cpu.data 27243619 # number of demand (read+write) accesses 489system.cpu.dcache.demand_accesses::total 27243619 # number of demand (read+write) accesses 490system.cpu.dcache.overall_accesses::cpu.data 27244131 # number of overall (read+write) accesses 491system.cpu.dcache.overall_accesses::total 27244131 # number of overall (read+write) accesses 492system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040648 # miss rate for ReadReq accesses 493system.cpu.dcache.ReadReq_miss_rate::total 0.040648 # miss rate for ReadReq accesses 494system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015689 # miss rate for WriteReq accesses 495system.cpu.dcache.WriteReq_miss_rate::total 0.015689 # miss rate for WriteReq accesses 496system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 497system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses 498system.cpu.dcache.demand_miss_rate::cpu.data 0.036310 # miss rate for demand accesses 499system.cpu.dcache.demand_miss_rate::total 0.036310 # miss rate for demand accesses 500system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses 501system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses 502system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.436099 # average ReadReq miss latency 503system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.436099 # average ReadReq miss latency 504system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34189.442582 # average WriteReq miss latency 505system.cpu.dcache.WriteReq_avg_miss_latency::total 34189.442582 # average WriteReq miss latency 506system.cpu.dcache.demand_avg_miss_latency::cpu.data 14616.680398 # average overall miss latency 507system.cpu.dcache.demand_avg_miss_latency::total 14616.680398 # average overall miss latency 508system.cpu.dcache.overall_avg_miss_latency::cpu.data 14616.621294 # average overall miss latency 509system.cpu.dcache.overall_avg_miss_latency::total 14616.621294 # average overall miss latency 510system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 511system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 512system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 513system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 514system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 515system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 516system.cpu.dcache.fast_writes 0 # number of fast writes performed 517system.cpu.dcache.cache_copies 0 # number of cache copies performed 518system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks 519system.cpu.dcache.writebacks::total 943278 # number of writebacks 520system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11500 # number of ReadReq MSHR hits 521system.cpu.dcache.ReadReq_mshr_hits::total 11500 # number of ReadReq MSHR hits 522system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27525 # number of WriteReq MSHR hits 523system.cpu.dcache.WriteReq_mshr_hits::total 27525 # number of WriteReq MSHR hits 524system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits 525system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits 526system.cpu.dcache.overall_mshr_hits::cpu.data 39025 # number of overall MSHR hits 527system.cpu.dcache.overall_mshr_hits::total 39025 # number of overall MSHR hits 528system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903426 # number of ReadReq MSHR misses 529system.cpu.dcache.ReadReq_mshr_misses::total 903426 # number of ReadReq MSHR misses 530system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses 531system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses 532system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 533system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 534system.cpu.dcache.demand_mshr_misses::cpu.data 950190 # number of demand (read+write) MSHR misses 535system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses 536system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses 537system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses 538system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865506000 # number of ReadReq MSHR miss cycles 539system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865506000 # number of ReadReq MSHR miss cycles 540system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1480423500 # number of WriteReq MSHR miss cycles 541system.cpu.dcache.WriteReq_mshr_miss_latency::total 1480423500 # number of WriteReq MSHR miss cycles 542system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles 543system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles 544system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345929500 # number of demand (read+write) MSHR miss cycles 545system.cpu.dcache.demand_mshr_miss_latency::total 12345929500 # number of demand (read+write) MSHR miss cycles 546system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346086000 # number of overall MSHR miss cycles 547system.cpu.dcache.overall_mshr_miss_latency::total 12346086000 # number of overall MSHR miss cycles 548system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040137 # mshr miss rate for ReadReq accesses 549system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040137 # mshr miss rate for ReadReq accesses 550system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 551system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 552system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 553system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 554system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034878 # mshr miss rate for demand accesses 555system.cpu.dcache.demand_mshr_miss_rate::total 0.034878 # mshr miss rate for demand accesses 556system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for overall accesses 557system.cpu.dcache.overall_mshr_miss_rate::total 0.034877 # mshr miss rate for overall accesses 558system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12027.001658 # average ReadReq mshr miss latency 559system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12027.001658 # average ReadReq mshr miss latency 560system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency 561system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency 562system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency 563system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency 564system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency 565system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency 566system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency 567system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency 568system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 569system.cpu.icache.tags.replacements 5 # number of replacements 570system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use 571system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks. 572system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. 573system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks. 574system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 575system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor 576system.cpu.icache.tags.occ_percent::cpu.inst 0.336476 # Average percentage of cache occupancy 577system.cpu.icache.tags.occ_percent::total 0.336476 # Average percentage of cache occupancy 578system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id 579system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 580system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 581system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 582system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 583system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id 584system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses 585system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses 586system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits 587system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits 588system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits 589system.cpu.icache.demand_hits::total 27766889 # number of demand (read+write) hits 590system.cpu.icache.overall_hits::cpu.inst 27766889 # number of overall hits 591system.cpu.icache.overall_hits::total 27766889 # number of overall hits 592system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses 593system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses 594system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses 595system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses 596system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses 597system.cpu.icache.overall_misses::total 801 # number of overall misses 598system.cpu.icache.ReadReq_miss_latency::cpu.inst 60228000 # number of ReadReq miss cycles 599system.cpu.icache.ReadReq_miss_latency::total 60228000 # number of ReadReq miss cycles 600system.cpu.icache.demand_miss_latency::cpu.inst 60228000 # number of demand (read+write) miss cycles 601system.cpu.icache.demand_miss_latency::total 60228000 # number of demand (read+write) miss cycles 602system.cpu.icache.overall_miss_latency::cpu.inst 60228000 # number of overall miss cycles 603system.cpu.icache.overall_miss_latency::total 60228000 # number of overall miss cycles 604system.cpu.icache.ReadReq_accesses::cpu.inst 27767690 # number of ReadReq accesses(hits+misses) 605system.cpu.icache.ReadReq_accesses::total 27767690 # number of ReadReq accesses(hits+misses) 606system.cpu.icache.demand_accesses::cpu.inst 27767690 # number of demand (read+write) accesses 607system.cpu.icache.demand_accesses::total 27767690 # number of demand (read+write) accesses 608system.cpu.icache.overall_accesses::cpu.inst 27767690 # number of overall (read+write) accesses 609system.cpu.icache.overall_accesses::total 27767690 # number of overall (read+write) accesses 610system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 611system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 612system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 613system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 614system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 615system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses 616system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75191.011236 # average ReadReq miss latency 617system.cpu.icache.ReadReq_avg_miss_latency::total 75191.011236 # average ReadReq miss latency 618system.cpu.icache.demand_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency 619system.cpu.icache.demand_avg_miss_latency::total 75191.011236 # average overall miss latency 620system.cpu.icache.overall_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency 621system.cpu.icache.overall_avg_miss_latency::total 75191.011236 # average overall miss latency 622system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 623system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 624system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 625system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 626system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 627system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 628system.cpu.icache.fast_writes 0 # number of fast writes performed 629system.cpu.icache.cache_copies 0 # number of cache copies performed 630system.cpu.icache.writebacks::writebacks 5 # number of writebacks 631system.cpu.icache.writebacks::total 5 # number of writebacks 632system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses 633system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses 634system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses 635system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses 636system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses 637system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses 638system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59427000 # number of ReadReq MSHR miss cycles 639system.cpu.icache.ReadReq_mshr_miss_latency::total 59427000 # number of ReadReq MSHR miss cycles 640system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59427000 # number of demand (read+write) MSHR miss cycles 641system.cpu.icache.demand_mshr_miss_latency::total 59427000 # number of demand (read+write) MSHR miss cycles 642system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59427000 # number of overall MSHR miss cycles 643system.cpu.icache.overall_mshr_miss_latency::total 59427000 # number of overall MSHR miss cycles 644system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 645system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 646system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 647system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 648system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 649system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses 650system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency 651system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency 652system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency 653system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency 654system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency 655system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency 656system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 657system.cpu.l2cache.tags.replacements 0 # number of replacements 658system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use 659system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks. 660system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks. 661system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks. 662system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 663system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor 664system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor 665system.cpu.l2cache.tags.occ_blocks::cpu.data 215.453494 # Average occupied blocks per requestor 666system.cpu.l2cache.tags.occ_percent::writebacks 0.285496 # Average percentage of cache occupancy 667system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020572 # Average percentage of cache occupancy 668system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy 669system.cpu.l2cache.tags.occ_percent::total 0.312643 # Average percentage of cache occupancy 670system.cpu.l2cache.tags.occ_task_id_blocks::1024 15556 # Occupied blocks per task id 671system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 672system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 673system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id 674system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1096 # Occupied blocks per task id 675system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id 676system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id 677system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses 678system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses 679system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits 680system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits 681system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits 682system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits 683system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 684system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 685system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits 686system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits 687system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903167 # number of ReadSharedReq hits 688system.cpu.l2cache.ReadSharedReq_hits::total 903167 # number of ReadSharedReq hits 689system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits 690system.cpu.l2cache.demand_hits::cpu.data 935387 # number of demand (read+write) hits 691system.cpu.l2cache.demand_hits::total 935413 # number of demand (read+write) hits 692system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits 693system.cpu.l2cache.overall_hits::cpu.data 935387 # number of overall hits 694system.cpu.l2cache.overall_hits::total 935413 # number of overall hits 695system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses 696system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses 697system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 775 # number of ReadCleanReq misses 698system.cpu.l2cache.ReadCleanReq_misses::total 775 # number of ReadCleanReq misses 699system.cpu.l2cache.ReadSharedReq_misses::cpu.data 262 # number of ReadSharedReq misses 700system.cpu.l2cache.ReadSharedReq_misses::total 262 # number of ReadSharedReq misses 701system.cpu.l2cache.demand_misses::cpu.inst 775 # number of demand (read+write) misses 702system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses 703system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses 704system.cpu.l2cache.overall_misses::cpu.inst 775 # number of overall misses 705system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses 706system.cpu.l2cache.overall_misses::total 15581 # number of overall misses 707system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1066480500 # number of ReadExReq miss cycles 708system.cpu.l2cache.ReadExReq_miss_latency::total 1066480500 # number of ReadExReq miss cycles 709system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57929500 # number of ReadCleanReq miss cycles 710system.cpu.l2cache.ReadCleanReq_miss_latency::total 57929500 # number of ReadCleanReq miss cycles 711system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22043500 # number of ReadSharedReq miss cycles 712system.cpu.l2cache.ReadSharedReq_miss_latency::total 22043500 # number of ReadSharedReq miss cycles 713system.cpu.l2cache.demand_miss_latency::cpu.inst 57929500 # number of demand (read+write) miss cycles 714system.cpu.l2cache.demand_miss_latency::cpu.data 1088524000 # number of demand (read+write) miss cycles 715system.cpu.l2cache.demand_miss_latency::total 1146453500 # number of demand (read+write) miss cycles 716system.cpu.l2cache.overall_miss_latency::cpu.inst 57929500 # number of overall miss cycles 717system.cpu.l2cache.overall_miss_latency::cpu.data 1088524000 # number of overall miss cycles 718system.cpu.l2cache.overall_miss_latency::total 1146453500 # number of overall miss cycles 719system.cpu.l2cache.WritebackDirty_accesses::writebacks 943278 # number of WritebackDirty accesses(hits+misses) 720system.cpu.l2cache.WritebackDirty_accesses::total 943278 # number of WritebackDirty accesses(hits+misses) 721system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) 722system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) 723system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) 724system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) 725system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) 726system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) 727system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903429 # number of ReadSharedReq accesses(hits+misses) 728system.cpu.l2cache.ReadSharedReq_accesses::total 903429 # number of ReadSharedReq accesses(hits+misses) 729system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses 730system.cpu.l2cache.demand_accesses::cpu.data 950193 # number of demand (read+write) accesses 731system.cpu.l2cache.demand_accesses::total 950994 # number of demand (read+write) accesses 732system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses 733system.cpu.l2cache.overall_accesses::cpu.data 950193 # number of overall (read+write) accesses 734system.cpu.l2cache.overall_accesses::total 950994 # number of overall (read+write) accesses 735system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses 736system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses 737system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.967541 # miss rate for ReadCleanReq accesses 738system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.967541 # miss rate for ReadCleanReq accesses 739system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses 740system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses 741system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967541 # miss rate for demand accesses 742system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses 743system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses 744system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967541 # miss rate for overall accesses 745system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses 746system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses 747system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73327.867162 # average ReadExReq miss latency 748system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73327.867162 # average ReadExReq miss latency 749system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74747.741935 # average ReadCleanReq miss latency 750system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74747.741935 # average ReadCleanReq miss latency 751system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84135.496183 # average ReadSharedReq miss latency 752system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84135.496183 # average ReadSharedReq miss latency 753system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74747.741935 # average overall miss latency 754system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency 755system.cpu.l2cache.demand_avg_miss_latency::total 73580.225916 # average overall miss latency 756system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74747.741935 # average overall miss latency 757system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency 758system.cpu.l2cache.overall_avg_miss_latency::total 73580.225916 # average overall miss latency 759system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 760system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 761system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 762system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 763system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 764system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 765system.cpu.l2cache.fast_writes 0 # number of fast writes performed 766system.cpu.l2cache.cache_copies 0 # number of cache copies performed 767system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 768system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 769system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 770system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 771system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 772system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 773system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits 774system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 775system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 776system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits 777system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses 778system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 779system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses 780system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses 781system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256 # number of ReadSharedReq MSHR misses 782system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256 # number of ReadSharedReq MSHR misses 783system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses 784system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses 785system.cpu.l2cache.demand_mshr_misses::total 15573 # number of demand (read+write) MSHR misses 786system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses 787system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses 788system.cpu.l2cache.overall_mshr_misses::total 15573 # number of overall MSHR misses 789system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 921040500 # number of ReadExReq MSHR miss cycles 790system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 921040500 # number of ReadExReq MSHR miss cycles 791system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50052500 # number of ReadCleanReq MSHR miss cycles 792system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50052500 # number of ReadCleanReq MSHR miss cycles 793system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19092500 # number of ReadSharedReq MSHR miss cycles 794system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19092500 # number of ReadSharedReq MSHR miss cycles 795system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50052500 # number of demand (read+write) MSHR miss cycles 796system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 940133000 # number of demand (read+write) MSHR miss cycles 797system.cpu.l2cache.demand_mshr_miss_latency::total 990185500 # number of demand (read+write) MSHR miss cycles 798system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50052500 # number of overall MSHR miss cycles 799system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 940133000 # number of overall MSHR miss cycles 800system.cpu.l2cache.overall_mshr_miss_latency::total 990185500 # number of overall MSHR miss cycles 801system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses 802system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses 803system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses 804system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses 805system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses 806system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses 807system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses 808system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses 809system.cpu.l2cache.demand_mshr_miss_rate::total 0.016375 # mshr miss rate for demand accesses 810system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses 811system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses 812system.cpu.l2cache.overall_mshr_miss_rate::total 0.016375 # mshr miss rate for overall accesses 813system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63327.867162 # average ReadExReq mshr miss latency 814system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63327.867162 # average ReadExReq mshr miss latency 815system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64750.970246 # average ReadCleanReq mshr miss latency 816system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64750.970246 # average ReadCleanReq mshr miss latency 817system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125 # average ReadSharedReq mshr miss latency 818system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125 # average ReadSharedReq mshr miss latency 819system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency 820system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency 821system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency 822system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency 823system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency 824system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency 825system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 826system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter. 827system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. 828system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 829system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 830system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 831system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 832system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution 833system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution 834system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution 835system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution 836system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 837system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 838system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution 839system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution 840system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) 841system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846483 # Packet count per connected master and slave (bytes) 842system.cpu.toL2Bus.pkt_count::total 2848090 # Packet count per connected master and slave (bytes) 843system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) 844system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) 845system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes) 846system.cpu.toL2Bus.snoops 0 # Total snoops (count) 847system.cpu.toL2Bus.snoop_fanout::samples 950994 # Request fanout histogram 848system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram 849system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram 850system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 851system.cpu.toL2Bus.snoop_fanout::0 950828 99.98% 99.98% # Request fanout histogram 852system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram 853system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 854system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 855system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 856system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 857system.cpu.toL2Bus.snoop_fanout::total 950994 # Request fanout histogram 858system.cpu.toL2Bus.reqLayer0.occupancy 1891831000 # Layer occupancy (ticks) 859system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) 860system.cpu.toL2Bus.respLayer0.occupancy 1202498 # Layer occupancy (ticks) 861system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 862system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) 863system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 864system.membus.trans_dist::ReadResp 1029 # Transaction distribution 865system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 866system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 867system.membus.trans_dist::ReadSharedReq 1029 # Transaction distribution 868system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31146 # Packet count per connected master and slave (bytes) 869system.membus.pkt_count::total 31146 # Packet count per connected master and slave (bytes) 870system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996672 # Cumulative packet size per connected master and slave (bytes) 871system.membus.pkt_size::total 996672 # Cumulative packet size per connected master and slave (bytes) 872system.membus.snoops 0 # Total snoops (count) 873system.membus.snoop_fanout::samples 15573 # Request fanout histogram 874system.membus.snoop_fanout::mean 0 # Request fanout histogram 875system.membus.snoop_fanout::stdev 0 # Request fanout histogram 876system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 877system.membus.snoop_fanout::0 15573 100.00% 100.00% # Request fanout histogram 878system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 879system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 880system.membus.snoop_fanout::min_value 0 # Request fanout histogram 881system.membus.snoop_fanout::max_value 0 # Request fanout histogram 882system.membus.snoop_fanout::total 15573 # Request fanout histogram 883system.membus.reqLayer0.occupancy 21737000 # Layer occupancy (ticks) 884system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 885system.membus.respLayer1.occupancy 82128750 # Layer occupancy (ticks) 886system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 887 888---------- End Simulation Statistics ---------- 889