stats.txt revision 10260:384d554cea8c
1 2---------- Begin Simulation Statistics ---------- 3final_tick 61269894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 4host_inst_rate 246086 # Simulator instruction rate (inst/s) 5host_mem_usage 426904 # Number of bytes of host memory used 6host_op_rate 247853 # Simulator op (including micro ops) rate (op/s) 7host_seconds 368.18 # Real time elapsed on the host 8host_tick_rate 166415131 # Simulator tick rate (ticks/s) 9sim_freq 1000000000000 # Frequency of simulated ticks 10sim_insts 90602849 # Number of instructions simulated 11sim_ops 91253402 # Number of ops (including micro ops) simulated 12sim_seconds 0.061270 # Number of seconds simulated 13sim_ticks 61269894500 # Number of ticks simulated 14system.clk_domain.clock 1000 # Clock period in ticks 15system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 16system.cpu.branchPred.BTBHitPct 98.707356 # BTB Hit Percentage 17system.cpu.branchPred.BTBHits 8859613 # Number of BTB hits 18system.cpu.branchPred.BTBLookups 8975636 # Number of BTB lookups 19system.cpu.branchPred.RASInCorrect 1020 # Number of incorrect RAS predictions. 20system.cpu.branchPred.condIncorrect 765388 # Number of conditional branches incorrect 21system.cpu.branchPred.condPredicted 17116903 # Number of conditional branches predicted 22system.cpu.branchPred.lookups 20794461 # Number of BP lookups 23system.cpu.branchPred.usedRAS 54785 # Number of times the RAS was used to get a target. 24system.cpu.committedInsts 90602849 # Number of instructions committed 25system.cpu.committedOps 91253402 # Number of ops (including micro ops) committed 26system.cpu.cpi 1.352494 # CPI: cycles per instruction 27system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 3887 # number of LoadLockedReq accesses(hits+misses) 28system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 29system.cpu.dcache.LoadLockedReq_hits::cpu.inst 3887 # number of LoadLockedReq hits 30system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 31system.cpu.dcache.ReadReq_accesses::cpu.inst 22606743 # number of ReadReq accesses(hits+misses) 32system.cpu.dcache.ReadReq_accesses::total 22606743 # number of ReadReq accesses(hits+misses) 33system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13018.894340 # average ReadReq miss latency 34system.cpu.dcache.ReadReq_avg_miss_latency::total 13018.894340 # average ReadReq miss latency 35system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11024.761855 # average ReadReq mshr miss latency 36system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.761855 # average ReadReq mshr miss latency 37system.cpu.dcache.ReadReq_hits::cpu.inst 21691800 # number of ReadReq hits 38system.cpu.dcache.ReadReq_hits::total 21691800 # number of ReadReq hits 39system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11911546244 # number of ReadReq miss cycles 40system.cpu.dcache.ReadReq_miss_latency::total 11911546244 # number of ReadReq miss cycles 41system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.040472 # miss rate for ReadReq accesses 42system.cpu.dcache.ReadReq_miss_rate::total 0.040472 # miss rate for ReadReq accesses 43system.cpu.dcache.ReadReq_misses::cpu.inst 914943 # number of ReadReq misses 44system.cpu.dcache.ReadReq_misses::total 914943 # number of ReadReq misses 45system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 11527 # number of ReadReq MSHR hits 46system.cpu.dcache.ReadReq_mshr_hits::total 11527 # number of ReadReq MSHR hits 47system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9959946256 # number of ReadReq MSHR miss cycles 48system.cpu.dcache.ReadReq_mshr_miss_latency::total 9959946256 # number of ReadReq MSHR miss cycles 49system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.039962 # mshr miss rate for ReadReq accesses 50system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039962 # mshr miss rate for ReadReq accesses 51system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 903416 # number of ReadReq MSHR misses 52system.cpu.dcache.ReadReq_mshr_misses::total 903416 # number of ReadReq MSHR misses 53system.cpu.dcache.StoreCondReq_accesses::cpu.inst 3887 # number of StoreCondReq accesses(hits+misses) 54system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 55system.cpu.dcache.StoreCondReq_hits::cpu.inst 3887 # number of StoreCondReq hits 56system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 57system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses) 58system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 59system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31690.074425 # average WriteReq miss latency 60system.cpu.dcache.WriteReq_avg_miss_latency::total 31690.074425 # average WriteReq miss latency 61system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28535.254491 # average WriteReq mshr miss latency 62system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28535.254491 # average WriteReq mshr miss latency 63system.cpu.dcache.WriteReq_hits::cpu.inst 4661081 # number of WriteReq hits 64system.cpu.dcache.WriteReq_hits::total 4661081 # number of WriteReq hits 65system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2341896500 # number of WriteReq miss cycles 66system.cpu.dcache.WriteReq_miss_latency::total 2341896500 # number of WriteReq miss cycles 67system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.015607 # miss rate for WriteReq accesses 68system.cpu.dcache.WriteReq_miss_rate::total 0.015607 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses::cpu.inst 73900 # number of WriteReq misses 70system.cpu.dcache.WriteReq_misses::total 73900 # number of WriteReq misses 71system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 27140 # number of WriteReq MSHR hits 72system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits 73system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334308500 # number of WriteReq MSHR miss cycles 74system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334308500 # number of WriteReq MSHR miss cycles 75system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009875 # mshr miss rate for WriteReq accesses 76system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009875 # mshr miss rate for WriteReq accesses 77system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 46760 # number of WriteReq MSHR misses 78system.cpu.dcache.WriteReq_mshr_misses::total 46760 # number of WriteReq MSHR misses 79system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 80system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 81system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 82system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 83system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 84system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85system.cpu.dcache.cache_copies 0 # number of cache copies performed 86system.cpu.dcache.demand_accesses::cpu.inst 27341724 # number of demand (read+write) accesses 87system.cpu.dcache.demand_accesses::total 27341724 # number of demand (read+write) accesses 88system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14414.262673 # average overall miss latency 89system.cpu.dcache.demand_avg_miss_latency::total 14414.262673 # average overall miss latency 90system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11886.487089 # average overall mshr miss latency 91system.cpu.dcache.demand_avg_mshr_miss_latency::total 11886.487089 # average overall mshr miss latency 92system.cpu.dcache.demand_hits::cpu.inst 26352881 # number of demand (read+write) hits 93system.cpu.dcache.demand_hits::total 26352881 # number of demand (read+write) hits 94system.cpu.dcache.demand_miss_latency::cpu.inst 14253442744 # number of demand (read+write) miss cycles 95system.cpu.dcache.demand_miss_latency::total 14253442744 # number of demand (read+write) miss cycles 96system.cpu.dcache.demand_miss_rate::cpu.inst 0.036166 # miss rate for demand accesses 97system.cpu.dcache.demand_miss_rate::total 0.036166 # miss rate for demand accesses 98system.cpu.dcache.demand_misses::cpu.inst 988843 # number of demand (read+write) misses 99system.cpu.dcache.demand_misses::total 988843 # number of demand (read+write) misses 100system.cpu.dcache.demand_mshr_hits::cpu.inst 38667 # number of demand (read+write) MSHR hits 101system.cpu.dcache.demand_mshr_hits::total 38667 # number of demand (read+write) MSHR hits 102system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11294254756 # number of demand (read+write) MSHR miss cycles 103system.cpu.dcache.demand_mshr_miss_latency::total 11294254756 # number of demand (read+write) MSHR miss cycles 104system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.034752 # mshr miss rate for demand accesses 105system.cpu.dcache.demand_mshr_miss_rate::total 0.034752 # mshr miss rate for demand accesses 106system.cpu.dcache.demand_mshr_misses::cpu.inst 950176 # number of demand (read+write) MSHR misses 107system.cpu.dcache.demand_mshr_misses::total 950176 # number of demand (read+write) MSHR misses 108system.cpu.dcache.fast_writes 0 # number of fast writes performed 109system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 110system.cpu.dcache.overall_accesses::cpu.inst 27341724 # number of overall (read+write) accesses 111system.cpu.dcache.overall_accesses::total 27341724 # number of overall (read+write) accesses 112system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14414.262673 # average overall miss latency 113system.cpu.dcache.overall_avg_miss_latency::total 14414.262673 # average overall miss latency 114system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11886.487089 # average overall mshr miss latency 115system.cpu.dcache.overall_avg_mshr_miss_latency::total 11886.487089 # average overall mshr miss latency 116system.cpu.dcache.overall_hits::cpu.inst 26352881 # number of overall hits 117system.cpu.dcache.overall_hits::total 26352881 # number of overall hits 118system.cpu.dcache.overall_miss_latency::cpu.inst 14253442744 # number of overall miss cycles 119system.cpu.dcache.overall_miss_latency::total 14253442744 # number of overall miss cycles 120system.cpu.dcache.overall_miss_rate::cpu.inst 0.036166 # miss rate for overall accesses 121system.cpu.dcache.overall_miss_rate::total 0.036166 # miss rate for overall accesses 122system.cpu.dcache.overall_misses::cpu.inst 988843 # number of overall misses 123system.cpu.dcache.overall_misses::total 988843 # number of overall misses 124system.cpu.dcache.overall_mshr_hits::cpu.inst 38667 # number of overall MSHR hits 125system.cpu.dcache.overall_mshr_hits::total 38667 # number of overall MSHR hits 126system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11294254756 # number of overall MSHR miss cycles 127system.cpu.dcache.overall_mshr_miss_latency::total 11294254756 # number of overall MSHR miss cycles 128system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034752 # mshr miss rate for overall accesses 129system.cpu.dcache.overall_mshr_miss_rate::total 0.034752 # mshr miss rate for overall accesses 130system.cpu.dcache.overall_mshr_misses::cpu.inst 950176 # number of overall MSHR misses 131system.cpu.dcache.overall_mshr_misses::total 950176 # number of overall MSHR misses 132system.cpu.dcache.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id 133system.cpu.dcache.tags.age_task_id_blocks_1024::1 2200 # Occupied blocks per task id 134system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id 135system.cpu.dcache.tags.avg_refs 27.742918 # Average number of references to valid blocks. 136system.cpu.dcache.tags.data_accesses 55649172 # Number of data accesses 137system.cpu.dcache.tags.occ_blocks::cpu.inst 3618.532737 # Average occupied blocks per requestor 138system.cpu.dcache.tags.occ_percent::cpu.inst 0.883431 # Average percentage of cache occupancy 139system.cpu.dcache.tags.occ_percent::total 0.883431 # Average percentage of cache occupancy 140system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 141system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 142system.cpu.dcache.tags.replacements 946080 # number of replacements 143system.cpu.dcache.tags.sampled_refs 950176 # Sample count of references to valid blocks. 144system.cpu.dcache.tags.tag_accesses 55649172 # Number of tag accesses 145system.cpu.dcache.tags.tagsinuse 3618.532737 # Cycle average of tags in use 146system.cpu.dcache.tags.total_refs 26360655 # Total number of references to valid blocks. 147system.cpu.dcache.tags.warmup_cycle 20496262250 # Cycle when the warmup percentage was hit. 148system.cpu.dcache.writebacks::writebacks 943298 # number of writebacks 149system.cpu.dcache.writebacks::total 943298 # number of writebacks 150system.cpu.discardedOps 2065378 # Number of ops (including micro ops) which were discarded before commit 151system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 152system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 153system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 155system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 156system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 157system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 158system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 159system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 160system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 161system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 162system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 163system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 164system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 165system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 166system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 167system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 168system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 169system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 170system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 171system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 172system.cpu.dtb.accesses 0 # DTB accesses 173system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 174system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 175system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 176system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 177system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 178system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 179system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 180system.cpu.dtb.hits 0 # DTB hits 181system.cpu.dtb.inst_accesses 0 # ITB inst accesses 182system.cpu.dtb.inst_hits 0 # ITB inst hits 183system.cpu.dtb.inst_misses 0 # ITB inst misses 184system.cpu.dtb.misses 0 # DTB misses 185system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 186system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 187system.cpu.dtb.read_accesses 0 # DTB read accesses 188system.cpu.dtb.read_hits 0 # DTB read hits 189system.cpu.dtb.read_misses 0 # DTB read misses 190system.cpu.dtb.write_accesses 0 # DTB write accesses 191system.cpu.dtb.write_hits 0 # DTB write hits 192system.cpu.dtb.write_misses 0 # DTB write misses 193system.cpu.icache.ReadReq_accesses::cpu.inst 27818907 # number of ReadReq accesses(hits+misses) 194system.cpu.icache.ReadReq_accesses::total 27818907 # number of ReadReq accesses(hits+misses) 195system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68915.429630 # average ReadReq miss latency 196system.cpu.icache.ReadReq_avg_miss_latency::total 68915.429630 # average ReadReq miss latency 197system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66500.619753 # average ReadReq mshr miss latency 198system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66500.619753 # average ReadReq mshr miss latency 199system.cpu.icache.ReadReq_hits::cpu.inst 27818097 # number of ReadReq hits 200system.cpu.icache.ReadReq_hits::total 27818097 # number of ReadReq hits 201system.cpu.icache.ReadReq_miss_latency::cpu.inst 55821498 # number of ReadReq miss cycles 202system.cpu.icache.ReadReq_miss_latency::total 55821498 # number of ReadReq miss cycles 203system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 204system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 205system.cpu.icache.ReadReq_misses::cpu.inst 810 # number of ReadReq misses 206system.cpu.icache.ReadReq_misses::total 810 # number of ReadReq misses 207system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53865502 # number of ReadReq MSHR miss cycles 208system.cpu.icache.ReadReq_mshr_miss_latency::total 53865502 # number of ReadReq MSHR miss cycles 209system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 210system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 211system.cpu.icache.ReadReq_mshr_misses::cpu.inst 810 # number of ReadReq MSHR misses 212system.cpu.icache.ReadReq_mshr_misses::total 810 # number of ReadReq MSHR misses 213system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 214system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 215system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 216system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 217system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 218system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 219system.cpu.icache.cache_copies 0 # number of cache copies performed 220system.cpu.icache.demand_accesses::cpu.inst 27818907 # number of demand (read+write) accesses 221system.cpu.icache.demand_accesses::total 27818907 # number of demand (read+write) accesses 222system.cpu.icache.demand_avg_miss_latency::cpu.inst 68915.429630 # average overall miss latency 223system.cpu.icache.demand_avg_miss_latency::total 68915.429630 # average overall miss latency 224system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66500.619753 # average overall mshr miss latency 225system.cpu.icache.demand_avg_mshr_miss_latency::total 66500.619753 # average overall mshr miss latency 226system.cpu.icache.demand_hits::cpu.inst 27818097 # number of demand (read+write) hits 227system.cpu.icache.demand_hits::total 27818097 # number of demand (read+write) hits 228system.cpu.icache.demand_miss_latency::cpu.inst 55821498 # number of demand (read+write) miss cycles 229system.cpu.icache.demand_miss_latency::total 55821498 # number of demand (read+write) miss cycles 230system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 231system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 232system.cpu.icache.demand_misses::cpu.inst 810 # number of demand (read+write) misses 233system.cpu.icache.demand_misses::total 810 # number of demand (read+write) misses 234system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53865502 # number of demand (read+write) MSHR miss cycles 235system.cpu.icache.demand_mshr_miss_latency::total 53865502 # number of demand (read+write) MSHR miss cycles 236system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 237system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 238system.cpu.icache.demand_mshr_misses::cpu.inst 810 # number of demand (read+write) MSHR misses 239system.cpu.icache.demand_mshr_misses::total 810 # number of demand (read+write) MSHR misses 240system.cpu.icache.fast_writes 0 # number of fast writes performed 241system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 242system.cpu.icache.overall_accesses::cpu.inst 27818907 # number of overall (read+write) accesses 243system.cpu.icache.overall_accesses::total 27818907 # number of overall (read+write) accesses 244system.cpu.icache.overall_avg_miss_latency::cpu.inst 68915.429630 # average overall miss latency 245system.cpu.icache.overall_avg_miss_latency::total 68915.429630 # average overall miss latency 246system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66500.619753 # average overall mshr miss latency 247system.cpu.icache.overall_avg_mshr_miss_latency::total 66500.619753 # average overall mshr miss latency 248system.cpu.icache.overall_hits::cpu.inst 27818097 # number of overall hits 249system.cpu.icache.overall_hits::total 27818097 # number of overall hits 250system.cpu.icache.overall_miss_latency::cpu.inst 55821498 # number of overall miss cycles 251system.cpu.icache.overall_miss_latency::total 55821498 # number of overall miss cycles 252system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 253system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses 254system.cpu.icache.overall_misses::cpu.inst 810 # number of overall misses 255system.cpu.icache.overall_misses::total 810 # number of overall misses 256system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53865502 # number of overall MSHR miss cycles 257system.cpu.icache.overall_mshr_miss_latency::total 53865502 # number of overall MSHR miss cycles 258system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 259system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses 260system.cpu.icache.overall_mshr_misses::cpu.inst 810 # number of overall MSHR misses 261system.cpu.icache.overall_mshr_misses::total 810 # number of overall MSHR misses 262system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 263system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 264system.cpu.icache.tags.age_task_id_blocks_1024::4 748 # Occupied blocks per task id 265system.cpu.icache.tags.avg_refs 34343.329630 # Average number of references to valid blocks. 266system.cpu.icache.tags.data_accesses 55638624 # Number of data accesses 267system.cpu.icache.tags.occ_blocks::cpu.inst 696.774140 # Average occupied blocks per requestor 268system.cpu.icache.tags.occ_percent::cpu.inst 0.340222 # Average percentage of cache occupancy 269system.cpu.icache.tags.occ_percent::total 0.340222 # Average percentage of cache occupancy 270system.cpu.icache.tags.occ_task_id_blocks::1024 805 # Occupied blocks per task id 271system.cpu.icache.tags.occ_task_id_percent::1024 0.393066 # Percentage of cache occupancy per task id 272system.cpu.icache.tags.replacements 5 # number of replacements 273system.cpu.icache.tags.sampled_refs 810 # Sample count of references to valid blocks. 274system.cpu.icache.tags.tag_accesses 55638624 # Number of tag accesses 275system.cpu.icache.tags.tagsinuse 696.774140 # Cycle average of tags in use 276system.cpu.icache.tags.total_refs 27818097 # Total number of references to valid blocks. 277system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 278system.cpu.idleCycles 13105167 # Total number of cycles that the CPU has spent unscheduled due to idling 279system.cpu.ipc 0.739375 # IPC: instructions per cycle 280system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 281system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 282system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 283system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 284system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 285system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 286system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 287system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 288system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 289system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 290system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 291system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 292system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 293system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 294system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 295system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 296system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 297system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 298system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 299system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 300system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 301system.cpu.itb.accesses 0 # DTB accesses 302system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 303system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 304system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 305system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 306system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 307system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 308system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 309system.cpu.itb.hits 0 # DTB hits 310system.cpu.itb.inst_accesses 0 # ITB inst accesses 311system.cpu.itb.inst_hits 0 # ITB inst hits 312system.cpu.itb.inst_misses 0 # ITB inst misses 313system.cpu.itb.misses 0 # DTB misses 314system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 315system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 316system.cpu.itb.read_accesses 0 # DTB read accesses 317system.cpu.itb.read_hits 0 # DTB read hits 318system.cpu.itb.read_misses 0 # DTB read misses 319system.cpu.itb.write_accesses 0 # DTB write accesses 320system.cpu.itb.write_hits 0 # DTB write hits 321system.cpu.itb.write_misses 0 # DTB write misses 322system.cpu.l2cache.ReadExReq_accesses::cpu.inst 46760 # number of ReadExReq accesses(hits+misses) 323system.cpu.l2cache.ReadExReq_accesses::total 46760 # number of ReadExReq accesses(hits+misses) 324system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65946.757667 # average ReadExReq miss latency 325system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65946.757667 # average ReadExReq miss latency 326system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53094.192683 # average ReadExReq mshr miss latency 327system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53094.192683 # average ReadExReq mshr miss latency 328system.cpu.l2cache.ReadExReq_hits::cpu.inst 32218 # number of ReadExReq hits 329system.cpu.l2cache.ReadExReq_hits::total 32218 # number of ReadExReq hits 330system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 958997750 # number of ReadExReq miss cycles 331system.cpu.l2cache.ReadExReq_miss_latency::total 958997750 # number of ReadExReq miss cycles 332system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.310992 # miss rate for ReadExReq accesses 333system.cpu.l2cache.ReadExReq_miss_rate::total 0.310992 # miss rate for ReadExReq accesses 334system.cpu.l2cache.ReadExReq_misses::cpu.inst 14542 # number of ReadExReq misses 335system.cpu.l2cache.ReadExReq_misses::total 14542 # number of ReadExReq misses 336system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772095750 # number of ReadExReq MSHR miss cycles 337system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772095750 # number of ReadExReq MSHR miss cycles 338system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.310992 # mshr miss rate for ReadExReq accesses 339system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310992 # mshr miss rate for ReadExReq accesses 340system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 14542 # number of ReadExReq MSHR misses 341system.cpu.l2cache.ReadExReq_mshr_misses::total 14542 # number of ReadExReq MSHR misses 342system.cpu.l2cache.ReadReq_accesses::cpu.inst 904226 # number of ReadReq accesses(hits+misses) 343system.cpu.l2cache.ReadReq_accesses::total 904226 # number of ReadReq accesses(hits+misses) 344system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69821.699905 # average ReadReq miss latency 345system.cpu.l2cache.ReadReq_avg_miss_latency::total 69821.699905 # average ReadReq miss latency 346system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57393.301435 # average ReadReq mshr miss latency 347system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57393.301435 # average ReadReq mshr miss latency 348system.cpu.l2cache.ReadReq_hits::cpu.inst 903173 # number of ReadReq hits 349system.cpu.l2cache.ReadReq_hits::total 903173 # number of ReadReq hits 350system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 73522250 # number of ReadReq miss cycles 351system.cpu.l2cache.ReadReq_miss_latency::total 73522250 # number of ReadReq miss cycles 352system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.001165 # miss rate for ReadReq accesses 353system.cpu.l2cache.ReadReq_miss_rate::total 0.001165 # miss rate for ReadReq accesses 354system.cpu.l2cache.ReadReq_misses::cpu.inst 1053 # number of ReadReq misses 355system.cpu.l2cache.ReadReq_misses::total 1053 # number of ReadReq misses 356system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits 357system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits 358system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59976000 # number of ReadReq MSHR miss cycles 359system.cpu.l2cache.ReadReq_mshr_miss_latency::total 59976000 # number of ReadReq MSHR miss cycles 360system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001156 # mshr miss rate for ReadReq accesses 361system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001156 # mshr miss rate for ReadReq accesses 362system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1045 # number of ReadReq MSHR misses 363system.cpu.l2cache.ReadReq_mshr_misses::total 1045 # number of ReadReq MSHR misses 364system.cpu.l2cache.Writeback_accesses::writebacks 943298 # number of Writeback accesses(hits+misses) 365system.cpu.l2cache.Writeback_accesses::total 943298 # number of Writeback accesses(hits+misses) 366system.cpu.l2cache.Writeback_hits::writebacks 943298 # number of Writeback hits 367system.cpu.l2cache.Writeback_hits::total 943298 # number of Writeback hits 368system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 369system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 370system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 371system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 372system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 374system.cpu.l2cache.cache_copies 0 # number of cache copies performed 375system.cpu.l2cache.demand_accesses::cpu.inst 950986 # number of demand (read+write) accesses 376system.cpu.l2cache.demand_accesses::total 950986 # number of demand (read+write) accesses 377system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66208.400128 # average overall miss latency 378system.cpu.l2cache.demand_avg_miss_latency::total 66208.400128 # average overall miss latency 379system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53382.418041 # average overall mshr miss latency 380system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53382.418041 # average overall mshr miss latency 381system.cpu.l2cache.demand_hits::cpu.inst 935391 # number of demand (read+write) hits 382system.cpu.l2cache.demand_hits::total 935391 # number of demand (read+write) hits 383system.cpu.l2cache.demand_miss_latency::cpu.inst 1032520000 # number of demand (read+write) miss cycles 384system.cpu.l2cache.demand_miss_latency::total 1032520000 # number of demand (read+write) miss cycles 385system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016399 # miss rate for demand accesses 386system.cpu.l2cache.demand_miss_rate::total 0.016399 # miss rate for demand accesses 387system.cpu.l2cache.demand_misses::cpu.inst 15595 # number of demand (read+write) misses 388system.cpu.l2cache.demand_misses::total 15595 # number of demand (read+write) misses 389system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits 390system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits 391system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 832071750 # number of demand (read+write) MSHR miss cycles 392system.cpu.l2cache.demand_mshr_miss_latency::total 832071750 # number of demand (read+write) MSHR miss cycles 393system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016390 # mshr miss rate for demand accesses 394system.cpu.l2cache.demand_mshr_miss_rate::total 0.016390 # mshr miss rate for demand accesses 395system.cpu.l2cache.demand_mshr_misses::cpu.inst 15587 # number of demand (read+write) MSHR misses 396system.cpu.l2cache.demand_mshr_misses::total 15587 # number of demand (read+write) MSHR misses 397system.cpu.l2cache.fast_writes 0 # number of fast writes performed 398system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 399system.cpu.l2cache.overall_accesses::cpu.inst 950986 # number of overall (read+write) accesses 400system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses 401system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66208.400128 # average overall miss latency 402system.cpu.l2cache.overall_avg_miss_latency::total 66208.400128 # average overall miss latency 403system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53382.418041 # average overall mshr miss latency 404system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53382.418041 # average overall mshr miss latency 405system.cpu.l2cache.overall_hits::cpu.inst 935391 # number of overall hits 406system.cpu.l2cache.overall_hits::total 935391 # number of overall hits 407system.cpu.l2cache.overall_miss_latency::cpu.inst 1032520000 # number of overall miss cycles 408system.cpu.l2cache.overall_miss_latency::total 1032520000 # number of overall miss cycles 409system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016399 # miss rate for overall accesses 410system.cpu.l2cache.overall_miss_rate::total 0.016399 # miss rate for overall accesses 411system.cpu.l2cache.overall_misses::cpu.inst 15595 # number of overall misses 412system.cpu.l2cache.overall_misses::total 15595 # number of overall misses 413system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits 414system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits 415system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 832071750 # number of overall MSHR miss cycles 416system.cpu.l2cache.overall_mshr_miss_latency::total 832071750 # number of overall MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016390 # mshr miss rate for overall accesses 418system.cpu.l2cache.overall_mshr_miss_rate::total 0.016390 # mshr miss rate for overall accesses 419system.cpu.l2cache.overall_mshr_misses::cpu.inst 15587 # number of overall MSHR misses 420system.cpu.l2cache.overall_mshr_misses::total 15587 # number of overall MSHR misses 421system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id 422system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 423system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id 424system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id 425system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13889 # Occupied blocks per task id 426system.cpu.l2cache.tags.avg_refs 117.618626 # Average number of references to valid blocks. 427system.cpu.l2cache.tags.data_accesses 15216602 # Number of data accesses 428system.cpu.l2cache.tags.occ_blocks::writebacks 9366.525575 # Average occupied blocks per requestor 429system.cpu.l2cache.tags.occ_blocks::cpu.inst 902.408366 # Average occupied blocks per requestor 430system.cpu.l2cache.tags.occ_percent::writebacks 0.285844 # Average percentage of cache occupancy 431system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027539 # Average percentage of cache occupancy 432system.cpu.l2cache.tags.occ_percent::total 0.313383 # Average percentage of cache occupancy 433system.cpu.l2cache.tags.occ_task_id_blocks::1024 15570 # Occupied blocks per task id 434system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475159 # Percentage of cache occupancy per task id 435system.cpu.l2cache.tags.replacements 0 # number of replacements 436system.cpu.l2cache.tags.sampled_refs 15570 # Sample count of references to valid blocks. 437system.cpu.l2cache.tags.tag_accesses 15216602 # Number of tag accesses 438system.cpu.l2cache.tags.tagsinuse 10268.933941 # Cycle average of tags in use 439system.cpu.l2cache.tags.total_refs 1831322 # Total number of references to valid blocks. 440system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 441system.cpu.numCycles 122539789 # number of cpu cycles simulated 442system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 443system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 444system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 445system.cpu.tickCycles 109434622 # Number of cycles that the CPU actually ticked 446system.cpu.toL2Bus.data_through_bus 121234176 # Total data (bytes) 447system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1620 # Packet count per connected master and slave (bytes) 448system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843650 # Packet count per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_count::total 2845270 # Packet count per connected master and slave (bytes) 450system.cpu.toL2Bus.reqLayer0.occupancy 1890440000 # Layer occupancy (ticks) 451system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) 452system.cpu.toL2Bus.respLayer0.occupancy 1382998 # Layer occupancy (ticks) 453system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 454system.cpu.toL2Bus.respLayer1.occupancy 1428632744 # Layer occupancy (ticks) 455system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 456system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 457system.cpu.toL2Bus.throughput 1978690791 # Throughput (bytes/s) 458system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51840 # Cumulative packet size per connected master and slave (bytes) 459system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182336 # Cumulative packet size per connected master and slave (bytes) 460system.cpu.toL2Bus.tot_pkt_size::total 121234176 # Cumulative packet size per connected master and slave (bytes) 461system.cpu.toL2Bus.trans_dist::ReadReq 904226 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::ReadResp 904226 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::Writeback 943298 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadExReq 46760 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::ReadExResp 46760 # Transaction distribution 466system.cpu.workload.num_syscalls 442 # Number of system calls 467system.cpu_clk_domain.clock 500 # Clock period in ticks 468system.membus.data_through_bus 997568 # Total data (bytes) 469system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31174 # Packet count per connected master and slave (bytes) 470system.membus.pkt_count::total 31174 # Packet count per connected master and slave (bytes) 471system.membus.reqLayer0.occupancy 21774500 # Layer occupancy (ticks) 472system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 473system.membus.respLayer1.occupancy 149672750 # Layer occupancy (ticks) 474system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 475system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 476system.membus.throughput 16281536 # Throughput (bytes/s) 477system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 997568 # Cumulative packet size per connected master and slave (bytes) 478system.membus.tot_pkt_size::total 997568 # Cumulative packet size per connected master and slave (bytes) 479system.membus.trans_dist::ReadReq 1045 # Transaction distribution 480system.membus.trans_dist::ReadResp 1045 # Transaction distribution 481system.membus.trans_dist::ReadExReq 14542 # Transaction distribution 482system.membus.trans_dist::ReadExResp 14542 # Transaction distribution 483system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 484system.physmem.avgGap 3930827.39 # Average gap between requests 485system.physmem.avgMemAccLat 23360.33 # Average memory access latency per DRAM burst 486system.physmem.avgQLat 4610.33 # Average queueing delay per DRAM burst 487system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s 488system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s 489system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 490system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 491system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 492system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 493system.physmem.busUtil 0.13 # Data bus utilization in percentage 494system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads 495system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 496system.physmem.bw_inst_read::cpu.inst 816845 # Instruction read bandwidth from this memory (bytes/s) 497system.physmem.bw_inst_read::total 816845 # Instruction read bandwidth from this memory (bytes/s) 498system.physmem.bw_read::cpu.inst 16281536 # Total read bandwidth from this memory (bytes/s) 499system.physmem.bw_read::total 16281536 # Total read bandwidth from this memory (bytes/s) 500system.physmem.bw_total::cpu.inst 16281536 # Total bandwidth to/from this memory (bytes/s) 501system.physmem.bw_total::total 16281536 # Total bandwidth to/from this memory (bytes/s) 502system.physmem.bytesPerActivate::samples 1547 # Bytes accessed per row activation 503system.physmem.bytesPerActivate::mean 643.557854 # Bytes accessed per row activation 504system.physmem.bytesPerActivate::gmean 434.536592 # Bytes accessed per row activation 505system.physmem.bytesPerActivate::stdev 403.240998 # Bytes accessed per row activation 506system.physmem.bytesPerActivate::0-127 258 16.68% 16.68% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::128-255 197 12.73% 29.41% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::256-383 72 4.65% 34.07% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::384-511 57 3.68% 37.75% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::512-639 69 4.46% 42.21% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::640-767 102 6.59% 48.80% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::768-895 43 2.78% 51.58% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::896-1023 57 3.68% 55.27% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::1024-1151 692 44.73% 100.00% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::total 1547 # Bytes accessed per row activation 516system.physmem.bytesReadDRAM 997568 # Total number of bytes read from DRAM 517system.physmem.bytesReadSys 997568 # Total read bytes from the system interface side 518system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 519system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 520system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 521system.physmem.bytes_inst_read::cpu.inst 50048 # Number of instructions bytes read from this memory 522system.physmem.bytes_inst_read::total 50048 # Number of instructions bytes read from this memory 523system.physmem.bytes_read::cpu.inst 997568 # Number of bytes read from this memory 524system.physmem.bytes_read::total 997568 # Number of bytes read from this memory 525system.physmem.memoryStateTime::IDLE 55978709750 # Time in different power states 526system.physmem.memoryStateTime::REF 2045680000 # Time in different power states 527system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 528system.physmem.memoryStateTime::ACT 3241107750 # Time in different power states 529system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 530system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 531system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 532system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 533system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 534system.physmem.num_reads::cpu.inst 15587 # Number of read requests responded to by this memory 535system.physmem.num_reads::total 15587 # Number of read requests responded to by this memory 536system.physmem.pageHitRate 90.01 # Row buffer hit rate, read and write combined 537system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 538system.physmem.perBankRdBursts::0 994 # Per bank write bursts 539system.physmem.perBankRdBursts::1 891 # Per bank write bursts 540system.physmem.perBankRdBursts::2 951 # Per bank write bursts 541system.physmem.perBankRdBursts::3 1028 # Per bank write bursts 542system.physmem.perBankRdBursts::4 1052 # Per bank write bursts 543system.physmem.perBankRdBursts::5 1115 # Per bank write bursts 544system.physmem.perBankRdBursts::6 1088 # Per bank write bursts 545system.physmem.perBankRdBursts::7 1088 # Per bank write bursts 546system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 547system.physmem.perBankRdBursts::9 962 # Per bank write bursts 548system.physmem.perBankRdBursts::10 941 # Per bank write bursts 549system.physmem.perBankRdBursts::11 899 # Per bank write bursts 550system.physmem.perBankRdBursts::12 904 # Per bank write bursts 551system.physmem.perBankRdBursts::13 869 # Per bank write bursts 552system.physmem.perBankRdBursts::14 877 # Per bank write bursts 553system.physmem.perBankRdBursts::15 904 # Per bank write bursts 554system.physmem.perBankWrBursts::0 0 # Per bank write bursts 555system.physmem.perBankWrBursts::1 0 # Per bank write bursts 556system.physmem.perBankWrBursts::2 0 # Per bank write bursts 557system.physmem.perBankWrBursts::3 0 # Per bank write bursts 558system.physmem.perBankWrBursts::4 0 # Per bank write bursts 559system.physmem.perBankWrBursts::5 0 # Per bank write bursts 560system.physmem.perBankWrBursts::6 0 # Per bank write bursts 561system.physmem.perBankWrBursts::7 0 # Per bank write bursts 562system.physmem.perBankWrBursts::8 0 # Per bank write bursts 563system.physmem.perBankWrBursts::9 0 # Per bank write bursts 564system.physmem.perBankWrBursts::10 0 # Per bank write bursts 565system.physmem.perBankWrBursts::11 0 # Per bank write bursts 566system.physmem.perBankWrBursts::12 0 # Per bank write bursts 567system.physmem.perBankWrBursts::13 0 # Per bank write bursts 568system.physmem.perBankWrBursts::14 0 # Per bank write bursts 569system.physmem.perBankWrBursts::15 0 # Per bank write bursts 570system.physmem.rdQLenPdf::0 15468 # What read queue length does an incoming req see 571system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see 572system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see 573system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 574system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 575system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 576system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 577system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 578system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 579system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 580system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 581system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 582system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 583system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 584system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 585system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 586system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 587system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 588system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 589system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 590system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 591system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 592system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 593system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 594system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 595system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 596system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 597system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 598system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 599system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 600system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 601system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 602system.physmem.readBursts 15587 # Number of DRAM read bursts, including those serviced by the write queue 603system.physmem.readPktSize::0 0 # Read request sizes (log2) 604system.physmem.readPktSize::1 0 # Read request sizes (log2) 605system.physmem.readPktSize::2 0 # Read request sizes (log2) 606system.physmem.readPktSize::3 0 # Read request sizes (log2) 607system.physmem.readPktSize::4 0 # Read request sizes (log2) 608system.physmem.readPktSize::5 0 # Read request sizes (log2) 609system.physmem.readPktSize::6 15587 # Read request sizes (log2) 610system.physmem.readReqs 15587 # Number of read requests accepted 611system.physmem.readRowHitRate 90.01 # Row buffer hit rate for reads 612system.physmem.readRowHits 14030 # Number of row buffer hits during reads 613system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 614system.physmem.totBusLat 77935000 # Total ticks spent in databus transfers 615system.physmem.totGap 61269806500 # Total gap between requests 616system.physmem.totMemAccLat 364117500 # Total ticks spent from burst creation until serviced by the DRAM 617system.physmem.totQLat 71861250 # Total ticks spent queuing 618system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 619system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 620system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 621system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 622system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 623system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 624system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 625system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 626system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 627system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 628system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 629system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 630system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 631system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 632system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 633system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 634system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 635system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 636system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 637system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 638system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 639system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 640system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 641system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 642system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 643system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 644system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 645system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 646system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 647system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 648system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 649system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 650system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 651system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 652system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 653system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 654system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 655system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 656system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 657system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 658system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 659system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 660system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 661system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 662system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 663system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 664system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 665system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 666system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 667system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 668system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 669system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 670system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 671system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 672system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 673system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 674system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 675system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 676system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 677system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 678system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 679system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 680system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 681system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 682system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 683system.physmem.writePktSize::0 0 # Write request sizes (log2) 684system.physmem.writePktSize::1 0 # Write request sizes (log2) 685system.physmem.writePktSize::2 0 # Write request sizes (log2) 686system.physmem.writePktSize::3 0 # Write request sizes (log2) 687system.physmem.writePktSize::4 0 # Write request sizes (log2) 688system.physmem.writePktSize::5 0 # Write request sizes (log2) 689system.physmem.writePktSize::6 0 # Write request sizes (log2) 690system.physmem.writeReqs 0 # Number of write requests accepted 691system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 692system.physmem.writeRowHits 0 # Number of row buffer hits during writes 693system.voltage_domain.voltage 1 # Voltage in Volts 694 695---------- End Simulation Statistics ---------- 696