111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 0.062555 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 62555455500 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 62555455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 428742 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 430877 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 296018745 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 404460 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 211.32 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 90602850 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 91054081 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 1711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory 1811570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 996800 # Number of bytes read from this memory 2011860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory 2111860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory 2211860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory 2311570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory 2411860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 15575 # Number of read requests responded to by this memory 2511860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 791873 # Total read bandwidth from this memory (bytes/s) 2611860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 15142788 # Total read bandwidth from this memory (bytes/s) 2711860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 15934661 # Total read bandwidth from this memory (bytes/s) 2811860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 791873 # Instruction read bandwidth from this memory (bytes/s) 2911860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 791873 # Instruction read bandwidth from this memory (bytes/s) 3011860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 791873 # Total bandwidth to/from this memory (bytes/s) 3111860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 15142788 # Total bandwidth to/from this memory (bytes/s) 3211860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 15934661 # Total bandwidth to/from this memory (bytes/s) 3311860Sandreas.hansson@arm.comsystem.physmem.readReqs 15575 # Number of read requests accepted 3411507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511860Sandreas.hansson@arm.comsystem.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue 3611507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711860Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM 3811507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 3911507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011860Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 996800 # Total read bytes from the system interface side 4111507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 4211507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4311507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4411507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 993 # Per bank write bursts 4611570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 891 # Per bank write bursts 4711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 949 # Per bank write bursts 4811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 1027 # Per bank write bursts 4911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 1050 # Per bank write bursts 5011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 1113 # Per bank write bursts 5111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 1088 # Per bank write bursts 5211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 1088 # Per bank write bursts 5311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 1024 # Per bank write bursts 5411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 962 # Per bank write bursts 5511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 938 # Per bank write bursts 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 899 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 904 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 867 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 876 # Per bank write bursts 6011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 906 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 7811507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911860Sandreas.hansson@arm.comsystem.physmem.totGap 62555354500 # Total gap between requests 8011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8311507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 8411507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 8511507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611860Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 15575 # Read request sizes (log2) 8711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 15455 # What read queue length does an incoming req see 9511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see 9611570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see 9711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 9811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 9911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation 19111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 646.524675 # Bytes accessed per row activation 19211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 437.465548 # Bytes accessed per row activation 19311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 402.658643 # Bytes accessed per row activation 19411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 259 16.82% 16.82% # Bytes accessed per row activation 19511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 177 11.49% 28.31% # Bytes accessed per row activation 19611860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 80 5.19% 33.51% # Bytes accessed per row activation 19711680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 62 4.03% 37.53% # Bytes accessed per row activation 19811680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 82 5.32% 42.86% # Bytes accessed per row activation 19911680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 81 5.26% 48.12% # Bytes accessed per row activation 20011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 40 2.60% 50.71% # Bytes accessed per row activation 20111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 67 4.35% 55.06% # Bytes accessed per row activation 20211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation 20311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation 20411860Sandreas.hansson@arm.comsystem.physmem.totQLat 211097500 # Total ticks spent queuing 20511860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 503128750 # Total ticks spent from burst creation until serviced by the DRAM 20611860Sandreas.hansson@arm.comsystem.physmem.totBusLat 77875000 # Total ticks spent in databus transfers 20711860Sandreas.hansson@arm.comsystem.physmem.avgQLat 13553.61 # Average queueing delay per DRAM burst 20811507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20911860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 32303.61 # Average memory access latency per DRAM burst 21011680SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s 21111507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21211680SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s 21311507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21411507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21511570SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.12 # Data bus utilization in percentage 21611570SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 21711507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21811507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 21911507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22011860Sandreas.hansson@arm.comsystem.physmem.readRowHits 14028 # Number of row buffer hits during reads 22111507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22211680SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads 22311507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22411860Sandreas.hansson@arm.comsystem.physmem.avgGap 4016395.15 # Average gap between requests 22511680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined 22611680SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ) 22711680SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ) 22811860Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 58540860 # Energy for read commands per rank (pJ) 22911507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23011680SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ) 23111860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 136590240 # Energy for active background per rank (pJ) 23211860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 8764320 # Energy for precharge background per rank (pJ) 23311860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 737385060 # Energy for active power-down per rank (pJ) 23411860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 211641120 # Energy for precharge power-down per rank (pJ) 23511860Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 14429375100 # Energy for self refresh per rank (pJ) 23611860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 15802368780 # Total energy per rank (pJ) 23711860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 252.613756 # Core power per rank (mW) 23811860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 62232966250 # Total Idle time Per DRAM Rank 23911680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states 24011680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 89372000 # Time in different power states 24111860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 60064867500 # Time in different power states 24211860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 551102250 # Time in different power states 24311860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 223150500 # Time in different power states 24411860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 1617057250 # Time in different power states 24511680SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 4998000 # Energy for activate commands per rank (pJ) 24611680SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 2641320 # Energy for precharge commands per rank (pJ) 24711680SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ) 24811507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24911680SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ) 25011860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 136410120 # Energy for active background per rank (pJ) 25111860Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 13262400 # Energy for precharge background per rank (pJ) 25211860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 827323080 # Energy for active power-down per rank (pJ) 25311860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 248273280 # Energy for precharge power-down per rank (pJ) 25411860Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 14377994265 # Energy for self refresh per rank (pJ) 25511860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 15920556885 # Total energy per rank (pJ) 25611860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 254.503090 # Core power per rank (mW) 25711860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 62220218000 # Total Idle time Per DRAM Rank 25811680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states 25911680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 109118000 # Time in different power states 26011860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 59760759500 # Time in different power states 26111860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 646525750 # Time in different power states 26211860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 203991750 # Time in different power states 26311860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 1814347500 # Time in different power states 26411860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 26511860Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 20806620 # Number of BP lookups 26611860Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 17114048 # Number of conditional branches predicted 26711860Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 756880 # Number of conditional branches incorrect 26811860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 8968258 # Number of BTB lookups 26911860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 8843232 # Number of BTB hits 27011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 27111860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 98.605905 # BTB Hit Percentage 27211860Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 61975 # Number of times the RAS was used to get a target. 27311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 27411570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. 27511860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectHits 24793 # Number of indirect target hits. 27611860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 1418 # Number of indirect misses. 27711860Sandreas.hansson@arm.comsystem.cpu.branchPredindirectMispredicted 666 # Number of mispredicted indirect branches. 27811507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 27911860Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 28011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 28111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 28211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 28311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 28411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 28511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 28611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 28711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 28811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 28911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 29011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 29111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 29211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 29311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 29411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 29511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 29611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 29711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 29811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 29911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 30011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 30111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 30211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 30311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 30411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 30511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 30611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 30711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 30811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 30911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 31011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 31111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 31211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 31311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 31411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 31511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 31611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 31711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 31811507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 31911507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 32011507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 32111507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 32211507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 32311507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 32411507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 32511507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 32811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 32911507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 33011507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 33111507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 33211507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 33411507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 33511507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 33611507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 33711507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 33811507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 33911860Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 34011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 34211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 34311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 34511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 34611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 34711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 34811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 34911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 35011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 35111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 35211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 35311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 35411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 35511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 35711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 35911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 36011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 36111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 36211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 36411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 36511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 36611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 36711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 36811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 36911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 37011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 37111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 37211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 37311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 37511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 37611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 37711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 37811507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 37911507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 38011507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 38111507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 38211507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 38311507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 38411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 38511507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38611507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 38711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 38811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 38911507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 39011507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 39111507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 39211507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39311507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 39411507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 39511507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 39611507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 39711507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 39811507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 39911955Sgabeblack@google.comsystem.cpu.workload.numSyscalls 442 # Number of system calls 40011860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::ON 62555455500 # Cumulative time (in ticks) in various power states 40111860Sandreas.hansson@arm.comsystem.cpu.numCycles 125110911 # number of cpu cycles simulated 40211507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40311507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40411507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 90602850 # Number of instructions committed 40511507SCurtis.Dunham@arm.comsystem.cpu.committedOps 91054081 # Number of ops (including micro ops) committed 40611860Sandreas.hansson@arm.comsystem.cpu.discardedOps 2181045 # Number of ops (including micro ops) which were discarded before commit 40711507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 40811860Sandreas.hansson@arm.comsystem.cpu.cpi 1.380872 # CPI: cycles per instruction 40911860Sandreas.hansson@arm.comsystem.cpu.ipc 0.724180 # IPC: instructions per cycle 41011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 41111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction 41211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 41311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 41411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 41511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 41611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 41711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 41811687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction 41911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 42011687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction 42111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 42211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 42311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 42411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 42511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 42611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 42711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 42811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 42911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 43011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 43111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 43211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 43311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 43411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 43511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 43611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 43711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 43811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 43911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 44011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 44111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 44211687Sandreas.hansson@arm.comsystem.cpu.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction 44311687Sandreas.hansson@arm.comsystem.cpu.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction 44411687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction 44511687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction 44611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 44711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 44811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 91054081 # Class of committed instruction 44911860Sandreas.hansson@arm.comsystem.cpu.tickCycles 110528679 # Number of cycles that the object actually ticked 45011860Sandreas.hansson@arm.comsystem.cpu.idleCycles 14582232 # Total number of cycles that the object has spent stopped 45111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 45211860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 946104 # number of replacements 45311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 3621.120784 # Cycle average of tags in use 45411860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 26274613 # Total number of references to valid blocks. 45511860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 950200 # Sample count of references to valid blocks. 45611860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 27.651666 # Average number of references to valid blocks. 45711860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 20754332500 # Cycle when the warmup percentage was hit. 45811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 3621.120784 # Average occupied blocks per requestor 45911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.884063 # Average percentage of cache occupancy 46011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.884063 # Average percentage of cache occupancy 46111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 46211680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id 46311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 2198 # Occupied blocks per task id 46411860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 1666 # Occupied blocks per task id 46511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 46611860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 55461064 # Number of tag accesses 46711860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 55461064 # Number of data accesses 46811860Sandreas.hansson@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 46911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 21605665 # number of ReadReq hits 47011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 21605665 # number of ReadReq hits 47111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4660666 # number of WriteReq hits 47211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4660666 # number of WriteReq hits 47311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 47411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 47511507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 47611507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 47711507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 47811507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 47911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 26266331 # number of demand (read+write) hits 48011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 26266331 # number of demand (read+write) hits 48111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 26266839 # number of overall hits 48211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 26266839 # number of overall hits 48311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 906500 # number of ReadReq misses 48411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 906500 # number of ReadReq misses 48511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 74315 # number of WriteReq misses 48611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 74315 # number of WriteReq misses 48711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 48811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses 48911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 980815 # number of demand (read+write) misses 49011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 980815 # number of demand (read+write) misses 49111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 980819 # number of overall misses 49211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 980819 # number of overall misses 49311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11832236000 # number of ReadReq miss cycles 49411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11832236000 # number of ReadReq miss cycles 49511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 2760278000 # number of WriteReq miss cycles 49611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 2760278000 # number of WriteReq miss cycles 49711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 14592514000 # number of demand (read+write) miss cycles 49811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 14592514000 # number of demand (read+write) miss cycles 49911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 14592514000 # number of overall miss cycles 50011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 14592514000 # number of overall miss cycles 50111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 22512165 # number of ReadReq accesses(hits+misses) 50211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 22512165 # number of ReadReq accesses(hits+misses) 50311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 50411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 50511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 50611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 50711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 50811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 50911507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 51011507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 51111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 27247146 # number of demand (read+write) accesses 51211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 27247146 # number of demand (read+write) accesses 51311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 27247658 # number of overall (read+write) accesses 51411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 27247658 # number of overall (read+write) accesses 51511754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses 51611754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses 51711680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses 51811680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.015695 # miss rate for WriteReq accesses 51911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 52011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses 52111754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.035997 # miss rate for demand accesses 52211754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses 52311754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses 52411754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses 52511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.659680 # average ReadReq miss latency 52611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 13052.659680 # average ReadReq miss latency 52711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.945570 # average WriteReq miss latency 52811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 37142.945570 # average WriteReq miss latency 52911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.947421 # average overall miss latency 53011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 14877.947421 # average overall miss latency 53111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.886746 # average overall miss latency 53211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 14877.886746 # average overall miss latency 53311507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 53411507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 53511507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 53611507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 53711507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 53811507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 53911860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 943285 # number of writebacks 54011860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 943285 # number of writebacks 54111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 3067 # number of ReadReq MSHR hits 54211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 3067 # number of ReadReq MSHR hits 54311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 27551 # number of WriteReq MSHR hits 54411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 27551 # number of WriteReq MSHR hits 54511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 30618 # number of demand (read+write) MSHR hits 54611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 30618 # number of demand (read+write) MSHR hits 54711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 30618 # number of overall MSHR hits 54811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 30618 # number of overall MSHR hits 54911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses 55011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses 55111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses 55211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses 55311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 55411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 55511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 950197 # number of demand (read+write) MSHR misses 55611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 950197 # number of demand (read+write) MSHR misses 55711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 950200 # number of overall MSHR misses 55811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 950200 # number of overall MSHR misses 55911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889912000 # number of ReadReq MSHR miss cycles 56011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 10889912000 # number of ReadReq MSHR miss cycles 56111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596274500 # number of WriteReq MSHR miss cycles 56211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1596274500 # number of WriteReq MSHR miss cycles 56311680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles 56411680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles 56511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486186500 # number of demand (read+write) MSHR miss cycles 56611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 12486186500 # number of demand (read+write) MSHR miss cycles 56711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486356500 # number of overall MSHR miss cycles 56811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 12486356500 # number of overall MSHR miss cycles 56911570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses 57011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses 57111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 57211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 57311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 57411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 57511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses 57611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses 57711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for overall accesses 57811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.034873 # mshr miss rate for overall accesses 57911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.923202 # average ReadReq mshr miss latency 58011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.923202 # average ReadReq mshr miss latency 58111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34134.686939 # average WriteReq mshr miss latency 58211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34134.686939 # average WriteReq mshr miss latency 58311680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency 58411680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency 58511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.629259 # average overall mshr miss latency 58611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.629259 # average overall mshr miss latency 58711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.766681 # average overall mshr miss latency 58811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.766681 # average overall mshr miss latency 58911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 59011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 5 # number of replacements 59111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 689.583421 # Cycle average of tags in use 59211860Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 27839479 # Total number of references to valid blocks. 59311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. 59411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 34712.567332 # Average number of references to valid blocks. 59511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 59611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 689.583421 # Average occupied blocks per requestor 59711860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.336711 # Average percentage of cache occupancy 59811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.336711 # Average percentage of cache occupancy 59911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id 60011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 60111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id 60211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 60311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 60411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id 60511860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 55681364 # Number of tag accesses 60611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 55681364 # Number of data accesses 60711860Sandreas.hansson@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 60811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 27839479 # number of ReadReq hits 60911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 27839479 # number of ReadReq hits 61011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 27839479 # number of demand (read+write) hits 61111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 27839479 # number of demand (read+write) hits 61211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 27839479 # number of overall hits 61311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 27839479 # number of overall hits 61411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses 61511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses 61611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses 61711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses 61811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses 61911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 802 # number of overall misses 62011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 71421000 # number of ReadReq miss cycles 62111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 71421000 # number of ReadReq miss cycles 62211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 71421000 # number of demand (read+write) miss cycles 62311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 71421000 # number of demand (read+write) miss cycles 62411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 71421000 # number of overall miss cycles 62511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 71421000 # number of overall miss cycles 62611860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 27840281 # number of ReadReq accesses(hits+misses) 62711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 27840281 # number of ReadReq accesses(hits+misses) 62811860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 27840281 # number of demand (read+write) accesses 62911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 27840281 # number of demand (read+write) accesses 63011860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 27840281 # number of overall (read+write) accesses 63111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 27840281 # number of overall (read+write) accesses 63211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 63311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 63411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 63511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 63611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 63711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses 63811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 89053.615960 # average ReadReq miss latency 63911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 89053.615960 # average ReadReq miss latency 64011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency 64111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 89053.615960 # average overall miss latency 64211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency 64311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 89053.615960 # average overall miss latency 64411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 64511507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 64611507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 64711507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 64811507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 64911507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 65011507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 5 # number of writebacks 65111507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 5 # number of writebacks 65211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses 65311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses 65411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses 65511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses 65611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses 65711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses 65811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70619000 # number of ReadReq MSHR miss cycles 65911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 70619000 # number of ReadReq MSHR miss cycles 66011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 70619000 # number of demand (read+write) MSHR miss cycles 66111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 70619000 # number of demand (read+write) MSHR miss cycles 66211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 70619000 # number of overall MSHR miss cycles 66311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 70619000 # number of overall MSHR miss cycles 66411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 66511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 66611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 66711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 66811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 66911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses 67011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 88053.615960 # average ReadReq mshr miss latency 67111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 88053.615960 # average ReadReq mshr miss latency 67211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 88053.615960 # average overall mshr miss latency 67311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 88053.615960 # average overall mshr miss latency 67411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 88053.615960 # average overall mshr miss latency 67511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 88053.615960 # average overall mshr miss latency 67611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 67711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 67811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 11308.105127 # Cycle average of tags in use 67911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1881379 # Total number of references to valid blocks. 68011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 15575 # Sample count of references to valid blocks. 68111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 120.794799 # Average number of references to valid blocks. 68211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 68311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 674.588306 # Average occupied blocks per requestor 68411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 10633.516821 # Average occupied blocks per requestor 68511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy 68611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.324509 # Average percentage of cache occupancy 68711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.345096 # Average percentage of cache occupancy 68811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 15575 # Occupied blocks per task id 68911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 69011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id 69111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id 69211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 69311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id 69411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.475311 # Percentage of cache occupancy per task id 69511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 15191263 # Number of tag accesses 69611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 15191263 # Number of data accesses 69711860Sandreas.hansson@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 69811860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 943285 # number of WritebackDirty hits 69911860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 943285 # number of WritebackDirty hits 70011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits 70111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits 70211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 70311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 70411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 27 # number of ReadCleanReq hits 70511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 27 # number of ReadCleanReq hits 70611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 903173 # number of ReadSharedReq hits 70711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 903173 # number of ReadSharedReq hits 70811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits 70911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 935393 # number of demand (read+write) hits 71011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 935420 # number of demand (read+write) hits 71111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits 71211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 935393 # number of overall hits 71311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 935420 # number of overall hits 71411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses 71511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses 71611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 775 # number of ReadCleanReq misses 71711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 775 # number of ReadCleanReq misses 71811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 263 # number of ReadSharedReq misses 71911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 263 # number of ReadSharedReq misses 72011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 775 # number of demand (read+write) misses 72111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 14807 # number of demand (read+write) misses 72211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses 72311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 775 # number of overall misses 72411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses 72511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 15582 # number of overall misses 72611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1182333500 # number of ReadExReq miss cycles 72711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1182333500 # number of ReadExReq miss cycles 72811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 69109000 # number of ReadCleanReq miss cycles 72911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 69109000 # number of ReadCleanReq miss cycles 73011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49239000 # number of ReadSharedReq miss cycles 73111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 49239000 # number of ReadSharedReq miss cycles 73211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 69109000 # number of demand (read+write) miss cycles 73311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 1231572500 # number of demand (read+write) miss cycles 73411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 1300681500 # number of demand (read+write) miss cycles 73511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 69109000 # number of overall miss cycles 73611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 1231572500 # number of overall miss cycles 73711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 1300681500 # number of overall miss cycles 73811860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 943285 # number of WritebackDirty accesses(hits+misses) 73911860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 943285 # number of WritebackDirty accesses(hits+misses) 74011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) 74111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) 74211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) 74311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) 74411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) 74511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) 74611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903436 # number of ReadSharedReq accesses(hits+misses) 74711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 903436 # number of ReadSharedReq accesses(hits+misses) 74811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses 74911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 950200 # number of demand (read+write) accesses 75011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 951002 # number of demand (read+write) accesses 75111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses 75211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 950200 # number of overall (read+write) accesses 75311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 951002 # number of overall (read+write) accesses 75411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses 75511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses 75611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966334 # miss rate for ReadCleanReq accesses 75711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966334 # miss rate for ReadCleanReq accesses 75811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses 75911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses 76011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.966334 # miss rate for demand accesses 76111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.015583 # miss rate for demand accesses 76211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses 76311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.966334 # miss rate for overall accesses 76411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses 76511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses 76611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81293.557481 # average ReadExReq miss latency 76711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 81293.557481 # average ReadExReq miss latency 76811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89172.903226 # average ReadCleanReq miss latency 76911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89172.903226 # average ReadCleanReq miss latency 77011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187220.532319 # average ReadSharedReq miss latency 77111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187220.532319 # average ReadSharedReq miss latency 77211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency 77311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency 77411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 83473.334617 # average overall miss latency 77511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency 77611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency 77711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 83473.334617 # average overall miss latency 77811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 77911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 78011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 78111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 78211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 78311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 78411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 78511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 78611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 78711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 78811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 78911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 79011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits 79111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 79211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 79311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits 79411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses 79511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 79611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 774 # number of ReadCleanReq MSHR misses 79711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 774 # number of ReadCleanReq MSHR misses 79811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses 79911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses 80011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses 80111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses 80211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses 80311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses 80411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses 80511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses 80611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036893500 # number of ReadExReq MSHR miss cycles 80711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036893500 # number of ReadExReq MSHR miss cycles 80811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61295500 # number of ReadCleanReq MSHR miss cycles 80911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61295500 # number of ReadCleanReq MSHR miss cycles 81011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46236000 # number of ReadSharedReq MSHR miss cycles 81111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46236000 # number of ReadSharedReq MSHR miss cycles 81211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61295500 # number of demand (read+write) MSHR miss cycles 81311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083129500 # number of demand (read+write) MSHR miss cycles 81411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 1144425000 # number of demand (read+write) MSHR miss cycles 81511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61295500 # number of overall MSHR miss cycles 81611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083129500 # number of overall MSHR miss cycles 81711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 1144425000 # number of overall MSHR miss cycles 81811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses 81911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses 82011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses 82111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses 82211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses 82311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses 82411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses 82511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses 82611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses 82711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses 82811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses 82911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses 83011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71293.557481 # average ReadExReq mshr miss latency 83111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71293.557481 # average ReadExReq mshr miss latency 83211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79193.152455 # average ReadCleanReq mshr miss latency 83311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79193.152455 # average ReadCleanReq mshr miss latency 83411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179906.614786 # average ReadSharedReq mshr miss latency 83511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179906.614786 # average ReadSharedReq mshr miss latency 83611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency 83711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency 83811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency 83911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency 84011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency 84111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency 84211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 1897111 # Total number of requests made to the snoop filter. 84311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 946125 # Number of requests hitting in the snoop filter with a single holder of the requested data. 84411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 84511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 84611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 84711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 84811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 84911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution 85011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 943285 # Transaction distribution 85111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution 85211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution 85311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 85411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 85511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution 85611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 903436 # Transaction distribution 85711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes) 85811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846504 # Packet count per connected master and slave (bytes) 85911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 2848113 # Packet count per connected master and slave (bytes) 86011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes) 86111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183040 # Cumulative packet size per connected master and slave (bytes) 86211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) 86311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 86411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 86511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 951002 # Request fanout histogram 86611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram 86711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram 86811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 86911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 950836 99.98% 99.98% # Request fanout histogram 87011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram 87111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 87211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 87311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 87411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 87511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 951002 # Request fanout histogram 87611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 1891845500 # Layer occupancy (ticks) 87711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%) 87811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1203499 # Layer occupancy (ticks) 87911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 88011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 1425302994 # Layer occupancy (ticks) 88111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 88211860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 15575 # Total number of requests made to the snoop filter. 88311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 88411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 88511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 88611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 88711606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 88811860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states 88911860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 1031 # Transaction distribution 89011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 14544 # Transaction distribution 89111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 14544 # Transaction distribution 89211860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 1031 # Transaction distribution 89311860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes) 89411860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes) 89511860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes) 89611860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes) 89711507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 89811570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 89911860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 15575 # Request fanout histogram 90011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 90111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 90211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 90311860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram 90411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 90511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 90611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 90711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 90811860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 15575 # Request fanout histogram 90911860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 21782500 # Layer occupancy (ticks) 91011507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 91111860Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 82144500 # Layer occupancy (ticks) 91211507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 91311507SCurtis.Dunham@arm.com 91411507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 915