config.json revision 11952
1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { 5 "kernel": "", 6 "mmap_using_noreserve": false, 7 "kernel_addr_check": true, 8 "rom": { 9 "range": "1099243192320:1099251580927:0:0:0:0", 10 "latency": 60, 11 "name": "rom", 12 "p_state_clk_gate_min": 2, 13 "eventq_index": 0, 14 "p_state_clk_gate_bins": 20, 15 "default_p_state": "UNDEFINED", 16 "kvm_map": true, 17 "clk_domain": "system.clk_domain", 18 "power_model": null, 19 "latency_var": 0, 20 "bandwidth": "0.000000", 21 "conf_table_reported": true, 22 "cxx_class": "SimpleMemory", 23 "p_state_clk_gate_max": 2000000000, 24 "path": "system.rom", 25 "null": false, 26 "type": "SimpleMemory", 27 "port": { 28 "peer": "system.membus.master[3]", 29 "role": "SLAVE" 30 }, 31 "in_addr_map": true 32 }, 33 "bridge": { 34 "ranges": [ 35 "133412421632:133412421639:0:0:0:0", 36 "134217728000:554050781183:0:0:0:0", 37 "644245094400:652835028991:0:0:0:0", 38 "725849473024:1095485095935:0:0:0:0", 39 "1099255955456:1099255955463:0:0:0:0" 40 ], 41 "slave": { 42 "peer": "system.membus.master[2]", 43 "role": "SLAVE" 44 }, 45 "name": "bridge", 46 "p_state_clk_gate_min": 2, 47 "p_state_clk_gate_bins": 20, 48 "cxx_class": "Bridge", 49 "req_size": 16, 50 "clk_domain": "system.clk_domain", 51 "power_model": null, 52 "delay": 100, 53 "eventq_index": 0, 54 "master": { 55 "peer": "system.iobus.slave[0]", 56 "role": "MASTER" 57 }, 58 "default_p_state": "UNDEFINED", 59 "p_state_clk_gate_max": 2000000000, 60 "path": "system.bridge", 61 "resp_size": 16, 62 "type": "Bridge" 63 }, 64 "iobus": { 65 "forward_latency": 1, 66 "slave": { 67 "peer": [ 68 "system.bridge.master" 69 ], 70 "role": "SLAVE" 71 }, 72 "name": "iobus", 73 "p_state_clk_gate_min": 2, 74 "p_state_clk_gate_bins": 20, 75 "cxx_class": "NoncoherentXBar", 76 "clk_domain": "system.clk_domain", 77 "power_model": null, 78 "width": 16, 79 "eventq_index": 0, 80 "master": { 81 "peer": [ 82 "system.t1000.fake_clk.pio", 83 "system.t1000.fake_membnks.pio", 84 "system.t1000.fake_l2_1.pio", 85 "system.t1000.fake_l2_2.pio", 86 "system.t1000.fake_l2_3.pio", 87 "system.t1000.fake_l2_4.pio", 88 "system.t1000.fake_l2esr_1.pio", 89 "system.t1000.fake_l2esr_2.pio", 90 "system.t1000.fake_l2esr_3.pio", 91 "system.t1000.fake_l2esr_4.pio", 92 "system.t1000.fake_ssi.pio", 93 "system.t1000.fake_jbi.pio", 94 "system.t1000.puart0.pio", 95 "system.t1000.hvuart.pio", 96 "system.disk0.pio" 97 ], 98 "role": "MASTER" 99 }, 100 "response_latency": 2, 101 "default_p_state": "UNDEFINED", 102 "p_state_clk_gate_max": 2000000000, 103 "path": "system.iobus", 104 "type": "NoncoherentXBar", 105 "use_default_range": false, 106 "frontend_latency": 2 107 }, 108 "t1000": { 109 "htod": { 110 "name": "htod", 111 "p_state_clk_gate_min": 2, 112 "pio": { 113 "peer": "system.membus.master[1]", 114 "role": "SLAVE" 115 }, 116 "p_state_clk_gate_bins": 20, 117 "cxx_class": "DumbTOD", 118 "pio_latency": 200, 119 "clk_domain": "system.clk_domain", 120 "power_model": null, 121 "system": "system", 122 "eventq_index": 0, 123 "time": "Thu Jan 1 00:00:00 2009", 124 "default_p_state": "UNDEFINED", 125 "p_state_clk_gate_max": 2000000000, 126 "path": "system.t1000.htod", 127 "pio_addr": 1099255906296, 128 "type": "DumbTOD" 129 }, 130 "puart0": { 131 "name": "puart0", 132 "p_state_clk_gate_min": 2, 133 "pio": { 134 "peer": "system.iobus.master[12]", 135 "role": "SLAVE" 136 }, 137 "p_state_clk_gate_bins": 20, 138 "cxx_class": "Uart8250", 139 "pio_latency": 200, 140 "clk_domain": "system.clk_domain", 141 "power_model": null, 142 "system": "system", 143 "terminal": "system.t1000.pterm", 144 "platform": "system.t1000", 145 "eventq_index": 0, 146 "default_p_state": "UNDEFINED", 147 "p_state_clk_gate_max": 2000000000, 148 "path": "system.t1000.puart0", 149 "pio_addr": 133412421632, 150 "type": "Uart8250" 151 }, 152 "fake_membnks": { 153 "pio": { 154 "peer": "system.iobus.master[1]", 155 "role": "SLAVE" 156 }, 157 "ret_data64": 0, 158 "fake_mem": false, 159 "clk_domain": "system.clk_domain", 160 "cxx_class": "IsaFake", 161 "pio_addr": 648540061696, 162 "update_data": false, 163 "warn_access": "", 164 "pio_latency": 200, 165 "system": "system", 166 "eventq_index": 0, 167 "default_p_state": "UNDEFINED", 168 "p_state_clk_gate_max": 2000000000, 169 "type": "IsaFake", 170 "p_state_clk_gate_min": 2, 171 "power_model": null, 172 "ret_data32": 4294967295, 173 "path": "system.t1000.fake_membnks", 174 "ret_data16": 65535, 175 "ret_data8": 255, 176 "name": "fake_membnks", 177 "ret_bad_addr": false, 178 "pio_size": 16384, 179 "p_state_clk_gate_bins": 20 180 }, 181 "cxx_class": "T1000", 182 "fake_jbi": { 183 "pio": { 184 "peer": "system.iobus.master[11]", 185 "role": "SLAVE" 186 }, 187 "ret_data64": 18446744073709551615, 188 "fake_mem": false, 189 "clk_domain": "system.clk_domain", 190 "cxx_class": "IsaFake", 191 "pio_addr": 549755813888, 192 "update_data": false, 193 "warn_access": "", 194 "pio_latency": 200, 195 "system": "system", 196 "eventq_index": 0, 197 "default_p_state": "UNDEFINED", 198 "p_state_clk_gate_max": 2000000000, 199 "type": "IsaFake", 200 "p_state_clk_gate_min": 2, 201 "power_model": null, 202 "ret_data32": 4294967295, 203 "path": "system.t1000.fake_jbi", 204 "ret_data16": 65535, 205 "ret_data8": 255, 206 "name": "fake_jbi", 207 "ret_bad_addr": false, 208 "pio_size": 4294967296, 209 "p_state_clk_gate_bins": 20 210 }, 211 "intrctrl": "system.intrctrl", 212 "fake_l2esr_2": { 213 "pio": { 214 "peer": "system.iobus.master[7]", 215 "role": "SLAVE" 216 }, 217 "ret_data64": 0, 218 "fake_mem": false, 219 "clk_domain": "system.clk_domain", 220 "cxx_class": "IsaFake", 221 "pio_addr": 734439407680, 222 "update_data": true, 223 "warn_access": "", 224 "pio_latency": 200, 225 "system": "system", 226 "eventq_index": 0, 227 "default_p_state": "UNDEFINED", 228 "p_state_clk_gate_max": 2000000000, 229 "type": "IsaFake", 230 "p_state_clk_gate_min": 2, 231 "power_model": null, 232 "ret_data32": 4294967295, 233 "path": "system.t1000.fake_l2esr_2", 234 "ret_data16": 65535, 235 "ret_data8": 255, 236 "name": "fake_l2esr_2", 237 "ret_bad_addr": false, 238 "pio_size": 8, 239 "p_state_clk_gate_bins": 20 240 }, 241 "system": "system", 242 "eventq_index": 0, 243 "hterm": { 244 "name": "hterm", 245 "output": true, 246 "number": 0, 247 "intr_control": "system.intrctrl", 248 "eventq_index": 0, 249 "cxx_class": "Terminal", 250 "path": "system.t1000.hterm", 251 "type": "Terminal", 252 "port": 3456 253 }, 254 "type": "T1000", 255 "fake_l2_4": { 256 "pio": { 257 "peer": "system.iobus.master[5]", 258 "role": "SLAVE" 259 }, 260 "ret_data64": 1, 261 "fake_mem": false, 262 "clk_domain": "system.clk_domain", 263 "cxx_class": "IsaFake", 264 "pio_addr": 725849473216, 265 "update_data": true, 266 "warn_access": "", 267 "pio_latency": 200, 268 "system": "system", 269 "eventq_index": 0, 270 "default_p_state": "UNDEFINED", 271 "p_state_clk_gate_max": 2000000000, 272 "type": "IsaFake", 273 "p_state_clk_gate_min": 2, 274 "power_model": null, 275 "ret_data32": 4294967295, 276 "path": "system.t1000.fake_l2_4", 277 "ret_data16": 65535, 278 "ret_data8": 255, 279 "name": "fake_l2_4", 280 "ret_bad_addr": false, 281 "pio_size": 8, 282 "p_state_clk_gate_bins": 20 283 }, 284 "fake_l2_1": { 285 "pio": { 286 "peer": "system.iobus.master[2]", 287 "role": "SLAVE" 288 }, 289 "ret_data64": 1, 290 "fake_mem": false, 291 "clk_domain": "system.clk_domain", 292 "cxx_class": "IsaFake", 293 "pio_addr": 725849473024, 294 "update_data": true, 295 "warn_access": "", 296 "pio_latency": 200, 297 "system": "system", 298 "eventq_index": 0, 299 "default_p_state": "UNDEFINED", 300 "p_state_clk_gate_max": 2000000000, 301 "type": "IsaFake", 302 "p_state_clk_gate_min": 2, 303 "power_model": null, 304 "ret_data32": 4294967295, 305 "path": "system.t1000.fake_l2_1", 306 "ret_data16": 65535, 307 "ret_data8": 255, 308 "name": "fake_l2_1", 309 "ret_bad_addr": false, 310 "pio_size": 8, 311 "p_state_clk_gate_bins": 20 312 }, 313 "fake_l2_2": { 314 "pio": { 315 "peer": "system.iobus.master[3]", 316 "role": "SLAVE" 317 }, 318 "ret_data64": 1, 319 "fake_mem": false, 320 "clk_domain": "system.clk_domain", 321 "cxx_class": "IsaFake", 322 "pio_addr": 725849473088, 323 "update_data": true, 324 "warn_access": "", 325 "pio_latency": 200, 326 "system": "system", 327 "eventq_index": 0, 328 "default_p_state": "UNDEFINED", 329 "p_state_clk_gate_max": 2000000000, 330 "type": "IsaFake", 331 "p_state_clk_gate_min": 2, 332 "power_model": null, 333 "ret_data32": 4294967295, 334 "path": "system.t1000.fake_l2_2", 335 "ret_data16": 65535, 336 "ret_data8": 255, 337 "name": "fake_l2_2", 338 "ret_bad_addr": false, 339 "pio_size": 8, 340 "p_state_clk_gate_bins": 20 341 }, 342 "fake_l2_3": { 343 "pio": { 344 "peer": "system.iobus.master[4]", 345 "role": "SLAVE" 346 }, 347 "ret_data64": 1, 348 "fake_mem": false, 349 "clk_domain": "system.clk_domain", 350 "cxx_class": "IsaFake", 351 "pio_addr": 725849473152, 352 "update_data": true, 353 "warn_access": "", 354 "pio_latency": 200, 355 "system": "system", 356 "eventq_index": 0, 357 "default_p_state": "UNDEFINED", 358 "p_state_clk_gate_max": 2000000000, 359 "type": "IsaFake", 360 "p_state_clk_gate_min": 2, 361 "power_model": null, 362 "ret_data32": 4294967295, 363 "path": "system.t1000.fake_l2_3", 364 "ret_data16": 65535, 365 "ret_data8": 255, 366 "name": "fake_l2_3", 367 "ret_bad_addr": false, 368 "pio_size": 8, 369 "p_state_clk_gate_bins": 20 370 }, 371 "pterm": { 372 "name": "pterm", 373 "output": true, 374 "number": 0, 375 "intr_control": "system.intrctrl", 376 "eventq_index": 0, 377 "cxx_class": "Terminal", 378 "path": "system.t1000.pterm", 379 "type": "Terminal", 380 "port": 3456 381 }, 382 "path": "system.t1000", 383 "iob": { 384 "name": "iob", 385 "p_state_clk_gate_min": 2, 386 "pio": { 387 "peer": "system.membus.master[0]", 388 "role": "SLAVE" 389 }, 390 "p_state_clk_gate_bins": 20, 391 "cxx_class": "Iob", 392 "pio_latency": 2, 393 "clk_domain": "system.clk_domain", 394 "power_model": null, 395 "system": "system", 396 "platform": "system.t1000", 397 "eventq_index": 0, 398 "default_p_state": "UNDEFINED", 399 "p_state_clk_gate_max": 2000000000, 400 "path": "system.t1000.iob", 401 "type": "Iob" 402 }, 403 "hvuart": { 404 "name": "hvuart", 405 "p_state_clk_gate_min": 2, 406 "pio": { 407 "peer": "system.iobus.master[13]", 408 "role": "SLAVE" 409 }, 410 "p_state_clk_gate_bins": 20, 411 "cxx_class": "Uart8250", 412 "pio_latency": 200, 413 "clk_domain": "system.clk_domain", 414 "power_model": null, 415 "system": "system", 416 "terminal": "system.t1000.hterm", 417 "platform": "system.t1000", 418 "eventq_index": 0, 419 "default_p_state": "UNDEFINED", 420 "p_state_clk_gate_max": 2000000000, 421 "path": "system.t1000.hvuart", 422 "pio_addr": 1099255955456, 423 "type": "Uart8250" 424 }, 425 "name": "t1000", 426 "fake_l2esr_3": { 427 "pio": { 428 "peer": "system.iobus.master[8]", 429 "role": "SLAVE" 430 }, 431 "ret_data64": 0, 432 "fake_mem": false, 433 "clk_domain": "system.clk_domain", 434 "cxx_class": "IsaFake", 435 "pio_addr": 734439407744, 436 "update_data": true, 437 "warn_access": "", 438 "pio_latency": 200, 439 "system": "system", 440 "eventq_index": 0, 441 "default_p_state": "UNDEFINED", 442 "p_state_clk_gate_max": 2000000000, 443 "type": "IsaFake", 444 "p_state_clk_gate_min": 2, 445 "power_model": null, 446 "ret_data32": 4294967295, 447 "path": "system.t1000.fake_l2esr_3", 448 "ret_data16": 65535, 449 "ret_data8": 255, 450 "name": "fake_l2esr_3", 451 "ret_bad_addr": false, 452 "pio_size": 8, 453 "p_state_clk_gate_bins": 20 454 }, 455 "fake_ssi": { 456 "pio": { 457 "peer": "system.iobus.master[10]", 458 "role": "SLAVE" 459 }, 460 "ret_data64": 18446744073709551615, 461 "fake_mem": false, 462 "clk_domain": "system.clk_domain", 463 "cxx_class": "IsaFake", 464 "pio_addr": 1095216660480, 465 "update_data": false, 466 "warn_access": "", 467 "pio_latency": 200, 468 "system": "system", 469 "eventq_index": 0, 470 "default_p_state": "UNDEFINED", 471 "p_state_clk_gate_max": 2000000000, 472 "type": "IsaFake", 473 "p_state_clk_gate_min": 2, 474 "power_model": null, 475 "ret_data32": 4294967295, 476 "path": "system.t1000.fake_ssi", 477 "ret_data16": 65535, 478 "ret_data8": 255, 479 "name": "fake_ssi", 480 "ret_bad_addr": false, 481 "pio_size": 268435456, 482 "p_state_clk_gate_bins": 20 483 }, 484 "fake_l2esr_1": { 485 "pio": { 486 "peer": "system.iobus.master[6]", 487 "role": "SLAVE" 488 }, 489 "ret_data64": 0, 490 "fake_mem": false, 491 "clk_domain": "system.clk_domain", 492 "cxx_class": "IsaFake", 493 "pio_addr": 734439407616, 494 "update_data": true, 495 "warn_access": "", 496 "pio_latency": 200, 497 "system": "system", 498 "eventq_index": 0, 499 "default_p_state": "UNDEFINED", 500 "p_state_clk_gate_max": 2000000000, 501 "type": "IsaFake", 502 "p_state_clk_gate_min": 2, 503 "power_model": null, 504 "ret_data32": 4294967295, 505 "path": "system.t1000.fake_l2esr_1", 506 "ret_data16": 65535, 507 "ret_data8": 255, 508 "name": "fake_l2esr_1", 509 "ret_bad_addr": false, 510 "pio_size": 8, 511 "p_state_clk_gate_bins": 20 512 }, 513 "fake_l2esr_4": { 514 "pio": { 515 "peer": "system.iobus.master[9]", 516 "role": "SLAVE" 517 }, 518 "ret_data64": 0, 519 "fake_mem": false, 520 "clk_domain": "system.clk_domain", 521 "cxx_class": "IsaFake", 522 "pio_addr": 734439407808, 523 "update_data": true, 524 "warn_access": "", 525 "pio_latency": 200, 526 "system": "system", 527 "eventq_index": 0, 528 "default_p_state": "UNDEFINED", 529 "p_state_clk_gate_max": 2000000000, 530 "type": "IsaFake", 531 "p_state_clk_gate_min": 2, 532 "power_model": null, 533 "ret_data32": 4294967295, 534 "path": "system.t1000.fake_l2esr_4", 535 "ret_data16": 65535, 536 "ret_data8": 255, 537 "name": "fake_l2esr_4", 538 "ret_bad_addr": false, 539 "pio_size": 8, 540 "p_state_clk_gate_bins": 20 541 }, 542 "fake_clk": { 543 "pio": { 544 "peer": "system.iobus.master[0]", 545 "role": "SLAVE" 546 }, 547 "ret_data64": 18446744073709551615, 548 "fake_mem": false, 549 "clk_domain": "system.clk_domain", 550 "cxx_class": "IsaFake", 551 "pio_addr": 644245094400, 552 "update_data": false, 553 "warn_access": "", 554 "pio_latency": 200, 555 "system": "system", 556 "eventq_index": 0, 557 "default_p_state": "UNDEFINED", 558 "p_state_clk_gate_max": 2000000000, 559 "type": "IsaFake", 560 "p_state_clk_gate_min": 2, 561 "power_model": null, 562 "ret_data32": 4294967295, 563 "path": "system.t1000.fake_clk", 564 "ret_data16": 65535, 565 "ret_data8": 255, 566 "name": "fake_clk", 567 "ret_bad_addr": false, 568 "pio_size": 4294967296, 569 "p_state_clk_gate_bins": 20 570 } 571 }, 572 "partition_desc_addr": 133445976064, 573 "symbolfile": "", 574 "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh", 575 "thermal_model": null, 576 "hypervisor_addr": 1099243257856, 577 "mem_ranges": [ 578 "1048576:68157439:0:0:0:0", 579 "2147483648:2415919103:0:0:0:0" 580 ], 581 "cxx_class": "SparcSystem", 582 "work_begin_cpu_id_exit": -1, 583 "load_offset": 0, 584 "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin", 585 "work_end_ckpt_count": 0, 586 "work_begin_exit_count": 0, 587 "openboot_addr": 1099243716608, 588 "p_state_clk_gate_min": 2, 589 "nvram_addr": 133429198848, 590 "memories": [ 591 "system.hypervisor_desc", 592 "system.nvram", 593 "system.partition_desc", 594 "system.physmem0", 595 "system.physmem1", 596 "system.rom" 597 ], 598 "work_begin_ckpt_count": 0, 599 "partition_desc": { 600 "range": "133445976064:133445984255:0:0:0:0", 601 "latency": 60, 602 "name": "partition_desc", 603 "p_state_clk_gate_min": 2, 604 "eventq_index": 0, 605 "p_state_clk_gate_bins": 20, 606 "default_p_state": "UNDEFINED", 607 "kvm_map": true, 608 "clk_domain": "system.clk_domain", 609 "power_model": null, 610 "latency_var": 0, 611 "bandwidth": "0.000000", 612 "conf_table_reported": true, 613 "cxx_class": "SimpleMemory", 614 "p_state_clk_gate_max": 2000000000, 615 "path": "system.partition_desc", 616 "null": false, 617 "type": "SimpleMemory", 618 "port": { 619 "peer": "system.membus.master[6]", 620 "role": "SLAVE" 621 }, 622 "in_addr_map": true 623 }, 624 "clk_domain": { 625 "name": "clk_domain", 626 "clock": [ 627 2 628 ], 629 "init_perf_level": 0, 630 "voltage_domain": "system.voltage_domain", 631 "eventq_index": 0, 632 "cxx_class": "SrcClockDomain", 633 "path": "system.clk_domain", 634 "type": "SrcClockDomain", 635 "domain_id": -1 636 }, 637 "hypervisor_desc": { 638 "range": "133446500352:133446508543:0:0:0:0", 639 "latency": 60, 640 "name": "hypervisor_desc", 641 "p_state_clk_gate_min": 2, 642 "eventq_index": 0, 643 "p_state_clk_gate_bins": 20, 644 "default_p_state": "UNDEFINED", 645 "kvm_map": true, 646 "clk_domain": "system.clk_domain", 647 "power_model": null, 648 "latency_var": 0, 649 "bandwidth": "0.000000", 650 "conf_table_reported": true, 651 "cxx_class": "SimpleMemory", 652 "p_state_clk_gate_max": 2000000000, 653 "path": "system.hypervisor_desc", 654 "null": false, 655 "type": "SimpleMemory", 656 "port": { 657 "peer": "system.membus.master[5]", 658 "role": "SLAVE" 659 }, 660 "in_addr_map": true 661 }, 662 "membus": { 663 "point_of_coherency": true, 664 "system": "system", 665 "response_latency": 2, 666 "cxx_class": "CoherentXBar", 667 "badaddr_responder": { 668 "pio": { 669 "peer": "system.membus.default", 670 "role": "SLAVE" 671 }, 672 "ret_data64": 18446744073709551615, 673 "fake_mem": false, 674 "clk_domain": "system.clk_domain", 675 "cxx_class": "IsaFake", 676 "pio_addr": 0, 677 "update_data": false, 678 "warn_access": "", 679 "pio_latency": 200, 680 "system": "system", 681 "eventq_index": 0, 682 "default_p_state": "UNDEFINED", 683 "p_state_clk_gate_max": 2000000000, 684 "type": "IsaFake", 685 "p_state_clk_gate_min": 2, 686 "power_model": null, 687 "ret_data32": 4294967295, 688 "path": "system.membus.badaddr_responder", 689 "ret_data16": 65535, 690 "ret_data8": 255, 691 "name": "badaddr_responder", 692 "ret_bad_addr": true, 693 "pio_size": 8, 694 "p_state_clk_gate_bins": 20 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