config.json revision 10315 
1{
2    "name": null, 
3    "sim_quantum": 0, 
4    "system": {
5        "bridge": {
6            "slave": {
7                "peer": "system.membus.master[2]", 
8                "role": "SLAVE"
9            }, 
10            "name": "bridge", 
11            "req_size": 16, 
12            "delay": 5.0000000000000004e-08, 
13            "eventq_index": 0, 
14            "master": {
15                "peer": "system.iobus.slave[0]", 
16                "role": "MASTER"
17            }, 
18            "cxx_class": "Bridge", 
19            "path": "system.bridge", 
20            "resp_size": 16, 
21            "type": "Bridge"
22        }, 
23        "kernel_addr_check": true, 
24        "rom": {
25            "latency": 3.0000000000000004e-08, 
26            "name": "rom", 
27            "eventq_index": 0, 
28            "latency_var": 0.0, 
29            "conf_table_reported": true, 
30            "cxx_class": "SimpleMemory", 
31            "path": "system.rom", 
32            "null": false, 
33            "type": "SimpleMemory", 
34            "port": {
35                "peer": "system.membus.master[3]", 
36                "role": "SLAVE"
37            }, 
38            "in_addr_map": true
39        }, 
40        "membus": {
41            "slave": {
42                "peer": [
43                    "system.system_port", 
44                    "system.cpu.icache_port", 
45                    "system.cpu.dcache_port"
46                ], 
47                "role": "SLAVE"
48            }, 
49            "name": "membus", 
50            "badaddr_responder": {
51                "ret_data8": 255, 
52                "name": "badaddr_responder", 
53                "pio": {
54                    "peer": "system.membus.default", 
55                    "role": "SLAVE"
56                }, 
57                "ret_bad_addr": true, 
58                "pio_latency": 1.0000000000000001e-07, 
59                "fake_mem": false, 
60                "pio_size": 8, 
61                "ret_data32": 4294967295, 
62                "eventq_index": 0, 
63                "update_data": false, 
64                "ret_data64": 18446744073709551615, 
65                "cxx_class": "IsaFake", 
66                "path": "system.membus.badaddr_responder", 
67                "pio_addr": 0, 
68                "type": "IsaFake", 
69                "ret_data16": 65535
70            }, 
71            "default": {
72                "peer": "system.membus.badaddr_responder.pio", 
73                "role": "MASTER"
74            }, 
75            "header_cycles": 1, 
76            "width": 8, 
77            "eventq_index": 0, 
78            "master": {
79                "peer": [
80                    "system.t1000.iob.pio", 
81                    "system.t1000.htod.pio", 
82                    "system.bridge.slave", 
83                    "system.rom.port", 
84                    "system.nvram.port", 
85                    "system.hypervisor_desc.port", 
86                    "system.partition_desc.port", 
87                    "system.physmem0.port", 
88                    "system.physmem1.port"
89                ], 
90                "role": "MASTER"
91            }, 
92            "cxx_class": "CoherentBus", 
93            "path": "system.membus", 
94            "type": "CoherentBus", 
95            "use_default_range": false
96        }, 
97        "iobus": {
98            "slave": {
99                "peer": [
100                    "system.bridge.master"
101                ], 
102                "role": "SLAVE"
103            }, 
104            "name": "iobus", 
105            "header_cycles": 1, 
106            "width": 8, 
107            "eventq_index": 0, 
108            "master": {
109                "peer": [
110                    "system.t1000.fake_clk.pio", 
111                    "system.t1000.fake_membnks.pio", 
112                    "system.t1000.fake_l2_1.pio", 
113                    "system.t1000.fake_l2_2.pio", 
114                    "system.t1000.fake_l2_3.pio", 
115                    "system.t1000.fake_l2_4.pio", 
116                    "system.t1000.fake_l2esr_1.pio", 
117                    "system.t1000.fake_l2esr_2.pio", 
118                    "system.t1000.fake_l2esr_3.pio", 
119                    "system.t1000.fake_l2esr_4.pio", 
120                    "system.t1000.fake_ssi.pio", 
121                    "system.t1000.fake_jbi.pio", 
122                    "system.t1000.puart0.pio", 
123                    "system.t1000.hvuart.pio", 
124                    "system.disk0.pio"
125                ], 
126                "role": "MASTER"
127            }, 
128            "cxx_class": "NoncoherentBus", 
129            "path": "system.iobus", 
130            "type": "NoncoherentBus", 
131            "use_default_range": false
132        }, 
133        "t1000": {
134            "htod": {
135                "name": "htod", 
136                "pio": {
137                    "peer": "system.membus.master[1]", 
138                    "role": "SLAVE"
139                }, 
140                "time": "Thu Jan  1 00:00:00 2009", 
141                "pio_latency": 1.0000000000000001e-07, 
142                "eventq_index": 0, 
143                "cxx_class": "DumbTOD", 
144                "path": "system.t1000.htod", 
145                "pio_addr": 1099255906296, 
146                "type": "DumbTOD"
147            }, 
148            "puart0": {
149                "name": "puart0", 
150                "pio": {
151                    "peer": "system.iobus.master[12]", 
152                    "role": "SLAVE"
153                }, 
154                "pio_latency": 1.0000000000000001e-07, 
155                "eventq_index": 0, 
156                "cxx_class": "Uart8250", 
157                "path": "system.t1000.puart0", 
158                "pio_addr": 133412421632, 
159                "type": "Uart8250"
160            }, 
161            "fake_membnks": {
162                "ret_data8": 255, 
163                "name": "fake_membnks", 
164                "pio": {
165                    "peer": "system.iobus.master[1]", 
166                    "role": "SLAVE"
167                }, 
168                "ret_bad_addr": false, 
169                "pio_latency": 1.0000000000000001e-07, 
170                "fake_mem": false, 
171                "pio_size": 16384, 
172                "ret_data32": 4294967295, 
173                "eventq_index": 0, 
174                "update_data": false, 
175                "ret_data64": 0, 
176                "cxx_class": "IsaFake", 
177                "path": "system.t1000.fake_membnks", 
178                "pio_addr": 648540061696, 
179                "type": "IsaFake", 
180                "ret_data16": 65535
181            }, 
182            "cxx_class": "T1000", 
183            "fake_jbi": {
184                "ret_data8": 255, 
185                "name": "fake_jbi", 
186                "pio": {
187                    "peer": "system.iobus.master[11]", 
188                    "role": "SLAVE"
189                }, 
190                "ret_bad_addr": false, 
191                "pio_latency": 1.0000000000000001e-07, 
192                "fake_mem": false, 
193                "pio_size": 4294967296, 
194                "ret_data32": 4294967295, 
195                "eventq_index": 0, 
196                "update_data": false, 
197                "ret_data64": 18446744073709551615, 
198                "cxx_class": "IsaFake", 
199                "path": "system.t1000.fake_jbi", 
200                "pio_addr": 549755813888, 
201                "type": "IsaFake", 
202                "ret_data16": 65535
203            }, 
204            "fake_l2esr_2": {
205                "ret_data8": 255, 
206                "name": "fake_l2esr_2", 
207                "pio": {
208                    "peer": "system.iobus.master[7]", 
209                    "role": "SLAVE"
210                }, 
211                "ret_bad_addr": false, 
212                "pio_latency": 1.0000000000000001e-07, 
213                "fake_mem": false, 
214                "pio_size": 8, 
215                "ret_data32": 4294967295, 
216                "eventq_index": 0, 
217                "update_data": true, 
218                "ret_data64": 0, 
219                "cxx_class": "IsaFake", 
220                "path": "system.t1000.fake_l2esr_2", 
221                "pio_addr": 734439407680, 
222                "type": "IsaFake", 
223                "ret_data16": 65535
224            }, 
225            "eventq_index": 0, 
226            "hterm": {
227                "name": "hterm", 
228                "output": true, 
229                "number": 0, 
230                "eventq_index": 0, 
231                "cxx_class": "Terminal", 
232                "path": "system.t1000.hterm", 
233                "type": "Terminal", 
234                "port": 3456
235            }, 
236            "type": "T1000", 
237            "fake_l2_4": {
238                "ret_data8": 255, 
239                "name": "fake_l2_4", 
240                "pio": {
241                    "peer": "system.iobus.master[5]", 
242                    "role": "SLAVE"
243                }, 
244                "ret_bad_addr": false, 
245                "pio_latency": 1.0000000000000001e-07, 
246                "fake_mem": false, 
247                "pio_size": 8, 
248                "ret_data32": 4294967295, 
249                "eventq_index": 0, 
250                "update_data": true, 
251                "ret_data64": 1, 
252                "cxx_class": "IsaFake", 
253                "path": "system.t1000.fake_l2_4", 
254                "pio_addr": 725849473216, 
255                "type": "IsaFake", 
256                "ret_data16": 65535
257            }, 
258            "fake_l2_1": {
259                "ret_data8": 255, 
260                "name": "fake_l2_1", 
261                "pio": {
262                    "peer": "system.iobus.master[2]", 
263                    "role": "SLAVE"
264                }, 
265                "ret_bad_addr": false, 
266                "pio_latency": 1.0000000000000001e-07, 
267                "fake_mem": false, 
268                "pio_size": 8, 
269                "ret_data32": 4294967295, 
270                "eventq_index": 0, 
271                "update_data": true, 
272                "ret_data64": 1, 
273                "cxx_class": "IsaFake", 
274                "path": "system.t1000.fake_l2_1", 
275                "pio_addr": 725849473024, 
276                "type": "IsaFake", 
277                "ret_data16": 65535
278            }, 
279            "fake_l2_2": {
280                "ret_data8": 255, 
281                "name": "fake_l2_2", 
282                "pio": {
283                    "peer": "system.iobus.master[3]", 
284                    "role": "SLAVE"
285                }, 
286                "ret_bad_addr": false, 
287                "pio_latency": 1.0000000000000001e-07, 
288                "fake_mem": false, 
289                "pio_size": 8, 
290                "ret_data32": 4294967295, 
291                "eventq_index": 0, 
292                "update_data": true, 
293                "ret_data64": 1, 
294                "cxx_class": "IsaFake", 
295                "path": "system.t1000.fake_l2_2", 
296                "pio_addr": 725849473088, 
297                "type": "IsaFake", 
298                "ret_data16": 65535
299            }, 
300            "fake_l2_3": {
301                "ret_data8": 255, 
302                "name": "fake_l2_3", 
303                "pio": {
304                    "peer": "system.iobus.master[4]", 
305                    "role": "SLAVE"
306                }, 
307                "ret_bad_addr": false, 
308                "pio_latency": 1.0000000000000001e-07, 
309                "fake_mem": false, 
310                "pio_size": 8, 
311                "ret_data32": 4294967295, 
312                "eventq_index": 0, 
313                "update_data": true, 
314                "ret_data64": 1, 
315                "cxx_class": "IsaFake", 
316                "path": "system.t1000.fake_l2_3", 
317                "pio_addr": 725849473152, 
318                "type": "IsaFake", 
319                "ret_data16": 65535
320            }, 
321            "pterm": {
322                "name": "pterm", 
323                "output": true, 
324                "number": 0, 
325                "eventq_index": 0, 
326                "cxx_class": "Terminal", 
327                "path": "system.t1000.pterm", 
328                "type": "Terminal", 
329                "port": 3456
330            }, 
331            "path": "system.t1000", 
332            "iob": {
333                "name": "iob", 
334                "pio": {
335                    "peer": "system.membus.master[0]", 
336                    "role": "SLAVE"
337                }, 
338                "pio_latency": 1e-09, 
339                "eventq_index": 0, 
340                "cxx_class": "Iob", 
341                "path": "system.t1000.iob", 
342                "type": "Iob"
343            }, 
344            "hvuart": {
345                "name": "hvuart", 
346                "pio": {
347                    "peer": "system.iobus.master[13]", 
348                    "role": "SLAVE"
349                }, 
350                "pio_latency": 1.0000000000000001e-07, 
351                "eventq_index": 0, 
352                "cxx_class": "Uart8250", 
353                "path": "system.t1000.hvuart", 
354                "pio_addr": 1099255955456, 
355                "type": "Uart8250"
356            }, 
357            "name": "t1000", 
358            "fake_l2esr_3": {
359                "ret_data8": 255, 
360                "name": "fake_l2esr_3", 
361                "pio": {
362                    "peer": "system.iobus.master[8]", 
363                    "role": "SLAVE"
364                }, 
365                "ret_bad_addr": false, 
366                "pio_latency": 1.0000000000000001e-07, 
367                "fake_mem": false, 
368                "pio_size": 8, 
369                "ret_data32": 4294967295, 
370                "eventq_index": 0, 
371                "update_data": true, 
372                "ret_data64": 0, 
373                "cxx_class": "IsaFake", 
374                "path": "system.t1000.fake_l2esr_3", 
375                "pio_addr": 734439407744, 
376                "type": "IsaFake", 
377                "ret_data16": 65535
378            }, 
379            "fake_ssi": {
380                "ret_data8": 255, 
381                "name": "fake_ssi", 
382                "pio": {
383                    "peer": "system.iobus.master[10]", 
384                    "role": "SLAVE"
385                }, 
386                "ret_bad_addr": false, 
387                "pio_latency": 1.0000000000000001e-07, 
388                "fake_mem": false, 
389                "pio_size": 268435456, 
390                "ret_data32": 4294967295, 
391                "eventq_index": 0, 
392                "update_data": false, 
393                "ret_data64": 18446744073709551615, 
394                "cxx_class": "IsaFake", 
395                "path": "system.t1000.fake_ssi", 
396                "pio_addr": 1095216660480, 
397                "type": "IsaFake", 
398                "ret_data16": 65535
399            }, 
400            "fake_l2esr_1": {
401                "ret_data8": 255, 
402                "name": "fake_l2esr_1", 
403                "pio": {
404                    "peer": "system.iobus.master[6]", 
405                    "role": "SLAVE"
406                }, 
407                "ret_bad_addr": false, 
408                "pio_latency": 1.0000000000000001e-07, 
409                "fake_mem": false, 
410                "pio_size": 8, 
411                "ret_data32": 4294967295, 
412                "eventq_index": 0, 
413                "update_data": true, 
414                "ret_data64": 0, 
415                "cxx_class": "IsaFake", 
416                "path": "system.t1000.fake_l2esr_1", 
417                "pio_addr": 734439407616, 
418                "type": "IsaFake", 
419                "ret_data16": 65535
420            }, 
421            "fake_l2esr_4": {
422                "ret_data8": 255, 
423                "name": "fake_l2esr_4", 
424                "pio": {
425                    "peer": "system.iobus.master[9]", 
426                    "role": "SLAVE"
427                }, 
428                "ret_bad_addr": false, 
429                "pio_latency": 1.0000000000000001e-07, 
430                "fake_mem": false, 
431                "pio_size": 8, 
432                "ret_data32": 4294967295, 
433                "eventq_index": 0, 
434                "update_data": true, 
435                "ret_data64": 0, 
436                "cxx_class": "IsaFake", 
437                "path": "system.t1000.fake_l2esr_4", 
438                "pio_addr": 734439407808, 
439                "type": "IsaFake", 
440                "ret_data16": 65535
441            }, 
442            "fake_clk": {
443                "ret_data8": 255, 
444                "name": "fake_clk", 
445                "pio": {
446                    "peer": "system.iobus.master[0]", 
447                    "role": "SLAVE"
448                }, 
449                "ret_bad_addr": false, 
450                "pio_latency": 1.0000000000000001e-07, 
451                "fake_mem": false, 
452                "pio_size": 4294967296, 
453                "ret_data32": 4294967295, 
454                "eventq_index": 0, 
455                "update_data": false, 
456                "ret_data64": 18446744073709551615, 
457                "cxx_class": "IsaFake", 
458                "path": "system.t1000.fake_clk", 
459                "pio_addr": 644245094400, 
460                "type": "IsaFake", 
461                "ret_data16": 65535
462            }
463        }, 
464        "partition_desc_addr": 133445976064, 
465        "physmem": [
466            {
467                "latency": 3.0000000000000004e-08, 
468                "name": "physmem0", 
469                "eventq_index": 0, 
470                "latency_var": 0.0, 
471                "conf_table_reported": true, 
472                "cxx_class": "SimpleMemory", 
473                "path": "system.physmem0", 
474                "null": false, 
475                "type": "SimpleMemory", 
476                "port": {
477                    "peer": "system.membus.master[7]", 
478                    "role": "SLAVE"
479                }, 
480                "in_addr_map": true
481            }, 
482            {
483                "latency": 3.0000000000000004e-08, 
484                "name": "physmem1", 
485                "eventq_index": 0, 
486                "latency_var": 0.0, 
487                "conf_table_reported": true, 
488                "cxx_class": "SimpleMemory", 
489                "path": "system.physmem1", 
490                "null": false, 
491                "type": "SimpleMemory", 
492                "port": {
493                    "peer": "system.membus.master[8]", 
494                    "role": "SLAVE"
495                }, 
496                "in_addr_map": true
497            }
498        ], 
499        "hypervisor_addr": 1099243257856, 
500        "cxx_class": "SparcSystem", 
501        "load_offset": 0, 
502        "openboot_addr": 1099243716608, 
503        "work_end_ckpt_count": 0, 
504        "nvram_addr": 133429198848, 
505        "work_begin_ckpt_count": 0, 
506        "partition_desc": {
507            "latency": 3.0000000000000004e-08, 
508            "name": "partition_desc", 
509            "eventq_index": 0, 
510            "latency_var": 0.0, 
511            "conf_table_reported": true, 
512            "cxx_class": "SimpleMemory", 
513            "path": "system.partition_desc", 
514            "null": false, 
515            "type": "SimpleMemory", 
516            "port": {
517                "peer": "system.membus.master[6]", 
518                "role": "SLAVE"
519            }, 
520            "in_addr_map": true
521        }, 
522        "clk_domain": {
523            "name": "clk_domain", 
524            "init_perf_level": 0, 
525            "eventq_index": 0, 
526            "cxx_class": "SrcClockDomain", 
527            "path": "system.clk_domain", 
528            "type": "SrcClockDomain", 
529            "domain_id": -1
530        }, 
531        "hypervisor_desc": {
532            "latency": 3.0000000000000004e-08, 
533            "name": "hypervisor_desc", 
534            "eventq_index": 0, 
535            "latency_var": 0.0, 
536            "conf_table_reported": true, 
537            "cxx_class": "SimpleMemory", 
538            "path": "system.hypervisor_desc", 
539            "null": false, 
540            "type": "SimpleMemory", 
541            "port": {
542                "peer": "system.membus.master[5]", 
543                "role": "SLAVE"
544            }, 
545            "in_addr_map": true
546        }, 
547        "nvram": {
548            "latency": 3.0000000000000004e-08, 
549            "name": "nvram", 
550            "eventq_index": 0, 
551            "latency_var": 0.0, 
552            "conf_table_reported": true, 
553            "cxx_class": "SimpleMemory", 
554            "path": "system.nvram", 
555            "null": false, 
556            "type": "SimpleMemory", 
557            "port": {
558                "peer": "system.membus.master[4]", 
559                "role": "SLAVE"
560            }, 
561            "in_addr_map": true
562        }, 
563        "eventq_index": 0, 
564        "dvfs_handler": {
565            "enable": false, 
566            "name": "dvfs_handler", 
567            "transition_latency": 9.999999999999999e-05, 
568            "eventq_index": 0, 
569            "cxx_class": "DVFSHandler", 
570            "path": "system.dvfs_handler", 
571            "type": "DVFSHandler"
572        }, 
573        "work_end_exit_count": 0, 
574        "type": "SparcSystem", 
575        "voltage_domain": {
576            "eventq_index": 0, 
577            "path": "system.voltage_domain", 
578            "type": "VoltageDomain", 
579            "name": "voltage_domain", 
580            "cxx_class": "VoltageDomain"
581        }, 
582        "cache_line_size": 64, 
583        "work_cpus_ckpt_count": 0, 
584        "work_begin_exit_count": 0, 
585        "num_work_ids": 16, 
586        "path": "system", 
587        "cpu_clk_domain": {
588            "name": "cpu_clk_domain", 
589            "init_perf_level": 0, 
590            "eventq_index": 0, 
591            "cxx_class": "SrcClockDomain", 
592            "path": "system.cpu_clk_domain", 
593            "type": "SrcClockDomain", 
594            "domain_id": -1
595        }, 
596        "mem_mode": "atomic", 
597        "name": "system", 
598        "init_param": 0, 
599        "system_port": {
600            "peer": "system.membus.slave[0]", 
601            "role": "MASTER"
602        }, 
603        "load_addr_mask": 1099511627775, 
604        "cpu": {
605            "simpoint_interval": 100000000, 
606            "do_statistics_insts": true, 
607            "numThreads": 1, 
608            "itb": {
609                "name": "itb", 
610                "eventq_index": 0, 
611                "cxx_class": "SparcISA::TLB", 
612                "path": "system.cpu.itb", 
613                "type": "SparcTLB", 
614                "size": 64
615            }, 
616            "function_trace": false, 
617            "do_checkpoint_insts": true, 
618            "cxx_class": "AtomicSimpleCPU", 
619            "max_loads_all_threads": 0, 
620            "simpoint_profile": false, 
621            "simulate_data_stalls": false, 
622            "function_trace_start": 0, 
623            "cpu_id": 0, 
624            "width": 1, 
625            "eventq_index": 0, 
626            "do_quiesce": true, 
627            "type": "AtomicSimpleCPU", 
628            "fastmem": false, 
629            "profile": 0.0, 
630            "icache_port": {
631                "peer": "system.membus.slave[1]", 
632                "role": "MASTER"
633            }, 
634            "interrupts": {
635                "eventq_index": 0, 
636                "path": "system.cpu.interrupts", 
637                "type": "SparcInterrupts", 
638                "name": "interrupts", 
639                "cxx_class": "SparcISA::Interrupts"
640            }, 
641            "socket_id": 0, 
642            "max_insts_all_threads": 0, 
643            "path": "system.cpu", 
644            "isa": [
645                {
646                    "eventq_index": 0, 
647                    "path": "system.cpu.isa", 
648                    "type": "SparcISA", 
649                    "name": "isa", 
650                    "cxx_class": "SparcISA::ISA"
651                }
652            ], 
653            "switched_out": false, 
654            "name": "cpu", 
655            "dtb": {
656                "name": "dtb", 
657                "eventq_index": 0, 
658                "cxx_class": "SparcISA::TLB", 
659                "path": "system.cpu.dtb", 
660                "type": "SparcTLB", 
661                "size": 64
662            }, 
663            "max_insts_any_thread": 0, 
664            "simulate_inst_stalls": false, 
665            "progress_interval": 0.0, 
666            "dcache_port": {
667                "peer": "system.membus.slave[2]", 
668                "role": "MASTER"
669            }, 
670            "max_loads_any_thread": 0, 
671            "tracer": {
672                "eventq_index": 0, 
673                "path": "system.cpu.tracer", 
674                "type": "ExeTracer", 
675                "name": "tracer", 
676                "cxx_class": "Trace::ExeTracer"
677            }
678        }, 
679        "intrctrl": {
680            "eventq_index": 0, 
681            "path": "system.intrctrl", 
682            "type": "IntrControl", 
683            "name": "intrctrl", 
684            "cxx_class": "IntrControl"
685        }, 
686        "disk0": {
687            "name": "disk0", 
688            "pio": {
689                "peer": "system.iobus.master[14]", 
690                "role": "SLAVE"
691            }, 
692            "image": {
693                "read_only": false, 
694                "name": "image", 
695                "child": {
696                    "read_only": true, 
697                    "name": "child", 
698                    "eventq_index": 0, 
699                    "cxx_class": "RawDiskImage", 
700                    "path": "system.disk0.image.child", 
701                    "type": "RawDiskImage"
702                }, 
703                "eventq_index": 0, 
704                "cxx_class": "CowDiskImage", 
705                "path": "system.disk0.image", 
706                "table_size": 65536, 
707                "type": "CowDiskImage"
708            }, 
709            "pio_latency": 1.0000000000000001e-07, 
710            "eventq_index": 0, 
711            "cxx_class": "MmDisk", 
712            "path": "system.disk0", 
713            "pio_addr": 134217728000, 
714            "type": "MmDisk"
715        }, 
716        "hypervisor_desc_addr": 133446500352, 
717        "reset_addr": 1099243192320, 
718        "work_item_id": -1, 
719        "work_begin_cpu_id_exit": -1
720    }, 
721    "time_sync_period": 0.1, 
722    "eventq_index": 0, 
723    "time_sync_spin_threshold": 9.999999999999999e-05, 
724    "cxx_class": "Root", 
725    "path": "root", 
726    "time_sync_enable": false, 
727    "type": "Root", 
728    "full_system": true
729}