config.json revision 10222 
1{
2    "name": null, 
3    "sim_quantum": 0, 
4    "system": {
5        "bridge": {
6            "slave": {
7                "peer": "system.membus.master[2]", 
8                "role": "SLAVE"
9            }, 
10            "name": "bridge", 
11            "req_size": 16, 
12            "delay": 5.0000000000000004e-08, 
13            "eventq_index": 0, 
14            "master": {
15                "peer": "system.iobus.slave[0]", 
16                "role": "MASTER"
17            }, 
18            "cxx_class": "Bridge", 
19            "path": "system.bridge", 
20            "resp_size": 16, 
21            "type": "Bridge"
22        }, 
23        "iobus": {
24            "slave": {
25                "peer": [
26                    "system.bridge.master"
27                ], 
28                "role": "SLAVE"
29            }, 
30            "name": "iobus", 
31            "header_cycles": 1, 
32            "width": 8, 
33            "eventq_index": 0, 
34            "master": {
35                "peer": [
36                    "system.t1000.fake_clk.pio", 
37                    "system.t1000.fake_membnks.pio", 
38                    "system.t1000.fake_l2_1.pio", 
39                    "system.t1000.fake_l2_2.pio", 
40                    "system.t1000.fake_l2_3.pio", 
41                    "system.t1000.fake_l2_4.pio", 
42                    "system.t1000.fake_l2esr_1.pio", 
43                    "system.t1000.fake_l2esr_2.pio", 
44                    "system.t1000.fake_l2esr_3.pio", 
45                    "system.t1000.fake_l2esr_4.pio", 
46                    "system.t1000.fake_ssi.pio", 
47                    "system.t1000.fake_jbi.pio", 
48                    "system.t1000.puart0.pio", 
49                    "system.t1000.hvuart.pio", 
50                    "system.disk0.pio"
51                ], 
52                "role": "MASTER"
53            }, 
54            "cxx_class": "NoncoherentBus", 
55            "path": "system.iobus", 
56            "type": "NoncoherentBus", 
57            "use_default_range": false
58        }, 
59        "rom": {
60            "latency": 3.0000000000000004e-08, 
61            "name": "rom", 
62            "eventq_index": 0, 
63            "latency_var": 0.0, 
64            "conf_table_reported": true, 
65            "cxx_class": "SimpleMemory", 
66            "path": "system.rom", 
67            "null": false, 
68            "type": "SimpleMemory", 
69            "port": {
70                "peer": "system.membus.master[3]", 
71                "role": "SLAVE"
72            }, 
73            "in_addr_map": true
74        }, 
75        "membus": {
76            "slave": {
77                "peer": [
78                    "system.system_port", 
79                    "system.cpu.icache_port", 
80                    "system.cpu.dcache_port"
81                ], 
82                "role": "SLAVE"
83            }, 
84            "name": "membus", 
85            "badaddr_responder": {
86                "ret_data8": 255, 
87                "name": "badaddr_responder", 
88                "pio": {
89                    "peer": "system.membus.default", 
90                    "role": "SLAVE"
91                }, 
92                "ret_bad_addr": true, 
93                "pio_latency": 1.0000000000000001e-07, 
94                "fake_mem": false, 
95                "pio_size": 8, 
96                "ret_data32": 4294967295, 
97                "eventq_index": 0, 
98                "update_data": false, 
99                "ret_data64": 18446744073709551615, 
100                "cxx_class": "IsaFake", 
101                "path": "system.membus.badaddr_responder", 
102                "pio_addr": 0, 
103                "type": "IsaFake", 
104                "ret_data16": 65535
105            }, 
106            "default": {
107                "peer": "system.membus.badaddr_responder.pio", 
108                "role": "MASTER"
109            }, 
110            "header_cycles": 1, 
111            "width": 8, 
112            "eventq_index": 0, 
113            "master": {
114                "peer": [
115                    "system.t1000.iob.pio", 
116                    "system.t1000.htod.pio", 
117                    "system.bridge.slave", 
118                    "system.rom.port", 
119                    "system.nvram.port", 
120                    "system.hypervisor_desc.port", 
121                    "system.partition_desc.port", 
122                    "system.physmem0.port", 
123                    "system.physmem1.port"
124                ], 
125                "role": "MASTER"
126            }, 
127            "cxx_class": "CoherentBus", 
128            "path": "system.membus", 
129            "type": "CoherentBus", 
130            "use_default_range": false
131        }, 
132        "t1000": {
133            "htod": {
134                "name": "htod", 
135                "pio": {
136                    "peer": "system.membus.master[1]", 
137                    "role": "SLAVE"
138                }, 
139                "time": "Thu Jan  1 00:00:00 2009", 
140                "pio_latency": 1.0000000000000001e-07, 
141                "eventq_index": 0, 
142                "cxx_class": "DumbTOD", 
143                "path": "system.t1000.htod", 
144                "pio_addr": 1099255906296, 
145                "type": "DumbTOD"
146            }, 
147            "puart0": {
148                "name": "puart0", 
149                "pio": {
150                    "peer": "system.iobus.master[12]", 
151                    "role": "SLAVE"
152                }, 
153                "pio_latency": 1.0000000000000001e-07, 
154                "eventq_index": 0, 
155                "cxx_class": "Uart8250", 
156                "path": "system.t1000.puart0", 
157                "pio_addr": 133412421632, 
158                "type": "Uart8250"
159            }, 
160            "fake_membnks": {
161                "ret_data8": 255, 
162                "name": "fake_membnks", 
163                "pio": {
164                    "peer": "system.iobus.master[1]", 
165                    "role": "SLAVE"
166                }, 
167                "ret_bad_addr": false, 
168                "pio_latency": 1.0000000000000001e-07, 
169                "fake_mem": false, 
170                "pio_size": 16384, 
171                "ret_data32": 4294967295, 
172                "eventq_index": 0, 
173                "update_data": false, 
174                "ret_data64": 0, 
175                "cxx_class": "IsaFake", 
176                "path": "system.t1000.fake_membnks", 
177                "pio_addr": 648540061696, 
178                "type": "IsaFake", 
179                "ret_data16": 65535
180            }, 
181            "cxx_class": "T1000", 
182            "fake_jbi": {
183                "ret_data8": 255, 
184                "name": "fake_jbi", 
185                "pio": {
186                    "peer": "system.iobus.master[11]", 
187                    "role": "SLAVE"
188                }, 
189                "ret_bad_addr": false, 
190                "pio_latency": 1.0000000000000001e-07, 
191                "fake_mem": false, 
192                "pio_size": 4294967296, 
193                "ret_data32": 4294967295, 
194                "eventq_index": 0, 
195                "update_data": false, 
196                "ret_data64": 18446744073709551615, 
197                "cxx_class": "IsaFake", 
198                "path": "system.t1000.fake_jbi", 
199                "pio_addr": 549755813888, 
200                "type": "IsaFake", 
201                "ret_data16": 65535
202            }, 
203            "fake_l2esr_2": {
204                "ret_data8": 255, 
205                "name": "fake_l2esr_2", 
206                "pio": {
207                    "peer": "system.iobus.master[7]", 
208                    "role": "SLAVE"
209                }, 
210                "ret_bad_addr": false, 
211                "pio_latency": 1.0000000000000001e-07, 
212                "fake_mem": false, 
213                "pio_size": 8, 
214                "ret_data32": 4294967295, 
215                "eventq_index": 0, 
216                "update_data": true, 
217                "ret_data64": 0, 
218                "cxx_class": "IsaFake", 
219                "path": "system.t1000.fake_l2esr_2", 
220                "pio_addr": 734439407680, 
221                "type": "IsaFake", 
222                "ret_data16": 65535
223            }, 
224            "eventq_index": 0, 
225            "hterm": {
226                "name": "hterm", 
227                "output": true, 
228                "number": 0, 
229                "eventq_index": 0, 
230                "cxx_class": "Terminal", 
231                "path": "system.t1000.hterm", 
232                "type": "Terminal", 
233                "port": 3456
234            }, 
235            "type": "T1000", 
236            "fake_l2_4": {
237                "ret_data8": 255, 
238                "name": "fake_l2_4", 
239                "pio": {
240                    "peer": "system.iobus.master[5]", 
241                    "role": "SLAVE"
242                }, 
243                "ret_bad_addr": false, 
244                "pio_latency": 1.0000000000000001e-07, 
245                "fake_mem": false, 
246                "pio_size": 8, 
247                "ret_data32": 4294967295, 
248                "eventq_index": 0, 
249                "update_data": true, 
250                "ret_data64": 1, 
251                "cxx_class": "IsaFake", 
252                "path": "system.t1000.fake_l2_4", 
253                "pio_addr": 725849473216, 
254                "type": "IsaFake", 
255                "ret_data16": 65535
256            }, 
257            "fake_l2_1": {
258                "ret_data8": 255, 
259                "name": "fake_l2_1", 
260                "pio": {
261                    "peer": "system.iobus.master[2]", 
262                    "role": "SLAVE"
263                }, 
264                "ret_bad_addr": false, 
265                "pio_latency": 1.0000000000000001e-07, 
266                "fake_mem": false, 
267                "pio_size": 8, 
268                "ret_data32": 4294967295, 
269                "eventq_index": 0, 
270                "update_data": true, 
271                "ret_data64": 1, 
272                "cxx_class": "IsaFake", 
273                "path": "system.t1000.fake_l2_1", 
274                "pio_addr": 725849473024, 
275                "type": "IsaFake", 
276                "ret_data16": 65535
277            }, 
278            "fake_l2_2": {
279                "ret_data8": 255, 
280                "name": "fake_l2_2", 
281                "pio": {
282                    "peer": "system.iobus.master[3]", 
283                    "role": "SLAVE"
284                }, 
285                "ret_bad_addr": false, 
286                "pio_latency": 1.0000000000000001e-07, 
287                "fake_mem": false, 
288                "pio_size": 8, 
289                "ret_data32": 4294967295, 
290                "eventq_index": 0, 
291                "update_data": true, 
292                "ret_data64": 1, 
293                "cxx_class": "IsaFake", 
294                "path": "system.t1000.fake_l2_2", 
295                "pio_addr": 725849473088, 
296                "type": "IsaFake", 
297                "ret_data16": 65535
298            }, 
299            "fake_l2_3": {
300                "ret_data8": 255, 
301                "name": "fake_l2_3", 
302                "pio": {
303                    "peer": "system.iobus.master[4]", 
304                    "role": "SLAVE"
305                }, 
306                "ret_bad_addr": false, 
307                "pio_latency": 1.0000000000000001e-07, 
308                "fake_mem": false, 
309                "pio_size": 8, 
310                "ret_data32": 4294967295, 
311                "eventq_index": 0, 
312                "update_data": true, 
313                "ret_data64": 1, 
314                "cxx_class": "IsaFake", 
315                "path": "system.t1000.fake_l2_3", 
316                "pio_addr": 725849473152, 
317                "type": "IsaFake", 
318                "ret_data16": 65535
319            }, 
320            "pterm": {
321                "name": "pterm", 
322                "output": true, 
323                "number": 0, 
324                "eventq_index": 0, 
325                "cxx_class": "Terminal", 
326                "path": "system.t1000.pterm", 
327                "type": "Terminal", 
328                "port": 3456
329            }, 
330            "path": "system.t1000", 
331            "iob": {
332                "name": "iob", 
333                "pio": {
334                    "peer": "system.membus.master[0]", 
335                    "role": "SLAVE"
336                }, 
337                "pio_latency": 1e-09, 
338                "eventq_index": 0, 
339                "cxx_class": "Iob", 
340                "path": "system.t1000.iob", 
341                "type": "Iob"
342            }, 
343            "hvuart": {
344                "name": "hvuart", 
345                "pio": {
346                    "peer": "system.iobus.master[13]", 
347                    "role": "SLAVE"
348                }, 
349                "pio_latency": 1.0000000000000001e-07, 
350                "eventq_index": 0, 
351                "cxx_class": "Uart8250", 
352                "path": "system.t1000.hvuart", 
353                "pio_addr": 1099255955456, 
354                "type": "Uart8250"
355            }, 
356            "name": "t1000", 
357            "fake_l2esr_3": {
358                "ret_data8": 255, 
359                "name": "fake_l2esr_3", 
360                "pio": {
361                    "peer": "system.iobus.master[8]", 
362                    "role": "SLAVE"
363                }, 
364                "ret_bad_addr": false, 
365                "pio_latency": 1.0000000000000001e-07, 
366                "fake_mem": false, 
367                "pio_size": 8, 
368                "ret_data32": 4294967295, 
369                "eventq_index": 0, 
370                "update_data": true, 
371                "ret_data64": 0, 
372                "cxx_class": "IsaFake", 
373                "path": "system.t1000.fake_l2esr_3", 
374                "pio_addr": 734439407744, 
375                "type": "IsaFake", 
376                "ret_data16": 65535
377            }, 
378            "fake_ssi": {
379                "ret_data8": 255, 
380                "name": "fake_ssi", 
381                "pio": {
382                    "peer": "system.iobus.master[10]", 
383                    "role": "SLAVE"
384                }, 
385                "ret_bad_addr": false, 
386                "pio_latency": 1.0000000000000001e-07, 
387                "fake_mem": false, 
388                "pio_size": 268435456, 
389                "ret_data32": 4294967295, 
390                "eventq_index": 0, 
391                "update_data": false, 
392                "ret_data64": 18446744073709551615, 
393                "cxx_class": "IsaFake", 
394                "path": "system.t1000.fake_ssi", 
395                "pio_addr": 1095216660480, 
396                "type": "IsaFake", 
397                "ret_data16": 65535
398            }, 
399            "fake_l2esr_1": {
400                "ret_data8": 255, 
401                "name": "fake_l2esr_1", 
402                "pio": {
403                    "peer": "system.iobus.master[6]", 
404                    "role": "SLAVE"
405                }, 
406                "ret_bad_addr": false, 
407                "pio_latency": 1.0000000000000001e-07, 
408                "fake_mem": false, 
409                "pio_size": 8, 
410                "ret_data32": 4294967295, 
411                "eventq_index": 0, 
412                "update_data": true, 
413                "ret_data64": 0, 
414                "cxx_class": "IsaFake", 
415                "path": "system.t1000.fake_l2esr_1", 
416                "pio_addr": 734439407616, 
417                "type": "IsaFake", 
418                "ret_data16": 65535
419            }, 
420            "fake_l2esr_4": {
421                "ret_data8": 255, 
422                "name": "fake_l2esr_4", 
423                "pio": {
424                    "peer": "system.iobus.master[9]", 
425                    "role": "SLAVE"
426                }, 
427                "ret_bad_addr": false, 
428                "pio_latency": 1.0000000000000001e-07, 
429                "fake_mem": false, 
430                "pio_size": 8, 
431                "ret_data32": 4294967295, 
432                "eventq_index": 0, 
433                "update_data": true, 
434                "ret_data64": 0, 
435                "cxx_class": "IsaFake", 
436                "path": "system.t1000.fake_l2esr_4", 
437                "pio_addr": 734439407808, 
438                "type": "IsaFake", 
439                "ret_data16": 65535
440            }, 
441            "fake_clk": {
442                "ret_data8": 255, 
443                "name": "fake_clk", 
444                "pio": {
445                    "peer": "system.iobus.master[0]", 
446                    "role": "SLAVE"
447                }, 
448                "ret_bad_addr": false, 
449                "pio_latency": 1.0000000000000001e-07, 
450                "fake_mem": false, 
451                "pio_size": 4294967296, 
452                "ret_data32": 4294967295, 
453                "eventq_index": 0, 
454                "update_data": false, 
455                "ret_data64": 18446744073709551615, 
456                "cxx_class": "IsaFake", 
457                "path": "system.t1000.fake_clk", 
458                "pio_addr": 644245094400, 
459                "type": "IsaFake", 
460                "ret_data16": 65535
461            }
462        }, 
463        "partition_desc_addr": 133445976064, 
464        "physmem": [
465            {
466                "latency": 3.0000000000000004e-08, 
467                "name": "physmem0", 
468                "eventq_index": 0, 
469                "latency_var": 0.0, 
470                "conf_table_reported": true, 
471                "cxx_class": "SimpleMemory", 
472                "path": "system.physmem0", 
473                "null": false, 
474                "type": "SimpleMemory", 
475                "port": {
476                    "peer": "system.membus.master[7]", 
477                    "role": "SLAVE"
478                }, 
479                "in_addr_map": true
480            }, 
481            {
482                "latency": 3.0000000000000004e-08, 
483                "name": "physmem1", 
484                "eventq_index": 0, 
485                "latency_var": 0.0, 
486                "conf_table_reported": true, 
487                "cxx_class": "SimpleMemory", 
488                "path": "system.physmem1", 
489                "null": false, 
490                "type": "SimpleMemory", 
491                "port": {
492                    "peer": "system.membus.master[8]", 
493                    "role": "SLAVE"
494                }, 
495                "in_addr_map": true
496            }
497        ], 
498        "hypervisor_addr": 1099243257856, 
499        "cxx_class": "SparcSystem", 
500        "load_offset": 0, 
501        "openboot_addr": 1099243716608, 
502        "work_end_ckpt_count": 0, 
503        "nvram_addr": 133429198848, 
504        "work_begin_ckpt_count": 0, 
505        "partition_desc": {
506            "latency": 3.0000000000000004e-08, 
507            "name": "partition_desc", 
508            "eventq_index": 0, 
509            "latency_var": 0.0, 
510            "conf_table_reported": true, 
511            "cxx_class": "SimpleMemory", 
512            "path": "system.partition_desc", 
513            "null": false, 
514            "type": "SimpleMemory", 
515            "port": {
516                "peer": "system.membus.master[6]", 
517                "role": "SLAVE"
518            }, 
519            "in_addr_map": true
520        }, 
521        "clk_domain": {
522            "name": "clk_domain", 
523            "clock": 1e-09, 
524            "eventq_index": 0, 
525            "cxx_class": "SrcClockDomain", 
526            "path": "system.clk_domain", 
527            "type": "SrcClockDomain"
528        }, 
529        "hypervisor_desc": {
530            "latency": 3.0000000000000004e-08, 
531            "name": "hypervisor_desc", 
532            "eventq_index": 0, 
533            "latency_var": 0.0, 
534            "conf_table_reported": true, 
535            "cxx_class": "SimpleMemory", 
536            "path": "system.hypervisor_desc", 
537            "null": false, 
538            "type": "SimpleMemory", 
539            "port": {
540                "peer": "system.membus.master[5]", 
541                "role": "SLAVE"
542            }, 
543            "in_addr_map": true
544        }, 
545        "nvram": {
546            "latency": 3.0000000000000004e-08, 
547            "name": "nvram", 
548            "eventq_index": 0, 
549            "latency_var": 0.0, 
550            "conf_table_reported": true, 
551            "cxx_class": "SimpleMemory", 
552            "path": "system.nvram", 
553            "null": false, 
554            "type": "SimpleMemory", 
555            "port": {
556                "peer": "system.membus.master[4]", 
557                "role": "SLAVE"
558            }, 
559            "in_addr_map": true
560        }, 
561        "eventq_index": 0, 
562        "work_end_exit_count": 0, 
563        "type": "SparcSystem", 
564        "voltage_domain": {
565            "eventq_index": 0, 
566            "path": "system.voltage_domain", 
567            "type": "VoltageDomain", 
568            "name": "voltage_domain", 
569            "cxx_class": "VoltageDomain"
570        }, 
571        "cache_line_size": 64, 
572        "work_cpus_ckpt_count": 0, 
573        "work_begin_exit_count": 0, 
574        "num_work_ids": 16, 
575        "path": "system", 
576        "cpu_clk_domain": {
577            "name": "cpu_clk_domain", 
578            "clock": 1e-09, 
579            "eventq_index": 0, 
580            "cxx_class": "SrcClockDomain", 
581            "path": "system.cpu_clk_domain", 
582            "type": "SrcClockDomain"
583        }, 
584        "mem_mode": "atomic", 
585        "name": "system", 
586        "init_param": 0, 
587        "system_port": {
588            "peer": "system.membus.slave[0]", 
589            "role": "MASTER"
590        }, 
591        "load_addr_mask": 1099511627775, 
592        "cpu": {
593            "simpoint_interval": 100000000, 
594            "do_statistics_insts": true, 
595            "numThreads": 1, 
596            "itb": {
597                "name": "itb", 
598                "eventq_index": 0, 
599                "cxx_class": "SparcISA::TLB", 
600                "path": "system.cpu.itb", 
601                "type": "SparcTLB", 
602                "size": 64
603            }, 
604            "function_trace": false, 
605            "do_checkpoint_insts": true, 
606            "cxx_class": "AtomicSimpleCPU", 
607            "max_loads_all_threads": 0, 
608            "simpoint_profile": false, 
609            "simulate_data_stalls": false, 
610            "function_trace_start": 0, 
611            "cpu_id": 0, 
612            "width": 1, 
613            "eventq_index": 0, 
614            "do_quiesce": true, 
615            "type": "AtomicSimpleCPU", 
616            "fastmem": false, 
617            "profile": 0.0, 
618            "icache_port": {
619                "peer": "system.membus.slave[1]", 
620                "role": "MASTER"
621            }, 
622            "interrupts": {
623                "eventq_index": 0, 
624                "path": "system.cpu.interrupts", 
625                "type": "SparcInterrupts", 
626                "name": "interrupts", 
627                "cxx_class": "SparcISA::Interrupts"
628            }, 
629            "socket_id": 0, 
630            "max_insts_all_threads": 0, 
631            "path": "system.cpu", 
632            "isa": [
633                {
634                    "eventq_index": 0, 
635                    "path": "system.cpu.isa", 
636                    "type": "SparcISA", 
637                    "name": "isa", 
638                    "cxx_class": "SparcISA::ISA"
639                }
640            ], 
641            "switched_out": false, 
642            "name": "cpu", 
643            "dtb": {
644                "name": "dtb", 
645                "eventq_index": 0, 
646                "cxx_class": "SparcISA::TLB", 
647                "path": "system.cpu.dtb", 
648                "type": "SparcTLB", 
649                "size": 64
650            }, 
651            "max_insts_any_thread": 0, 
652            "simulate_inst_stalls": false, 
653            "progress_interval": 0.0, 
654            "dcache_port": {
655                "peer": "system.membus.slave[2]", 
656                "role": "MASTER"
657            }, 
658            "max_loads_any_thread": 0, 
659            "tracer": {
660                "eventq_index": 0, 
661                "path": "system.cpu.tracer", 
662                "type": "ExeTracer", 
663                "name": "tracer", 
664                "cxx_class": "Trace::ExeTracer"
665            }
666        }, 
667        "intrctrl": {
668            "eventq_index": 0, 
669            "path": "system.intrctrl", 
670            "type": "IntrControl", 
671            "name": "intrctrl", 
672            "cxx_class": "IntrControl"
673        }, 
674        "disk0": {
675            "name": "disk0", 
676            "pio": {
677                "peer": "system.iobus.master[14]", 
678                "role": "SLAVE"
679            }, 
680            "image": {
681                "read_only": false, 
682                "name": "image", 
683                "child": {
684                    "read_only": true, 
685                    "name": "child", 
686                    "eventq_index": 0, 
687                    "cxx_class": "RawDiskImage", 
688                    "path": "system.disk0.image.child", 
689                    "type": "RawDiskImage"
690                }, 
691                "eventq_index": 0, 
692                "cxx_class": "CowDiskImage", 
693                "path": "system.disk0.image", 
694                "table_size": 65536, 
695                "type": "CowDiskImage"
696            }, 
697            "pio_latency": 1.0000000000000001e-07, 
698            "eventq_index": 0, 
699            "cxx_class": "MmDisk", 
700            "path": "system.disk0", 
701            "pio_addr": 134217728000, 
702            "type": "MmDisk"
703        }, 
704        "hypervisor_desc_addr": 133446500352, 
705        "reset_addr": 1099243192320, 
706        "work_item_id": -1, 
707        "work_begin_cpu_id_exit": -1
708    }, 
709    "time_sync_period": 0.1, 
710    "eventq_index": 0, 
711    "time_sync_spin_threshold": 9.999999999999999e-05, 
712    "cxx_class": "Root", 
713    "path": "root", 
714    "time_sync_enable": false, 
715    "type": "Root", 
716    "full_system": true
717}