config.json revision 11950
1{ 2 "name": null, 3 "sim_quantum": 0, 4 "system": { 5 "kernel": "", 6 "mmap_using_noreserve": false, 7 "kernel_addr_check": true, 8 "rom": { 9 "range": "1099243192320:1099251580927", 10 "latency": 60, 11 "name": "rom", 12 "p_state_clk_gate_min": 2, 13 "eventq_index": 0, 14 "p_state_clk_gate_bins": 20, 15 "default_p_state": "UNDEFINED", 16 "clk_domain": "system.clk_domain", 17 "power_model": null, 18 "latency_var": 0, 19 "bandwidth": "0.000000", 20 "conf_table_reported": true, 21 "cxx_class": "SimpleMemory", 22 "p_state_clk_gate_max": 2000000000, 23 "path": "system.rom", 24 "null": false, 25 "type": "SimpleMemory", 26 "port": { 27 "peer": "system.membus.master[3]", 28 "role": "SLAVE" 29 }, 30 "in_addr_map": true 31 }, 32 "bridge": { 33 "ranges": [ 34 "133412421632:133412421639", 35 "134217728000:554050781183", 36 "644245094400:652835028991", 37 "725849473024:1095485095935", 38 "1099255955456:1099255955463" 39 ], 40 "slave": { 41 "peer": "system.membus.master[2]", 42 "role": "SLAVE" 43 }, 44 "name": "bridge", 45 "p_state_clk_gate_min": 2, 46 "p_state_clk_gate_bins": 20, 47 "cxx_class": "Bridge", 48 "req_size": 16, 49 "clk_domain": "system.clk_domain", 50 "power_model": null, 51 "delay": 100, 52 "eventq_index": 0, 53 "master": { 54 "peer": "system.iobus.slave[0]", 55 "role": "MASTER" 56 }, 57 "default_p_state": "UNDEFINED", 58 "p_state_clk_gate_max": 2000000000, 59 "path": "system.bridge", 60 "resp_size": 16, 61 "type": "Bridge" 62 }, 63 "iobus": { 64 "forward_latency": 1, 65 "slave": { 66 "peer": [ 67 "system.bridge.master" 68 ], 69 "role": "SLAVE" 70 }, 71 "name": "iobus", 72 "p_state_clk_gate_min": 2, 73 "p_state_clk_gate_bins": 20, 74 "cxx_class": "NoncoherentXBar", 75 "clk_domain": "system.clk_domain", 76 "power_model": null, 77 "width": 16, 78 "eventq_index": 0, 79 "master": { 80 "peer": [ 81 "system.t1000.fake_clk.pio", 82 "system.t1000.fake_membnks.pio", 83 "system.t1000.fake_l2_1.pio", 84 "system.t1000.fake_l2_2.pio", 85 "system.t1000.fake_l2_3.pio", 86 "system.t1000.fake_l2_4.pio", 87 "system.t1000.fake_l2esr_1.pio", 88 "system.t1000.fake_l2esr_2.pio", 89 "system.t1000.fake_l2esr_3.pio", 90 "system.t1000.fake_l2esr_4.pio", 91 "system.t1000.fake_ssi.pio", 92 "system.t1000.fake_jbi.pio", 93 "system.t1000.puart0.pio", 94 "system.t1000.hvuart.pio", 95 "system.disk0.pio" 96 ], 97 "role": "MASTER" 98 }, 99 "response_latency": 2, 100 "default_p_state": "UNDEFINED", 101 "p_state_clk_gate_max": 2000000000, 102 "path": "system.iobus", 103 "type": "NoncoherentXBar", 104 "use_default_range": false, 105 "frontend_latency": 2 106 }, 107 "t1000": { 108 "htod": { 109 "name": "htod", 110 "p_state_clk_gate_min": 2, 111 "pio": { 112 "peer": "system.membus.master[1]", 113 "role": "SLAVE" 114 }, 115 "p_state_clk_gate_bins": 20, 116 "cxx_class": "DumbTOD", 117 "pio_latency": 200, 118 "clk_domain": "system.clk_domain", 119 "power_model": null, 120 "system": "system", 121 "eventq_index": 0, 122 "time": "Thu Jan 1 00:00:00 2009", 123 "default_p_state": "UNDEFINED", 124 "p_state_clk_gate_max": 2000000000, 125 "path": "system.t1000.htod", 126 "pio_addr": 1099255906296, 127 "type": "DumbTOD" 128 }, 129 "puart0": { 130 "name": "puart0", 131 "p_state_clk_gate_min": 2, 132 "pio": { 133 "peer": "system.iobus.master[12]", 134 "role": "SLAVE" 135 }, 136 "p_state_clk_gate_bins": 20, 137 "cxx_class": "Uart8250", 138 "pio_latency": 200, 139 "clk_domain": "system.clk_domain", 140 "power_model": null, 141 "system": "system", 142 "terminal": "system.t1000.pterm", 143 "platform": "system.t1000", 144 "eventq_index": 0, 145 "default_p_state": "UNDEFINED", 146 "p_state_clk_gate_max": 2000000000, 147 "path": "system.t1000.puart0", 148 "pio_addr": 133412421632, 149 "type": "Uart8250" 150 }, 151 "fake_membnks": { 152 "pio": { 153 "peer": "system.iobus.master[1]", 154 "role": "SLAVE" 155 }, 156 "ret_data64": 0, 157 "fake_mem": false, 158 "clk_domain": "system.clk_domain", 159 "cxx_class": "IsaFake", 160 "pio_addr": 648540061696, 161 "update_data": false, 162 "warn_access": "", 163 "pio_latency": 200, 164 "system": "system", 165 "eventq_index": 0, 166 "default_p_state": "UNDEFINED", 167 "p_state_clk_gate_max": 2000000000, 168 "type": "IsaFake", 169 "p_state_clk_gate_min": 2, 170 "power_model": null, 171 "ret_data32": 4294967295, 172 "path": "system.t1000.fake_membnks", 173 "ret_data16": 65535, 174 "ret_data8": 255, 175 "name": "fake_membnks", 176 "ret_bad_addr": false, 177 "pio_size": 16384, 178 "p_state_clk_gate_bins": 20 179 }, 180 "cxx_class": "T1000", 181 "fake_jbi": { 182 "pio": { 183 "peer": "system.iobus.master[11]", 184 "role": "SLAVE" 185 }, 186 "ret_data64": 18446744073709551615, 187 "fake_mem": false, 188 "clk_domain": "system.clk_domain", 189 "cxx_class": "IsaFake", 190 "pio_addr": 549755813888, 191 "update_data": false, 192 "warn_access": "", 193 "pio_latency": 200, 194 "system": "system", 195 "eventq_index": 0, 196 "default_p_state": "UNDEFINED", 197 "p_state_clk_gate_max": 2000000000, 198 "type": "IsaFake", 199 "p_state_clk_gate_min": 2, 200 "power_model": null, 201 "ret_data32": 4294967295, 202 "path": "system.t1000.fake_jbi", 203 "ret_data16": 65535, 204 "ret_data8": 255, 205 "name": "fake_jbi", 206 "ret_bad_addr": false, 207 "pio_size": 4294967296, 208 "p_state_clk_gate_bins": 20 209 }, 210 "intrctrl": "system.intrctrl", 211 "fake_l2esr_2": { 212 "pio": { 213 "peer": "system.iobus.master[7]", 214 "role": "SLAVE" 215 }, 216 "ret_data64": 0, 217 "fake_mem": false, 218 "clk_domain": "system.clk_domain", 219 "cxx_class": "IsaFake", 220 "pio_addr": 734439407680, 221 "update_data": true, 222 "warn_access": "", 223 "pio_latency": 200, 224 "system": "system", 225 "eventq_index": 0, 226 "default_p_state": "UNDEFINED", 227 "p_state_clk_gate_max": 2000000000, 228 "type": "IsaFake", 229 "p_state_clk_gate_min": 2, 230 "power_model": null, 231 "ret_data32": 4294967295, 232 "path": "system.t1000.fake_l2esr_2", 233 "ret_data16": 65535, 234 "ret_data8": 255, 235 "name": "fake_l2esr_2", 236 "ret_bad_addr": false, 237 "pio_size": 8, 238 "p_state_clk_gate_bins": 20 239 }, 240 "system": "system", 241 "eventq_index": 0, 242 "hterm": { 243 "name": "hterm", 244 "output": true, 245 "number": 0, 246 "intr_control": "system.intrctrl", 247 "eventq_index": 0, 248 "cxx_class": "Terminal", 249 "path": "system.t1000.hterm", 250 "type": "Terminal", 251 "port": 3456 252 }, 253 "type": "T1000", 254 "fake_l2_4": { 255 "pio": { 256 "peer": "system.iobus.master[5]", 257 "role": "SLAVE" 258 }, 259 "ret_data64": 1, 260 "fake_mem": false, 261 "clk_domain": "system.clk_domain", 262 "cxx_class": "IsaFake", 263 "pio_addr": 725849473216, 264 "update_data": true, 265 "warn_access": "", 266 "pio_latency": 200, 267 "system": "system", 268 "eventq_index": 0, 269 "default_p_state": "UNDEFINED", 270 "p_state_clk_gate_max": 2000000000, 271 "type": "IsaFake", 272 "p_state_clk_gate_min": 2, 273 "power_model": null, 274 "ret_data32": 4294967295, 275 "path": "system.t1000.fake_l2_4", 276 "ret_data16": 65535, 277 "ret_data8": 255, 278 "name": "fake_l2_4", 279 "ret_bad_addr": false, 280 "pio_size": 8, 281 "p_state_clk_gate_bins": 20 282 }, 283 "fake_l2_1": { 284 "pio": { 285 "peer": "system.iobus.master[2]", 286 "role": "SLAVE" 287 }, 288 "ret_data64": 1, 289 "fake_mem": false, 290 "clk_domain": "system.clk_domain", 291 "cxx_class": "IsaFake", 292 "pio_addr": 725849473024, 293 "update_data": true, 294 "warn_access": "", 295 "pio_latency": 200, 296 "system": "system", 297 "eventq_index": 0, 298 "default_p_state": "UNDEFINED", 299 "p_state_clk_gate_max": 2000000000, 300 "type": "IsaFake", 301 "p_state_clk_gate_min": 2, 302 "power_model": null, 303 "ret_data32": 4294967295, 304 "path": "system.t1000.fake_l2_1", 305 "ret_data16": 65535, 306 "ret_data8": 255, 307 "name": "fake_l2_1", 308 "ret_bad_addr": false, 309 "pio_size": 8, 310 "p_state_clk_gate_bins": 20 311 }, 312 "fake_l2_2": { 313 "pio": { 314 "peer": "system.iobus.master[3]", 315 "role": "SLAVE" 316 }, 317 "ret_data64": 1, 318 "fake_mem": false, 319 "clk_domain": "system.clk_domain", 320 "cxx_class": "IsaFake", 321 "pio_addr": 725849473088, 322 "update_data": true, 323 "warn_access": "", 324 "pio_latency": 200, 325 "system": "system", 326 "eventq_index": 0, 327 "default_p_state": "UNDEFINED", 328 "p_state_clk_gate_max": 2000000000, 329 "type": "IsaFake", 330 "p_state_clk_gate_min": 2, 331 "power_model": null, 332 "ret_data32": 4294967295, 333 "path": "system.t1000.fake_l2_2", 334 "ret_data16": 65535, 335 "ret_data8": 255, 336 "name": "fake_l2_2", 337 "ret_bad_addr": false, 338 "pio_size": 8, 339 "p_state_clk_gate_bins": 20 340 }, 341 "fake_l2_3": { 342 "pio": { 343 "peer": "system.iobus.master[4]", 344 "role": "SLAVE" 345 }, 346 "ret_data64": 1, 347 "fake_mem": false, 348 "clk_domain": "system.clk_domain", 349 "cxx_class": "IsaFake", 350 "pio_addr": 725849473152, 351 "update_data": true, 352 "warn_access": "", 353 "pio_latency": 200, 354 "system": "system", 355 "eventq_index": 0, 356 "default_p_state": "UNDEFINED", 357 "p_state_clk_gate_max": 2000000000, 358 "type": "IsaFake", 359 "p_state_clk_gate_min": 2, 360 "power_model": null, 361 "ret_data32": 4294967295, 362 "path": "system.t1000.fake_l2_3", 363 "ret_data16": 65535, 364 "ret_data8": 255, 365 "name": "fake_l2_3", 366 "ret_bad_addr": false, 367 "pio_size": 8, 368 "p_state_clk_gate_bins": 20 369 }, 370 "pterm": { 371 "name": "pterm", 372 "output": true, 373 "number": 0, 374 "intr_control": "system.intrctrl", 375 "eventq_index": 0, 376 "cxx_class": "Terminal", 377 "path": "system.t1000.pterm", 378 "type": "Terminal", 379 "port": 3456 380 }, 381 "path": "system.t1000", 382 "iob": { 383 "name": "iob", 384 "p_state_clk_gate_min": 2, 385 "pio": { 386 "peer": "system.membus.master[0]", 387 "role": "SLAVE" 388 }, 389 "p_state_clk_gate_bins": 20, 390 "cxx_class": "Iob", 391 "pio_latency": 2, 392 "clk_domain": "system.clk_domain", 393 "power_model": null, 394 "system": "system", 395 "platform": "system.t1000", 396 "eventq_index": 0, 397 "default_p_state": "UNDEFINED", 398 "p_state_clk_gate_max": 2000000000, 399 "path": "system.t1000.iob", 400 "type": "Iob" 401 }, 402 "hvuart": { 403 "name": "hvuart", 404 "p_state_clk_gate_min": 2, 405 "pio": { 406 "peer": "system.iobus.master[13]", 407 "role": "SLAVE" 408 }, 409 "p_state_clk_gate_bins": 20, 410 "cxx_class": "Uart8250", 411 "pio_latency": 200, 412 "clk_domain": "system.clk_domain", 413 "power_model": null, 414 "system": "system", 415 "terminal": "system.t1000.hterm", 416 "platform": "system.t1000", 417 "eventq_index": 0, 418 "default_p_state": "UNDEFINED", 419 "p_state_clk_gate_max": 2000000000, 420 "path": "system.t1000.hvuart", 421 "pio_addr": 1099255955456, 422 "type": "Uart8250" 423 }, 424 "name": "t1000", 425 "fake_l2esr_3": { 426 "pio": { 427 "peer": "system.iobus.master[8]", 428 "role": "SLAVE" 429 }, 430 "ret_data64": 0, 431 "fake_mem": false, 432 "clk_domain": "system.clk_domain", 433 "cxx_class": "IsaFake", 434 "pio_addr": 734439407744, 435 "update_data": true, 436 "warn_access": "", 437 "pio_latency": 200, 438 "system": "system", 439 "eventq_index": 0, 440 "default_p_state": "UNDEFINED", 441 "p_state_clk_gate_max": 2000000000, 442 "type": "IsaFake", 443 "p_state_clk_gate_min": 2, 444 "power_model": null, 445 "ret_data32": 4294967295, 446 "path": "system.t1000.fake_l2esr_3", 447 "ret_data16": 65535, 448 "ret_data8": 255, 449 "name": "fake_l2esr_3", 450 "ret_bad_addr": false, 451 "pio_size": 8, 452 "p_state_clk_gate_bins": 20 453 }, 454 "fake_ssi": { 455 "pio": { 456 "peer": "system.iobus.master[10]", 457 "role": "SLAVE" 458 }, 459 "ret_data64": 18446744073709551615, 460 "fake_mem": false, 461 "clk_domain": "system.clk_domain", 462 "cxx_class": "IsaFake", 463 "pio_addr": 1095216660480, 464 "update_data": false, 465 "warn_access": "", 466 "pio_latency": 200, 467 "system": "system", 468 "eventq_index": 0, 469 "default_p_state": "UNDEFINED", 470 "p_state_clk_gate_max": 2000000000, 471 "type": "IsaFake", 472 "p_state_clk_gate_min": 2, 473 "power_model": null, 474 "ret_data32": 4294967295, 475 "path": "system.t1000.fake_ssi", 476 "ret_data16": 65535, 477 "ret_data8": 255, 478 "name": "fake_ssi", 479 "ret_bad_addr": false, 480 "pio_size": 268435456, 481 "p_state_clk_gate_bins": 20 482 }, 483 "fake_l2esr_1": { 484 "pio": { 485 "peer": "system.iobus.master[6]", 486 "role": "SLAVE" 487 }, 488 "ret_data64": 0, 489 "fake_mem": false, 490 "clk_domain": "system.clk_domain", 491 "cxx_class": "IsaFake", 492 "pio_addr": 734439407616, 493 "update_data": true, 494 "warn_access": "", 495 "pio_latency": 200, 496 "system": "system", 497 "eventq_index": 0, 498 "default_p_state": "UNDEFINED", 499 "p_state_clk_gate_max": 2000000000, 500 "type": "IsaFake", 501 "p_state_clk_gate_min": 2, 502 "power_model": null, 503 "ret_data32": 4294967295, 504 "path": "system.t1000.fake_l2esr_1", 505 "ret_data16": 65535, 506 "ret_data8": 255, 507 "name": "fake_l2esr_1", 508 "ret_bad_addr": false, 509 "pio_size": 8, 510 "p_state_clk_gate_bins": 20 511 }, 512 "fake_l2esr_4": { 513 "pio": { 514 "peer": "system.iobus.master[9]", 515 "role": "SLAVE" 516 }, 517 "ret_data64": 0, 518 "fake_mem": false, 519 "clk_domain": "system.clk_domain", 520 "cxx_class": "IsaFake", 521 "pio_addr": 734439407808, 522 "update_data": true, 523 "warn_access": "", 524 "pio_latency": 200, 525 "system": "system", 526 "eventq_index": 0, 527 "default_p_state": "UNDEFINED", 528 "p_state_clk_gate_max": 2000000000, 529 "type": "IsaFake", 530 "p_state_clk_gate_min": 2, 531 "power_model": null, 532 "ret_data32": 4294967295, 533 "path": "system.t1000.fake_l2esr_4", 534 "ret_data16": 65535, 535 "ret_data8": 255, 536 "name": "fake_l2esr_4", 537 "ret_bad_addr": false, 538 "pio_size": 8, 539 "p_state_clk_gate_bins": 20 540 }, 541 "fake_clk": { 542 "pio": { 543 "peer": "system.iobus.master[0]", 544 "role": "SLAVE" 545 }, 546 "ret_data64": 18446744073709551615, 547 "fake_mem": false, 548 "clk_domain": "system.clk_domain", 549 "cxx_class": "IsaFake", 550 "pio_addr": 644245094400, 551 "update_data": false, 552 "warn_access": "", 553 "pio_latency": 200, 554 "system": "system", 555 "eventq_index": 0, 556 "default_p_state": "UNDEFINED", 557 "p_state_clk_gate_max": 2000000000, 558 "type": "IsaFake", 559 "p_state_clk_gate_min": 2, 560 "power_model": null, 561 "ret_data32": 4294967295, 562 "path": "system.t1000.fake_clk", 563 "ret_data16": 65535, 564 "ret_data8": 255, 565 "name": "fake_clk", 566 "ret_bad_addr": false, 567 "pio_size": 4294967296, 568 "p_state_clk_gate_bins": 20 569 } 570 }, 571 "partition_desc_addr": 133445976064, 572 "symbolfile": "", 573 "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh", 574 "thermal_model": null, 575 "hypervisor_addr": 1099243257856, 576 "mem_ranges": [ 577 "1048576:68157439", 578 "2147483648:2415919103" 579 ], 580 "cxx_class": "SparcSystem", 581 "work_begin_cpu_id_exit": -1, 582 "load_offset": 0, 583 "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin", 584 "work_end_ckpt_count": 0, 585 "work_begin_exit_count": 0, 586 "openboot_addr": 1099243716608, 587 "p_state_clk_gate_min": 2, 588 "nvram_addr": 133429198848, 589 "memories": [ 590 "system.hypervisor_desc", 591 "system.nvram", 592 "system.partition_desc", 593 "system.physmem0", 594 "system.physmem1", 595 "system.rom" 596 ], 597 "work_begin_ckpt_count": 0, 598 "partition_desc": { 599 "range": "133445976064:133445984255", 600 "latency": 60, 601 "name": "partition_desc", 602 "p_state_clk_gate_min": 2, 603 "eventq_index": 0, 604 "p_state_clk_gate_bins": 20, 605 "default_p_state": "UNDEFINED", 606 "clk_domain": "system.clk_domain", 607 "power_model": null, 608 "latency_var": 0, 609 "bandwidth": "0.000000", 610 "conf_table_reported": true, 611 "cxx_class": "SimpleMemory", 612 "p_state_clk_gate_max": 2000000000, 613 "path": "system.partition_desc", 614 "null": false, 615 "type": "SimpleMemory", 616 "port": { 617 "peer": "system.membus.master[6]", 618 "role": "SLAVE" 619 }, 620 "in_addr_map": true 621 }, 622 "clk_domain": { 623 "name": "clk_domain", 624 "clock": [ 625 2 626 ], 627 "init_perf_level": 0, 628 "voltage_domain": "system.voltage_domain", 629 "eventq_index": 0, 630 "cxx_class": "SrcClockDomain", 631 "path": "system.clk_domain", 632 "type": "SrcClockDomain", 633 "domain_id": -1 634 }, 635 "hypervisor_desc": { 636 "range": "133446500352:133446508543", 637 "latency": 60, 638 "name": "hypervisor_desc", 639 "p_state_clk_gate_min": 2, 640 "eventq_index": 0, 641 "p_state_clk_gate_bins": 20, 642 "default_p_state": "UNDEFINED", 643 "clk_domain": "system.clk_domain", 644 "power_model": null, 645 "latency_var": 0, 646 "bandwidth": "0.000000", 647 "conf_table_reported": true, 648 "cxx_class": "SimpleMemory", 649 "p_state_clk_gate_max": 2000000000, 650 "path": "system.hypervisor_desc", 651 "null": false, 652 "type": "SimpleMemory", 653 "port": { 654 "peer": "system.membus.master[5]", 655 "role": "SLAVE" 656 }, 657 "in_addr_map": true 658 }, 659 "membus": { 660 "point_of_coherency": true, 661 "system": "system", 662 "response_latency": 2, 663 "cxx_class": "CoherentXBar", 664 "badaddr_responder": { 665 "pio": { 666 "peer": "system.membus.default", 667 "role": "SLAVE" 668 }, 669 "ret_data64": 18446744073709551615, 670 "fake_mem": false, 671 "clk_domain": "system.clk_domain", 672 "cxx_class": "IsaFake", 673 "pio_addr": 0, 674 "update_data": false, 675 "warn_access": "", 676 "pio_latency": 200, 677 "system": "system", 678 "eventq_index": 0, 679 "default_p_state": "UNDEFINED", 680 "p_state_clk_gate_max": 2000000000, 681 "type": "IsaFake", 682 "p_state_clk_gate_min": 2, 683 "power_model": null, 684 "ret_data32": 4294967295, 685 "path": "system.membus.badaddr_responder", 686 "ret_data16": 65535, 687 "ret_data8": 255, 688 "name": "badaddr_responder", 689 "ret_bad_addr": true, 690 "pio_size": 8, 691 "p_state_clk_gate_bins": 20 692 }, 693 "forward_latency": 4, 694 "clk_domain": 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