stats.txt revision 11201
18968SN/A
28968SN/A---------- Begin Simulation Statistics ----------
311201Sandreas.hansson@arm.comsim_seconds                                  5.221365                       # Number of seconds simulated
411201Sandreas.hansson@arm.comsim_ticks                                5221365015000                       # Number of ticks simulated
511201Sandreas.hansson@arm.comfinal_tick                               5221365015000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68968SN/Asim_freq                                 1000000000000                       # Frequency of simulated ticks
711201Sandreas.hansson@arm.comhost_inst_rate                                 248453                       # Simulator instruction rate (inst/s)
811201Sandreas.hansson@arm.comhost_op_rate                                   482434                       # Simulator op (including micro ops) rate (op/s)
911201Sandreas.hansson@arm.comhost_tick_rate                             8587928983                       # Simulator tick rate (ticks/s)
1011201Sandreas.hansson@arm.comhost_mem_usage                                 826144                       # Number of bytes of host memory used
1111201Sandreas.hansson@arm.comhost_seconds                                   607.99                       # Real time elapsed on the host
1211201Sandreas.hansson@arm.comsim_insts                                   151056354                       # Number of instructions simulated
1311201Sandreas.hansson@arm.comsim_ops                                     293314765                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                          1000                       # Clock period in ticks
1611201Sandreas.hansson@arm.comsystem.mem_ctrls.bytes_read::ruby.dir_cntrl0     11629312                       # Number of bytes read from this memory
1711201Sandreas.hansson@arm.comsystem.mem_ctrls.bytes_read::total           11629312                       # Number of bytes read from this memory
1811201Sandreas.hansson@arm.comsystem.mem_ctrls.bytes_written::ruby.dir_cntrl0      9426176                       # Number of bytes written to this memory
1911201Sandreas.hansson@arm.comsystem.mem_ctrls.bytes_written::total         9426176                       # Number of bytes written to this memory
2011201Sandreas.hansson@arm.comsystem.mem_ctrls.num_reads::ruby.dir_cntrl0       181708                       # Number of read requests responded to by this memory
2111201Sandreas.hansson@arm.comsystem.mem_ctrls.num_reads::total              181708                       # Number of read requests responded to by this memory
2211201Sandreas.hansson@arm.comsystem.mem_ctrls.num_writes::ruby.dir_cntrl0       147284                       # Number of write requests responded to by this memory
2311201Sandreas.hansson@arm.comsystem.mem_ctrls.num_writes::total             147284                       # Number of write requests responded to by this memory
2411201Sandreas.hansson@arm.comsystem.mem_ctrls.bw_read::ruby.dir_cntrl0      2227255                       # Total read bandwidth from this memory (bytes/s)
2511201Sandreas.hansson@arm.comsystem.mem_ctrls.bw_read::total               2227255                       # Total read bandwidth from this memory (bytes/s)
2611201Sandreas.hansson@arm.comsystem.mem_ctrls.bw_write::ruby.dir_cntrl0      1805309                       # Write bandwidth from this memory (bytes/s)
2711201Sandreas.hansson@arm.comsystem.mem_ctrls.bw_write::total              1805309                       # Write bandwidth from this memory (bytes/s)
2811201Sandreas.hansson@arm.comsystem.mem_ctrls.bw_total::ruby.dir_cntrl0      4032564                       # Total bandwidth to/from this memory (bytes/s)
2911201Sandreas.hansson@arm.comsystem.mem_ctrls.bw_total::total              4032564                       # Total bandwidth to/from this memory (bytes/s)
3011201Sandreas.hansson@arm.comsystem.mem_ctrls.readReqs                      181708                       # Number of read requests accepted
3111201Sandreas.hansson@arm.comsystem.mem_ctrls.writeReqs                     147284                       # Number of write requests accepted
3211201Sandreas.hansson@arm.comsystem.mem_ctrls.readBursts                    181708                       # Number of DRAM read bursts, including those serviced by the write queue
3311201Sandreas.hansson@arm.comsystem.mem_ctrls.writeBursts                   147284                       # Number of DRAM write bursts, including those merged in the write queue
3411201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesReadDRAM               11602944                       # Total number of bytes read from DRAM
3511201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesReadWrQ                   26368                       # Total number of bytes read from write queue
3611201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesWritten                 9422144                       # Total number of bytes written to DRAM
3711201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesReadSys                11629312                       # Total read bytes from the system interface side
3811201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesWrittenSys              9426176                       # Total written bytes from the system interface side
3911201Sandreas.hansson@arm.comsystem.mem_ctrls.servicedByWrQ                    412                       # Number of DRAM read bursts serviced by the write queue
4011201Sandreas.hansson@arm.comsystem.mem_ctrls.mergedWrBursts                    33                       # Number of DRAM write bursts merged with an existing one
4110526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
4211201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::0             11315                       # Per bank write bursts
4311201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::1             10810                       # Per bank write bursts
4411201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::2             10914                       # Per bank write bursts
4511201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::3             11597                       # Per bank write bursts
4611201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::4             11232                       # Per bank write bursts
4711201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::5             10763                       # Per bank write bursts
4811201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::6             11930                       # Per bank write bursts
4911201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::7             10887                       # Per bank write bursts
5011201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::8             12498                       # Per bank write bursts
5111201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::9             12229                       # Per bank write bursts
5211201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::10            11811                       # Per bank write bursts
5311201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::11            12012                       # Per bank write bursts
5411201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::12            11054                       # Per bank write bursts
5511201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::13            10768                       # Per bank write bursts
5611201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::14            10809                       # Per bank write bursts
5711201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::15            10667                       # Per bank write bursts
5811201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::0             10064                       # Per bank write bursts
5911201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::1              9276                       # Per bank write bursts
6011201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::2              8835                       # Per bank write bursts
6111201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::3              9280                       # Per bank write bursts
6211201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::4              9017                       # Per bank write bursts
6311201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::5              9023                       # Per bank write bursts
6411201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::6              9283                       # Per bank write bursts
6511201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::7              8385                       # Per bank write bursts
6611201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::8              9360                       # Per bank write bursts
6711201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::9              9330                       # Per bank write bursts
6811201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::10             9168                       # Per bank write bursts
6911201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::11             9776                       # Per bank write bursts
7011201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::12             9055                       # Per bank write bursts
7111201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::13             9211                       # Per bank write bursts
7211201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::14             9312                       # Per bank write bursts
7311201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::15             8846                       # Per bank write bursts
7410526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
7510526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
7611201Sandreas.hansson@arm.comsystem.mem_ctrls.totGap                  5221364905500                       # Total gap between requests
7710526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
8311201Sandreas.hansson@arm.comsystem.mem_ctrls.readPktSize::6                181708                       # Read request sizes (log2)
8410526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
9011201Sandreas.hansson@arm.comsystem.mem_ctrls.writePktSize::6               147284                       # Write request sizes (log2)
9111201Sandreas.hansson@arm.comsystem.mem_ctrls.rdQLenPdf::0                  181190                       # What read queue length does an incoming req see
9211201Sandreas.hansson@arm.comsystem.mem_ctrls.rdQLenPdf::1                     106                       # What read queue length does an incoming req see
9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
12310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
13811201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::15                   2024                       # What write queue length does an incoming req see
13911201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::16                   2744                       # What write queue length does an incoming req see
14011201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::17                   8771                       # What write queue length does an incoming req see
14111201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::18                   9315                       # What write queue length does an incoming req see
14211201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::19                   8851                       # What write queue length does an incoming req see
14311201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::20                   9482                       # What write queue length does an incoming req see
14411201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::21                   9472                       # What write queue length does an incoming req see
14511201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::22                   8660                       # What write queue length does an incoming req see
14611201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::23                   9268                       # What write queue length does an incoming req see
14711201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::24                   9345                       # What write queue length does an incoming req see
14811201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::25                   8736                       # What write queue length does an incoming req see
14911201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::26                   8808                       # What write queue length does an incoming req see
15011201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::27                   8668                       # What write queue length does an incoming req see
15111201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::28                   8747                       # What write queue length does an incoming req see
15211201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::29                   8343                       # What write queue length does an incoming req see
15311201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::30                   8394                       # What write queue length does an incoming req see
15411201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::31                   8477                       # What write queue length does an incoming req see
15511201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::32                   8268                       # What write queue length does an incoming req see
15611201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::33                    147                       # What write queue length does an incoming req see
15711201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::34                    120                       # What write queue length does an incoming req see
15811201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::35                    118                       # What write queue length does an incoming req see
15911201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::36                    107                       # What write queue length does an incoming req see
16011201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::37                     92                       # What write queue length does an incoming req see
16111201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::38                     78                       # What write queue length does an incoming req see
16211201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::39                     67                       # What write queue length does an incoming req see
16311201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::40                     52                       # What write queue length does an incoming req see
16411201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::41                     36                       # What write queue length does an incoming req see
16511201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::42                     21                       # What write queue length does an incoming req see
16611201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::43                     12                       # What write queue length does an incoming req see
16711201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::44                      9                       # What write queue length does an incoming req see
16811201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::45                      2                       # What write queue length does an incoming req see
16911201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::46                      1                       # What write queue length does an incoming req see
17011201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::47                      1                       # What write queue length does an incoming req see
17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
18711201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::samples        59927                       # Bytes accessed per row activation
18811201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::mean    350.843927                       # Bytes accessed per row activation
18911201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::gmean   206.536657                       # Bytes accessed per row activation
19011201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::stdev   350.281857                       # Bytes accessed per row activation
19111201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::0-127        19886     33.18%     33.18% # Bytes accessed per row activation
19211201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::128-255        13813     23.05%     56.23% # Bytes accessed per row activation
19311201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::256-383         6078     10.14%     66.38% # Bytes accessed per row activation
19411201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::384-511         3680      6.14%     72.52% # Bytes accessed per row activation
19511201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::512-639         2560      4.27%     76.79% # Bytes accessed per row activation
19611201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::640-767         2039      3.40%     80.19% # Bytes accessed per row activation
19711201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::768-895         1649      2.75%     82.94% # Bytes accessed per row activation
19811201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::896-1023         1406      2.35%     85.29% # Bytes accessed per row activation
19911201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::1024-1151         8816     14.71%    100.00% # Bytes accessed per row activation
20011201Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::total        59927                       # Bytes accessed per row activation
20111201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::samples         8212                       # Reads before turning the bus around for writes
20211201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::mean      22.072577                       # Reads before turning the bus around for writes
20311201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::stdev    311.491456                       # Reads before turning the bus around for writes
20411201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::0-1023         8206     99.93%     99.93% # Reads before turning the bus around for writes
20510892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::1024-2047            3      0.04%     99.96% # Reads before turning the bus around for writes
20611026Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
20710526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::10240-11263            1      0.01%     99.99% # Reads before turning the bus around for writes
20810526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
20911201Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::total          8212                       # Reads before turning the bus around for writes
21011201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::samples         8212                       # Writes before turning the bus around for reads
21111201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::mean      17.927545                       # Writes before turning the bus around for reads
21211201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::gmean     17.596423                       # Writes before turning the bus around for reads
21311201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::stdev      3.937922                       # Writes before turning the bus around for reads
21411201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::16             6145     74.83%     74.83% # Writes before turning the bus around for reads
21511201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::17               16      0.19%     75.02% # Writes before turning the bus around for reads
21611201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::18              149      1.81%     76.84% # Writes before turning the bus around for reads
21711201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::19               20      0.24%     77.08% # Writes before turning the bus around for reads
21811201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::20               39      0.47%     77.56% # Writes before turning the bus around for reads
21911201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::21              481      5.86%     83.41% # Writes before turning the bus around for reads
22011201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::22              195      2.37%     85.79% # Writes before turning the bus around for reads
22111201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::23               59      0.72%     86.51% # Writes before turning the bus around for reads
22211201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::24              612      7.45%     93.96% # Writes before turning the bus around for reads
22311201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::25              113      1.38%     95.34% # Writes before turning the bus around for reads
22411201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::26                6      0.07%     95.41% # Writes before turning the bus around for reads
22511201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::27               13      0.16%     95.57% # Writes before turning the bus around for reads
22611201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::28              284      3.46%     99.03% # Writes before turning the bus around for reads
22711201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::29                4      0.05%     99.07% # Writes before turning the bus around for reads
22811201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::30                6      0.07%     99.15% # Writes before turning the bus around for reads
22911201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::31                4      0.05%     99.20% # Writes before turning the bus around for reads
23011201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::32                7      0.09%     99.28% # Writes before turning the bus around for reads
23111201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::33                5      0.06%     99.34% # Writes before turning the bus around for reads
23211201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::34                1      0.01%     99.35% # Writes before turning the bus around for reads
23311201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::35                1      0.01%     99.37% # Writes before turning the bus around for reads
23411201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::36                6      0.07%     99.44% # Writes before turning the bus around for reads
23511201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::37                4      0.05%     99.49% # Writes before turning the bus around for reads
23611201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::38                2      0.02%     99.51% # Writes before turning the bus around for reads
23711201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::39                6      0.07%     99.59% # Writes before turning the bus around for reads
23811201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::40                1      0.01%     99.60% # Writes before turning the bus around for reads
23911201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::41                8      0.10%     99.70% # Writes before turning the bus around for reads
24011201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::42                3      0.04%     99.73% # Writes before turning the bus around for reads
24111201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::43                2      0.02%     99.76% # Writes before turning the bus around for reads
24211201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::44                6      0.07%     99.83% # Writes before turning the bus around for reads
24311201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::45                4      0.05%     99.88% # Writes before turning the bus around for reads
24411201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::46                1      0.01%     99.89% # Writes before turning the bus around for reads
24511201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::47                1      0.01%     99.90% # Writes before turning the bus around for reads
24611201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::48                3      0.04%     99.94% # Writes before turning the bus around for reads
24711201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::50                1      0.01%     99.95% # Writes before turning the bus around for reads
24811201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::51                4      0.05%    100.00% # Writes before turning the bus around for reads
24911201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::total          8212                       # Writes before turning the bus around for reads
25011201Sandreas.hansson@arm.comsystem.mem_ctrls.totQLat                   1926712996                       # Total ticks spent queuing
25111201Sandreas.hansson@arm.comsystem.mem_ctrls.totMemAccLat              5326012996                       # Total ticks spent from burst creation until serviced by the DRAM
25211201Sandreas.hansson@arm.comsystem.mem_ctrls.totBusLat                  906480000                       # Total ticks spent in databus transfers
25311201Sandreas.hansson@arm.comsystem.mem_ctrls.avgQLat                     10627.44                       # Average queueing delay per DRAM burst
25410526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
25511201Sandreas.hansson@arm.comsystem.mem_ctrls.avgMemAccLat                29377.44                       # Average memory access latency per DRAM burst
25611026Snilay@cs.wisc.edusystem.mem_ctrls.avgRdBW                         2.22                       # Average DRAM read bandwidth in MiByte/s
25711201Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrBW                         1.80                       # Average achieved write bandwidth in MiByte/s
25811201Sandreas.hansson@arm.comsystem.mem_ctrls.avgRdBWSys                      2.23                       # Average system read bandwidth in MiByte/s
25911201Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrBWSys                      1.81                       # Average system write bandwidth in MiByte/s
26010526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
26110526Snilay@cs.wisc.edusystem.mem_ctrls.busUtil                         0.03                       # Data bus utilization in percentage
26210526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilRead                     0.02                       # Data bus utilization in percentage for reads
26310526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilWrite                    0.01                       # Data bus utilization in percentage for writes
26410526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
26511201Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrQLen                      25.95                       # Average write queue length when enqueuing
26611201Sandreas.hansson@arm.comsystem.mem_ctrls.readRowHits                   146991                       # Number of row buffer hits during reads
26711201Sandreas.hansson@arm.comsystem.mem_ctrls.writeRowHits                  121598                       # Number of row buffer hits during writes
26811201Sandreas.hansson@arm.comsystem.mem_ctrls.readRowHitRate                 81.08                       # Row buffer hit rate for reads
26911201Sandreas.hansson@arm.comsystem.mem_ctrls.writeRowHitRate                82.58                       # Row buffer hit rate for writes
27011201Sandreas.hansson@arm.comsystem.mem_ctrls.avgGap                   15870795.96                       # Average gap between requests
27111201Sandreas.hansson@arm.comsystem.mem_ctrls.pageHitRate                    81.75                       # Row buffer hit rate, read and write combined
27211201Sandreas.hansson@arm.comsystem.mem_ctrls_0.actEnergy                221946480                       # Energy for activate commands per rank (pJ)
27311201Sandreas.hansson@arm.comsystem.mem_ctrls_0.preEnergy                121101750                       # Energy for precharge commands per rank (pJ)
27411201Sandreas.hansson@arm.comsystem.mem_ctrls_0.readEnergy               697686600                       # Energy for read commands per rank (pJ)
27511201Sandreas.hansson@arm.comsystem.mem_ctrls_0.writeEnergy              474096240                       # Energy for write commands per rank (pJ)
27611201Sandreas.hansson@arm.comsystem.mem_ctrls_0.refreshEnergy         341033724720                       # Energy for refresh commands per rank (pJ)
27711201Sandreas.hansson@arm.comsystem.mem_ctrls_0.actBackEnergy         139619979810                       # Energy for active background per rank (pJ)
27811201Sandreas.hansson@arm.comsystem.mem_ctrls_0.preBackEnergy         3010341298500                       # Energy for precharge background per rank (pJ)
27911201Sandreas.hansson@arm.comsystem.mem_ctrls_0.totalEnergy           3492509834100                       # Total energy per rank (pJ)
28011201Sandreas.hansson@arm.comsystem.mem_ctrls_0.averagePower            668.889138                       # Core power per rank (mW)
28111201Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::IDLE 5007866146000                       # Time in different power states
28211201Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::REF  174352620000                       # Time in different power states
28310628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
28411201Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT   39146148500                       # Time in different power states
28510628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
28611201Sandreas.hansson@arm.comsystem.mem_ctrls_1.actEnergy                231101640                       # Energy for activate commands per rank (pJ)
28711201Sandreas.hansson@arm.comsystem.mem_ctrls_1.preEnergy                126097125                       # Energy for precharge commands per rank (pJ)
28811201Sandreas.hansson@arm.comsystem.mem_ctrls_1.readEnergy               716414400                       # Energy for read commands per rank (pJ)
28911201Sandreas.hansson@arm.comsystem.mem_ctrls_1.writeEnergy              479895840                       # Energy for write commands per rank (pJ)
29011201Sandreas.hansson@arm.comsystem.mem_ctrls_1.refreshEnergy         341033724720                       # Energy for refresh commands per rank (pJ)
29111201Sandreas.hansson@arm.comsystem.mem_ctrls_1.actBackEnergy         139466264490                       # Energy for active background per rank (pJ)
29211201Sandreas.hansson@arm.comsystem.mem_ctrls_1.preBackEnergy         3010476136500                       # Energy for precharge background per rank (pJ)
29311201Sandreas.hansson@arm.comsystem.mem_ctrls_1.totalEnergy           3492529634715                       # Total energy per rank (pJ)
29411201Sandreas.hansson@arm.comsystem.mem_ctrls_1.averagePower            668.892930                       # Core power per rank (mW)
29511201Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::IDLE 5008078591499                       # Time in different power states
29611201Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::REF  174352620000                       # Time in different power states
29710628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
29811201Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT   38927077251                       # Time in different power states
29910628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
30010315Snilay@cs.wisc.edusystem.cpu_clk_domain.clock                       500                       # Clock period in ticks
30110036SAli.Saidi@ARM.comsystem.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
30211201Sandreas.hansson@arm.comsystem.cpu0.numCycles                     10442730030                       # number of cpu cycles simulated
3038968SN/Asystem.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
3048968SN/Asystem.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
30511201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
30611201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
30711201Sandreas.hansson@arm.comsystem.cpu0.committedInsts                  100536790                       # Number of instructions committed
30811201Sandreas.hansson@arm.comsystem.cpu0.committedOps                    194797787                       # Number of ops (including micro ops) committed
30911201Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses            182088702                       # Number of integer alu accesses
31010645Snilay@cs.wisc.edusystem.cpu0.num_fp_alu_accesses                    48                       # Number of float alu accesses
31111201Sandreas.hansson@arm.comsystem.cpu0.num_func_calls                    1786032                       # number of times a function call or return occured
31211201Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts     17861740                       # number of instructions that are conditional controls
31311201Sandreas.hansson@arm.comsystem.cpu0.num_int_insts                   182088702                       # number of integer instructions
31410645Snilay@cs.wisc.edusystem.cpu0.num_fp_insts                           48                       # number of float instructions
31511201Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads          340614933                       # number of times the integer registers were read
31611201Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes         155369927                       # number of times the integer registers were written
31710645Snilay@cs.wisc.edusystem.cpu0.num_fp_register_reads                  48                       # number of times the floating registers were read
3188968SN/Asystem.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
31911201Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads           104545094                       # number of times the CC registers were read
32011201Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes           75102328                       # number of times the CC registers were written
32111201Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs                     18441277                       # number of memory refs
32211201Sandreas.hansson@arm.comsystem.cpu0.num_load_insts                   11598406                       # Number of load instructions
32311201Sandreas.hansson@arm.comsystem.cpu0.num_store_insts                   6842871                       # Number of store instructions
32411201Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles              9945203438.030096                       # Number of idle cycles
32511201Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles              497526591.969905                       # Number of busy cycles
32611201Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction                0.047643                       # Percentage of non-idle cycles
32711201Sandreas.hansson@arm.comsystem.cpu0.idle_fraction                    0.952357                       # Percentage of idle cycles
32811201Sandreas.hansson@arm.comsystem.cpu0.Branches                         20259437                       # Number of branches fetched
32911201Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass               186593      0.10%      0.10% # Class of executed instruction
33011201Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu                175972173     90.34%     90.43% # Class of executed instruction
33111201Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult                  117562      0.06%     90.49% # Class of executed instruction
33211201Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv                    85263      0.04%     90.54% # Class of executed instruction
33311201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd                      0      0.00%     90.54% # Class of executed instruction
33411201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp                      0      0.00%     90.54% # Class of executed instruction
33511201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt                     16      0.00%     90.54% # Class of executed instruction
33611201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult                     0      0.00%     90.54% # Class of executed instruction
33711201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv                      0      0.00%     90.54% # Class of executed instruction
33811201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt                     0      0.00%     90.54% # Class of executed instruction
33911201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd                       0      0.00%     90.54% # Class of executed instruction
34011201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc                    0      0.00%     90.54% # Class of executed instruction
34111201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu                       0      0.00%     90.54% # Class of executed instruction
34211201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp                       0      0.00%     90.54% # Class of executed instruction
34311201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt                       0      0.00%     90.54% # Class of executed instruction
34411201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc                      0      0.00%     90.54% # Class of executed instruction
34511201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult                      0      0.00%     90.54% # Class of executed instruction
34611201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc                   0      0.00%     90.54% # Class of executed instruction
34711201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift                     0      0.00%     90.54% # Class of executed instruction
34811201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.54% # Class of executed instruction
34911201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt                      0      0.00%     90.54% # Class of executed instruction
35011201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.54% # Class of executed instruction
35111201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.54% # Class of executed instruction
35211201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.54% # Class of executed instruction
35311201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.54% # Class of executed instruction
35411201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.54% # Class of executed instruction
35511201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.54% # Class of executed instruction
35611201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult                 0      0.00%     90.54% # Class of executed instruction
35711201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.54% # Class of executed instruction
35811201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.54% # Class of executed instruction
35911201Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead                11594262      5.95%     96.49% # Class of executed instruction
36011201Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite                6842871      3.51%    100.00% # Class of executed instruction
36110220Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
36210220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
36311201Sandreas.hansson@arm.comsystem.cpu0.op_class::total                 194798740                       # Class of executed instruction
36410036SAli.Saidi@ARM.comsystem.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
36511201Sandreas.hansson@arm.comsystem.cpu1.numCycles                     10442397548                       # number of cpu cycles simulated
3668968SN/Asystem.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
3678968SN/Asystem.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
36811201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
36911201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
37011201Sandreas.hansson@arm.comsystem.cpu1.committedInsts                   50519564                       # Number of instructions committed
37111201Sandreas.hansson@arm.comsystem.cpu1.committedOps                     98516978                       # Number of ops (including micro ops) committed
37211201Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses             91922994                       # Number of integer alu accesses
37310645Snilay@cs.wisc.edusystem.cpu1.num_fp_alu_accesses                    48                       # Number of float alu accesses
37411201Sandreas.hansson@arm.comsystem.cpu1.num_func_calls                     994306                       # number of times a function call or return occured
37511201Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts      9151225                       # number of instructions that are conditional controls
37611201Sandreas.hansson@arm.comsystem.cpu1.num_int_insts                    91922994                       # number of integer instructions
37710645Snilay@cs.wisc.edusystem.cpu1.num_fp_insts                           48                       # number of float instructions
37811201Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads          171998955                       # number of times the integer registers were read
37911201Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes          78483891                       # number of times the integer registers were written
38010645Snilay@cs.wisc.edusystem.cpu1.num_fp_register_reads                  48                       # number of times the floating registers were read
3818968SN/Asystem.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
38211201Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads            52229827                       # number of times the CC registers were read
38311201Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes           37031962                       # number of times the CC registers were written
38411201Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs                      8648347                       # number of memory refs
38511201Sandreas.hansson@arm.comsystem.cpu1.num_load_insts                    5505950                       # Number of load instructions
38611201Sandreas.hansson@arm.comsystem.cpu1.num_store_insts                   3142397                       # Number of store instructions
38711201Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles              10281439289.330288                       # Number of idle cycles
38811201Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles              160958258.669712                       # Number of busy cycles
38911201Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction                0.015414                       # Percentage of non-idle cycles
39011201Sandreas.hansson@arm.comsystem.cpu1.idle_fraction                    0.984586                       # Percentage of idle cycles
39111201Sandreas.hansson@arm.comsystem.cpu1.Branches                         10509152                       # Number of branches fetched
39211201Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass               118845      0.12%      0.12% # Class of executed instruction
39311201Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu                 89646727     91.00%     91.12% # Class of executed instruction
39411201Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult                   68401      0.07%     91.19% # Class of executed instruction
39511201Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv                    39477      0.04%     91.23% # Class of executed instruction
39611201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd                      0      0.00%     91.23% # Class of executed instruction
39711201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp                      0      0.00%     91.23% # Class of executed instruction
39811201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt                     16      0.00%     91.23% # Class of executed instruction
39911201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult                     0      0.00%     91.23% # Class of executed instruction
40011201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv                      0      0.00%     91.23% # Class of executed instruction
40111201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt                     0      0.00%     91.23% # Class of executed instruction
40211201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd                       0      0.00%     91.23% # Class of executed instruction
40311201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc                    0      0.00%     91.23% # Class of executed instruction
40411201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu                       0      0.00%     91.23% # Class of executed instruction
40511201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp                       0      0.00%     91.23% # Class of executed instruction
40611201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt                       0      0.00%     91.23% # Class of executed instruction
40711201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc                      0      0.00%     91.23% # Class of executed instruction
40811201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult                      0      0.00%     91.23% # Class of executed instruction
40911201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc                   0      0.00%     91.23% # Class of executed instruction
41011201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift                     0      0.00%     91.23% # Class of executed instruction
41111201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc                  0      0.00%     91.23% # Class of executed instruction
41211201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt                      0      0.00%     91.23% # Class of executed instruction
41311201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd                  0      0.00%     91.23% # Class of executed instruction
41411201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu                  0      0.00%     91.23% # Class of executed instruction
41511201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp                  0      0.00%     91.23% # Class of executed instruction
41611201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt                  0      0.00%     91.23% # Class of executed instruction
41711201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv                  0      0.00%     91.23% # Class of executed instruction
41811201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc                 0      0.00%     91.23% # Class of executed instruction
41911201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult                 0      0.00%     91.23% # Class of executed instruction
42011201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc              0      0.00%     91.23% # Class of executed instruction
42111201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt                 0      0.00%     91.23% # Class of executed instruction
42211201Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead                 5501755      5.58%     96.81% # Class of executed instruction
42311201Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite                3142397      3.19%    100.00% # Class of executed instruction
42410220Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
42510220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
42611201Sandreas.hansson@arm.comsystem.cpu1.op_class::total                  98517618                       # Class of executed instruction
42711201Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq               883857                       # Transaction distribution
42811201Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp              883857                       # Transaction distribution
42911201Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq               36766                       # Transaction distribution
43011201Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp              36766                       # Transaction distribution
43111201Sandreas.hansson@arm.comsystem.iobus.trans_dist::MessageReq              1833                       # Transaction distribution
43211201Sandreas.hansson@arm.comsystem.iobus.trans_dist::MessageResp             1833                       # Transaction distribution
43311201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1736                       # Packet count per connected master and slave (bytes)
43411201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1682                       # Packet count per connected master and slave (bytes)
43511201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3418                       # Packet count per connected master and slave (bytes)
43611201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
43711201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         6154                       # Packet count per connected master and slave (bytes)
43811201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           88                       # Packet count per connected master and slave (bytes)
43911201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          712                       # Packet count per connected master and slave (bytes)
44011201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           74                       # Packet count per connected master and slave (bytes)
44111201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           38                       # Packet count per connected master and slave (bytes)
44210560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
44311201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       917434                       # Packet count per connected master and slave (bytes)
44411201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1422                       # Packet count per connected master and slave (bytes)
44511201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           90                       # Packet count per connected master and slave (bytes)
44610560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
44711201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        14468                       # Packet count per connected master and slave (bytes)
44811201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       811270                       # Packet count per connected master and slave (bytes)
44911201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          178                       # Packet count per connected master and slave (bytes)
45010560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         2126                       # Packet count per connected master and slave (bytes)
45111201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1754122                       # Packet count per connected master and slave (bytes)
45211201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           16                       # Packet count per connected master and slave (bytes)
45311201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
45411201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4888                       # Packet count per connected master and slave (bytes)
45511201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           92                       # Packet count per connected master and slave (bytes)
45611201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          652                       # Packet count per connected master and slave (bytes)
45711201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           12                       # Packet count per connected master and slave (bytes)
45811201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
45911201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        31650                       # Packet count per connected master and slave (bytes)
46011201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          676                       # Packet count per connected master and slave (bytes)
46111201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        31738                       # Packet count per connected master and slave (bytes)
46211201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        12896                       # Packet count per connected master and slave (bytes)
46311201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
46411201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
46511201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
46611201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
46711201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port           70                       # Packet count per connected master and slave (bytes)
46811201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         4614                       # Packet count per connected master and slave (bytes)
46911201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        87372                       # Packet count per connected master and slave (bytes)
47011201Sandreas.hansson@arm.comsystem.iobus.pkt_count::total                 1844912                       # Packet count per connected master and slave (bytes)
47111201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3472                       # Cumulative packet size per connected master and slave (bytes)
47211201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3364                       # Cumulative packet size per connected master and slave (bytes)
47311201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6836                       # Cumulative packet size per connected master and slave (bytes)
47411201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
47511201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3500                       # Cumulative packet size per connected master and slave (bytes)
47611201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          149                       # Cumulative packet size per connected master and slave (bytes)
47711201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          356                       # Cumulative packet size per connected master and slave (bytes)
47811201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           37                       # Cumulative packet size per connected master and slave (bytes)
47911201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           19                       # Cumulative packet size per connected master and slave (bytes)
48010560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
48111201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       458717                       # Cumulative packet size per connected master and slave (bytes)
48211201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         2844                       # Cumulative packet size per connected master and slave (bytes)
48311201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           45                       # Cumulative packet size per connected master and slave (bytes)
48410560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
48511201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         7234                       # Cumulative packet size per connected master and slave (bytes)
48611201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1622534                       # Cumulative packet size per connected master and slave (bytes)
48711201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          356                       # Cumulative packet size per connected master and slave (bytes)
48810560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         4252                       # Cumulative packet size per connected master and slave (bytes)
48911201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      2100077                       # Cumulative packet size per connected master and slave (bytes)
49011201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio            8                       # Cumulative packet size per connected master and slave (bytes)
49111201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
49211201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3160                       # Cumulative packet size per connected master and slave (bytes)
49311201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           72                       # Cumulative packet size per connected master and slave (bytes)
49411201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          326                       # Cumulative packet size per connected master and slave (bytes)
49511201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            6                       # Cumulative packet size per connected master and slave (bytes)
49611201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
49711201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        15825                       # Cumulative packet size per connected master and slave (bytes)
49811201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1352                       # Cumulative packet size per connected master and slave (bytes)
49911201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        15869                       # Cumulative packet size per connected master and slave (bytes)
50011201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6448                       # Cumulative packet size per connected master and slave (bytes)
50111201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50211201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50311201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50411201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
50511201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          140                       # Cumulative packet size per connected master and slave (bytes)
50611201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         9225                       # Cumulative packet size per connected master and slave (bytes)
50711201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        52465                       # Cumulative packet size per connected master and slave (bytes)
50811201Sandreas.hansson@arm.comsystem.iobus.pkt_size::total                  2159378                       # Cumulative packet size per connected master and slave (bytes)
50911201Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy                43000                       # Layer occupancy (ticks)
51010560Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
51111201Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy                 7500                       # Layer occupancy (ticks)
51210560Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
51311201Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy              9039000                       # Layer occupancy (ticks)
51410560Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
51511201Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy               159000                       # Layer occupancy (ticks)
51610560Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
51711201Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy               945000                       # Layer occupancy (ticks)
51810560Sandreas.hansson@arm.comsystem.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
51911201Sandreas.hansson@arm.comsystem.iobus.reqLayer5.occupancy                85000                       # Layer occupancy (ticks)
52010560Sandreas.hansson@arm.comsystem.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
52111201Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy                51500                       # Layer occupancy (ticks)
52210560Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
52311201Sandreas.hansson@arm.comsystem.iobus.reqLayer7.occupancy             21127500                       # Layer occupancy (ticks)
52410560Sandreas.hansson@arm.comsystem.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
52511201Sandreas.hansson@arm.comsystem.iobus.reqLayer8.occupancy            458718000                       # Layer occupancy (ticks)
52610560Sandreas.hansson@arm.comsystem.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
52711201Sandreas.hansson@arm.comsystem.iobus.reqLayer9.occupancy              1770984                       # Layer occupancy (ticks)
52810560Sandreas.hansson@arm.comsystem.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
52911201Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy            31828500                       # Layer occupancy (ticks)
53010560Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
53111201Sandreas.hansson@arm.comsystem.iobus.reqLayer12.occupancy                2500                       # Layer occupancy (ticks)
53210560Sandreas.hansson@arm.comsystem.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
53311201Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy            20526000                       # Layer occupancy (ticks)
53410560Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
53511201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
53610560Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
53710892Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
53810560Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
53911026Snilay@cs.wisc.edusystem.iobus.reqLayer16.occupancy                9500                       # Layer occupancy (ticks)
54010560Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
54110892Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
54210560Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
54311201Sandreas.hansson@arm.comsystem.iobus.reqLayer18.occupancy           410368779                       # Layer occupancy (ticks)
54410560Sandreas.hansson@arm.comsystem.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
54511201Sandreas.hansson@arm.comsystem.iobus.reqLayer19.occupancy             7668139                       # Layer occupancy (ticks)
54610560Sandreas.hansson@arm.comsystem.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
54711026Snilay@cs.wisc.edusystem.iobus.reqLayer21.occupancy             1592000                       # Layer occupancy (ticks)
54810560Sandreas.hansson@arm.comsystem.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
54911201Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy             2481464                       # Layer occupancy (ticks)
55010560Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
55111201Sandreas.hansson@arm.comsystem.iobus.respLayer2.occupancy          1948163500                       # Layer occupancy (ticks)
55210560Sandreas.hansson@arm.comsystem.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
55311201Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy            60411500                       # Layer occupancy (ticks)
55410560Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
55510560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
55610560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
55711066Snilay@cs.wisc.edusystem.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
55810560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
55910560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_bytes      2987008                       # Number of bytes transfered via DMA writes.
56011201Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
56110560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
56210560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
56310560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
56410560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
56510560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
56610560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
56710560Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock                      500                       # Clock period in ticks
56810560Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
56910560Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
57011201Sandreas.hansson@arm.comsystem.ruby.delayHist::samples               11180744                       # delay histogram for all message
57111201Sandreas.hansson@arm.comsystem.ruby.delayHist::mean                  0.431770                       # delay histogram for all message
57211201Sandreas.hansson@arm.comsystem.ruby.delayHist::stdev                 1.809571                       # delay histogram for all message
57311201Sandreas.hansson@arm.comsystem.ruby.delayHist                    |    10577839     94.61%     94.61% |        2056      0.02%     94.63% |      600268      5.37%     99.99% |         190      0.00%    100.00% |         314      0.00%    100.00% |          12      0.00%    100.00% |          62      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
57411201Sandreas.hansson@arm.comsystem.ruby.delayHist::total                 11180744                       # delay histogram for all message
57510560Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::bucket_size            1                      
57610560Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::max_bucket            9                      
57711201Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::samples    197955014                      
57811201Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::mean       1.000129                      
57911201Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::gmean      1.000089                      
58011201Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::stdev      0.011356                      
58111201Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   197929484     99.99%     99.99% |       25530      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
58211201Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::total     197955014                      
58311066Snilay@cs.wisc.edusystem.ruby.latency_hist::bucket_size             128                      
58411066Snilay@cs.wisc.edusystem.ruby.latency_hist::max_bucket             1279                      
58511201Sandreas.hansson@arm.comsystem.ruby.latency_hist::samples           197955013                      
58611201Sandreas.hansson@arm.comsystem.ruby.latency_hist::mean               1.340863                      
58711201Sandreas.hansson@arm.comsystem.ruby.latency_hist::gmean              1.042158                      
58811201Sandreas.hansson@arm.comsystem.ruby.latency_hist::stdev              5.086284                      
58911201Sandreas.hansson@arm.comsystem.ruby.latency_hist                 |   197919444     99.98%     99.98% |       26717      0.01%    100.00% |        2924      0.00%    100.00% |        3327      0.00%    100.00% |        1642      0.00%    100.00% |         886      0.00%    100.00% |           9      0.00%    100.00% |          33      0.00%    100.00% |          23      0.00%    100.00% |           8      0.00%    100.00%
59011201Sandreas.hansson@arm.comsystem.ruby.latency_hist::total             197955013                      
59110560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::bucket_size            1                      
59210560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::max_bucket            9                      
59311201Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::samples       195243076                      
59411026Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::mean                  1                      
59511026Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::gmean                 1                      
59611201Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist             |           0      0.00%      0.00% |   195243076    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
59711201Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::total         195243076                      
59811066Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::bucket_size          128                      
59911066Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::max_bucket         1279                      
60011201Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::samples        2711937                      
60111201Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::mean         25.880928                      
60211201Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::gmean        20.371838                      
60311201Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::stdev        35.746268                      
60411201Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist            |     2676368     98.69%     98.69% |       26717      0.99%     99.67% |        2924      0.11%     99.78% |        3327      0.12%     99.90% |        1642      0.06%     99.96% |         886      0.03%    100.00% |           9      0.00%    100.00% |          33      0.00%    100.00% |          23      0.00%    100.00% |           8      0.00%    100.00%
60511201Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::total          2711937                      
60611201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Dcache.demand_hits     16386658                       # Number of cache demand hits
60711201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Dcache.demand_misses      1208703                       # Number of cache demand misses
60811201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Dcache.demand_accesses     17595361                       # Number of cache demand accesses
60911201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Icache.demand_hits    114457594                       # Number of cache demand hits
61011201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Icache.demand_misses       551051                       # Number of cache demand misses
61111201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Icache.demand_accesses    115008645                       # Number of cache demand accesses
61210560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
61310560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
61410560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
61510560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
61610560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
61710560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.hits               0                       # number of prefetched blocks accessed
61810560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
61910560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
62010560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
62111201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.fully_busy_cycles            14                       # cycles for which number of transistions == max transitions
62211201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Dcache.demand_hits      7947911                       # Number of cache demand hits
62311201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Dcache.demand_misses       682965                       # Number of cache demand misses
62411201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Dcache.demand_accesses      8630876                       # Number of cache demand accesses
62511201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Icache.demand_hits     56450913                       # Number of cache demand hits
62611201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Icache.demand_misses       269218                       # Number of cache demand misses
62711201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Icache.demand_accesses     56720131                       # Number of cache demand accesses
62810560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.miss_observed            0                       # number of misses observed
62910560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
63010560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.prefetches_requested            0                       # number of prefetch requests made
63110560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
63210560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
63310560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.hits               0                       # number of prefetched blocks accessed
63410560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
63510560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
63610560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
63711201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.fully_busy_cycles            14                       # cycles for which number of transistions == max transitions
63811201Sandreas.hansson@arm.comsystem.ruby.l2_cntrl0.L2cache.demand_hits      2479106                       # Number of cache demand hits
63911201Sandreas.hansson@arm.comsystem.ruby.l2_cntrl0.L2cache.demand_misses       232831                       # Number of cache demand misses
64011201Sandreas.hansson@arm.comsystem.ruby.l2_cntrl0.L2cache.demand_accesses      2711937                       # Number of cache demand accesses
64110560Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock             1500                       # Clock period in ticks
64211201Sandreas.hansson@arm.comsystem.ruby.network.routers0.percent_links_utilized     0.059056                      
64311201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Control::0      1759754                      
64411201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Request_Control::2        45501                      
64511201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Response_Data::1      1788735                      
64611201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Response_Control::1      1174106                      
64711201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Response_Control::2      1170476                      
64811201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Writeback_Data::0       411011                      
64911201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Writeback_Data::1          193                      
65011201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Writeback_Control::0       718896                      
65111201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Control::0     14078032                      
65211201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Request_Control::2       364008                      
65311201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Response_Data::1    128788920                      
65411201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Response_Control::1      9392848                      
65511201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Response_Control::2      9363808                      
65611201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Writeback_Data::0     29592792                      
65711201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Writeback_Data::1        13896                      
65811201Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Writeback_Control::0      5751168                      
65911201Sandreas.hansson@arm.comsystem.ruby.network.routers1.percent_links_utilized     0.031129                      
66011201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Control::0       952183                      
66111201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Request_Control::2        41487                      
66211201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Response_Data::1       977973                      
66311201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Response_Control::1       652847                      
66411201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Response_Control::2       651858                      
66511201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Writeback_Data::0       161021                      
66611201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Writeback_Data::1          301                      
66711201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Writeback_Control::0       450874                      
66811201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Control::0      7617464                      
66911201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Request_Control::2       331896                      
67011201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Response_Data::1     70414056                      
67111201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Response_Control::1      5222776                      
67211201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Response_Control::2      5214864                      
67311201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Writeback_Data::0     11593512                      
67411201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Writeback_Data::1        21672                      
67511201Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Writeback_Control::0      3606992                      
67611201Sandreas.hansson@arm.comsystem.ruby.network.routers2.percent_links_utilized     0.094716                      
67711201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Control::0      2893171                      
67811201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Request_Control::2        85123                      
67911201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Response_Data::1      2948036                      
68011201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Response_Control::1      1908362                      
68111201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Response_Control::2      1822334                      
68211201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Writeback_Data::0       572032                      
68311201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Writeback_Data::1          494                      
68411201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Writeback_Control::0      1169770                      
68511201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Control::0     23145368                      
68611201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Request_Control::2       680984                      
68711201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Response_Data::1    212258592                      
68811201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Response_Control::1     15266896                      
68911201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Response_Control::2     14578672                      
69011201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Writeback_Data::0     41186304                      
69111201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Writeback_Data::1        35568                      
69211201Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Writeback_Control::0      9358160                      
69311201Sandreas.hansson@arm.comsystem.ruby.network.routers3.percent_links_utilized     0.007127                      
69411201Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Control::0       181234                      
69511201Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Response_Data::1       285341                      
69611201Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Response_Control::1       133293                      
69711201Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Writeback_Control::0        47555                      
69810560Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Writeback_Control::1        46736                      
69911201Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Control::0      1449872                      
70011201Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Response_Data::1     20544552                      
70111201Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Response_Control::1      1066344                      
70211201Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Writeback_Control::0       380440                      
70310560Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Writeback_Control::1       373888                      
70411026Snilay@cs.wisc.edusystem.ruby.network.routers4.percent_links_utilized     0.000243                      
70511201Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_count.Response_Data::1          819                      
70611201Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_count.Writeback_Control::0        47555                      
70710560Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_count.Writeback_Control::1        46736                      
70811201Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_bytes.Response_Data::1        58968                      
70911201Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_bytes.Writeback_Control::0       380440                      
71010560Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_bytes.Writeback_Control::1       373888                      
71110560Sandreas.hansson@arm.comsystem.ruby.network.routers5.percent_links_utilized            0                      
71211201Sandreas.hansson@arm.comsystem.ruby.network.routers6.percent_links_utilized     0.032046                      
71311201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Control::0      2893171                      
71411201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Request_Control::2        86988                      
71511201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Response_Data::1      3000452                      
71611201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Response_Control::1      1934304                      
71711201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Response_Control::2      1822334                      
71811201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Writeback_Data::0       572032                      
71911201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Writeback_Data::1          494                      
72011201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Writeback_Control::0      1217325                      
72110560Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Writeback_Control::1        46736                      
72211201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Control::0     23145368                      
72311201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Request_Control::2       695904                      
72411201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Response_Data::1    216032544                      
72511201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Response_Control::1     15474432                      
72611201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Response_Control::2     14578672                      
72711201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Writeback_Data::0     41186304                      
72811201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Writeback_Data::1        35568                      
72911201Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Writeback_Control::0      9738600                      
73010560Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Writeback_Control::1       373888                      
73111201Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Control         8679513                      
73211201Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Request_Control       259099                      
73311201Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Response_Data      9001356                      
73411201Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Response_Control     11269914                      
73511201Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Writeback_Data      1717578                      
73611201Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Writeback_Control      3792183                      
73711201Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Control         69436104                      
73811201Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Request_Control      2072792                      
73911201Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Response_Data    648097632                      
74011201Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Response_Control     90159312                      
74111201Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Writeback_Data    123665616                      
74211201Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Writeback_Control     30337464                      
74311201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.link_utilization     0.081037                      
74411201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_count.Request_Control::2        45501                      
74511201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_count.Response_Data::1      1747073                      
74611201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_count.Response_Control::1      1155797                      
74711201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2       364008                      
74811201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1    125789256                      
74911201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1      9246376                      
75011201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.link_utilization     0.037075                      
75111201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Control::0      1759754                      
75211201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Response_Data::1        41662                      
75311201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Response_Control::1        18309                      
75411201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Response_Control::2      1170476                      
75511201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0       411011                      
75611201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1          193                      
75711201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0       718896                      
75811201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Control::0     14078032                      
75911201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1      2999664                      
76011201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1       146472                      
76111201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2      9363808                      
76211201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0     29592792                      
76311201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        13896                      
76411201Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0      5751168                      
76511201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.link_utilization     0.043775                      
76611201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_count.Request_Control::2        41487                      
76711201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_count.Response_Data::1       940552                      
76811201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_count.Response_Control::1       636259                      
76911201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2       331896                      
77011201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1     67719744                      
77111201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1      5090072                      
77211201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.link_utilization     0.018483                      
77311201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Control::0       952183                      
77411201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Data::1        37421                      
77511201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Control::1        16588                      
77611201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Control::2       651858                      
77711201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0       161021                      
77811201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1          301                      
77911201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0       450874                      
78011201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Control::0      7617464                      
78111201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1      2694312                      
78211201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1       132704                      
78311201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2      5214864                      
78411201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0     11593512                      
78511201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1        21672                      
78611201Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0      3606992                      
78711201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.link_utilization     0.061593                      
78811201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Control::0      2711937                      
78911201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Data::1       208720                      
79011201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Control::1       128788                      
79111201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Control::2      1822334                      
79211201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0       572032                      
79311201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1          494                      
79411201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0      1169770                      
79511201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Control::0     21695496                      
79611201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1     15027840                      
79711201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1      1030304                      
79811201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2     14578672                      
79911201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0     41186304                      
80011201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1        35568                      
80111201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0      9358160                      
80211201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.link_utilization     0.127839                      
80311201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_count.Control::0       181234                      
80411201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_count.Request_Control::2        85123                      
80511201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_count.Response_Data::1      2739316                      
80611201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_count.Response_Control::1      1779574                      
80711201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_bytes.Control::0      1449872                      
80811201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2       680984                      
80911201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1    197230752                      
81011201Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1     14236592                      
81111201Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle0.link_utilization     0.005611                      
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81311201Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle0.msg_count.Response_Data::1       103288                      
81411201Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle0.msg_count.Response_Control::1        13460                      
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81611201Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle0.msg_bytes.Control::0      1449872                      
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8239978SN/Asystem.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1        46736                      
82411201Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1     13107816                      
82511201Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1       958664                      
8269978SN/Asystem.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1       373888                      
82711026Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.link_utilization     0.000259                      
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8299978SN/Asystem.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1        46736                      
83011201Sandreas.hansson@arm.comsystem.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1        58968                      
8319978SN/Asystem.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1       373888                      
83211201Sandreas.hansson@arm.comsystem.ruby.network.routers4.throttle1.link_utilization     0.000228                      
83311201Sandreas.hansson@arm.comsystem.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0        47555                      
83411201Sandreas.hansson@arm.comsystem.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0       380440                      
83510526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle0.link_utilization            0                      
83610526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle1.link_utilization            0                      
83711201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.link_utilization     0.081037                      
83811201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.msg_count.Request_Control::2        45501                      
83911201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.msg_count.Response_Data::1      1747073                      
84011201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.msg_count.Response_Control::1      1155797                      
84111201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2       364008                      
84211201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1    125789256                      
84311201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1      9246376                      
84411201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.link_utilization     0.043775                      
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84611201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.msg_count.Response_Data::1       940552                      
84711201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.msg_count.Response_Control::1       636259                      
84811201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2       331896                      
84911201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1     67719744                      
85011201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1      5090072                      
85111201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.link_utilization     0.061593                      
85211201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Control::0      2711937                      
85311201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Response_Data::1       208720                      
85411201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Response_Control::1       128788                      
85511201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Response_Control::2      1822334                      
85611201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0       572032                      
85711201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1          494                      
85811201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0      1169770                      
85911201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Control::0     21695496                      
86011201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1     15027840                      
86111201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1      1030304                      
86211201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2     14578672                      
86311201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0     41186304                      
86411201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1        35568                      
86511201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0      9358160                      
86611201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.link_utilization     0.005611                      
86711201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_count.Control::0       181234                      
86811201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_count.Response_Data::1       103288                      
86911201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_count.Response_Control::1        13460                      
87011201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0        47555                      
87111201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_bytes.Control::0      1449872                      
87211201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1      7436736                      
87311201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1       107680                      
87411201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0       380440                      
87511026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.link_utilization     0.000259                      
87611201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle4.msg_count.Response_Data::1          819                      
87710526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1        46736                      
87811201Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1        58968                      
87910526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1       373888                      
88010526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle5.link_utilization            0                      
88110229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
88210229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
88311201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_0::samples       6276073                       # delay histogram for vnet_0
88411201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_0::mean         0.731694                       # delay histogram for vnet_0
88511201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_0::stdev        2.309515                       # delay histogram for vnet_0
88611201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_0           |     5702895     90.87%     90.87% |         563      0.01%     90.88% |      572045      9.11%     99.99% |         184      0.00%     99.99% |         309      0.00%    100.00% |          12      0.00%    100.00% |          62      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
88711201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_0::total         6276073                       # delay histogram for vnet_0
88810229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
88910229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
89011201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::samples       4817683                       # delay histogram for vnet_1
89111201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::mean         0.048845                       # delay histogram for vnet_1
89211201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::stdev        0.619508                       # delay histogram for vnet_1
89311201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1           |     4787335     99.37%     99.37% |         621      0.01%     99.38% |         650      0.01%     99.40% |         843      0.02%     99.41% |       27983      0.58%     99.99% |         240      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           3      0.00%    100.00% |           2      0.00%    100.00% # delay histogram for vnet_1
89411201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::total         4817683                       # delay histogram for vnet_1
89510315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
89610315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
89711201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2::samples         86988                       # delay histogram for vnet_2
89811201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2::mean         0.000184                       # delay histogram for vnet_2
89911201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2::stdev        0.019179                       # delay histogram for vnet_2
90011201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2           |       86980     99.99%     99.99% |           0      0.00%     99.99% |           8      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
90111201Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2::total           86988                       # delay histogram for vnet_2
90210628Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::bucket_size          128                      
90310628Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::max_bucket          1279                      
90411201Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::samples         15432046                      
90511201Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::mean            2.853578                      
90611201Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::gmean           1.313269                      
90711201Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::stdev           9.014347                      
90811201Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist              |    15417213     99.90%     99.90% |       12849      0.08%     99.99% |         809      0.01%     99.99% |         750      0.00%    100.00% |         322      0.00%    100.00% |          89      0.00%    100.00% |           3      0.00%    100.00% |           6      0.00%    100.00% |           3      0.00%    100.00% |           2      0.00%    100.00%
90911201Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::total           15432046                      
91010013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size            1                      
91110013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket            9                      
91211201Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist::samples     13998284                      
91311026Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean               1                      
91411026Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean              1                      
91511201Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |    13998284    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
91611201Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist::total       13998284                      
91710628Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::bucket_size          128                      
91810628Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::max_bucket         1279                      
91911201Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::samples      1433762                      
92011201Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::mean      20.950658                      
92111201Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::gmean     18.787895                      
92211201Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::stdev     22.661921                      
92311201Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist         |     1418929     98.97%     98.97% |       12849      0.90%     99.86% |         809      0.06%     99.92% |         750      0.05%     99.97% |         322      0.02%     99.99% |          89      0.01%    100.00% |           3      0.00%    100.00% |           6      0.00%    100.00% |           3      0.00%    100.00% |           2      0.00%    100.00%
92411201Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::total       1433762                      
92511066Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size          128                      
92611066Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket          1279                      
92711201Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::samples          9612989                      
92811201Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::mean            3.237181                      
92911201Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::gmean           1.143928                      
93011201Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::stdev          17.959095                      
93111201Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist              |     9598428     99.85%     99.85% |        8674      0.09%     99.94% |        1607      0.02%     99.96% |        2294      0.02%     99.98% |        1185      0.01%     99.99% |         751      0.01%    100.00% |           6      0.00%    100.00% |          22      0.00%    100.00% |          16      0.00%    100.00% |           6      0.00%    100.00%
93211201Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::total            9612989                      
93310013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size            1                      
93410013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket            9                      
93511201Sandreas.hansson@arm.comsystem.ruby.ST.hit_latency_hist::samples      9259406                      
93611026Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean               1                      
93711026Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean              1                      
93811201Sandreas.hansson@arm.comsystem.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |     9259406    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
93911201Sandreas.hansson@arm.comsystem.ruby.ST.hit_latency_hist::total        9259406                      
94011066Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size          128                      
94111066Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket         1279                      
94211201Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::samples       353583                      
94311201Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::mean      61.823054                      
94411201Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::gmean     38.699181                      
94511201Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::stdev     72.148162                      
94611201Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist         |      339022     95.88%     95.88% |        8674      2.45%     98.34% |        1607      0.45%     98.79% |        2294      0.65%     99.44% |        1185      0.34%     99.77% |         751      0.21%     99.99% |           6      0.00%     99.99% |          22      0.01%     99.99% |          16      0.00%    100.00% |           6      0.00%    100.00%
94711201Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::total        353583                      
94810526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size          128                      
94910526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket         1279                      
95011201Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::samples    171728776                      
95111201Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::mean        1.087723                      
95211201Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::gmean       1.013813                      
95311201Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::stdev       1.876064                      
95411201Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist          |   171723049    100.00%    100.00% |        4816      0.00%    100.00% |         477      0.00%    100.00% |         266      0.00%    100.00% |         120      0.00%    100.00% |          39      0.00%    100.00% |           0      0.00%    100.00% |           5      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00%
95511201Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::total      171728776                      
95610013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
95710013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
95811201Sandreas.hansson@arm.comsystem.ruby.IFETCH.hit_latency_hist::samples    170908507                      
95911026Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean            1                      
96011026Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean            1                      
96111201Sandreas.hansson@arm.comsystem.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |   170908507    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
96211201Sandreas.hansson@arm.comsystem.ruby.IFETCH.hit_latency_hist::total    170908507                      
96310526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size          128                      
96410526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket         1279                      
96511201Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::samples       820269                      
96611201Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::mean    19.365461                      
96711201Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::gmean    17.675024                      
96811201Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::stdev    20.029392                      
96911201Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist     |      814542     99.30%     99.30% |        4816      0.59%     99.89% |         477      0.06%     99.95% |         266      0.03%     99.98% |         120      0.01%     99.99% |          39      0.00%    100.00% |           0      0.00%    100.00% |           5      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00%
97011201Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::total       820269                      
97110526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::bucket_size          128                      
97210526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::max_bucket         1279                      
97311201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist::samples       500824                      
97411201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist::mean      4.015684                      
97511201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist::gmean     1.504004                      
97611201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist::stdev    10.245462                      
97711201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist        |      500634     99.96%     99.96% |         144      0.03%     99.99% |          19      0.00%     99.99% |          11      0.00%    100.00% |           9      0.00%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
97811201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist::total       500824                      
97910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::bucket_size            1                      
98010013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::max_bucket            9                      
98111201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.hit_latency_hist::samples       434823                      
98211026Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::mean            1                      
98311026Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::gmean            1                      
98411201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |      434823    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
98511201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.hit_latency_hist::total       434823                      
98610526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::bucket_size          128                      
98710526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::max_bucket         1279                      
98811201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist::samples        66001                      
98911201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist::mean    23.883396                      
99011201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist::gmean    22.130353                      
99111201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist::stdev    18.490127                      
99211201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist   |       65811     99.71%     99.71% |         144      0.22%     99.93% |          19      0.03%     99.96% |          11      0.02%     99.98% |           9      0.01%     99.99% |           7      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
99311201Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist::total        66001                      
99411201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::bucket_size           64                      
99511201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::max_bucket          639                      
99611201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::samples       340189                      
99711201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::mean     3.322441                      
99811201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::gmean     1.405056                      
99911201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::stdev     8.375867                      
100011201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist |      339841     99.90%     99.90% |          90      0.03%     99.92% |         233      0.07%     99.99% |           1      0.00%     99.99% |           4      0.00%     99.99% |           8      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           1      0.00%    100.00% |           5      0.00%    100.00%
100111201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::total       340189                      
100210013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size            1                      
100310013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket            9                      
100411201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.hit_latency_hist::samples       301867                      
100511026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::mean            1                      
100611026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::gmean            1                      
100711201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |      301867    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
100811201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.hit_latency_hist::total       301867                      
100911201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size           64                      
101011201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket          639                      
101111201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::samples        38322                      
101211201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::mean    21.616591                      
101311201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::gmean    20.468877                      
101411201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::stdev    15.672180                      
101511201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist |       37974     99.09%     99.09% |          90      0.23%     99.33% |         233      0.61%     99.93% |           1      0.00%     99.94% |           4      0.01%     99.95% |           8      0.02%     99.97% |           5      0.01%     99.98% |           1      0.00%     99.98% |           1      0.00%     99.99% |           5      0.01%    100.00%
101611201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::total        38322                      
101710013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::bucket_size            1                      
101810013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::max_bucket            9                      
101911201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.latency_hist::samples       340189                      
102011026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::mean            1                      
102111026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::gmean            1                      
102211201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |      340189    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
102311201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.latency_hist::total       340189                      
102410013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size            1                      
102510013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket            9                      
102611201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.hit_latency_hist::samples       340189                      
102711026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::mean            1                      
102811026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::gmean            1                      
102911201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |      340189    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
103011201Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.hit_latency_hist::total       340189                      
103111201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Fetch         181234      0.00%      0.00%
103211201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Data          103288      0.00%      0.00%
103311201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Data       181708      0.00%      0.00%
103411201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Ack       147284      0.00%      0.00%
103511201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.DMA_READ          819      0.00%      0.00%
103610560Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.DMA_WRITE        46736      0.00%      0.00%
103711201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.CleanReplacement        13460      0.00%      0.00%
103811201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.I.Fetch       181234      0.00%      0.00%
103911201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.I.DMA_READ          474      0.00%      0.00%
104011201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.I.DMA_WRITE        43996      0.00%      0.00%
104111201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.ID.Memory_Data          474      0.00%      0.00%
104211201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.ID_W.Memory_Ack        43996      0.00%      0.00%
104311201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.Data        100203      0.00%      0.00%
104411201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.DMA_READ          345      0.00%      0.00%
104511201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.DMA_WRITE         2740      0.00%      0.00%
104611201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.CleanReplacement        13460      0.00%      0.00%
104711201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.IM.Memory_Data       181234      0.00%      0.00%
104811201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.MI.Memory_Ack       100203      0.00%      0.00%
104911201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M_DRD.Data          345      0.00%      0.00%
105011201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M_DRDI.Memory_Ack          345      0.00%      0.00%
105111201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M_DWR.Data         2740      0.00%      0.00%
105211201Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M_DWRI.Memory_Ack         2740      0.00%      0.00%
105311201Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.ReadRequest   |         819    100.00%    100.00% |           0      0.00%    100.00%
105411201Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.ReadRequest::total          819                      
105510560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.WriteRequest  |       46736    100.00%    100.00% |           0      0.00%    100.00%
105610560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.WriteRequest::total        46736                      
105711201Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Data          |         819    100.00%    100.00% |           0      0.00%    100.00%
105811201Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Data::total            819                      
105910560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Ack           |       46736    100.00%    100.00% |           0      0.00%    100.00%
106010560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Ack::total           46736                      
106111201Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.ReadRequest |         819    100.00%    100.00% |           0      0.00%    100.00%
106211201Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.ReadRequest::total          819                      
106310560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.WriteRequest |       46736    100.00%    100.00% |           0      0.00%    100.00%
106410560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.WriteRequest::total        46736                      
106511201Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_RD.Data  |         819    100.00%    100.00% |           0      0.00%    100.00%
106611201Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_RD.Data::total          819                      
106710560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_WR.Ack   |       46736    100.00%    100.00% |           0      0.00%    100.00%
106810560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_WR.Ack::total        46736                      
106911201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Load      |    10196157     66.07%     66.07% |     5235889     33.93%    100.00%
107011201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Load::total     15432046                      
107111201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ifetch    |   115008649     66.97%     66.97% |    56720132     33.03%    100.00%
107211201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ifetch::total    171728781                      
107311201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Store     |     7399204     68.55%     68.55% |     3394987     31.45%    100.00%
107411201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Store::total     10794191                      
107511201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Inv       |       18502     52.28%     52.28% |       16889     47.72%    100.00%
107611201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Inv::total        35391                      
107711201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.L1_Replacement |     1730094     65.23%     65.23% |      922339     34.77%    100.00%
107811201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.L1_Replacement::total      2652433                      
107911201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Fwd_GETX  |       12336     51.16%     51.16% |       11775     48.84%    100.00%
108011201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Fwd_GETX::total        24111                      
108111201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Fwd_GETS  |       14659     53.34%     53.34% |       12823     46.66%    100.00%
108211201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Fwd_GETS::total        27482                      
108310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
108410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR::total            4                      
108511201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data      |         528     32.39%     32.39% |        1102     67.61%    100.00%
108611201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data::total         1630                      
108711201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data_Exclusive |      840504     62.87%     62.87% |      496438     37.13%    100.00%
108811201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data_Exclusive::total      1336942                      
108911201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.DataS_fromL1 |       12823     46.65%     46.65% |       14663     53.35%    100.00%
109011201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.DataS_fromL1::total        27486                      
109111201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data_all_Acks |      893218     67.59%     67.59% |      428349     32.41%    100.00%
109211201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data_all_Acks::total      1321567                      
109311201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ack       |       12681     52.16%     52.16% |       11631     47.84%    100.00%
109411201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ack::total        24312                      
109511201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ack_all   |       13209     50.92%     50.92% |       12733     49.08%    100.00%
109611201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ack_all::total        25942                      
109711201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.WB_Ack    |     1129907     64.87%     64.87% |      611895     35.13%    100.00%
109811201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.WB_Ack::total      1741802                      
109911201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Load   |      881473     62.40%     62.40% |      531116     37.60%    100.00%
110011201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Load::total      1412589                      
110111201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Ifetch |      550888     67.18%     67.18% |      269077     32.82%    100.00%
110211201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Ifetch::total       819965                      
110311201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Store  |      298756     70.81%     70.81% |      123170     29.19%    100.00%
110411201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Store::total       421926                      
110511201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Inv    |        5771     62.78%     62.78% |        3422     37.22%    100.00%
110611201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Inv::total         9193                      
110711201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Load    |       10081     47.61%     47.61% |       11092     52.39%    100.00%
110811201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Load::total        21173                      
110911201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Ifetch  |         163     53.62%     53.62% |         141     46.38%    100.00%
111011201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Ifetch::total          304                      
111111201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Store   |        5712     48.96%     48.96% |        5955     51.04%    100.00%
111211201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Store::total        11667                      
111311201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.L1_Replacement |        9111     53.32%     53.32% |        7975     46.68%    100.00%
111411201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.L1_Replacement::total        17086                      
111511201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Load    |      850617     63.10%     63.10% |      497429     36.90%    100.00%
111611201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Load::total      1348046                      
111711201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Ifetch  |   114457594     66.97%     66.97% |    56450913     33.03%    100.00%
111811201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Ifetch::total    170908507                      
111911201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Store   |       12681     52.16%     52.16% |       11632     47.84%    100.00%
112011201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Store::total        24313                      
112111201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Inv     |       12466     48.73%     48.73% |       13117     51.27%    100.00%
112211201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Inv::total        25583                      
112311201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.L1_Replacement |      591076     66.15%     66.15% |      302469     33.85%    100.00%
112411201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.L1_Replacement::total       893545                      
112511201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Load    |     2398204     64.14%     64.14% |     1340570     35.86%    100.00%
112611201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Load::total      3738774                      
112711201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Store   |      120081     73.14%     73.14% |       44106     26.86%    100.00%
112811201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Store::total       164187                      
112911201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Inv     |          72     60.00%     60.00% |          48     40.00%    100.00%
113011201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Inv::total          120                      
113111201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.L1_Replacement |      718896     61.46%     61.46% |      450874     38.54%    100.00%
113211201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.L1_Replacement::total      1169770                      
113311201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Fwd_GETX |         233     64.01%     64.01% |         131     35.99%    100.00%
113411201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Fwd_GETX::total          364                      
113511201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Fwd_GETS |        1000     46.06%     46.06% |        1171     53.94%    100.00%
113611201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Fwd_GETS::total         2171                      
113711201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Load    |     6055782     67.95%     67.95% |     2855682     32.05%    100.00%
113811201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Load::total      8911464                      
113911201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Store   |     6961974     68.44%     68.44% |     3210124     31.56%    100.00%
114011201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Store::total     10172098                      
114111201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Inv     |         193     39.07%     39.07% |         301     60.93%    100.00%
114211201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Inv::total          494                      
114311201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.L1_Replacement |      411011     71.85%     71.85% |      161021     28.15%    100.00%
114411201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.L1_Replacement::total       572032                      
114511201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Fwd_GETX |       12103     50.97%     50.97% |       11644     49.03%    100.00%
114611201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Fwd_GETX::total        23747                      
114711201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Fwd_GETS |       13659     53.96%     53.96% |       11652     46.04%    100.00%
114811201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Fwd_GETS::total        25311                      
114910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
115010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total            4                      
115111201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.Data_Exclusive |      840504     62.87%     62.87% |      496438     37.13%    100.00%
115211201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1336942                      
115311201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.DataS_fromL1 |       12823     46.65%     46.65% |       14663     53.35%    100.00%
115411201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.DataS_fromL1::total        27486                      
115511201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.Data_all_Acks |      589278     66.24%     66.24% |      300325     33.76%    100.00%
115611201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.Data_all_Acks::total       889603                      
115711201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IM.Data   |         528     32.39%     32.39% |        1102     67.61%    100.00%
115811201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IM.Data::total         1630                      
115911201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IM.Data_all_Acks |      303940     70.36%     70.36% |      128024     29.64%    100.00%
116011201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IM.Data_all_Acks::total       431964                      
116111201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.SM.Inv    |           0      0.00%      0.00% |           1    100.00%    100.00%
116211201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.SM.Inv::total            1                      
116311201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.SM.Ack    |       12681     52.16%     52.16% |       11631     47.84%    100.00%
116411201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.SM.Ack::total        24312                      
116511201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.SM.Ack_all |       13209     50.92%     50.92% |       12733     49.08%    100.00%
116611201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.SM.Ack_all::total        25942                      
116711201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M_I.Ifetch |           4     80.00%     80.00% |           1     20.00%    100.00%
116811026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.Ifetch::total            5                      
116911201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M_I.WB_Ack |     1129907     64.87%     64.87% |      611895     35.13%    100.00%
117011201Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M_I.WB_Ack::total      1741802                      
117111201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L1_GET_INSTR       820269      0.00%      0.00%
117211201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L1_GETS        1434154      0.00%      0.00%
117311201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L1_GETX         433597      0.00%      0.00%
117411201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L1_UPGRADE        24313      0.00%      0.00%
117511201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L1_PUTX        1741802      0.00%      0.00%
117611201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L2_Replacement       100151      0.00%      0.00%
117711201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L2_Replacement_clean        13512      0.00%      0.00%
117811201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Mem_Data        181234      0.00%      0.00%
117911201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Mem_Ack         116748      0.00%      0.00%
118011201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.WB_Data          25809      0.00%      0.00%
118111201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.WB_Data_clean         2171      0.00%      0.00%
118211201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Ack               1865      0.00%      0.00%
118311201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Ack_all           7090      0.00%      0.00%
118411201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Unblock          27486      0.00%      0.00%
118511201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Exclusive_Unblock      1794848      0.00%      0.00%
118611201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MEM_Inv           6170      0.00%      0.00%
118711201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.NP.L1_GET_INSTR        15428      0.00%      0.00%
118811201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.NP.L1_GETS        32321      0.00%      0.00%
118911201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.NP.L1_GETX       133485      0.00%      0.00%
119011201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L1_GET_INSTR       804811      0.00%      0.00%
119111201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L1_GETS        69338      0.00%      0.00%
119211201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L1_GETX         1923      0.00%      0.00%
119311201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L1_UPGRADE        24312      0.00%      0.00%
119411201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L2_Replacement          291      0.00%      0.00%
119511201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L2_Replacement_clean         6674      0.00%      0.00%
119611201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.MEM_Inv            5      0.00%      0.00%
119711201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L1_GET_INSTR           26      0.00%      0.00%
119811201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L1_GETS      1304621      0.00%      0.00%
119911201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L1_GETX       274075      0.00%      0.00%
120011201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L2_Replacement        99609      0.00%      0.00%
120111201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L2_Replacement_clean         6704      0.00%      0.00%
120211201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.MEM_Inv         2851      0.00%      0.00%
120310013Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GET_INSTR            4      0.00%      0.00%
120411201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.L1_GETS        27482      0.00%      0.00%
120511201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.L1_GETX        24111      0.00%      0.00%
120611201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.L1_PUTX      1741802      0.00%      0.00%
120711201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.L2_Replacement          251      0.00%      0.00%
120811201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.L2_Replacement_clean          134      0.00%      0.00%
120911201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.MEM_Inv          229      0.00%      0.00%
121011201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M_I.Mem_Ack       116748      0.00%      0.00%
121111201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M_I.MEM_Inv         2851      0.00%      0.00%
121211201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_I.WB_Data          442      0.00%      0.00%
121311201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_I.Ack_all           38      0.00%      0.00%
121411201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_I.MEM_Inv          229      0.00%      0.00%
121511201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MCT_I.WB_Data           52      0.00%      0.00%
121611201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MCT_I.Ack_all           82      0.00%      0.00%
121711201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.I_I.Ack           1570      0.00%      0.00%
121811201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.I_I.Ack_all         6674      0.00%      0.00%
121911201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.S_I.Ack            295      0.00%      0.00%
122011201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.S_I.Ack_all          296      0.00%      0.00%
122111201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.S_I.MEM_Inv            5      0.00%      0.00%
122211201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.ISS.Mem_Data        32321      0.00%      0.00%
122311201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.IS.Mem_Data        15428      0.00%      0.00%
122411201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.IM.Mem_Data       133485      0.00%      0.00%
122511201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS_MB.L1_GETS          235      0.00%      0.00%
122611201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS_MB.L1_GETX            1      0.00%      0.00%
122711201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE            1      0.00%      0.00%
122811201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        26235      0.00%      0.00%
122911201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_MB.L1_GETS          157      0.00%      0.00%
123011201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_MB.L1_GETX            2      0.00%      0.00%
123111201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1768613      0.00%      0.00%
123211201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_IIB.WB_Data        25310      0.00%      0.00%
123311201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2170      0.00%      0.00%
123411201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_IIB.Unblock            6      0.00%      0.00%
123511201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_IB.WB_Data            5      0.00%      0.00%
123611201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_IB.WB_Data_clean            1      0.00%      0.00%
123711201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_SB.Unblock        27480      0.00%      0.00%
12388968SN/A
12398968SN/A---------- End Simulation Statistics   ----------
1240