stats.txt revision 11026
18968SN/A
28968SN/A---------- Begin Simulation Statistics ----------
311026Snilay@cs.wisc.edusim_seconds                                  5.224199                       # Number of seconds simulated
411026Snilay@cs.wisc.edusim_ticks                                5224199387500                       # Number of ticks simulated
511026Snilay@cs.wisc.edufinal_tick                               5224199387500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68968SN/Asim_freq                                 1000000000000                       # Frequency of simulated ticks
711026Snilay@cs.wisc.eduhost_inst_rate                                 181246                       # Simulator instruction rate (inst/s)
811026Snilay@cs.wisc.eduhost_op_rate                                   351982                       # Simulator op (including micro ops) rate (op/s)
911026Snilay@cs.wisc.eduhost_tick_rate                             6214161959                       # Simulator tick rate (ticks/s)
1011026Snilay@cs.wisc.eduhost_mem_usage                                1108196                       # Number of bytes of host memory used
1111026Snilay@cs.wisc.eduhost_seconds                                   840.69                       # Real time elapsed on the host
1211026Snilay@cs.wisc.edusim_insts                                   152372487                       # Number of instructions simulated
1311026Snilay@cs.wisc.edusim_ops                                     295908921                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                          1000                       # Clock period in ticks
1611026Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::ruby.dir_cntrl0     11634048                       # Number of bytes read from this memory
1711026Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::total           11634048                       # Number of bytes read from this memory
1811026Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::ruby.dir_cntrl0      9365120                       # Number of bytes written to this memory
1911026Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::total         9365120                       # Number of bytes written to this memory
2011026Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::ruby.dir_cntrl0       181782                       # Number of read requests responded to by this memory
2111026Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::total              181782                       # Number of read requests responded to by this memory
2211026Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::ruby.dir_cntrl0       146330                       # Number of write requests responded to by this memory
2311026Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::total             146330                       # Number of write requests responded to by this memory
2411026Snilay@cs.wisc.edusystem.mem_ctrls.bw_read::ruby.dir_cntrl0      2226953                       # Total read bandwidth from this memory (bytes/s)
2511026Snilay@cs.wisc.edusystem.mem_ctrls.bw_read::total               2226953                       # Total read bandwidth from this memory (bytes/s)
2611026Snilay@cs.wisc.edusystem.mem_ctrls.bw_write::ruby.dir_cntrl0      1792642                       # Write bandwidth from this memory (bytes/s)
2711026Snilay@cs.wisc.edusystem.mem_ctrls.bw_write::total              1792642                       # Write bandwidth from this memory (bytes/s)
2811026Snilay@cs.wisc.edusystem.mem_ctrls.bw_total::ruby.dir_cntrl0      4019595                       # Total bandwidth to/from this memory (bytes/s)
2911026Snilay@cs.wisc.edusystem.mem_ctrls.bw_total::total              4019595                       # Total bandwidth to/from this memory (bytes/s)
3011026Snilay@cs.wisc.edusystem.mem_ctrls.readReqs                      181782                       # Number of read requests accepted
3111026Snilay@cs.wisc.edusystem.mem_ctrls.writeReqs                     146330                       # Number of write requests accepted
3211026Snilay@cs.wisc.edusystem.mem_ctrls.readBursts                    181782                       # Number of DRAM read bursts, including those serviced by the write queue
3311026Snilay@cs.wisc.edusystem.mem_ctrls.writeBursts                   146330                       # Number of DRAM write bursts, including those merged in the write queue
3411026Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadDRAM               11603776                       # Total number of bytes read from DRAM
3511026Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadWrQ                   30272                       # Total number of bytes read from write queue
3611026Snilay@cs.wisc.edusystem.mem_ctrls.bytesWritten                 9361152                       # Total number of bytes written to DRAM
3711026Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadSys                11634048                       # Total read bytes from the system interface side
3811026Snilay@cs.wisc.edusystem.mem_ctrls.bytesWrittenSys              9365120                       # Total written bytes from the system interface side
3911026Snilay@cs.wisc.edusystem.mem_ctrls.servicedByWrQ                    473                       # Number of DRAM read bursts serviced by the write queue
4011026Snilay@cs.wisc.edusystem.mem_ctrls.mergedWrBursts                    34                       # Number of DRAM write bursts merged with an existing one
4110526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
4211026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::0             11150                       # Per bank write bursts
4311026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::1             11614                       # Per bank write bursts
4411026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::2             11088                       # Per bank write bursts
4511026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::3             11198                       # Per bank write bursts
4611026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::4             11307                       # Per bank write bursts
4711026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::5             11653                       # Per bank write bursts
4811026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::6             10979                       # Per bank write bursts
4911026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::7             10504                       # Per bank write bursts
5011026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::8             11290                       # Per bank write bursts
5111026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::9             11823                       # Per bank write bursts
5211026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::10            12275                       # Per bank write bursts
5311026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::11            12209                       # Per bank write bursts
5411026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::12            11037                       # Per bank write bursts
5511026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::13            10843                       # Per bank write bursts
5611026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::14            11600                       # Per bank write bursts
5711026Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::15            10739                       # Per bank write bursts
5811026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::0              9147                       # Per bank write bursts
5911026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::1              9195                       # Per bank write bursts
6011026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::2              8950                       # Per bank write bursts
6111026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::3              9212                       # Per bank write bursts
6211026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::4              9068                       # Per bank write bursts
6311026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::5              9215                       # Per bank write bursts
6411026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::6              8804                       # Per bank write bursts
6511026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::7              8265                       # Per bank write bursts
6611026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::8              8949                       # Per bank write bursts
6711026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::9              9397                       # Per bank write bursts
6811026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::10             9286                       # Per bank write bursts
6911026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::11             9574                       # Per bank write bursts
7011026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::12             9238                       # Per bank write bursts
7111026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::13             9086                       # Per bank write bursts
7211026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::14             9706                       # Per bank write bursts
7311026Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::15             9176                       # Per bank write bursts
7410526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
7510526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
7611026Snilay@cs.wisc.edusystem.mem_ctrls.totGap                  5224199278000                       # Total gap between requests
7710526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
8311026Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::6                181782                       # Read request sizes (log2)
8410526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
9011026Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::6               146330                       # Write request sizes (log2)
9111026Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::0                  181171                       # What read queue length does an incoming req see
9211026Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::1                     138                       # What read queue length does an incoming req see
9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
12310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
13811026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::15                   2037                       # What write queue length does an incoming req see
13911026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::16                   2815                       # What write queue length does an incoming req see
14011026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::17                   8710                       # What write queue length does an incoming req see
14111026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::18                   9309                       # What write queue length does an incoming req see
14211026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::19                   8795                       # What write queue length does an incoming req see
14311026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::20                   9425                       # What write queue length does an incoming req see
14411026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::21                   9408                       # What write queue length does an incoming req see
14511026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::22                   8642                       # What write queue length does an incoming req see
14611026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::23                   9288                       # What write queue length does an incoming req see
14711026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::24                   9277                       # What write queue length does an incoming req see
14811026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::25                   8685                       # What write queue length does an incoming req see
14911026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::26                   8775                       # What write queue length does an incoming req see
15011026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::27                   8579                       # What write queue length does an incoming req see
15111026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::28                   8665                       # What write queue length does an incoming req see
15211026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::29                   8282                       # What write queue length does an incoming req see
15311026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::30                   8324                       # What write queue length does an incoming req see
15411026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::31                   8396                       # What write queue length does an incoming req see
15511026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::32                   8193                       # What write queue length does an incoming req see
15611026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::33                    125                       # What write queue length does an incoming req see
15711026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::34                    100                       # What write queue length does an incoming req see
15811026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35                     86                       # What write queue length does an incoming req see
15911026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::36                     80                       # What write queue length does an incoming req see
16010892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::37                     64                       # What write queue length does an incoming req see
16111026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::38                     62                       # What write queue length does an incoming req see
16211026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::39                     53                       # What write queue length does an incoming req see
16311026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::40                     34                       # What write queue length does an incoming req see
16411026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::41                     27                       # What write queue length does an incoming req see
16511026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::42                     24                       # What write queue length does an incoming req see
16611026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::43                     13                       # What write queue length does an incoming req see
16711026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::44                      7                       # What write queue length does an incoming req see
16811026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::45                      1                       # What write queue length does an incoming req see
16911026Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
17010892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
18711026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::samples        59255                       # Bytes accessed per row activation
18811026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::mean    353.807510                       # Bytes accessed per row activation
18911026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::gmean   209.383376                       # Bytes accessed per row activation
19011026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::stdev   350.503043                       # Bytes accessed per row activation
19111026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::0-127        19159     32.33%     32.33% # Bytes accessed per row activation
19211026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::128-255        13849     23.37%     55.71% # Bytes accessed per row activation
19311026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::256-383         6106     10.30%     66.01% # Bytes accessed per row activation
19411026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::384-511         3747      6.32%     72.33% # Bytes accessed per row activation
19511026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::512-639         2604      4.39%     76.73% # Bytes accessed per row activation
19611026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::640-767         1953      3.30%     80.02% # Bytes accessed per row activation
19711026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::768-895         1628      2.75%     82.77% # Bytes accessed per row activation
19811026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::896-1023         1375      2.32%     85.09% # Bytes accessed per row activation
19911026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::1024-1151         8834     14.91%    100.00% # Bytes accessed per row activation
20011026Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::total        59255                       # Bytes accessed per row activation
20111026Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::samples         8155                       # Reads before turning the bus around for writes
20211026Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::mean      22.229552                       # Reads before turning the bus around for writes
20311026Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::stdev    312.599698                       # Reads before turning the bus around for writes
20411026Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::0-1023         8149     99.93%     99.93% # Reads before turning the bus around for writes
20510892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::1024-2047            3      0.04%     99.96% # Reads before turning the bus around for writes
20611026Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
20710526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::10240-11263            1      0.01%     99.99% # Reads before turning the bus around for writes
20810526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
20911026Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::total          8155                       # Reads before turning the bus around for writes
21011026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::samples         8155                       # Writes before turning the bus around for reads
21111026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::mean      17.935990                       # Writes before turning the bus around for reads
21211026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::gmean     17.612159                       # Writes before turning the bus around for reads
21311026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::stdev      3.859511                       # Writes before turning the bus around for reads
21411026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::16             6056     74.26%     74.26% # Writes before turning the bus around for reads
21511026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::17               22      0.27%     74.53% # Writes before turning the bus around for reads
21611026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::18              156      1.91%     76.44% # Writes before turning the bus around for reads
21711026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::19               23      0.28%     76.73% # Writes before turning the bus around for reads
21811026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::20               50      0.61%     77.34% # Writes before turning the bus around for reads
21911026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::21              492      6.03%     83.37% # Writes before turning the bus around for reads
22011026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::22              184      2.26%     85.63% # Writes before turning the bus around for reads
22111026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::23               46      0.56%     86.19% # Writes before turning the bus around for reads
22211026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::24              633      7.76%     93.95% # Writes before turning the bus around for reads
22311026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::25              108      1.32%     95.28% # Writes before turning the bus around for reads
22411026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::26                7      0.09%     95.36% # Writes before turning the bus around for reads
22511026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::27               19      0.23%     95.60% # Writes before turning the bus around for reads
22611026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::28              284      3.48%     99.08% # Writes before turning the bus around for reads
22711026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::29                8      0.10%     99.18% # Writes before turning the bus around for reads
22811026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::30                7      0.09%     99.26% # Writes before turning the bus around for reads
22911026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::31                5      0.06%     99.33% # Writes before turning the bus around for reads
23011026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::32                5      0.06%     99.39% # Writes before turning the bus around for reads
23111026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::33                5      0.06%     99.45% # Writes before turning the bus around for reads
23211026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::34                1      0.01%     99.46% # Writes before turning the bus around for reads
23311026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::35                1      0.01%     99.47% # Writes before turning the bus around for reads
23411026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::36                5      0.06%     99.53% # Writes before turning the bus around for reads
23511026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::37                4      0.05%     99.58% # Writes before turning the bus around for reads
23611026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::38                3      0.04%     99.62% # Writes before turning the bus around for reads
23711026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::39                6      0.07%     99.69% # Writes before turning the bus around for reads
23811026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::40                4      0.05%     99.74% # Writes before turning the bus around for reads
23911026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::41                3      0.04%     99.78% # Writes before turning the bus around for reads
24011026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::43                3      0.04%     99.82% # Writes before turning the bus around for reads
24111026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::44                5      0.06%     99.88% # Writes before turning the bus around for reads
24211026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::45                2      0.02%     99.90% # Writes before turning the bus around for reads
24311026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::46                3      0.04%     99.94% # Writes before turning the bus around for reads
24411026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::48                2      0.02%     99.96% # Writes before turning the bus around for reads
24511026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::51                3      0.04%    100.00% # Writes before turning the bus around for reads
24611026Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::total          8155                       # Writes before turning the bus around for reads
24711026Snilay@cs.wisc.edusystem.mem_ctrls.totQLat                   1909551997                       # Total ticks spent queuing
24811026Snilay@cs.wisc.edusystem.mem_ctrls.totMemAccLat              5309095747                       # Total ticks spent from burst creation until serviced by the DRAM
24911026Snilay@cs.wisc.edusystem.mem_ctrls.totBusLat                  906545000                       # Total ticks spent in databus transfers
25011026Snilay@cs.wisc.edusystem.mem_ctrls.avgQLat                     10532.03                       # Average queueing delay per DRAM burst
25110526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
25211026Snilay@cs.wisc.edusystem.mem_ctrls.avgMemAccLat                29282.03                       # Average memory access latency per DRAM burst
25311026Snilay@cs.wisc.edusystem.mem_ctrls.avgRdBW                         2.22                       # Average DRAM read bandwidth in MiByte/s
25411026Snilay@cs.wisc.edusystem.mem_ctrls.avgWrBW                         1.79                       # Average achieved write bandwidth in MiByte/s
25511026Snilay@cs.wisc.edusystem.mem_ctrls.avgRdBWSys                      2.23                       # Average system read bandwidth in MiByte/s
25611026Snilay@cs.wisc.edusystem.mem_ctrls.avgWrBWSys                      1.79                       # Average system write bandwidth in MiByte/s
25710526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
25810526Snilay@cs.wisc.edusystem.mem_ctrls.busUtil                         0.03                       # Data bus utilization in percentage
25910526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilRead                     0.02                       # Data bus utilization in percentage for reads
26010526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilWrite                    0.01                       # Data bus utilization in percentage for writes
26110526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
26211026Snilay@cs.wisc.edusystem.mem_ctrls.avgWrQLen                      24.22                       # Average write queue length when enqueuing
26311026Snilay@cs.wisc.edusystem.mem_ctrls.readRowHits                   147266                       # Number of row buffer hits during reads
26411026Snilay@cs.wisc.edusystem.mem_ctrls.writeRowHits                  121055                       # Number of row buffer hits during writes
26511026Snilay@cs.wisc.edusystem.mem_ctrls.readRowHitRate                 81.22                       # Row buffer hit rate for reads
26611026Snilay@cs.wisc.edusystem.mem_ctrls.writeRowHitRate                82.75                       # Row buffer hit rate for writes
26711026Snilay@cs.wisc.edusystem.mem_ctrls.avgGap                   15922000.04                       # Average gap between requests
26811026Snilay@cs.wisc.edusystem.mem_ctrls.pageHitRate                    81.90                       # Row buffer hit rate, read and write combined
26911026Snilay@cs.wisc.edusystem.mem_ctrls_0.actEnergy                216465480                       # Energy for activate commands per rank (pJ)
27011026Snilay@cs.wisc.edusystem.mem_ctrls_0.preEnergy                118111125                       # Energy for precharge commands per rank (pJ)
27111026Snilay@cs.wisc.edusystem.mem_ctrls_0.readEnergy               698037600                       # Energy for read commands per rank (pJ)
27211026Snilay@cs.wisc.edusystem.mem_ctrls_0.writeEnergy              465626880                       # Energy for write commands per rank (pJ)
27311026Snilay@cs.wisc.edusystem.mem_ctrls_0.refreshEnergy         341218840560                       # Energy for refresh commands per rank (pJ)
27411026Snilay@cs.wisc.edusystem.mem_ctrls_0.actBackEnergy         139333087125                       # Energy for active background per rank (pJ)
27511026Snilay@cs.wisc.edusystem.mem_ctrls_0.preBackEnergy         3012293484000                       # Energy for precharge background per rank (pJ)
27611026Snilay@cs.wisc.edusystem.mem_ctrls_0.totalEnergy           3494343652770                       # Total energy per rank (pJ)
27711026Snilay@cs.wisc.edusystem.mem_ctrls_0.averagePower            668.877279                       # Core power per rank (mW)
27811026Snilay@cs.wisc.edusystem.mem_ctrls_0.memoryStateTime::IDLE 5011116201500                       # Time in different power states
27911026Snilay@cs.wisc.edusystem.mem_ctrls_0.memoryStateTime::REF  174447260000                       # Time in different power states
28010628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
28111026Snilay@cs.wisc.edusystem.mem_ctrls_0.memoryStateTime::ACT   38635825500                       # Time in different power states
28210628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
28311026Snilay@cs.wisc.edusystem.mem_ctrls_1.actEnergy                231502320                       # Energy for activate commands per rank (pJ)
28411026Snilay@cs.wisc.edusystem.mem_ctrls_1.preEnergy                126315750                       # Energy for precharge commands per rank (pJ)
28511026Snilay@cs.wisc.edusystem.mem_ctrls_1.readEnergy               716164800                       # Energy for read commands per rank (pJ)
28611026Snilay@cs.wisc.edusystem.mem_ctrls_1.writeEnergy              482189760                       # Energy for write commands per rank (pJ)
28711026Snilay@cs.wisc.edusystem.mem_ctrls_1.refreshEnergy         341218840560                       # Energy for refresh commands per rank (pJ)
28811026Snilay@cs.wisc.edusystem.mem_ctrls_1.actBackEnergy         140605884585                       # Energy for active background per rank (pJ)
28911026Snilay@cs.wisc.edusystem.mem_ctrls_1.preBackEnergy         3011176995000                       # Energy for precharge background per rank (pJ)
29011026Snilay@cs.wisc.edusystem.mem_ctrls_1.totalEnergy           3494557892775                       # Total energy per rank (pJ)
29111026Snilay@cs.wisc.edusystem.mem_ctrls_1.averagePower            668.918288                       # Core power per rank (mW)
29211026Snilay@cs.wisc.edusystem.mem_ctrls_1.memoryStateTime::IDLE 5009239707000                       # Time in different power states
29311026Snilay@cs.wisc.edusystem.mem_ctrls_1.memoryStateTime::REF  174447260000                       # Time in different power states
29410628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
29511026Snilay@cs.wisc.edusystem.mem_ctrls_1.memoryStateTime::ACT   40505530500                       # Time in different power states
29610628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
29710315Snilay@cs.wisc.edusystem.cpu_clk_domain.clock                       500                       # Clock period in ticks
29810036SAli.Saidi@ARM.comsystem.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
29911026Snilay@cs.wisc.edusystem.cpu0.numCycles                     10448398775                       # number of cpu cycles simulated
3008968SN/Asystem.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
3018968SN/Asystem.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
30211026Snilay@cs.wisc.edusystem.cpu0.committedInsts                  134854206                       # Number of instructions committed
30311026Snilay@cs.wisc.edusystem.cpu0.committedOps                    263157336                       # Number of ops (including micro ops) committed
30411026Snilay@cs.wisc.edusystem.cpu0.num_int_alu_accesses            244684041                       # Number of integer alu accesses
30510645Snilay@cs.wisc.edusystem.cpu0.num_fp_alu_accesses                    48                       # Number of float alu accesses
30611026Snilay@cs.wisc.edusystem.cpu0.num_func_calls                    2136969                       # number of times a function call or return occured
30711026Snilay@cs.wisc.edusystem.cpu0.num_conditional_control_insts     24844681                       # number of instructions that are conditional controls
30811026Snilay@cs.wisc.edusystem.cpu0.num_int_insts                   244684041                       # number of integer instructions
30910645Snilay@cs.wisc.edusystem.cpu0.num_fp_insts                           48                       # number of float instructions
31011026Snilay@cs.wisc.edusystem.cpu0.num_int_register_reads          453367941                       # number of times the integer registers were read
31111026Snilay@cs.wisc.edusystem.cpu0.num_int_register_writes         210194907                       # number of times the integer registers were written
31210645Snilay@cs.wisc.edusystem.cpu0.num_fp_register_reads                  48                       # number of times the floating registers were read
3138968SN/Asystem.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
31411026Snilay@cs.wisc.edusystem.cpu0.num_cc_register_reads           140919836                       # number of times the CC registers were read
31511026Snilay@cs.wisc.edusystem.cpu0.num_cc_register_writes          102049817                       # number of times the CC registers were written
31611026Snilay@cs.wisc.edusystem.cpu0.num_mem_refs                     20320896                       # number of memory refs
31711026Snilay@cs.wisc.edusystem.cpu0.num_load_insts                   13137087                       # Number of load instructions
31811026Snilay@cs.wisc.edusystem.cpu0.num_store_insts                   7183809                       # Number of store instructions
31911026Snilay@cs.wisc.edusystem.cpu0.num_idle_cycles              9867676778.078112                       # Number of idle cycles
32011026Snilay@cs.wisc.edusystem.cpu0.num_busy_cycles              580721996.921889                       # Number of busy cycles
32111026Snilay@cs.wisc.edusystem.cpu0.not_idle_fraction                0.055580                       # Percentage of non-idle cycles
32211026Snilay@cs.wisc.edusystem.cpu0.idle_fraction                    0.944420                       # Percentage of idle cycles
32311026Snilay@cs.wisc.edusystem.cpu0.Branches                         27711250                       # Number of branches fetched
32411026Snilay@cs.wisc.edusystem.cpu0.op_class::No_OpClass               205485      0.08%      0.08% # Class of executed instruction
32511026Snilay@cs.wisc.edusystem.cpu0.op_class::IntAlu                242421466     92.12%     92.20% # Class of executed instruction
32611026Snilay@cs.wisc.edusystem.cpu0.op_class::IntMult                  122075      0.05%     92.24% # Class of executed instruction
32711026Snilay@cs.wisc.edusystem.cpu0.op_class::IntDiv                    93292      0.04%     92.28% # Class of executed instruction
32811026Snilay@cs.wisc.edusystem.cpu0.op_class::FloatAdd                      0      0.00%     92.28% # Class of executed instruction
32911026Snilay@cs.wisc.edusystem.cpu0.op_class::FloatCmp                      0      0.00%     92.28% # Class of executed instruction
33011026Snilay@cs.wisc.edusystem.cpu0.op_class::FloatCvt                     16      0.00%     92.28% # Class of executed instruction
33111026Snilay@cs.wisc.edusystem.cpu0.op_class::FloatMult                     0      0.00%     92.28% # Class of executed instruction
33211026Snilay@cs.wisc.edusystem.cpu0.op_class::FloatDiv                      0      0.00%     92.28% # Class of executed instruction
33311026Snilay@cs.wisc.edusystem.cpu0.op_class::FloatSqrt                     0      0.00%     92.28% # Class of executed instruction
33411026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdAdd                       0      0.00%     92.28% # Class of executed instruction
33511026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdAddAcc                    0      0.00%     92.28% # Class of executed instruction
33611026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdAlu                       0      0.00%     92.28% # Class of executed instruction
33711026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdCmp                       0      0.00%     92.28% # Class of executed instruction
33811026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdCvt                       0      0.00%     92.28% # Class of executed instruction
33911026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdMisc                      0      0.00%     92.28% # Class of executed instruction
34011026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdMult                      0      0.00%     92.28% # Class of executed instruction
34111026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdMultAcc                   0      0.00%     92.28% # Class of executed instruction
34211026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdShift                     0      0.00%     92.28% # Class of executed instruction
34311026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdShiftAcc                  0      0.00%     92.28% # Class of executed instruction
34411026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdSqrt                      0      0.00%     92.28% # Class of executed instruction
34511026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatAdd                  0      0.00%     92.28% # Class of executed instruction
34611026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatAlu                  0      0.00%     92.28% # Class of executed instruction
34711026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatCmp                  0      0.00%     92.28% # Class of executed instruction
34811026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatCvt                  0      0.00%     92.28% # Class of executed instruction
34911026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatDiv                  0      0.00%     92.28% # Class of executed instruction
35011026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatMisc                 0      0.00%     92.28% # Class of executed instruction
35111026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatMult                 0      0.00%     92.28% # Class of executed instruction
35211026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatMultAcc              0      0.00%     92.28% # Class of executed instruction
35311026Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatSqrt                 0      0.00%     92.28% # Class of executed instruction
35411026Snilay@cs.wisc.edusystem.cpu0.op_class::MemRead                13132199      4.99%     97.27% # Class of executed instruction
35511026Snilay@cs.wisc.edusystem.cpu0.op_class::MemWrite                7183809      2.73%    100.00% # Class of executed instruction
35610220Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
35710220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
35811026Snilay@cs.wisc.edusystem.cpu0.op_class::total                 263158342                       # Class of executed instruction
3598968SN/Asystem.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
3608968SN/Asystem.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
36110036SAli.Saidi@ARM.comsystem.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
36211026Snilay@cs.wisc.edusystem.cpu1.numCycles                     10447240338                       # number of cpu cycles simulated
3638968SN/Asystem.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
3648968SN/Asystem.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
36511026Snilay@cs.wisc.edusystem.cpu1.committedInsts                   17518281                       # Number of instructions committed
36611026Snilay@cs.wisc.edusystem.cpu1.committedOps                     32751585                       # Number of ops (including micro ops) committed
36711026Snilay@cs.wisc.edusystem.cpu1.num_int_alu_accesses             31851643                       # Number of integer alu accesses
36810645Snilay@cs.wisc.edusystem.cpu1.num_fp_alu_accesses                    48                       # Number of float alu accesses
36911026Snilay@cs.wisc.edusystem.cpu1.num_func_calls                     684497                       # number of times a function call or return occured
37011026Snilay@cs.wisc.edusystem.cpu1.num_conditional_control_insts      2335543                       # number of instructions that are conditional controls
37111026Snilay@cs.wisc.edusystem.cpu1.num_int_insts                    31851643                       # number of integer instructions
37210645Snilay@cs.wisc.edusystem.cpu1.num_fp_insts                           48                       # number of float instructions
37311026Snilay@cs.wisc.edusystem.cpu1.num_int_register_reads           64487007                       # number of times the integer registers were read
37411026Snilay@cs.wisc.edusystem.cpu1.num_int_register_writes          25788501                       # number of times the integer registers were written
37510645Snilay@cs.wisc.edusystem.cpu1.num_fp_register_reads                  48                       # number of times the floating registers were read
3768968SN/Asystem.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
37711026Snilay@cs.wisc.edusystem.cpu1.num_cc_register_reads            17633066                       # number of times the CC registers were read
37811026Snilay@cs.wisc.edusystem.cpu1.num_cc_register_writes           10874194                       # number of times the CC registers were written
37911026Snilay@cs.wisc.edusystem.cpu1.num_mem_refs                      7388986                       # number of memory refs
38011026Snilay@cs.wisc.edusystem.cpu1.num_load_insts                    4376633                       # Number of load instructions
38111026Snilay@cs.wisc.edusystem.cpu1.num_store_insts                   3012353                       # Number of store instructions
38211026Snilay@cs.wisc.edusystem.cpu1.num_idle_cycles              10365585755.923355                       # Number of idle cycles
38311026Snilay@cs.wisc.edusystem.cpu1.num_busy_cycles              81654582.076644                       # Number of busy cycles
38411026Snilay@cs.wisc.edusystem.cpu1.not_idle_fraction                0.007816                       # Percentage of non-idle cycles
38511026Snilay@cs.wisc.edusystem.cpu1.idle_fraction                    0.992184                       # Percentage of idle cycles
38611026Snilay@cs.wisc.edusystem.cpu1.Branches                          3292078                       # Number of branches fetched
38711026Snilay@cs.wisc.edusystem.cpu1.op_class::No_OpClass               121362      0.37%      0.37% # Class of executed instruction
38811026Snilay@cs.wisc.edusystem.cpu1.op_class::IntAlu                 25129008     76.72%     77.10% # Class of executed instruction
38911026Snilay@cs.wisc.edusystem.cpu1.op_class::IntMult                   70611      0.22%     77.31% # Class of executed instruction
39011026Snilay@cs.wisc.edusystem.cpu1.op_class::IntDiv                    47212      0.14%     77.45% # Class of executed instruction
39111026Snilay@cs.wisc.edusystem.cpu1.op_class::FloatAdd                      0      0.00%     77.45% # Class of executed instruction
39211026Snilay@cs.wisc.edusystem.cpu1.op_class::FloatCmp                      0      0.00%     77.45% # Class of executed instruction
39311026Snilay@cs.wisc.edusystem.cpu1.op_class::FloatCvt                     16      0.00%     77.46% # Class of executed instruction
39411026Snilay@cs.wisc.edusystem.cpu1.op_class::FloatMult                     0      0.00%     77.46% # Class of executed instruction
39511026Snilay@cs.wisc.edusystem.cpu1.op_class::FloatDiv                      0      0.00%     77.46% # Class of executed instruction
39611026Snilay@cs.wisc.edusystem.cpu1.op_class::FloatSqrt                     0      0.00%     77.46% # Class of executed instruction
39711026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAdd                       0      0.00%     77.46% # Class of executed instruction
39811026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAddAcc                    0      0.00%     77.46% # Class of executed instruction
39911026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAlu                       0      0.00%     77.46% # Class of executed instruction
40011026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdCmp                       0      0.00%     77.46% # Class of executed instruction
40111026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdCvt                       0      0.00%     77.46% # Class of executed instruction
40211026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMisc                      0      0.00%     77.46% # Class of executed instruction
40311026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMult                      0      0.00%     77.46% # Class of executed instruction
40411026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMultAcc                   0      0.00%     77.46% # Class of executed instruction
40511026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdShift                     0      0.00%     77.46% # Class of executed instruction
40611026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdShiftAcc                  0      0.00%     77.46% # Class of executed instruction
40711026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdSqrt                      0      0.00%     77.46% # Class of executed instruction
40811026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatAdd                  0      0.00%     77.46% # Class of executed instruction
40911026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatAlu                  0      0.00%     77.46% # Class of executed instruction
41011026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatCmp                  0      0.00%     77.46% # Class of executed instruction
41111026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatCvt                  0      0.00%     77.46% # Class of executed instruction
41211026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatDiv                  0      0.00%     77.46% # Class of executed instruction
41311026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMisc                 0      0.00%     77.46% # Class of executed instruction
41411026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMult                 0      0.00%     77.46% # Class of executed instruction
41511026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMultAcc              0      0.00%     77.46% # Class of executed instruction
41611026Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatSqrt                 0      0.00%     77.46% # Class of executed instruction
41711026Snilay@cs.wisc.edusystem.cpu1.op_class::MemRead                 4371617     13.35%     90.80% # Class of executed instruction
41811026Snilay@cs.wisc.edusystem.cpu1.op_class::MemWrite                3012353      9.20%    100.00% # Class of executed instruction
41910220Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
42010220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
42111026Snilay@cs.wisc.edusystem.cpu1.op_class::total                  32752179                       # Class of executed instruction
4228968SN/Asystem.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
4238968SN/Asystem.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
42411026Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadReq               907253                       # Transaction distribution
42511026Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadResp              907253                       # Transaction distribution
42611026Snilay@cs.wisc.edusystem.iobus.trans_dist::WriteReq               37589                       # Transaction distribution
42711026Snilay@cs.wisc.edusystem.iobus.trans_dist::WriteResp              37589                       # Transaction distribution
42811026Snilay@cs.wisc.edusystem.iobus.trans_dist::MessageReq              1832                       # Transaction distribution
42911026Snilay@cs.wisc.edusystem.iobus.trans_dist::MessageResp             1832                       # Transaction distribution
43011026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1742                       # Packet count per connected master and slave (bytes)
43111026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1688                       # Packet count per connected master and slave (bytes)
43211026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3430                       # Packet count per connected master and slave (bytes)
43311026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           52                       # Packet count per connected master and slave (bytes)
43411026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
43511026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         6724                       # Packet count per connected master and slave (bytes)
43611026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
43711026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          960                       # Packet count per connected master and slave (bytes)
43811026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           78                       # Packet count per connected master and slave (bytes)
43911026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           46                       # Packet count per connected master and slave (bytes)
44010560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
44111026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       943400                       # Packet count per connected master and slave (bytes)
44211026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1332                       # Packet count per connected master and slave (bytes)
44311026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio          178                       # Packet count per connected master and slave (bytes)
44410560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
44511026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        21174                       # Packet count per connected master and slave (bytes)
44611026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
44711026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
44811026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
44911026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
45011026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       831240                       # Packet count per connected master and slave (bytes)
45111026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          170                       # Packet count per connected master and slave (bytes)
45210560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         2126                       # Packet count per connected master and slave (bytes)
45311026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1807744                       # Packet count per connected master and slave (bytes)
45411026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4456                       # Packet count per connected master and slave (bytes)
45511026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          404                       # Packet count per connected master and slave (bytes)
45611026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            8                       # Packet count per connected master and slave (bytes)
45711026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Packet count per connected master and slave (bytes)
45811026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        32826                       # Packet count per connected master and slave (bytes)
45911026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          788                       # Packet count per connected master and slave (bytes)
46011026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        32826                       # Packet count per connected master and slave (bytes)
46111026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6198                       # Packet count per connected master and slave (bytes)
46211026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port           64                       # Packet count per connected master and slave (bytes)
46311026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         4596                       # Packet count per connected master and slave (bytes)
46411026Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        82174                       # Packet count per connected master and slave (bytes)
46511026Snilay@cs.wisc.edusystem.iobus.pkt_count::total                 1893348                       # Packet count per connected master and slave (bytes)
46611026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3484                       # Cumulative packet size per connected master and slave (bytes)
46711026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3376                       # Cumulative packet size per connected master and slave (bytes)
46811026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6860                       # Cumulative packet size per connected master and slave (bytes)
46911026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           26                       # Cumulative packet size per connected master and slave (bytes)
47011026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
47111026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4231                       # Cumulative packet size per connected master and slave (bytes)
47211026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
47311026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          480                       # Cumulative packet size per connected master and slave (bytes)
47411026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           39                       # Cumulative packet size per connected master and slave (bytes)
47511026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           23                       # Cumulative packet size per connected master and slave (bytes)
47610560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
47711026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       471700                       # Cumulative packet size per connected master and slave (bytes)
47811026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         2664                       # Cumulative packet size per connected master and slave (bytes)
47911026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           89                       # Cumulative packet size per connected master and slave (bytes)
48010560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
48111026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        10587                       # Cumulative packet size per connected master and slave (bytes)
48211026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
48311026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
48411026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
48511026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
48611026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1662474                       # Cumulative packet size per connected master and slave (bytes)
48711026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          340                       # Cumulative packet size per connected master and slave (bytes)
48810560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         4252                       # Cumulative packet size per connected master and slave (bytes)
48911026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      2157168                       # Cumulative packet size per connected master and slave (bytes)
49011026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         2507                       # Cumulative packet size per connected master and slave (bytes)
49111026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          202                       # Cumulative packet size per connected master and slave (bytes)
49211026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            4                       # Cumulative packet size per connected master and slave (bytes)
49311026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            4                       # Cumulative packet size per connected master and slave (bytes)
49411026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        16413                       # Cumulative packet size per connected master and slave (bytes)
49511026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1576                       # Cumulative packet size per connected master and slave (bytes)
49611026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        16413                       # Cumulative packet size per connected master and slave (bytes)
49711026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         3099                       # Cumulative packet size per connected master and slave (bytes)
49811026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          128                       # Cumulative packet size per connected master and slave (bytes)
49911026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         9189                       # Cumulative packet size per connected master and slave (bytes)
50011026Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        49535                       # Cumulative packet size per connected master and slave (bytes)
50111026Snilay@cs.wisc.edusystem.iobus.pkt_size::total                  2213563                       # Cumulative packet size per connected master and slave (bytes)
50210892Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy                43500                       # Layer occupancy (ticks)
50310560Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
50410892Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy                 6500                       # Layer occupancy (ticks)
50510560Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
50611026Snilay@cs.wisc.edusystem.iobus.reqLayer2.occupancy              9190500                       # Layer occupancy (ticks)
50710560Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
50811026Snilay@cs.wisc.edusystem.iobus.reqLayer3.occupancy               158000                       # Layer occupancy (ticks)
50910560Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
51011026Snilay@cs.wisc.edusystem.iobus.reqLayer4.occupancy               938000                       # Layer occupancy (ticks)
51110560Sandreas.hansson@arm.comsystem.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
51211026Snilay@cs.wisc.edusystem.iobus.reqLayer5.occupancy                82500                       # Layer occupancy (ticks)
51310560Sandreas.hansson@arm.comsystem.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
51410892Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy                52500                       # Layer occupancy (ticks)
51510560Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
51611026Snilay@cs.wisc.edusystem.iobus.reqLayer7.occupancy             21911000                       # Layer occupancy (ticks)
51710560Sandreas.hansson@arm.comsystem.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
51811026Snilay@cs.wisc.edusystem.iobus.reqLayer8.occupancy            471701000                       # Layer occupancy (ticks)
51910560Sandreas.hansson@arm.comsystem.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
52011026Snilay@cs.wisc.edusystem.iobus.reqLayer9.occupancy              1783484                       # Layer occupancy (ticks)
52110560Sandreas.hansson@arm.comsystem.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
52211026Snilay@cs.wisc.edusystem.iobus.reqLayer10.occupancy            33004000                       # Layer occupancy (ticks)
52310560Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
52410645Snilay@cs.wisc.edusystem.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
52510560Sandreas.hansson@arm.comsystem.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
52611026Snilay@cs.wisc.edusystem.iobus.reqLayer13.occupancy            20531500                       # Layer occupancy (ticks)
52710560Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
52811026Snilay@cs.wisc.edusystem.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
52910560Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
53010892Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
53110560Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
53211026Snilay@cs.wisc.edusystem.iobus.reqLayer16.occupancy                9500                       # Layer occupancy (ticks)
53310560Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
53410892Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
53510560Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
53611026Snilay@cs.wisc.edusystem.iobus.reqLayer18.occupancy           420355749                       # Layer occupancy (ticks)
53710560Sandreas.hansson@arm.comsystem.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
53811026Snilay@cs.wisc.edusystem.iobus.reqLayer19.occupancy             7349167                       # Layer occupancy (ticks)
53910560Sandreas.hansson@arm.comsystem.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
54011026Snilay@cs.wisc.edusystem.iobus.reqLayer21.occupancy             1592000                       # Layer occupancy (ticks)
54110560Sandreas.hansson@arm.comsystem.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
54211026Snilay@cs.wisc.edusystem.iobus.respLayer0.occupancy             2487964                       # Layer occupancy (ticks)
54310560Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
54411026Snilay@cs.wisc.edusystem.iobus.respLayer2.occupancy          2005769459                       # Layer occupancy (ticks)
54510560Sandreas.hansson@arm.comsystem.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
54611026Snilay@cs.wisc.edusystem.iobus.respLayer4.occupancy            55682477                       # Layer occupancy (ticks)
54710560Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
54810560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
54910560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
55011026Snilay@cs.wisc.edusystem.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
55110560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
55210560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_bytes      2987008                       # Number of bytes transfered via DMA writes.
55310560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_txs          813                       # Number of DMA write transactions.
55410560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
55510560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
55610560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
55710560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
55810560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
55910560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
56010560Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock                      500                       # Clock period in ticks
56110560Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
56210560Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
56311026Snilay@cs.wisc.edusystem.ruby.delayHist::samples               11129562                       # delay histogram for all message
56411026Snilay@cs.wisc.edusystem.ruby.delayHist::mean                  0.432347                       # delay histogram for all message
56511026Snilay@cs.wisc.edusystem.ruby.delayHist::stdev                 1.816100                       # delay histogram for all message
56611026Snilay@cs.wisc.edusystem.ruby.delayHist                    |    10529728     94.61%     94.61% |        6807      0.06%     94.67% |      590648      5.31%     99.98% |         485      0.00%     99.98% |        1771      0.02%    100.00% |          21      0.00%    100.00% |         100      0.00%    100.00% |           1      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
56711026Snilay@cs.wisc.edusystem.ruby.delayHist::total                 11129562                       # delay histogram for all message
56810560Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::bucket_size            1                      
56910560Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::max_bucket            9                      
57011026Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::samples    200348840                      
57111026Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::mean       1.000143                      
57211026Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::gmean      1.000099                      
57311026Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::stdev      0.011958                      
57411026Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   200320188     99.99%     99.99% |       28652      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
57511026Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::total     200348840                      
57611026Snilay@cs.wisc.edusystem.ruby.latency_hist::bucket_size             256                      
57711026Snilay@cs.wisc.edusystem.ruby.latency_hist::max_bucket             2559                      
57811026Snilay@cs.wisc.edusystem.ruby.latency_hist::samples           200348839                      
57911026Snilay@cs.wisc.edusystem.ruby.latency_hist::mean               1.335360                      
58011026Snilay@cs.wisc.edusystem.ruby.latency_hist::gmean              1.041255                      
58111026Snilay@cs.wisc.edusystem.ruby.latency_hist::stdev              5.049559                      
58211026Snilay@cs.wisc.edusystem.ruby.latency_hist                 |   200339965    100.00%    100.00% |        6290      0.00%    100.00% |        2522      0.00%    100.00% |          39      0.00%    100.00% |          22      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
58311026Snilay@cs.wisc.edusystem.ruby.latency_hist::total             200348839                      
58410560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::bucket_size            1                      
58510560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::max_bucket            9                      
58611026Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::samples       197666799                      
58711026Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::mean                  1                      
58811026Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::gmean                 1                      
58911026Snilay@cs.wisc.edusystem.ruby.hit_latency_hist             |           0      0.00%      0.00% |   197666799    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
59011026Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::total         197666799                      
59111026Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::bucket_size          256                      
59211026Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::max_bucket         2559                      
59311026Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::samples        2682040                      
59411026Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::mean         26.051460                      
59511026Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::gmean        20.489156                      
59611026Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::stdev        35.854350                      
59711026Snilay@cs.wisc.edusystem.ruby.miss_latency_hist            |     2673166     99.67%     99.67% |        6290      0.23%     99.90% |        2522      0.09%    100.00% |          39      0.00%    100.00% |          22      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
59811026Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::total          2682040                      
59911026Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Dcache.demand_hits     17844481                       # Number of cache demand hits
60011026Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Dcache.demand_misses      1606977                       # Number of cache demand misses
60111026Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Dcache.demand_accesses     19451458                       # Number of cache demand accesses
60211026Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Icache.demand_hits    150537966                       # Number of cache demand hits
60311026Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Icache.demand_misses       501574                       # Number of cache demand misses
60411026Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Icache.demand_accesses    151039540                       # Number of cache demand accesses
60510560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
60610560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
60710560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
60810560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
60910560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
61010560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.hits               0                       # number of prefetched blocks accessed
61110560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
61210560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
61310560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
61411026Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.fully_busy_cycles            11                       # cycles for which number of transistions == max transitions
61511026Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Dcache.demand_hits      7085830                       # Number of cache demand hits
61611026Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Dcache.demand_misses       288461                       # Number of cache demand misses
61711026Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Dcache.demand_accesses      7374291                       # Number of cache demand accesses
61811026Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Icache.demand_hits     22198522                       # Number of cache demand hits
61911026Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Icache.demand_misses       285028                       # Number of cache demand misses
62011026Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Icache.demand_accesses     22483550                       # Number of cache demand accesses
62110560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.miss_observed            0                       # number of misses observed
62210560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
62310560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.prefetches_requested            0                       # number of prefetch requests made
62410560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
62510560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
62610560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.hits               0                       # number of prefetched blocks accessed
62710560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
62810560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
62910560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
63011026Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.fully_busy_cycles            11                       # cycles for which number of transistions == max transitions
63111026Snilay@cs.wisc.edusystem.ruby.l2_cntrl0.L2cache.demand_hits      2423734                       # Number of cache demand hits
63211026Snilay@cs.wisc.edusystem.ruby.l2_cntrl0.L2cache.demand_misses       258306                       # Number of cache demand misses
63311026Snilay@cs.wisc.edusystem.ruby.l2_cntrl0.L2cache.demand_accesses      2682040                       # Number of cache demand accesses
63411026Snilay@cs.wisc.edusystem.ruby.l2_cntrl0.fully_busy_cycles             1                       # cycles for which number of transistions == max transitions
63510560Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock             1500                       # Clock period in ticks
63611026Snilay@cs.wisc.edusystem.ruby.network.routers0.percent_links_utilized     0.070387                      
63711026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Control::0      2108551                      
63811026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Request_Control::2        69045                      
63911026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Data::1      2150836                      
64011026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Control::1      1572041                      
64111026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Control::2      1562467                      
64211026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Data::0       405747                      
64311026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Data::1          218                      
64411026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Control::0      1093821                      
64511026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Control::0     16868408                      
64611026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Request_Control::2       552360                      
64711026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Data::1    154860192                      
64811026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Control::1     12576328                      
64911026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Control::2     12499736                      
65011026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Data::0     29213784                      
65111026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Data::1        15696                      
65211026Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Control::0      8750568                      
65311026Snilay@cs.wisc.edusystem.ruby.network.routers1.percent_links_utilized     0.019105                      
65411026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Control::0       573489                      
65511026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Request_Control::2        63892                      
65611026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Data::1       612502                      
65711026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Control::1       272070                      
65811026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Control::2       264031                      
65911026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Data::0       136644                      
66011026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Data::1          449                      
66111026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Control::0        64765                      
66211026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Control::0      4587912                      
66311026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Request_Control::2       511136                      
66411026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Data::1     44100144                      
66511026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Control::1      2176560                      
66611026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Control::2      2112248                      
66711026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Data::0      9838368                      
66811026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Data::1        32328                      
66911026Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Control::0       518120                      
67011026Snilay@cs.wisc.edusystem.ruby.network.routers2.percent_links_utilized     0.092817                      
67111026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Control::0      2863371                      
67211026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Request_Control::2       130680                      
67311026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Data::1      2892953                      
67411026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Control::1      1888154                      
67511026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Control::2      1826498                      
67611026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Data::0       542391                      
67711026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Data::1          667                      
67811026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Control::0      1158586                      
67911026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Control::0     22906968                      
68011026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Request_Control::2      1045440                      
68111026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Data::1    208292616                      
68211026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Control::1     15105232                      
68311026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Control::2     14611984                      
68411026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Data::0     39052152                      
68511026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Data::1        48024                      
68611026Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Control::0      9268688                      
68711026Snilay@cs.wisc.edusystem.ruby.network.routers3.percent_links_utilized     0.007106                      
68811026Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Control::0       181331                      
68911026Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Response_Data::1       284375                      
69011026Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Response_Control::1       134795                      
69111026Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Writeback_Control::0        47546                      
69210560Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Writeback_Control::1        46736                      
69311026Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Control::0      1450648                      
69411026Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Response_Data::1     20475000                      
69511026Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Response_Control::1      1078360                      
69611026Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Writeback_Control::0       380368                      
69710560Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Writeback_Control::1       373888                      
69811026Snilay@cs.wisc.edusystem.ruby.network.routers4.percent_links_utilized     0.000243                      
69911026Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_count.Response_Data::1          810                      
70011026Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_count.Writeback_Control::0        47546                      
70110560Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_count.Writeback_Control::1        46736                      
70211026Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_bytes.Response_Data::1        58320                      
70311026Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_bytes.Writeback_Control::0       380368                      
70410560Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_bytes.Writeback_Control::1       373888                      
70510560Sandreas.hansson@arm.comsystem.ruby.network.routers5.percent_links_utilized            0                      
70611026Snilay@cs.wisc.edusystem.ruby.network.routers6.percent_links_utilized     0.031610                      
70711026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Control::0      2863371                      
70811026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Request_Control::2       132937                      
70911026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Response_Data::1      2970738                      
71011026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Response_Control::1      1933530                      
71111026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Response_Control::2      1826498                      
71211026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Writeback_Data::0       542391                      
71311026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Writeback_Data::1          667                      
71411026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Writeback_Control::0      1206132                      
71510560Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Writeback_Control::1        46736                      
71611026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Control::0     22906968                      
71711026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Request_Control::2      1063496                      
71811026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Response_Data::1    213893136                      
71911026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Response_Control::1     15468240                      
72011026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Response_Control::2     14611984                      
72111026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Writeback_Data::0     39052152                      
72211026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Writeback_Data::1        48024                      
72311026Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Writeback_Control::0      9649056                      
72410560Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Writeback_Control::1       373888                      
72511026Snilay@cs.wisc.edusystem.ruby.network.msg_count.Control         8590113                      
72611026Snilay@cs.wisc.edusystem.ruby.network.msg_count.Request_Control       396554                      
72711026Snilay@cs.wisc.edusystem.ruby.network.msg_count.Response_Data      8912214                      
72811026Snilay@cs.wisc.edusystem.ruby.network.msg_count.Response_Control     11280084                      
72911026Snilay@cs.wisc.edusystem.ruby.network.msg_count.Writeback_Data      1629174                      
73011026Snilay@cs.wisc.edusystem.ruby.network.msg_count.Writeback_Control      3758604                      
73111026Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Control         68720904                      
73211026Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Request_Control      3172432                      
73311026Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Response_Data    641679408                      
73411026Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Response_Control     90240672                      
73511026Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Writeback_Data    117300528                      
73611026Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Writeback_Control     30068832                      
73711026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.link_utilization     0.097642                      
73811026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Request_Control::2        69045                      
73911026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::1      2088072                      
74011026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Control::1      1542287                      
74111026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2       552360                      
74211026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1    150341184                      
74311026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1     12338296                      
74411026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.link_utilization     0.043132                      
74511026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::0      2108551                      
74611026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Response_Data::1        62764                      
74711026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Response_Control::1        29754                      
74811026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Response_Control::2      1562467                      
74911026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0       405747                      
75011026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1          218                      
75111026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0      1093821                      
75211026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::0     16868408                      
75311026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1      4519008                      
75411026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1       238032                      
75511026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2     12499736                      
75611026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0     29213784                      
75711026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        15696                      
75811026Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0      8750568                      
75911026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.link_utilization     0.025238                      
76011026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Request_Control::2        63892                      
76111026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Response_Data::1       551505                      
76211026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Response_Control::1       246529                      
76311026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2       511136                      
76411026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1     39708360                      
76511026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1      1972232                      
76611026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.link_utilization     0.012972                      
76711026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Control::0       573489                      
76811026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::1        60997                      
76911026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Control::1        25541                      
77011026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Control::2       264031                      
77111026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0       136644                      
77211026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1          449                      
77311026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0        64765                      
77411026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Control::0      4587912                      
77511026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1      4391784                      
77611026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1       204328                      
77711026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2      2112248                      
77811026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0      9838368                      
77911026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1        32328                      
78011026Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0       518120                      
78111026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.link_utilization     0.060955                      
78211026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Control::0      2682040                      
78311026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::1       228117                      
78411026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Control::1       129933                      
78511026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Control::2      1826498                      
78611026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0       542391                      
78711026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1          667                      
78811026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0      1158586                      
78911026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Control::0     21456320                      
79011026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1     16424424                      
79111026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1      1039464                      
79211026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2     14611984                      
79311026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0     39052152                      
79411026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1        48024                      
79511026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0      9268688                      
79611026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.link_utilization     0.124678                      
79711026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::0       181331                      
79811026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Request_Control::2       130680                      
79911026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Response_Data::1      2664836                      
80011026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Response_Control::1      1758221                      
80111026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::0      1450648                      
80211026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2      1045440                      
80311026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1    191868192                      
80411026Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1     14065768                      
80511026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.link_utilization     0.005569                      
80611026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Control::0       181331                      
80711026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Response_Data::1       102234                      
80811026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Response_Control::1        14781                      
80911026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0        47546                      
81011026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Control::0      1450648                      
81111026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1      7360848                      
81211026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1       118248                      
81311026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0       380368                      
81411026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.link_utilization     0.008643                      
81511026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_count.Response_Data::1       182141                      
81611026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_count.Response_Control::1       120014                      
8179978SN/Asystem.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1        46736                      
81811026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1     13114152                      
81911026Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1       960112                      
8209978SN/Asystem.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1       373888                      
82111026Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.link_utilization     0.000259                      
82211026Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.msg_count.Response_Data::1          810                      
8239978SN/Asystem.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1        46736                      
82411026Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1        58320                      
8259978SN/Asystem.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1       373888                      
82611026Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle1.link_utilization     0.000228                      
82711026Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0        47546                      
82811026Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0       380368                      
82910526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle0.link_utilization            0                      
83010526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle1.link_utilization            0                      
83111026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.link_utilization     0.097642                      
83211026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_count.Request_Control::2        69045                      
83311026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_count.Response_Data::1      2088072                      
83411026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_count.Response_Control::1      1542287                      
83511026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2       552360                      
83611026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1    150341184                      
83711026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1     12338296                      
83811026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.link_utilization     0.025238                      
83911026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_count.Request_Control::2        63892                      
84011026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_count.Response_Data::1       551505                      
84111026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_count.Response_Control::1       246529                      
84211026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2       511136                      
84311026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1     39708360                      
84411026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1      1972232                      
84511026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.link_utilization     0.060955                      
84611026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Control::0      2682040                      
84711026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Response_Data::1       228117                      
84811026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Response_Control::1       129933                      
84911026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Response_Control::2      1826498                      
85011026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0       542391                      
85111026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1          667                      
85211026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0      1158586                      
85311026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Control::0     21456320                      
85411026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1     16424424                      
85511026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1      1039464                      
85611026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2     14611984                      
85711026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0     39052152                      
85811026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1        48024                      
85911026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0      9268688                      
86011026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.link_utilization     0.005569                      
86111026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Control::0       181331                      
86211026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Response_Data::1       102234                      
86311026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Response_Control::1        14781                      
86411026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0        47546                      
86511026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Control::0      1450648                      
86611026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1      7360848                      
86711026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1       118248                      
86811026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0       380368                      
86911026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.link_utilization     0.000259                      
87011026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_count.Response_Data::1          810                      
87110526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1        46736                      
87211026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1        58320                      
87310526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1       373888                      
87410526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle5.link_utilization            0                      
87510229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
87610229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
87711026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::samples       6209515                       # delay histogram for vnet_0
87811026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::mean         0.707046                       # delay histogram for vnet_0
87911026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::stdev        2.283958                       # delay histogram for vnet_0
88011026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0           |     5663572     91.21%     91.21% |        1821      0.03%     91.24% |      541762      8.72%     99.96% |         478      0.01%     99.97% |        1759      0.03%    100.00% |          21      0.00%    100.00% |         100      0.00%    100.00% |           1      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
88111026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::total         6209515                       # delay histogram for vnet_0
88210229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
88310229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
88411026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples       4787110                       # delay histogram for vnet_1
88511026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::mean         0.088019                       # delay histogram for vnet_1
88611026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::stdev        0.824587                       # delay histogram for vnet_1
88711026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1           |     4731394     98.84%     98.84% |        1825      0.04%     98.87% |        2296      0.05%     98.92% |        2690      0.06%     98.98% |       48377      1.01%     99.99% |         509      0.01%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00% |          11      0.00%    100.00% |           1      0.00%    100.00% # delay histogram for vnet_1
88811026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total         4787110                       # delay histogram for vnet_1
88910315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
89010315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
89111026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples        132937                       # delay histogram for vnet_2
89211026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::mean         0.000451                       # delay histogram for vnet_2
89311026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::stdev        0.030041                       # delay histogram for vnet_2
89411026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2           |      132907     99.98%     99.98% |           0      0.00%     99.98% |          30      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
89511026Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total          132937                       # delay histogram for vnet_2
89610628Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::bucket_size          128                      
89710628Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::max_bucket          1279                      
89811026Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::samples         15792182                      
89911026Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::mean            2.811933                      
90011026Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::gmean           1.304177                      
90111026Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::stdev           8.972746                      
90211026Snilay@cs.wisc.edusystem.ruby.LD.latency_hist              |    15777332     99.91%     99.91% |       12811      0.08%     99.99% |         834      0.01%     99.99% |         747      0.00%    100.00% |         344      0.00%    100.00% |         100      0.00%    100.00% |           3      0.00%    100.00% |           8      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00%
90311026Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::total           15792182                      
90410013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size            1                      
90510013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket            9                      
90611026Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::samples     14362699                      
90711026Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean               1                      
90811026Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean              1                      
90911026Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |    14362699    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
91011026Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::total       14362699                      
91110628Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::bucket_size          128                      
91210628Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::max_bucket         1279                      
91311026Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::samples      1429483                      
91411026Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::mean      21.017285                      
91511026Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::gmean     18.800854                      
91611026Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::stdev     22.913162                      
91711026Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist         |     1414633     98.96%     98.96% |       12811      0.90%     99.86% |         834      0.06%     99.92% |         747      0.05%     99.97% |         344      0.02%     99.99% |         100      0.01%    100.00% |           3      0.00%    100.00% |           8      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00%
91811026Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::total       1429483                      
91911026Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size          256                      
92011026Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket          2559                      
92111026Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::samples          9820148                      
92211026Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::mean            3.180305                      
92311026Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::gmean           1.140437                      
92411026Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::stdev          17.669492                      
92511026Snilay@cs.wisc.edusystem.ruby.ST.latency_hist              |     9814336     99.94%     99.94% |        3870      0.04%     99.98% |        1895      0.02%    100.00% |          27      0.00%    100.00% |          19      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
92611026Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::total            9820148                      
92710013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size            1                      
92810013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket            9                      
92911026Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::samples      9468305                      
93011026Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean               1                      
93111026Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean              1                      
93211026Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |     9468305    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
93311026Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::total        9468305                      
93411026Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size          256                      
93511026Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket         2559                      
93611026Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::samples       351843                      
93711026Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::mean      61.853599                      
93811026Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::gmean     39.164823                      
93911026Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::stdev     71.718379                      
94011026Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist         |      346031     98.35%     98.35% |        3870      1.10%     99.45% |        1895      0.54%     99.99% |          27      0.01%     99.99% |          19      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
94111026Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::total        351843                      
94210526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size          128                      
94310526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket         1279                      
94411026Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::samples    173523090                      
94511026Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::mean        1.084209                      
94611026Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::gmean       1.013123                      
94711026Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::stdev       1.872190                      
94811026Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist          |   173516994    100.00%    100.00% |        5126      0.00%    100.00% |         502      0.00%    100.00% |         299      0.00%    100.00% |         121      0.00%    100.00% |          47      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
94911026Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::total      173523090                      
95010013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
95110013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
95211026Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::samples    172736488                      
95311026Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean            1                      
95411026Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean            1                      
95511026Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |   172736488    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
95611026Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::total    172736488                      
95710526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size          128                      
95810526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket         1279                      
95911026Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::samples       786602                      
96011026Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::mean    19.576388                      
96111026Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::gmean    17.746225                      
96211026Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::stdev    20.729229                      
96311026Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist     |      780506     99.23%     99.23% |        5126      0.65%     99.88% |         502      0.06%     99.94% |         299      0.04%     99.98% |         121      0.02%     99.99% |          47      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
96411026Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::total       786602                      
96510526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::bucket_size          128                      
96610526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::max_bucket         1279                      
96711026Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::samples       524087                      
96811026Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::mean      4.129171                      
96911026Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::gmean     1.528491                      
97011026Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::stdev    10.035752                      
97111026Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist        |      523906     99.97%     99.97% |         145      0.03%     99.99% |          16      0.00%    100.00% |           8      0.00%    100.00% |           8      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
97211026Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::total       524087                      
97310013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::bucket_size            1                      
97410013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::max_bucket            9                      
97511026Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::samples       452510                      
97611026Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::mean            1                      
97711026Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::gmean            1                      
97811026Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |      452510    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
97911026Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::total       452510                      
98010526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::bucket_size          128                      
98110526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::max_bucket         1279                      
98211026Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::samples        71577                      
98311026Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::mean    23.911801                      
98411026Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::gmean    22.344653                      
98511026Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::stdev    16.857997                      
98611026Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist   |       71396     99.75%     99.75% |         145      0.20%     99.95% |          16      0.02%     99.97% |           8      0.01%     99.98% |           8      0.01%     99.99% |           4      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
98711026Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::total        71577                      
98810645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::bucket_size          128                      
98910645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::max_bucket         1279                      
99011026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::samples       344666                      
99111026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::mean     3.644746                      
99211026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::gmean     1.459313                      
99311026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::stdev     8.575482                      
99411026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist |      344399     99.92%     99.92% |         250      0.07%    100.00% |          12      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
99511026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::total       344666                      
99610013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size            1                      
99710013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket            9                      
99811026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::samples       302131                      
99911026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::mean            1                      
100011026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::gmean            1                      
100111026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |      302131    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
100211026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::total       302131                      
100310645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size          128                      
100410645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket         1279                      
100511026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::samples        42535                      
100611026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::mean    22.430681                      
100711026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::gmean    21.385224                      
100811026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::stdev    13.903294                      
100911026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist |       42268     99.37%     99.37% |         250      0.59%     99.96% |          12      0.03%     99.99% |           2      0.00%     99.99% |           1      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
101011026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::total        42535                      
101110013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::bucket_size            1                      
101210013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::max_bucket            9                      
101311026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::samples       344666                      
101411026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::mean            1                      
101511026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::gmean            1                      
101611026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |      344666    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
101711026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::total       344666                      
101810013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size            1                      
101910013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket            9                      
102011026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::samples       344666                      
102111026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::mean            1                      
102211026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::gmean            1                      
102311026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |      344666    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
102411026Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::total       344666                      
102511026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Fetch         181331      0.00%      0.00%
102611026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Data          102234      0.00%      0.00%
102711026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Data       181782      0.00%      0.00%
102811026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Ack       146330      0.00%      0.00%
102911026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.DMA_READ          810      0.00%      0.00%
103010560Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.DMA_WRITE        46736      0.00%      0.00%
103111026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.CleanReplacement        14781      0.00%      0.00%
103211026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.Fetch       181331      0.00%      0.00%
103311026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.DMA_READ          451      0.00%      0.00%
103411026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.DMA_WRITE        44096      0.00%      0.00%
103511026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.ID.Memory_Data          451      0.00%      0.00%
103611026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.ID_W.Memory_Ack        44096      0.00%      0.00%
103711026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.Data         99235      0.00%      0.00%
103811026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.DMA_READ          359      0.00%      0.00%
103911026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.DMA_WRITE         2640      0.00%      0.00%
104011026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.CleanReplacement        14781      0.00%      0.00%
104111026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.IM.Memory_Data       181331      0.00%      0.00%
104211026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.MI.Memory_Ack        99235      0.00%      0.00%
104311026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DRD.Data          359      0.00%      0.00%
104411026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DRDI.Memory_Ack          359      0.00%      0.00%
104511026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DWR.Data         2640      0.00%      0.00%
104611026Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DWRI.Memory_Ack         2640      0.00%      0.00%
104711026Snilay@cs.wisc.edusystem.ruby.DMA_Controller.ReadRequest   |         810    100.00%    100.00% |           0      0.00%    100.00%
104811026Snilay@cs.wisc.edusystem.ruby.DMA_Controller.ReadRequest::total          810                      
104910560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.WriteRequest  |       46736    100.00%    100.00% |           0      0.00%    100.00%
105010560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.WriteRequest::total        46736                      
105111026Snilay@cs.wisc.edusystem.ruby.DMA_Controller.Data          |         810    100.00%    100.00% |           0      0.00%    100.00%
105211026Snilay@cs.wisc.edusystem.ruby.DMA_Controller.Data::total            810                      
105310560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Ack           |       46736    100.00%    100.00% |           0      0.00%    100.00%
105410560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Ack::total           46736                      
105511026Snilay@cs.wisc.edusystem.ruby.DMA_Controller.READY.ReadRequest |         810    100.00%    100.00% |           0      0.00%    100.00%
105611026Snilay@cs.wisc.edusystem.ruby.DMA_Controller.READY.ReadRequest::total          810                      
105710560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.WriteRequest |       46736    100.00%    100.00% |           0      0.00%    100.00%
105810560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.WriteRequest::total        46736                      
105911026Snilay@cs.wisc.edusystem.ruby.DMA_Controller.BUSY_RD.Data  |         810    100.00%    100.00% |           0      0.00%    100.00%
106011026Snilay@cs.wisc.edusystem.ruby.DMA_Controller.BUSY_RD.Data::total          810                      
106110560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_WR.Ack   |       46736    100.00%    100.00% |           0      0.00%    100.00%
106210560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_WR.Ack::total        46736                      
106311026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load      |    11728304     74.27%     74.27% |     4063878     25.73%    100.00%
106411026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load::total     15792182                      
106511026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch    |   151039544     87.04%     87.04% |    22483551     12.96%    100.00%
106611026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch::total    173523095                      
106711026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store     |     7723154     70.00%     70.00% |     3310413     30.00%    100.00%
106811026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store::total     11033567                      
106911026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Inv       |       29972     53.56%     53.56% |       25990     46.44%    100.00%
107011026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Inv::total        55962                      
107111026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.L1_Replacement |     2062863     79.71%     79.71% |      525198     20.29%    100.00%
107211026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.L1_Replacement::total      2588061                      
107311026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETX  |       15382     50.95%     50.95% |       14807     49.05%    100.00%
107411026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETX::total        30189                      
107511026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETS  |       23687     50.63%     50.63% |       23095     49.37%    100.00%
107611026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETS::total        46782                      
107710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
107810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR::total            4                      
107911026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data      |        1761     60.45%     60.45% |        1152     39.55%    100.00%
108011026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data::total         2913                      
108111026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_Exclusive |     1215318     92.51%     92.51% |       98439      7.49%    100.00%
108211026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_Exclusive::total      1313757                      
108311026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.DataS_fromL1 |       23095     49.36%     49.36% |       23691     50.64%    100.00%
108411026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.DataS_fromL1::total        46786                      
108511026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_all_Acks |      847898     66.44%     66.44% |      428223     33.56%    100.00%
108611026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_all_Acks::total      1276121                      
108711026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack       |       20479     48.23%     48.23% |       21984     51.77%    100.00%
108811026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack::total        42463                      
108911026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack_all   |       22240     49.01%     49.01% |       23136     50.99%    100.00%
109011026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack_all::total        45376                      
109111026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.WB_Ack    |     1499568     88.16%     88.16% |      201409     11.84%    100.00%
109211026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.WB_Ack::total      1700977                      
109311026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Load   |     1266490     90.67%     90.67% |      130317      9.33%    100.00%
109411026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Load::total      1396807                      
109511026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Ifetch |      501126     63.78%     63.78% |      284584     36.22%    100.00%
109611026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Ifetch::total       785710                      
109711026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Store  |      296269     72.69%     72.69% |      111321     27.31%    100.00%
109811026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Store::total       407590                      
109911026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Inv    |        6842     68.45%     68.45% |        3153     31.55%    100.00%
110011026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Inv::total         9995                      
110111026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load    |       16433     50.29%     50.29% |       16243     49.71%    100.00%
110211026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load::total        32676                      
110311026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch  |         448     50.22%     50.22% |         444     49.78%    100.00%
110411026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch::total          892                      
110511026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store   |        7300     45.93%     45.93% |        8594     54.07%    100.00%
110611026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store::total        15894                      
110711026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.L1_Replacement |       14321     53.77%     53.77% |       12311     46.23%    100.00%
110811026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.L1_Replacement::total        26632                      
110911026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Load    |      961054     62.74%     62.74% |      570843     37.26%    100.00%
111011026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Load::total      1531897                      
111111026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Ifetch  |   150537966     87.15%     87.15% |    22198522     12.85%    100.00%
111211026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Ifetch::total    172736488                      
111311026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Store   |       20485     48.23%     48.23% |       21986     51.77%    100.00%
111411026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Store::total        42471                      
111511026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Inv     |       22871     50.77%     50.77% |       22179     49.23%    100.00%
111611026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Inv::total        45050                      
111711026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.L1_Replacement |      548974     63.80%     63.80% |      311478     36.20%    100.00%
111811026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.L1_Replacement::total       860452                      
111911026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Load    |     3041832     82.22%     82.22% |      657704     17.78%    100.00%
112011026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Load::total      3699536                      
112111026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Store   |      119741     78.96%     78.96% |       31903     21.04%    100.00%
112211026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Store::total       151644                      
112311026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Inv     |          35     14.46%     14.46% |         207     85.54%    100.00%
112411026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Inv::total          242                      
112511026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.L1_Replacement |     1093821     94.41%     94.41% |       64765      5.59%    100.00%
112611026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.L1_Replacement::total      1158586                      
112711026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETX |         218     66.87%     66.87% |         108     33.13%    100.00%
112811026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETX::total          326                      
112911026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETS |        1319     49.83%     49.83% |        1328     50.17%    100.00%
113011026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETS::total         2647                      
113111026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load    |     6442495     70.55%     70.55% |     2688771     29.45%    100.00%
113211026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load::total      9131266                      
113311026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store   |     7279359     69.89%     69.89% |     3136609     30.11%    100.00%
113411026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store::total     10415968                      
113511026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Inv     |         218     32.68%     32.68% |         449     67.32%    100.00%
113611026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Inv::total          667                      
113711026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.L1_Replacement |      405747     74.81%     74.81% |      136644     25.19%    100.00%
113811026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.L1_Replacement::total       542391                      
113911026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETX |       15164     50.78%     50.78% |       14699     49.22%    100.00%
114011026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETX::total        29863                      
114111026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETS |       22368     50.68%     50.68% |       21767     49.32%    100.00%
114211026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETS::total        44135                      
114310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
114410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total            4                      
114511026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_Exclusive |     1215318     92.51%     92.51% |       98439      7.49%    100.00%
114611026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1313757                      
114711026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.DataS_fromL1 |       23095     49.36%     49.36% |       23691     50.64%    100.00%
114811026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.DataS_fromL1::total        46786                      
114911026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_all_Acks |      546084     63.83%     63.83% |      309458     36.17%    100.00%
115011026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_all_Acks::total       855542                      
115111026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data   |        1761     60.45%     60.45% |        1152     39.55%    100.00%
115211026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data::total         2913                      
115311026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data_all_Acks |      301814     71.76%     71.76% |      118765     28.24%    100.00%
115411026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data_all_Acks::total       420579                      
115511026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Inv    |           6     75.00%     75.00% |           2     25.00%    100.00%
115611026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Inv::total            8                      
115711026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack    |       20479     48.23%     48.23% |       21984     51.77%    100.00%
115811026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack::total        42463                      
115911026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack_all |       22240     49.01%     49.01% |       23136     50.99%    100.00%
116011026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack_all::total        45376                      
116111026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.Ifetch |           4     80.00%     80.00% |           1     20.00%    100.00%
116211026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.Ifetch::total            5                      
116311026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.WB_Ack |     1499568     88.16%     88.16% |      201409     11.84%    100.00%
116411026Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.WB_Ack::total      1700977                      
116511026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_GET_INSTR       786602      0.00%      0.00%
116611026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_GETS        1429851      0.00%      0.00%
116711026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_GETX         423493      0.00%      0.00%
116811026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_UPGRADE        42471      0.00%      0.00%
116911026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_PUTX        1700977      0.00%      0.00%
117011026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L2_Replacement        99083      0.00%      0.00%
117111026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L2_Replacement_clean        14933      0.00%      0.00%
117211026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Mem_Data        181331      0.00%      0.00%
117311026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Mem_Ack         117015      0.00%      0.00%
117411026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.WB_Data          44806      0.00%      0.00%
117511026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.WB_Data_clean         2647      0.00%      0.00%
117611026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Ack               2257      0.00%      0.00%
117711026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Ack_all           7662      0.00%      0.00%
117811026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Unblock          46786      0.00%      0.00%
117911026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Exclusive_Unblock      1779712      0.00%      0.00%
118011026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MEM_Inv           5998      0.00%      0.00%
118111026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.NP.L1_GET_INSTR        15983      0.00%      0.00%
118211026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.NP.L1_GETS        33150      0.00%      0.00%
118311026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.NP.L1_GETX       132198      0.00%      0.00%
118411026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_GET_INSTR       770589      0.00%      0.00%
118511026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_GETS        68944      0.00%      0.00%
118611026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_GETX         3072      0.00%      0.00%
118711026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_UPGRADE        42463      0.00%      0.00%
118811026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L2_Replacement          229      0.00%      0.00%
118911026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L2_Replacement_clean         7185      0.00%      0.00%
119011026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.MEM_Inv            6      0.00%      0.00%
119110628Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L1_GET_INSTR           26      0.00%      0.00%
119211026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L1_GETS      1280607      0.00%      0.00%
119311026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L1_GETX       258033      0.00%      0.00%
119411026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L2_Replacement        98530      0.00%      0.00%
119511026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L2_Replacement_clean         7402      0.00%      0.00%
119611026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.MEM_Inv         2754      0.00%      0.00%
119710013Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GET_INSTR            4      0.00%      0.00%
119811026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GETS        46782      0.00%      0.00%
119911026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GETX        30189      0.00%      0.00%
120011026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_PUTX      1700977      0.00%      0.00%
120111026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L2_Replacement          324      0.00%      0.00%
120211026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L2_Replacement_clean          346      0.00%      0.00%
120311026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.MEM_Inv          239      0.00%      0.00%
120411026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M_I.Mem_Ack       117015      0.00%      0.00%
120511026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M_I.MEM_Inv         2754      0.00%      0.00%
120611026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_I.WB_Data          515      0.00%      0.00%
120711026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_I.Ack_all           48      0.00%      0.00%
120811026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_I.MEM_Inv          239      0.00%      0.00%
120911026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MCT_I.WB_Data          152      0.00%      0.00%
121011026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MCT_I.Ack_all          194      0.00%      0.00%
121111026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.I_I.Ack           2023      0.00%      0.00%
121211026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.I_I.Ack_all         7185      0.00%      0.00%
121311026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.S_I.Ack            234      0.00%      0.00%
121411026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.S_I.Ack_all          235      0.00%      0.00%
121511026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.S_I.MEM_Inv            6      0.00%      0.00%
121611026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.ISS.Mem_Data        33150      0.00%      0.00%
121711026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.IS.Mem_Data        15983      0.00%      0.00%
121811026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.IM.Mem_Data       132198      0.00%      0.00%
121911026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS_MB.L1_GETS          234      0.00%      0.00%
122011026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE            8      0.00%      0.00%
122111026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        45535      0.00%      0.00%
122211026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_MB.L1_GETS          134      0.00%      0.00%
122311026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_MB.L1_GETX            1      0.00%      0.00%
122411026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1734177      0.00%      0.00%
122511026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IIB.WB_Data        44127      0.00%      0.00%
122611026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2647      0.00%      0.00%
122711026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IIB.Unblock           12      0.00%      0.00%
122811026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IB.WB_Data           12      0.00%      0.00%
122911026Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_SB.Unblock        46774      0.00%      0.00%
12308968SN/A
12318968SN/A---------- End Simulation Statistics   ----------
1232