stats.txt revision 10892
18968SN/A
28968SN/A---------- Begin Simulation Statistics ----------
310892Sandreas.hansson@arm.comsim_seconds                                  5.305855                       # Number of seconds simulated
410892Sandreas.hansson@arm.comsim_ticks                                5305855051000                       # Number of ticks simulated
510892Sandreas.hansson@arm.comfinal_tick                               5305855051000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68968SN/Asim_freq                                 1000000000000                       # Frequency of simulated ticks
710892Sandreas.hansson@arm.comhost_inst_rate                                 186796                       # Simulator instruction rate (inst/s)
810892Sandreas.hansson@arm.comhost_op_rate                                   357991                       # Simulator op (including micro ops) rate (op/s)
910892Sandreas.hansson@arm.comhost_tick_rate                             9246678170                       # Simulator tick rate (ticks/s)
1010892Sandreas.hansson@arm.comhost_mem_usage                                1105624                       # Number of bytes of host memory used
1110892Sandreas.hansson@arm.comhost_seconds                                   573.81                       # Real time elapsed on the host
1210892Sandreas.hansson@arm.comsim_insts                                   107186053                       # Number of instructions simulated
1310892Sandreas.hansson@arm.comsim_ops                                     205419480                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                          1000                       # Clock period in ticks
1610892Sandreas.hansson@arm.comsystem.mem_ctrls.bytes_read::ruby.dir_cntrl0     11371136                       # Number of bytes read from this memory
1710892Sandreas.hansson@arm.comsystem.mem_ctrls.bytes_read::total           11371136                       # Number of bytes read from this memory
1810892Sandreas.hansson@arm.comsystem.mem_ctrls.bytes_written::ruby.dir_cntrl0      9131456                       # Number of bytes written to this memory
1910892Sandreas.hansson@arm.comsystem.mem_ctrls.bytes_written::total         9131456                       # Number of bytes written to this memory
2010892Sandreas.hansson@arm.comsystem.mem_ctrls.num_reads::ruby.dir_cntrl0       177674                       # Number of read requests responded to by this memory
2110892Sandreas.hansson@arm.comsystem.mem_ctrls.num_reads::total              177674                       # Number of read requests responded to by this memory
2210892Sandreas.hansson@arm.comsystem.mem_ctrls.num_writes::ruby.dir_cntrl0       142679                       # Number of write requests responded to by this memory
2310892Sandreas.hansson@arm.comsystem.mem_ctrls.num_writes::total             142679                       # Number of write requests responded to by this memory
2410892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_read::ruby.dir_cntrl0      2143130                       # Total read bandwidth from this memory (bytes/s)
2510892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_read::total               2143130                       # Total read bandwidth from this memory (bytes/s)
2610892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_write::ruby.dir_cntrl0      1721015                       # Write bandwidth from this memory (bytes/s)
2710892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_write::total              1721015                       # Write bandwidth from this memory (bytes/s)
2810892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_total::ruby.dir_cntrl0      3864145                       # Total bandwidth to/from this memory (bytes/s)
2910892Sandreas.hansson@arm.comsystem.mem_ctrls.bw_total::total              3864145                       # Total bandwidth to/from this memory (bytes/s)
3010892Sandreas.hansson@arm.comsystem.mem_ctrls.readReqs                      177674                       # Number of read requests accepted
3110892Sandreas.hansson@arm.comsystem.mem_ctrls.writeReqs                     142679                       # Number of write requests accepted
3210892Sandreas.hansson@arm.comsystem.mem_ctrls.readBursts                    177674                       # Number of DRAM read bursts, including those serviced by the write queue
3310892Sandreas.hansson@arm.comsystem.mem_ctrls.writeBursts                   142679                       # Number of DRAM write bursts, including those merged in the write queue
3410892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesReadDRAM               11313280                       # Total number of bytes read from DRAM
3510892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesReadWrQ                   57856                       # Total number of bytes read from write queue
3610892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesWritten                 9121152                       # Total number of bytes written to DRAM
3710892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesReadSys                11371136                       # Total read bytes from the system interface side
3810892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesWrittenSys              9131456                       # Total written bytes from the system interface side
3910892Sandreas.hansson@arm.comsystem.mem_ctrls.servicedByWrQ                    904                       # Number of DRAM read bursts serviced by the write queue
4010892Sandreas.hansson@arm.comsystem.mem_ctrls.mergedWrBursts                   135                       # Number of DRAM write bursts merged with an existing one
4110526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
4210892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::0             10805                       # Per bank write bursts
4310892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::1             10794                       # Per bank write bursts
4410892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::2             10981                       # Per bank write bursts
4510892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::3             11389                       # Per bank write bursts
4610892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::4             11550                       # Per bank write bursts
4710892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::5             12175                       # Per bank write bursts
4810892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::6             10978                       # Per bank write bursts
4910892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::7             10407                       # Per bank write bursts
5010892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::8             10706                       # Per bank write bursts
5110892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::9             10369                       # Per bank write bursts
5210892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::10            10514                       # Per bank write bursts
5310892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::11            13718                       # Per bank write bursts
5410892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::12            10819                       # Per bank write bursts
5510892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::13            10294                       # Per bank write bursts
5610892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::14            10714                       # Per bank write bursts
5710892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankRdBursts::15            10557                       # Per bank write bursts
5810892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::0              8779                       # Per bank write bursts
5910892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::1              8773                       # Per bank write bursts
6010892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::2              8745                       # Per bank write bursts
6110892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::3              9209                       # Per bank write bursts
6210892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::4              9395                       # Per bank write bursts
6310892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::5              9648                       # Per bank write bursts
6410892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::6              8754                       # Per bank write bursts
6510892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::7              8594                       # Per bank write bursts
6610892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::8              8776                       # Per bank write bursts
6710892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::9              8713                       # Per bank write bursts
6810892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::10             8651                       # Per bank write bursts
6910892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::11             9041                       # Per bank write bursts
7010892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::12             8739                       # Per bank write bursts
7110892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::13             8605                       # Per bank write bursts
7210892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::14             9111                       # Per bank write bursts
7310892Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::15             8985                       # Per bank write bursts
7410526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
7510526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
7610892Sandreas.hansson@arm.comsystem.mem_ctrls.totGap                  5305854916500                       # Total gap between requests
7710526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
8310892Sandreas.hansson@arm.comsystem.mem_ctrls.readPktSize::6                177674                       # Read request sizes (log2)
8410526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
9010892Sandreas.hansson@arm.comsystem.mem_ctrls.writePktSize::6               142679                       # Write request sizes (log2)
9110892Sandreas.hansson@arm.comsystem.mem_ctrls.rdQLenPdf::0                  176703                       # What read queue length does an incoming req see
9210892Sandreas.hansson@arm.comsystem.mem_ctrls.rdQLenPdf::1                      67                       # What read queue length does an incoming req see
9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
12310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
13810892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::15                   2059                       # What write queue length does an incoming req see
13910892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::16                   2790                       # What write queue length does an incoming req see
14010892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::17                   8563                       # What write queue length does an incoming req see
14110892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::18                   9122                       # What write queue length does an incoming req see
14210892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::19                   8572                       # What write queue length does an incoming req see
14310892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::20                   9212                       # What write queue length does an incoming req see
14410892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::21                   9228                       # What write queue length does an incoming req see
14510892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::22                   8314                       # What write queue length does an incoming req see
14610892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::23                   9034                       # What write queue length does an incoming req see
14710892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::24                   9060                       # What write queue length does an incoming req see
14810892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::25                   8413                       # What write queue length does an incoming req see
14910892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::26                   8500                       # What write queue length does an incoming req see
15010892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::27                   8357                       # What write queue length does an incoming req see
15110892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::28                   8453                       # What write queue length does an incoming req see
15210892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::29                   8029                       # What write queue length does an incoming req see
15310892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::30                   8097                       # What write queue length does an incoming req see
15410892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::31                   8147                       # What write queue length does an incoming req see
15510892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::32                   7952                       # What write queue length does an incoming req see
15610892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::33                    108                       # What write queue length does an incoming req see
15710892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::34                     85                       # What write queue length does an incoming req see
15810892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::35                     89                       # What write queue length does an incoming req see
15910892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::36                     75                       # What write queue length does an incoming req see
16010892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::37                     64                       # What write queue length does an incoming req see
16110892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::38                     57                       # What write queue length does an incoming req see
16210892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::39                     48                       # What write queue length does an incoming req see
16310892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::40                     39                       # What write queue length does an incoming req see
16410892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::41                     28                       # What write queue length does an incoming req see
16510892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::42                     18                       # What write queue length does an incoming req see
16610892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::43                      9                       # What write queue length does an incoming req see
16710892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::44                      4                       # What write queue length does an incoming req see
16810892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::45                      2                       # What write queue length does an incoming req see
16910892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::46                      1                       # What write queue length does an incoming req see
17010892Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
18710892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::samples        60336                       # Bytes accessed per row activation
18810892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::mean    338.676213                       # Bytes accessed per row activation
18910892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::gmean   200.551275                       # Bytes accessed per row activation
19010892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::stdev   343.723517                       # Bytes accessed per row activation
19110892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::0-127        20068     33.26%     33.26% # Bytes accessed per row activation
19210892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::128-255        14736     24.42%     57.68% # Bytes accessed per row activation
19310892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::256-383         6373     10.56%     68.25% # Bytes accessed per row activation
19410892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::384-511         3491      5.79%     74.03% # Bytes accessed per row activation
19510892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::512-639         2657      4.40%     78.44% # Bytes accessed per row activation
19610892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::640-767         1861      3.08%     81.52% # Bytes accessed per row activation
19710892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::768-895         1364      2.26%     83.78% # Bytes accessed per row activation
19810892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::896-1023         1338      2.22%     86.00% # Bytes accessed per row activation
19910892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::1024-1151         8448     14.00%    100.00% # Bytes accessed per row activation
20010892Sandreas.hansson@arm.comsystem.mem_ctrls.bytesPerActivate::total        60336                       # Bytes accessed per row activation
20110892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::samples         7897                       # Reads before turning the bus around for writes
20210892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::mean      22.382170                       # Reads before turning the bus around for writes
20310892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::stdev    317.489285                       # Reads before turning the bus around for writes
20410892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::0-1023         7891     99.92%     99.92% # Reads before turning the bus around for writes
20510892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::1024-2047            3      0.04%     99.96% # Reads before turning the bus around for writes
20610892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::2048-3071            1      0.01%     99.97% # Reads before turning the bus around for writes
20710526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::10240-11263            1      0.01%     99.99% # Reads before turning the bus around for writes
20810526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
20910892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::total          7897                       # Reads before turning the bus around for writes
21010892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::samples         7897                       # Writes before turning the bus around for reads
21110892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::mean      18.047106                       # Writes before turning the bus around for reads
21210892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::gmean     17.696875                       # Writes before turning the bus around for reads
21310892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::stdev      4.065797                       # Writes before turning the bus around for reads
21410892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::16             5800     73.45%     73.45% # Writes before turning the bus around for reads
21510892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::17                9      0.11%     73.56% # Writes before turning the bus around for reads
21610892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::18              169      2.14%     75.70% # Writes before turning the bus around for reads
21710892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::19               20      0.25%     75.95% # Writes before turning the bus around for reads
21810892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::20               37      0.47%     76.42% # Writes before turning the bus around for reads
21910892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::21              500      6.33%     82.75% # Writes before turning the bus around for reads
22010892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::22              145      1.84%     84.59% # Writes before turning the bus around for reads
22110892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::23               43      0.54%     85.13% # Writes before turning the bus around for reads
22210892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::24              653      8.27%     93.40% # Writes before turning the bus around for reads
22310892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::25              111      1.41%     94.81% # Writes before turning the bus around for reads
22410892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::26               12      0.15%     94.96% # Writes before turning the bus around for reads
22510892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::27               19      0.24%     95.20% # Writes before turning the bus around for reads
22610892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::28              304      3.85%     99.05% # Writes before turning the bus around for reads
22710892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::29                7      0.09%     99.14% # Writes before turning the bus around for reads
22810892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::30                3      0.04%     99.18% # Writes before turning the bus around for reads
22910892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::31                6      0.08%     99.25% # Writes before turning the bus around for reads
23010892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::32                6      0.08%     99.33% # Writes before turning the bus around for reads
23110892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::33                2      0.03%     99.35% # Writes before turning the bus around for reads
23210892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::34                1      0.01%     99.37% # Writes before turning the bus around for reads
23310892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::35                3      0.04%     99.40% # Writes before turning the bus around for reads
23410892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::37                1      0.01%     99.42% # Writes before turning the bus around for reads
23510892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::38                3      0.04%     99.46% # Writes before turning the bus around for reads
23610892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::39                7      0.09%     99.54% # Writes before turning the bus around for reads
23710892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::40                3      0.04%     99.58% # Writes before turning the bus around for reads
23810892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::41                3      0.04%     99.62% # Writes before turning the bus around for reads
23910892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::42                6      0.08%     99.70% # Writes before turning the bus around for reads
24010892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::43                2      0.03%     99.72% # Writes before turning the bus around for reads
24110892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::44                6      0.08%     99.80% # Writes before turning the bus around for reads
24210892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::45                1      0.01%     99.81% # Writes before turning the bus around for reads
24310892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::47                1      0.01%     99.82% # Writes before turning the bus around for reads
24410892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::48                4      0.05%     99.87% # Writes before turning the bus around for reads
24510892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::51                9      0.11%     99.99% # Writes before turning the bus around for reads
24610892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::52                1      0.01%    100.00% # Writes before turning the bus around for reads
24710892Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::total          7897                       # Writes before turning the bus around for reads
24810892Sandreas.hansson@arm.comsystem.mem_ctrls.totQLat                   1934453242                       # Total ticks spent queuing
24910892Sandreas.hansson@arm.comsystem.mem_ctrls.totMemAccLat              5248890742                       # Total ticks spent from burst creation until serviced by the DRAM
25010892Sandreas.hansson@arm.comsystem.mem_ctrls.totBusLat                  883850000                       # Total ticks spent in databus transfers
25110892Sandreas.hansson@arm.comsystem.mem_ctrls.avgQLat                     10943.33                       # Average queueing delay per DRAM burst
25210526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
25310892Sandreas.hansson@arm.comsystem.mem_ctrls.avgMemAccLat                29693.33                       # Average memory access latency per DRAM burst
25410892Sandreas.hansson@arm.comsystem.mem_ctrls.avgRdBW                         2.13                       # Average DRAM read bandwidth in MiByte/s
25510892Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrBW                         1.72                       # Average achieved write bandwidth in MiByte/s
25610892Sandreas.hansson@arm.comsystem.mem_ctrls.avgRdBWSys                      2.14                       # Average system read bandwidth in MiByte/s
25710892Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrBWSys                      1.72                       # Average system write bandwidth in MiByte/s
25810526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
25910526Snilay@cs.wisc.edusystem.mem_ctrls.busUtil                         0.03                       # Data bus utilization in percentage
26010526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilRead                     0.02                       # Data bus utilization in percentage for reads
26110526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilWrite                    0.01                       # Data bus utilization in percentage for writes
26210526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
26310892Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrQLen                      24.42                       # Average write queue length when enqueuing
26410892Sandreas.hansson@arm.comsystem.mem_ctrls.readRowHits                   140774                       # Number of row buffer hits during reads
26510892Sandreas.hansson@arm.comsystem.mem_ctrls.writeRowHits                  118177                       # Number of row buffer hits during writes
26610892Sandreas.hansson@arm.comsystem.mem_ctrls.readRowHitRate                 79.64                       # Row buffer hit rate for reads
26710892Sandreas.hansson@arm.comsystem.mem_ctrls.writeRowHitRate                82.91                       # Row buffer hit rate for writes
26810892Sandreas.hansson@arm.comsystem.mem_ctrls.avgGap                   16562526.08                       # Average gap between requests
26910892Sandreas.hansson@arm.comsystem.mem_ctrls.pageHitRate                    81.10                       # Row buffer hit rate, read and write combined
27010892Sandreas.hansson@arm.comsystem.mem_ctrls_0.actEnergy                229839120                       # Energy for activate commands per rank (pJ)
27110892Sandreas.hansson@arm.comsystem.mem_ctrls_0.preEnergy                125408250                       # Energy for precharge commands per rank (pJ)
27210892Sandreas.hansson@arm.comsystem.mem_ctrls_0.readEnergy               694816200                       # Energy for read commands per rank (pJ)
27310892Sandreas.hansson@arm.comsystem.mem_ctrls_0.writeEnergy              465892560                       # Energy for write commands per rank (pJ)
27410892Sandreas.hansson@arm.comsystem.mem_ctrls_0.refreshEnergy         346552617840                       # Energy for refresh commands per rank (pJ)
27510892Sandreas.hansson@arm.comsystem.mem_ctrls_0.actBackEnergy         149179147425                       # Energy for active background per rank (pJ)
27610892Sandreas.hansson@arm.comsystem.mem_ctrls_0.preBackEnergy         3052653894750                       # Energy for precharge background per rank (pJ)
27710892Sandreas.hansson@arm.comsystem.mem_ctrls_0.totalEnergy           3549901616145                       # Total energy per rank (pJ)
27810892Sandreas.hansson@arm.comsystem.mem_ctrls_0.averagePower            669.053686                       # Core power per rank (mW)
27910892Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::IDLE 5078195767000                       # Time in different power states
28010892Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::REF  177174140000                       # Time in different power states
28110628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
28210892Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT   50484766750                       # Time in different power states
28310628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
28410892Sandreas.hansson@arm.comsystem.mem_ctrls_1.actEnergy                226301040                       # Energy for activate commands per rank (pJ)
28510892Sandreas.hansson@arm.comsystem.mem_ctrls_1.preEnergy                123477750                       # Energy for precharge commands per rank (pJ)
28610892Sandreas.hansson@arm.comsystem.mem_ctrls_1.readEnergy               683982000                       # Energy for read commands per rank (pJ)
28710892Sandreas.hansson@arm.comsystem.mem_ctrls_1.writeEnergy              457624080                       # Energy for write commands per rank (pJ)
28810892Sandreas.hansson@arm.comsystem.mem_ctrls_1.refreshEnergy         346552617840                       # Energy for refresh commands per rank (pJ)
28910892Sandreas.hansson@arm.comsystem.mem_ctrls_1.actBackEnergy         148537848690                       # Energy for active background per rank (pJ)
29010892Sandreas.hansson@arm.comsystem.mem_ctrls_1.preBackEnergy         3053216437500                       # Energy for precharge background per rank (pJ)
29110892Sandreas.hansson@arm.comsystem.mem_ctrls_1.totalEnergy           3549798288900                       # Total energy per rank (pJ)
29210892Sandreas.hansson@arm.comsystem.mem_ctrls_1.averagePower            669.034212                       # Core power per rank (mW)
29310892Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::IDLE 5079136661250                       # Time in different power states
29410892Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::REF  177174140000                       # Time in different power states
29510628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
29610892Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT   49544125250                       # Time in different power states
29710628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
29810315Snilay@cs.wisc.edusystem.cpu_clk_domain.clock                       500                       # Clock period in ticks
29910036SAli.Saidi@ARM.comsystem.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
30010892Sandreas.hansson@arm.comsystem.cpu0.numCycles                     10611710102                       # number of cpu cycles simulated
3018968SN/Asystem.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
3028968SN/Asystem.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
30310892Sandreas.hansson@arm.comsystem.cpu0.committedInsts                   59039296                       # Number of instructions committed
30410892Sandreas.hansson@arm.comsystem.cpu0.committedOps                    113305650                       # Number of ops (including micro ops) committed
30510892Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses            106292214                       # Number of integer alu accesses
30610645Snilay@cs.wisc.edusystem.cpu0.num_fp_alu_accesses                    48                       # Number of float alu accesses
30710892Sandreas.hansson@arm.comsystem.cpu0.num_func_calls                    1017385                       # number of times a function call or return occured
30810892Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts     10037497                       # number of instructions that are conditional controls
30910892Sandreas.hansson@arm.comsystem.cpu0.num_int_insts                   106292214                       # number of integer instructions
31010645Snilay@cs.wisc.edusystem.cpu0.num_fp_insts                           48                       # number of float instructions
31110892Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads          200616677                       # number of times the integer registers were read
31210892Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes          90211380                       # number of times the integer registers were written
31310645Snilay@cs.wisc.edusystem.cpu0.num_fp_register_reads                  48                       # number of times the floating registers were read
3148968SN/Asystem.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
31510892Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads            60966470                       # number of times the CC registers were read
31610892Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes           44030878                       # number of times the CC registers were written
31710892Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs                     12456031                       # number of memory refs
31810892Sandreas.hansson@arm.comsystem.cpu0.num_load_insts                    7518228                       # Number of load instructions
31910892Sandreas.hansson@arm.comsystem.cpu0.num_store_insts                   4937803                       # Number of store instructions
32010892Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles              10088651138.334099                       # Number of idle cycles
32110892Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles              523058963.665901                       # Number of busy cycles
32210892Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction                0.049291                       # Percentage of non-idle cycles
32310892Sandreas.hansson@arm.comsystem.cpu0.idle_fraction                    0.950709                       # Percentage of idle cycles
32410892Sandreas.hansson@arm.comsystem.cpu0.Branches                         11416966                       # Number of branches fetched
32510892Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass               131109      0.12%      0.12% # Class of executed instruction
32610892Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu                100580264     88.77%     88.88% # Class of executed instruction
32710892Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult                   86269      0.08%     88.96% # Class of executed instruction
32810892Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv                    57079      0.05%     89.01% # Class of executed instruction
32910892Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd                      0      0.00%     89.01% # Class of executed instruction
33010892Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp                      0      0.00%     89.01% # Class of executed instruction
33110892Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt                     16      0.00%     89.01% # Class of executed instruction
33210892Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult                     0      0.00%     89.01% # Class of executed instruction
33310892Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv                      0      0.00%     89.01% # Class of executed instruction
33410892Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt                     0      0.00%     89.01% # Class of executed instruction
33510892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd                       0      0.00%     89.01% # Class of executed instruction
33610892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc                    0      0.00%     89.01% # Class of executed instruction
33710892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu                       0      0.00%     89.01% # Class of executed instruction
33810892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp                       0      0.00%     89.01% # Class of executed instruction
33910892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt                       0      0.00%     89.01% # Class of executed instruction
34010892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc                      0      0.00%     89.01% # Class of executed instruction
34110892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult                      0      0.00%     89.01% # Class of executed instruction
34210892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc                   0      0.00%     89.01% # Class of executed instruction
34310892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift                     0      0.00%     89.01% # Class of executed instruction
34410892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc                  0      0.00%     89.01% # Class of executed instruction
34510892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt                      0      0.00%     89.01% # Class of executed instruction
34610892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd                  0      0.00%     89.01% # Class of executed instruction
34710892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu                  0      0.00%     89.01% # Class of executed instruction
34810892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp                  0      0.00%     89.01% # Class of executed instruction
34910892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt                  0      0.00%     89.01% # Class of executed instruction
35010892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv                  0      0.00%     89.01% # Class of executed instruction
35110892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc                 0      0.00%     89.01% # Class of executed instruction
35210892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult                 0      0.00%     89.01% # Class of executed instruction
35310892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc              0      0.00%     89.01% # Class of executed instruction
35410892Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt                 0      0.00%     89.01% # Class of executed instruction
35510892Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead                 7514027      6.63%     95.64% # Class of executed instruction
35610892Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite                4937803      4.36%    100.00% # Class of executed instruction
35710220Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
35810220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
35910892Sandreas.hansson@arm.comsystem.cpu0.op_class::total                 113306567                       # Class of executed instruction
3608968SN/Asystem.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
3618968SN/Asystem.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
36210036SAli.Saidi@ARM.comsystem.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
36310892Sandreas.hansson@arm.comsystem.cpu1.numCycles                     10608777066                       # number of cpu cycles simulated
3648968SN/Asystem.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
3658968SN/Asystem.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
36610892Sandreas.hansson@arm.comsystem.cpu1.committedInsts                   48146757                       # Number of instructions committed
36710892Sandreas.hansson@arm.comsystem.cpu1.committedOps                     92113830                       # Number of ops (including micro ops) committed
36810892Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses             88441893                       # Number of integer alu accesses
36910645Snilay@cs.wisc.edusystem.cpu1.num_fp_alu_accesses                    48                       # Number of float alu accesses
37010892Sandreas.hansson@arm.comsystem.cpu1.num_func_calls                    1752446                       # number of times a function call or return occured
37110892Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts      8219760                       # number of instructions that are conditional controls
37210892Sandreas.hansson@arm.comsystem.cpu1.num_int_insts                    88441893                       # number of integer instructions
37310645Snilay@cs.wisc.edusystem.cpu1.num_fp_insts                           48                       # number of float instructions
37410892Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads          171408328                       # number of times the integer registers were read
37510892Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes          73196137                       # number of times the integer registers were written
37610645Snilay@cs.wisc.edusystem.cpu1.num_fp_register_reads                  48                       # number of times the floating registers were read
3778968SN/Asystem.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
37810892Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads            50924734                       # number of times the CC registers were read
37910892Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes           32745964                       # number of times the CC registers were written
38010892Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs                     14124901                       # number of memory refs
38110892Sandreas.hansson@arm.comsystem.cpu1.num_load_insts                    9133293                       # Number of load instructions
38210892Sandreas.hansson@arm.comsystem.cpu1.num_store_insts                   4991608                       # Number of store instructions
38310892Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles              10274072284.207695                       # Number of idle cycles
38410892Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles              334704781.792306                       # Number of busy cycles
38510892Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction                0.031550                       # Percentage of non-idle cycles
38610892Sandreas.hansson@arm.comsystem.cpu1.idle_fraction                    0.968450                       # Percentage of idle cycles
38710892Sandreas.hansson@arm.comsystem.cpu1.Branches                         10581617                       # Number of branches fetched
38810892Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass               169787      0.18%      0.18% # Class of executed instruction
38910892Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu                 77653530     84.30%     84.49% # Class of executed instruction
39010892Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult                   98479      0.11%     84.59% # Class of executed instruction
39110892Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv                    71918      0.08%     84.67% # Class of executed instruction
39210645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatAdd                      0      0.00%     84.67% # Class of executed instruction
39310645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatCmp                      0      0.00%     84.67% # Class of executed instruction
39410645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatCvt                     16      0.00%     84.67% # Class of executed instruction
39510645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatMult                     0      0.00%     84.67% # Class of executed instruction
39610645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatDiv                      0      0.00%     84.67% # Class of executed instruction
39710645Snilay@cs.wisc.edusystem.cpu1.op_class::FloatSqrt                     0      0.00%     84.67% # Class of executed instruction
39810645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAdd                       0      0.00%     84.67% # Class of executed instruction
39910645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAddAcc                    0      0.00%     84.67% # Class of executed instruction
40010645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAlu                       0      0.00%     84.67% # Class of executed instruction
40110645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdCmp                       0      0.00%     84.67% # Class of executed instruction
40210645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdCvt                       0      0.00%     84.67% # Class of executed instruction
40310645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMisc                      0      0.00%     84.67% # Class of executed instruction
40410645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMult                      0      0.00%     84.67% # Class of executed instruction
40510645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMultAcc                   0      0.00%     84.67% # Class of executed instruction
40610645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdShift                     0      0.00%     84.67% # Class of executed instruction
40710645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdShiftAcc                  0      0.00%     84.67% # Class of executed instruction
40810645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdSqrt                      0      0.00%     84.67% # Class of executed instruction
40910645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatAdd                  0      0.00%     84.67% # Class of executed instruction
41010645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatAlu                  0      0.00%     84.67% # Class of executed instruction
41110645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatCmp                  0      0.00%     84.67% # Class of executed instruction
41210645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatCvt                  0      0.00%     84.67% # Class of executed instruction
41310645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatDiv                  0      0.00%     84.67% # Class of executed instruction
41410645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMisc                 0      0.00%     84.67% # Class of executed instruction
41510645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMult                 0      0.00%     84.67% # Class of executed instruction
41610645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMultAcc              0      0.00%     84.67% # Class of executed instruction
41710645Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatSqrt                 0      0.00%     84.67% # Class of executed instruction
41810892Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead                 9129153      9.91%     94.58% # Class of executed instruction
41910892Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite                4991608      5.42%    100.00% # Class of executed instruction
42010220Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
42110220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
42210892Sandreas.hansson@arm.comsystem.cpu1.op_class::total                  92114491                       # Class of executed instruction
4238968SN/Asystem.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
4248968SN/Asystem.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
42510892Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq               842290                       # Transaction distribution
42610892Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp              842290                       # Transaction distribution
42710892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq               35657                       # Transaction distribution
42810892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp              35657                       # Transaction distribution
42910645Snilay@cs.wisc.edusystem.iobus.trans_dist::MessageReq              1791                       # Transaction distribution
43010645Snilay@cs.wisc.edusystem.iobus.trans_dist::MessageResp             1791                       # Transaction distribution
43110645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1702                       # Packet count per connected master and slave (bytes)
43210645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1646                       # Packet count per connected master and slave (bytes)
43310645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3348                       # Packet count per connected master and slave (bytes)
43410560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
43510645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         5758                       # Packet count per connected master and slave (bytes)
43610560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           88                       # Packet count per connected master and slave (bytes)
43710645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          968                       # Packet count per connected master and slave (bytes)
43810645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           66                       # Packet count per connected master and slave (bytes)
43910628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           38                       # Packet count per connected master and slave (bytes)
44010560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
44110892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       917434                       # Packet count per connected master and slave (bytes)
44210645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          964                       # Packet count per connected master and slave (bytes)
44310560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           90                       # Packet count per connected master and slave (bytes)
44410560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
44510645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        14814                       # Packet count per connected master and slave (bytes)
44610892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       729402                       # Packet count per connected master and slave (bytes)
44710645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          158                       # Packet count per connected master and slave (bytes)
44810560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         2126                       # Packet count per connected master and slave (bytes)
44910892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1671974                       # Packet count per connected master and slave (bytes)
45010560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           16                       # Packet count per connected master and slave (bytes)
45110560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
45210645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         5284                       # Packet count per connected master and slave (bytes)
45310560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           92                       # Packet count per connected master and slave (bytes)
45410645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          396                       # Packet count per connected master and slave (bytes)
45510645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           28                       # Packet count per connected master and slave (bytes)
45610628Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
45710892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        30330                       # Packet count per connected master and slave (bytes)
45810645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          384                       # Packet count per connected master and slave (bytes)
45910892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        30418                       # Packet count per connected master and slave (bytes)
46010645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        12448                       # Packet count per connected master and slave (bytes)
46110560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
46210560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
46310560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
46410560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
46510645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port           76                       # Packet count per connected master and slave (bytes)
46610645Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         4614                       # Packet count per connected master and slave (bytes)
46710892Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        84154                       # Packet count per connected master and slave (bytes)
46810892Sandreas.hansson@arm.comsystem.iobus.pkt_count::total                 1759476                       # Packet count per connected master and slave (bytes)
46910645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3404                       # Cumulative packet size per connected master and slave (bytes)
47010645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3292                       # Cumulative packet size per connected master and slave (bytes)
47110645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6696                       # Cumulative packet size per connected master and slave (bytes)
47210560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
47310645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3266                       # Cumulative packet size per connected master and slave (bytes)
47410560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          149                       # Cumulative packet size per connected master and slave (bytes)
47510645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          484                       # Cumulative packet size per connected master and slave (bytes)
47610645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           33                       # Cumulative packet size per connected master and slave (bytes)
47710628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           19                       # Cumulative packet size per connected master and slave (bytes)
47810560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
47910892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       458717                       # Cumulative packet size per connected master and slave (bytes)
48010645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1928                       # Cumulative packet size per connected master and slave (bytes)
48110560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           45                       # Cumulative packet size per connected master and slave (bytes)
48210560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
48310645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         7407                       # Cumulative packet size per connected master and slave (bytes)
48410892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1458798                       # Cumulative packet size per connected master and slave (bytes)
48510645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          316                       # Cumulative packet size per connected master and slave (bytes)
48610560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         4252                       # Cumulative packet size per connected master and slave (bytes)
48710892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1935448                       # Cumulative packet size per connected master and slave (bytes)
48810560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio            8                       # Cumulative packet size per connected master and slave (bytes)
48910560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
49010645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3394                       # Cumulative packet size per connected master and slave (bytes)
49110560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           72                       # Cumulative packet size per connected master and slave (bytes)
49210645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          198                       # Cumulative packet size per connected master and slave (bytes)
49310645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           14                       # Cumulative packet size per connected master and slave (bytes)
49410628Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
49510892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        15165                       # Cumulative packet size per connected master and slave (bytes)
49610645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          768                       # Cumulative packet size per connected master and slave (bytes)
49710892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        15209                       # Cumulative packet size per connected master and slave (bytes)
49810645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6224                       # Cumulative packet size per connected master and slave (bytes)
49910560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50010560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50110560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50210560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
50310645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          152                       # Cumulative packet size per connected master and slave (bytes)
50410645Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         9225                       # Cumulative packet size per connected master and slave (bytes)
50510892Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        50463                       # Cumulative packet size per connected master and slave (bytes)
50610892Sandreas.hansson@arm.comsystem.iobus.pkt_size::total                  1992607                       # Cumulative packet size per connected master and slave (bytes)
50710892Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy                43500                       # Layer occupancy (ticks)
50810560Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
50910892Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy                 6500                       # Layer occupancy (ticks)
51010560Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
51110892Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy              9032500                       # Layer occupancy (ticks)
51210560Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
51310892Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy               154500                       # Layer occupancy (ticks)
51410560Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
51510892Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy               940000                       # Layer occupancy (ticks)
51610560Sandreas.hansson@arm.comsystem.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
51710892Sandreas.hansson@arm.comsystem.iobus.reqLayer5.occupancy                92000                       # Layer occupancy (ticks)
51810560Sandreas.hansson@arm.comsystem.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
51910892Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy                52500                       # Layer occupancy (ticks)
52010560Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
52110892Sandreas.hansson@arm.comsystem.iobus.reqLayer7.occupancy             20247500                       # Layer occupancy (ticks)
52210560Sandreas.hansson@arm.comsystem.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
52310892Sandreas.hansson@arm.comsystem.iobus.reqLayer8.occupancy            458718000                       # Layer occupancy (ticks)
52410560Sandreas.hansson@arm.comsystem.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
52510892Sandreas.hansson@arm.comsystem.iobus.reqLayer9.occupancy              1157500                       # Layer occupancy (ticks)
52610560Sandreas.hansson@arm.comsystem.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
52710892Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy            30508000                       # Layer occupancy (ticks)
52810560Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
52910645Snilay@cs.wisc.edusystem.iobus.reqLayer12.occupancy                2000                       # Layer occupancy (ticks)
53010560Sandreas.hansson@arm.comsystem.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
53110892Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy            20468500                       # Layer occupancy (ticks)
53210560Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
53310892Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
53410560Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
53510892Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
53610560Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
53710892Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy                9000                       # Layer occupancy (ticks)
53810560Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
53910892Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy               11500                       # Layer occupancy (ticks)
54010560Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
54110892Sandreas.hansson@arm.comsystem.iobus.reqLayer18.occupancy           369412820                       # Layer occupancy (ticks)
54210560Sandreas.hansson@arm.comsystem.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
54310892Sandreas.hansson@arm.comsystem.iobus.reqLayer19.occupancy             7528580                       # Layer occupancy (ticks)
54410560Sandreas.hansson@arm.comsystem.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
54510892Sandreas.hansson@arm.comsystem.iobus.reqLayer21.occupancy             1593000                       # Layer occupancy (ticks)
54610560Sandreas.hansson@arm.comsystem.iobus.reqLayer21.utilization               0.0                       # Layer utilization (%)
54710892Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy             2422900                       # Layer occupancy (ticks)
54810560Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
54910892Sandreas.hansson@arm.comsystem.iobus.respLayer2.occupancy          1846190500                       # Layer occupancy (ticks)
55010560Sandreas.hansson@arm.comsystem.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
55110892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy            57610000                       # Layer occupancy (ticks)
55210560Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
55310560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
55410560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
55510560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
55610560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
55710560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_bytes      2987008                       # Number of bytes transfered via DMA writes.
55810560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_txs          813                       # Number of DMA write transactions.
55910560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
56010560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
56110560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
56210560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
56310560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
56410560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
56510560Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock                      500                       # Clock period in ticks
56610560Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
56710560Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
56810892Sandreas.hansson@arm.comsystem.ruby.delayHist::samples               10891010                       # delay histogram for all message
56910892Sandreas.hansson@arm.comsystem.ruby.delayHist::mean                  0.442869                       # delay histogram for all message
57010892Sandreas.hansson@arm.comsystem.ruby.delayHist::stdev                 1.830823                       # delay histogram for all message
57110892Sandreas.hansson@arm.comsystem.ruby.delayHist                    |    10288616     94.47%     94.47% |        1282      0.01%     94.48% |      600649      5.52%    100.00% |         161      0.00%    100.00% |         257      0.00%    100.00% |          11      0.00%    100.00% |          34      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
57210892Sandreas.hansson@arm.comsystem.ruby.delayHist::total                 10891010                       # delay histogram for all message
57310560Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::bucket_size            1                      
57410560Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::max_bucket            9                      
57510892Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::samples    152756591                      
57610645Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::mean       1.000166                      
57710645Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::gmean      1.000115                      
57810892Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::stdev      0.012901                      
57910892Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   152731162     99.98%     99.98% |       25429      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
58010892Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist::total     152756591                      
58110892Sandreas.hansson@arm.comsystem.ruby.latency_hist::bucket_size             128                      
58210892Sandreas.hansson@arm.comsystem.ruby.latency_hist::max_bucket             1279                      
58310892Sandreas.hansson@arm.comsystem.ruby.latency_hist::samples           152756590                      
58410892Sandreas.hansson@arm.comsystem.ruby.latency_hist::mean               3.433707                      
58510892Sandreas.hansson@arm.comsystem.ruby.latency_hist::gmean              3.107293                      
58610892Sandreas.hansson@arm.comsystem.ruby.latency_hist::stdev              5.733578                      
58710892Sandreas.hansson@arm.comsystem.ruby.latency_hist                 |   152719525     99.98%     99.98% |       28048      0.02%     99.99% |        2695      0.00%    100.00% |        3637      0.00%    100.00% |        2109      0.00%    100.00% |         523      0.00%    100.00% |           9      0.00%    100.00% |          20      0.00%    100.00% |          17      0.00%    100.00% |           7      0.00%    100.00%
58810892Sandreas.hansson@arm.comsystem.ruby.latency_hist::total             152756590                      
58910560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::bucket_size            1                      
59010560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::max_bucket            9                      
59110892Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::samples       150094333                      
59210560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::mean                  3                      
59310560Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::gmean          3.000000                      
59410892Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   150094333    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
59510892Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist::total         150094333                      
59610892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::bucket_size          128                      
59710892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::max_bucket         1279                      
59810892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::samples        2662257                      
59910892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::mean         27.885506                      
60010892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::gmean        22.530762                      
60110892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::stdev        35.745831                      
60210892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist            |     2625192     98.61%     98.61% |       28048      1.05%     99.66% |        2695      0.10%     99.76% |        3637      0.14%     99.90% |        2109      0.08%     99.98% |         523      0.02%    100.00% |           9      0.00%    100.00% |          20      0.00%    100.00% |          17      0.00%    100.00% |           7      0.00%    100.00%
60310892Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist::total          2662257                      
60410892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Dcache.demand_hits     11119260                       # Number of cache demand hits
60510892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Dcache.demand_misses       532503                       # Number of cache demand misses
60610892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Dcache.demand_accesses     11651763                       # Number of cache demand accesses
60710892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Icache.demand_hits     68488995                       # Number of cache demand hits
60810892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Icache.demand_misses       323914                       # Number of cache demand misses
60910892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.L1Icache.demand_accesses     68812909                       # Number of cache demand accesses
61010560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
61110560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
61210560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
61310560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
61410560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
61510560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.hits               0                       # number of prefetched blocks accessed
61610560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
61710560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
61810560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
61910892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.fully_busy_cycles            16                       # cycles for which number of transistions == max transitions
62010892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Dcache.demand_hits     12794938                       # Number of cache demand hits
62110892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Dcache.demand_misses      1313574                       # Number of cache demand misses
62210892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Dcache.demand_accesses     14108512                       # Number of cache demand accesses
62310892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Icache.demand_hits     57691140                       # Number of cache demand hits
62410892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Icache.demand_misses       492266                       # Number of cache demand misses
62510892Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.L1Icache.demand_accesses     58183406                       # Number of cache demand accesses
62610560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.miss_observed            0                       # number of misses observed
62710560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
62810560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.prefetches_requested            0                       # number of prefetch requests made
62910560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
63010560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
63110560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.hits               0                       # number of prefetched blocks accessed
63210560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
63310560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
63410560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
63510645Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.fully_busy_cycles             7                       # cycles for which number of transistions == max transitions
63610892Sandreas.hansson@arm.comsystem.ruby.l2_cntrl0.L2cache.demand_hits      2435460                       # Number of cache demand hits
63710892Sandreas.hansson@arm.comsystem.ruby.l2_cntrl0.L2cache.demand_misses       226797                       # Number of cache demand misses
63810892Sandreas.hansson@arm.comsystem.ruby.l2_cntrl0.L2cache.demand_accesses      2662257                       # Number of cache demand accesses
63910892Sandreas.hansson@arm.comsystem.ruby.l2_cntrl0.fully_busy_cycles             5                       # cycles for which number of transistions == max transitions
64010560Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock             1500                       # Clock period in ticks
64110892Sandreas.hansson@arm.comsystem.ruby.network.routers0.percent_links_utilized     0.030013                      
64210892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Control::0       856417                      
64310892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Request_Control::2        42660                      
64410892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Response_Data::1       884950                      
64510892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Response_Control::1       510141                      
64610892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Response_Control::2       507455                      
64710892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Writeback_Data::0       298492                      
64810892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Writeback_Data::1          178                      
64910892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_count.Writeback_Control::0       170402                      
65010892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Control::0      6851336                      
65110892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Request_Control::2       341280                      
65210892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Response_Data::1     63716400                      
65310892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Response_Control::1      4081128                      
65410892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Response_Control::2      4059640                      
65510892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Writeback_Data::0     21491424                      
65610892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Writeback_Data::1        12816                      
65710892Sandreas.hansson@arm.comsystem.ruby.network.routers0.msg_bytes.Writeback_Control::0      1363216                      
65810892Sandreas.hansson@arm.comsystem.ruby.network.routers1.percent_links_utilized     0.057139                      
65910892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Control::0      1805840                      
66010892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Request_Control::2        40537                      
66110892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Response_Data::1      1830038                      
66210892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Response_Control::1      1255303                      
66310892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Response_Control::2      1254313                      
66410892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Writeback_Data::0       276120                      
66510892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Writeback_Data::1          190                      
66610892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_count.Writeback_Control::0       940436                      
66710892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Control::0     14446720                      
66810892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Request_Control::2       324296                      
66910892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Response_Data::1    131762736                      
67010892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Response_Control::1     10042424                      
67110892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Response_Control::2     10034504                      
67210892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Writeback_Data::0     19880640                      
67310892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Writeback_Data::1        13680                      
67410892Sandreas.hansson@arm.comsystem.ruby.network.routers1.msg_bytes.Writeback_Control::0      7523488                      
67510892Sandreas.hansson@arm.comsystem.ruby.network.routers2.percent_links_utilized     0.091475                      
67610892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Control::0      2839469                      
67710892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Request_Control::2        81710                      
67810892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Response_Data::1      2890401                      
67910892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Response_Control::1      1846120                      
68010892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Response_Control::2      1761768                      
68110892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Writeback_Data::0       574612                      
68210892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Writeback_Data::1          368                      
68310892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_count.Writeback_Control::0      1110838                      
68410892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Control::0     22715752                      
68510892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Request_Control::2       653680                      
68610892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Response_Data::1    208108872                      
68710892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Response_Control::1     14768960                      
68810892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Response_Control::2     14094144                      
68910892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Writeback_Data::0     41372064                      
69010892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Writeback_Data::1        26496                      
69110892Sandreas.hansson@arm.comsystem.ruby.network.routers2.msg_bytes.Writeback_Control::0      8886704                      
69210892Sandreas.hansson@arm.comsystem.ruby.network.routers3.percent_links_utilized     0.006783                      
69310892Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Control::0       177212                      
69410892Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Response_Data::1       275392                      
69510892Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Response_Control::1       129266                      
69610645Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Writeback_Control::0        47545                      
69710560Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Writeback_Control::1        46736                      
69810892Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Control::0      1417696                      
69910892Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Response_Data::1     19828224                      
70010892Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Response_Control::1      1034128                      
70110645Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Writeback_Control::0       380360                      
70210560Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Writeback_Control::1       373888                      
70310628Sandreas.hansson@arm.comsystem.ruby.network.routers4.percent_links_utilized     0.000239                      
70410645Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_count.Response_Data::1          809                      
70510645Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_count.Writeback_Control::0        47545                      
70610560Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_count.Writeback_Control::1        46736                      
70710645Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_bytes.Response_Data::1        58248                      
70810645Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_bytes.Writeback_Control::0       380360                      
70910560Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_bytes.Writeback_Control::1       373888                      
71010560Sandreas.hansson@arm.comsystem.ruby.network.routers5.percent_links_utilized            0                      
71110892Sandreas.hansson@arm.comsystem.ruby.network.routers6.percent_links_utilized     0.030942                      
71210892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Control::0      2839469                      
71310892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Request_Control::2        83197                      
71410892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Response_Data::1      2940795                      
71510892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Response_Control::1      1870415                      
71610892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Response_Control::2      1761768                      
71710892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Writeback_Data::0       574612                      
71810892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Writeback_Data::1          368                      
71910892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Writeback_Control::0      1158383                      
72010560Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Writeback_Control::1        46736                      
72110892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Control::0     22715752                      
72210892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Request_Control::2       665576                      
72310892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Response_Data::1    211737240                      
72410892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Response_Control::1     14963320                      
72510892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Response_Control::2     14094144                      
72610892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Writeback_Data::0     41372064                      
72710892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Writeback_Data::1        26496                      
72810892Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Writeback_Control::0      9267064                      
72910560Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Writeback_Control::1       373888                      
73010892Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Control         8518407                      
73110892Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Request_Control       248104                      
73210892Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Response_Data      8822385                      
73310892Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Response_Control     10896549                      
73410892Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Writeback_Data      1724940                      
73510892Sandreas.hansson@arm.comsystem.ruby.network.msg_count.Writeback_Control      3615357                      
73610892Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Control         68147256                      
73710892Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Request_Control      1984832                      
73810892Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Response_Data    635211720                      
73910892Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Response_Control     87172392                      
74010892Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Writeback_Data    124195680                      
74110892Sandreas.hansson@arm.comsystem.ruby.network.msg_byte.Writeback_Control     28922856                      
74210892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.link_utilization     0.038328                      
74310892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_count.Request_Control::2        42660                      
74410892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_count.Response_Data::1       844192                      
74510892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_count.Response_Control::1       494162                      
74610892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2       341280                      
74710892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1     60781824                      
74810892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1      3953296                      
74910892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.link_utilization     0.021698                      
75010892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Control::0       856417                      
75110892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Response_Data::1        40758                      
75210892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Response_Control::1        15979                      
75310892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Response_Control::2       507455                      
75410892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0       298492                      
75510892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1          178                      
75610892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0       170402                      
75710892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Control::0      6851336                      
75810892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1      2934576                      
75910892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1       127832                      
76010892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2      4059640                      
76110892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0     21491424                      
76210892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        12816                      
76310892Sandreas.hansson@arm.comsystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0      1363216                      
76410892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.link_utilization     0.082169                      
76510892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_count.Request_Control::2        40537                      
76610892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_count.Response_Data::1      1795610                      
76710892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_count.Response_Control::1      1238038                      
76810892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2       324296                      
76910892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1    129283920                      
77010892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1      9904304                      
77110892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.link_utilization     0.032108                      
77210892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Control::0      1805840                      
77310892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Data::1        34428                      
77410892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Control::1        17265                      
77510892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Control::2      1254313                      
77610892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0       276120                      
77710892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1          190                      
77810892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0       940436                      
77910892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Control::0     14446720                      
78010892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1      2478816                      
78110892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1       138120                      
78210892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2     10034504                      
78310892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0     19880640                      
78410892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1        13680                      
78510892Sandreas.hansson@arm.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0      7523488                      
78610892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.link_utilization     0.059642                      
78710892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Control::0      2662257                      
78810892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Data::1       202813                      
78910892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Control::1       123155                      
79010892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Control::2      1761768                      
79110892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0       574612                      
79210892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1          368                      
79310892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0      1110838                      
79410892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Control::0     21298056                      
79510892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1     14602536                      
79610892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1       985240                      
79710892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2     14094144                      
79810892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0     41372064                      
79910892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1        26496                      
80010892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0      8886704                      
80110892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.link_utilization     0.123308                      
80210892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_count.Control::0       177212                      
80310892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_count.Request_Control::2        81710                      
80410892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_count.Response_Data::1      2687588                      
80510892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_count.Response_Control::1      1722965                      
80610892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_bytes.Control::0      1417696                      
80710892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2       653680                      
80810892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1    193506336                      
80910892Sandreas.hansson@arm.comsystem.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1     13783720                      
81010892Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle0.link_utilization     0.005259                      
81110892Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle0.msg_count.Control::0       177212                      
81210892Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle0.msg_count.Response_Data::1        97371                      
81310892Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle0.msg_count.Response_Control::1        15060                      
81410645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0        47545                      
81510892Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle0.msg_bytes.Control::0      1417696                      
81610892Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1      7010712                      
81710892Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1       120480                      
81810645Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0       380360                      
81910892Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle1.link_utilization     0.008307                      
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82110892Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle1.msg_count.Response_Control::1       114206                      
8229978SN/Asystem.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1        46736                      
82310892Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1     12817512                      
82410892Sandreas.hansson@arm.comsystem.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1       913648                      
8259978SN/Asystem.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1       373888                      
82610526Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.link_utilization     0.000255                      
82710645Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.msg_count.Response_Data::1          809                      
8289978SN/Asystem.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1        46736                      
82910645Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1        58248                      
8309978SN/Asystem.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1       373888                      
8319978SN/Asystem.ruby.network.routers4.throttle1.link_utilization     0.000224                      
83210645Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0        47545                      
83310645Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0       380360                      
83410526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle0.link_utilization            0                      
83510526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle1.link_utilization            0                      
83610892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.link_utilization     0.038328                      
83710892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.msg_count.Request_Control::2        42660                      
83810892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.msg_count.Response_Data::1       844192                      
83910892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.msg_count.Response_Control::1       494162                      
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84110892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1     60781824                      
84210892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1      3953296                      
84310892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.link_utilization     0.082169                      
84410892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.msg_count.Request_Control::2        40537                      
84510892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.msg_count.Response_Data::1      1795610                      
84610892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.msg_count.Response_Control::1      1238038                      
84710892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2       324296                      
84810892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1    129283920                      
84910892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1      9904304                      
85010892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.link_utilization     0.059642                      
85110892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Control::0      2662257                      
85210892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Response_Data::1       202813                      
85310892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Response_Control::1       123155                      
85410892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Response_Control::2      1761768                      
85510892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0       574612                      
85610892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1          368                      
85710892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0      1110838                      
85810892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Control::0     21298056                      
85910892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1     14602536                      
86010892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1       985240                      
86110892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2     14094144                      
86210892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0     41372064                      
86310892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1        26496                      
86410892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0      8886704                      
86510892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.link_utilization     0.005259                      
86610892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_count.Control::0       177212                      
86710892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_count.Response_Data::1        97371                      
86810892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_count.Response_Control::1        15060                      
86910645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0        47545                      
87010892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_bytes.Control::0      1417696                      
87110892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1      7010712                      
87210892Sandreas.hansson@arm.comsystem.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1       120480                      
87310645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0       380360                      
87410526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.link_utilization     0.000255                      
87510645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_count.Response_Data::1          809                      
87610526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1        46736                      
87710645Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1        58248                      
87810526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1       373888                      
87910526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle5.link_utilization            0                      
88010229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
88110229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
88210892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_0::samples       6109475                       # delay histogram for vnet_0
88310892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_0::mean         0.754420                       # delay histogram for vnet_0
88410892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_0::stdev        2.340404                       # delay histogram for vnet_0
88510892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_0           |     5533989     90.58%     90.58% |         406      0.01%     90.59% |      574630      9.41%     99.99% |         158      0.00%    100.00% |         247      0.00%    100.00% |          11      0.00%    100.00% |          34      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
88610892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_0::total         6109475                       # delay histogram for vnet_0
88710229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
88810229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
88910892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::samples       4698338                       # delay histogram for vnet_1
89010892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::mean         0.045583                       # delay histogram for vnet_1
89110892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::stdev        0.599791                       # delay histogram for vnet_1
89210892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1           |     4670953     99.42%     99.42% |         477      0.01%     99.43% |         336      0.01%     99.43% |         540      0.01%     99.45% |       25880      0.55%    100.00% |         139      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |          10      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_1
89310892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_1::total         4698338                       # delay histogram for vnet_1
89410315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
89510315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
89610892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2::samples         83197                       # delay histogram for vnet_2
89710892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2::mean         0.000192                       # delay histogram for vnet_2
89810892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2::stdev        0.019611                       # delay histogram for vnet_2
89910892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2           |       83189     99.99%     99.99% |           0      0.00%     99.99% |           8      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
90010892Sandreas.hansson@arm.comsystem.ruby.delayVCHist.vnet_2::total           83197                       # delay histogram for vnet_2
90110628Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::bucket_size          128                      
90210628Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::max_bucket          1279                      
90310892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::samples         15027912                      
90410892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::mean            4.869020                      
90510892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::gmean           3.591147                      
90610892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::stdev           9.231737                      
90710892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist              |    15011958     99.89%     99.89% |       13851      0.09%     99.99% |         851      0.01%     99.99% |         792      0.01%    100.00% |         329      0.00%    100.00% |         121      0.00%    100.00% |           2      0.00%    100.00% |           3      0.00%    100.00% |           4      0.00%    100.00% |           1      0.00%    100.00%
90810892Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist::total           15027912                      
90910013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size            1                      
91010013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket            9                      
91110892Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist::samples     13637263                      
91210013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean               3                      
91310013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean       3.000000                      
91410892Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |    13637263    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
91510892Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist::total       13637263                      
91610628Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::bucket_size          128                      
91710628Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::max_bucket         1279                      
91810892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::samples      1390649                      
91910892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::mean      23.197386                      
92010892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::gmean     20.952196                      
92110892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::stdev     23.468925                      
92210892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist         |     1374695     98.85%     98.85% |       13851      1.00%     99.85% |         851      0.06%     99.91% |         792      0.06%     99.97% |         329      0.02%     99.99% |         121      0.01%    100.00% |           2      0.00%    100.00% |           3      0.00%    100.00% |           4      0.00%    100.00% |           1      0.00%    100.00%
92310892Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist::total       1390649                      
92410892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::bucket_size          128                      
92510892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::max_bucket          1279                      
92610892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::samples          9558783                      
92710892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::mean            5.170026                      
92810892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::gmean           3.300098                      
92910892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::stdev          17.579302                      
93010892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist              |     9544781     99.85%     99.85% |        8164      0.09%     99.94% |        1330      0.01%     99.95% |        2504      0.03%     99.98% |        1628      0.02%    100.00% |         340      0.00%    100.00% |           7      0.00%    100.00% |          12      0.00%    100.00% |          11      0.00%    100.00% |           6      0.00%    100.00%
93110892Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist::total            9558783                      
93210013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size            1                      
93310013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket            9                      
93410892Sandreas.hansson@arm.comsystem.ruby.ST.hit_latency_hist::samples      9207752                      
93510013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean               3                      
93610013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean       3.000000                      
93710892Sandreas.hansson@arm.comsystem.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |     9207752    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
93810892Sandreas.hansson@arm.comsystem.ruby.ST.hit_latency_hist::total        9207752                      
93910892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::bucket_size          128                      
94010892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::max_bucket         1279                      
94110892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::samples       351031                      
94210892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::mean      62.091086                      
94310892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::gmean     40.236579                      
94410892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::stdev     71.074662                      
94510892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist         |      337029     96.01%     96.01% |        8164      2.33%     98.34% |        1330      0.38%     98.72% |        2504      0.71%     99.43% |        1628      0.46%     99.89% |         340      0.10%     99.99% |           7      0.00%     99.99% |          12      0.00%    100.00% |          11      0.00%    100.00% |           6      0.00%    100.00%
94610892Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist::total        351031                      
94710526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size          128                      
94810526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket         1279                      
94910892Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::samples    126996315                      
95010892Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::mean        3.119134                      
95110892Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::gmean       3.036572                      
95210892Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::stdev       2.233716                      
95310892Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist          |   126989642     99.99%     99.99% |        5673      0.00%    100.00% |         484      0.00%    100.00% |         317      0.00%    100.00% |         137      0.00%    100.00% |          55      0.00%    100.00% |           0      0.00%    100.00% |           5      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
95410892Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist::total      126996315                      
95510013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
95610013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
95710892Sandreas.hansson@arm.comsystem.ruby.IFETCH.hit_latency_hist::samples    126180135                      
95810013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean            3                      
95910013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean     3.000000                      
96010892Sandreas.hansson@arm.comsystem.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   126180135    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
96110892Sandreas.hansson@arm.comsystem.ruby.IFETCH.hit_latency_hist::total    126180135                      
96210526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size          128                      
96310526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket         1279                      
96410892Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::samples       816180                      
96510892Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::mean    21.537108                      
96610892Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::gmean    19.766480                      
96710892Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::stdev    20.855244                      
96810892Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist     |      809507     99.18%     99.18% |        5673      0.70%     99.88% |         484      0.06%     99.94% |         317      0.04%     99.98% |         137      0.02%     99.99% |          55      0.01%    100.00% |           0      0.00%    100.00% |           5      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
96910892Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist::total       816180                      
97010526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::bucket_size          128                      
97110526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::max_bucket         1279                      
97210892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist::samples       494272                      
97310892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist::mean      6.020764                      
97410892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist::gmean     3.952362                      
97510892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist::stdev    10.313773                      
97610892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist        |      494092     99.96%     99.96% |         129      0.03%     99.99% |          18      0.00%     99.99% |          18      0.00%    100.00% |          11      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
97710892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist::total       494272                      
97810013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::bucket_size            1                      
97910013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::max_bucket            9                      
98010892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.hit_latency_hist::samples       428940                      
98110013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::mean            3                      
98210013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::gmean     3.000000                      
98310892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      428940    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
98410892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.hit_latency_hist::total       428940                      
98510526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::bucket_size          128                      
98610526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::max_bucket         1279                      
98710892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist::samples        65332                      
98810892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist::mean    25.853716                      
98910892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist::gmean    24.153784                      
99010892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist::stdev    18.748956                      
99110892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist   |       65152     99.72%     99.72% |         129      0.20%     99.92% |          18      0.03%     99.95% |          18      0.03%     99.98% |          11      0.02%     99.99% |           4      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
99210892Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist::total        65332                      
99310645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::bucket_size          128                      
99410645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::max_bucket         1279                      
99510892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::samples       339654                      
99610892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::mean     5.351331                      
99710892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::gmean     3.780101                      
99810892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::stdev     8.370233                      
99910892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist |      339398     99.92%     99.92% |         231      0.07%     99.99% |          12      0.00%    100.00% |           6      0.00%    100.00% |           4      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
100010892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist::total       339654                      
100110013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size            1                      
100210013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket            9                      
100310892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.hit_latency_hist::samples       300589                      
100410013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::mean            3                      
100510013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::gmean     3.000000                      
100610892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      300589    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
100710892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.hit_latency_hist::total       300589                      
100810645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size          128                      
100910645Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket         1279                      
101010892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::samples        39065                      
101110892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::mean    23.443850                      
101210892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::gmean    22.382210                      
101310892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::stdev    15.468459                      
101410892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist |       38809     99.34%     99.34% |         231      0.59%     99.94% |          12      0.03%     99.97% |           6      0.02%     99.98% |           4      0.01%     99.99% |           3      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
101510892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist::total        39065                      
101610013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::bucket_size            1                      
101710013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::max_bucket            9                      
101810892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.latency_hist::samples       339654                      
101910013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::mean            3                      
102010013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::gmean     3.000000                      
102110892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339654    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
102210892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.latency_hist::total       339654                      
102310013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size            1                      
102410013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket            9                      
102510892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.hit_latency_hist::samples       339654                      
102610013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::mean            3                      
102710013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::gmean     3.000000                      
102810892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339654    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
102910892Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.hit_latency_hist::total       339654                      
103010892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Fetch         177212      0.00%      0.00%
103110892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Data           97371      0.00%      0.00%
103210892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Data       177674      0.00%      0.00%
103310892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.Memory_Ack       142679      0.00%      0.00%
103410645Snilay@cs.wisc.edusystem.ruby.Directory_Controller.DMA_READ          809      0.00%      0.00%
103510560Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.DMA_WRITE        46736      0.00%      0.00%
103610892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.CleanReplacement        15060      0.00%      0.00%
103710892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.I.Fetch       177212      0.00%      0.00%
103810892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.I.DMA_READ          462      0.00%      0.00%
103910892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.I.DMA_WRITE        45308      0.00%      0.00%
104010892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.ID.Memory_Data          462      0.00%      0.00%
104110892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.ID_W.Memory_Ack        45308      0.00%      0.00%
104210892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.Data         95596      0.00%      0.00%
104310892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.DMA_READ          347      0.00%      0.00%
104410892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.DMA_WRITE         1428      0.00%      0.00%
104510892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M.CleanReplacement        15060      0.00%      0.00%
104610892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.IM.Memory_Data       177212      0.00%      0.00%
104710892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.MI.Memory_Ack        95596      0.00%      0.00%
104810892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M_DRD.Data          347      0.00%      0.00%
104910892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M_DRDI.Memory_Ack          347      0.00%      0.00%
105010892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M_DWR.Data         1428      0.00%      0.00%
105110892Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.M_DWRI.Memory_Ack         1428      0.00%      0.00%
105210645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.ReadRequest   |         809    100.00%    100.00% |           0      0.00%    100.00%
105310645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.ReadRequest::total          809                      
105410560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.WriteRequest  |       46736    100.00%    100.00% |           0      0.00%    100.00%
105510560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.WriteRequest::total        46736                      
105610645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.Data          |         809    100.00%    100.00% |           0      0.00%    100.00%
105710645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.Data::total            809                      
105810560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Ack           |       46736    100.00%    100.00% |           0      0.00%    100.00%
105910560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Ack::total           46736                      
106010645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.READY.ReadRequest |         809    100.00%    100.00% |           0      0.00%    100.00%
106110645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.READY.ReadRequest::total          809                      
106210560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.WriteRequest |       46736    100.00%    100.00% |           0      0.00%    100.00%
106310560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.WriteRequest::total        46736                      
106410645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.BUSY_RD.Data  |         809    100.00%    100.00% |           0      0.00%    100.00%
106510645Snilay@cs.wisc.edusystem.ruby.DMA_Controller.BUSY_RD.Data::total          809                      
106610560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_WR.Ack   |       46736    100.00%    100.00% |           0      0.00%    100.00%
106710560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_WR.Ack::total        46736                      
106810892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Load      |     6279317     41.78%     41.78% |     8748595     58.22%    100.00%
106910892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Load::total     15027912                      
107010892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ifetch    |    68812914     54.18%     54.18% |    58183407     45.82%    100.00%
107110892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ifetch::total    126996321                      
107210892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Store     |     5372446     50.06%     50.06% |     5359917     49.94%    100.00%
107310892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Store::total     10732363                      
107410892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Inv       |       16157     48.07%     48.07% |       17455     51.93%    100.00%
107510892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Inv::total        33612                      
107610892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.L1_Replacement |      828605     31.79%     31.79% |     1777971     68.21%    100.00%
107710892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.L1_Replacement::total      2606576                      
107810892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Fwd_GETX  |       12248     51.07%     51.07% |       11736     48.93%    100.00%
107910892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Fwd_GETX::total        23984                      
108010892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Fwd_GETS  |       14251     55.67%     55.67% |       11346     44.33%    100.00%
108110892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Fwd_GETS::total        25597                      
108210013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
108310013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR::total            4                      
108410892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data      |         818     44.46%     44.46% |        1022     55.54%    100.00%
108510892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data::total         1840                      
108610892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data_Exclusive |      252712     19.73%     19.73% |     1028027     80.27%    100.00%
108710892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data_Exclusive::total      1280739                      
108810892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.DataS_fromL1 |       11346     44.32%     44.32% |       14255     55.68%    100.00%
108910892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.DataS_fromL1::total        25601                      
109010892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data_all_Acks |      579316     43.50%     43.50% |      752306     56.50%    100.00%
109110892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Data_all_Acks::total      1331622                      
109210892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ack       |       12225     54.44%     54.44% |       10230     45.56%    100.00%
109310892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ack::total        22455                      
109410892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ack_all   |       13043     53.69%     53.69% |       11252     46.31%    100.00%
109510892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.Ack_all::total        24295                      
109610892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.WB_Ack    |      468894     27.82%     27.82% |     1216556     72.18%    100.00%
109710892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.WB_Ack::total      1685450                      
109810892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Load   |      280382     20.44%     20.44% |     1091184     79.56%    100.00%
109910892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Load::total      1371566                      
110010892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Ifetch |      323814     39.71%     39.71% |      491732     60.29%    100.00%
110110892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Ifetch::total       815546                      
110210892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Store  |      225433     53.48%     53.48% |      196079     46.52%    100.00%
110310892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Store::total       421512                      
110410892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Inv    |        4849     54.09%     54.09% |        4115     45.91%    100.00%
110510892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.NP.Inv::total         8964                      
110610892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Load    |        8724     45.72%     45.72% |       10359     54.28%    100.00%
110710892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Load::total        19083                      
110810892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Ifetch  |         100     15.77%     15.77% |         534     84.23%    100.00%
110910892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Ifetch::total          634                      
111010892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Store   |        5739     50.07%     50.07% |        5722     49.93%    100.00%
111110892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.Store::total        11461                      
111210892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.L1_Replacement |        8993     51.78%     51.78% |        8375     48.22%    100.00%
111310892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.I.L1_Replacement::total        17368                      
111410892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Load    |      555624     51.88%     51.88% |      515377     48.12%    100.00%
111510892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Load::total      1071001                      
111610892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Ifetch  |    68488995     54.28%     54.28% |    57691140     45.72%    100.00%
111710892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Ifetch::total    126180135                      
111810892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Store   |       12225     54.44%     54.44% |       10230     45.56%    100.00%
111910892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Store::total        22455                      
112010892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Inv     |       11078     45.79%     45.79% |       13115     54.21%    100.00%
112110892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.Inv::total        24193                      
112210892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.L1_Replacement |      350718     38.81%     38.81% |      553040     61.19%    100.00%
112310892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.S.L1_Replacement::total       903758                      
112410892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Load    |     1152084     29.74%     29.74% |     2722150     70.26%    100.00%
112510892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Load::total      3874234                      
112610892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Store   |       80726     48.37%     48.37% |       86165     51.63%    100.00%
112710892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Store::total       166891                      
112810892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Inv     |          52     59.77%     59.77% |          35     40.23%    100.00%
112910892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Inv::total           87                      
113010892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.L1_Replacement |      170402     15.34%     15.34% |      940436     84.66%    100.00%
113110892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.L1_Replacement::total      1110838                      
113210892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Fwd_GETX |         330     72.53%     72.53% |         125     27.47%    100.00%
113310892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Fwd_GETX::total          455                      
113410892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Fwd_GETS |         996     45.17%     45.17% |        1209     54.83%    100.00%
113510892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.E.Fwd_GETS::total         2205                      
113610892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Load    |     4282503     49.27%     49.27% |     4409525     50.73%    100.00%
113710892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Load::total      8692028                      
113810892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Store   |     5048323     49.93%     49.93% |     5061721     50.07%    100.00%
113910892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Store::total     10110044                      
114010892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Inv     |         178     48.37%     48.37% |         190     51.63%    100.00%
114110892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Inv::total          368                      
114210892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.L1_Replacement |      298492     51.95%     51.95% |      276120     48.05%    100.00%
114310892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.L1_Replacement::total       574612                      
114410892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Fwd_GETX |       11918     50.65%     50.65% |       11611     49.35%    100.00%
114510892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Fwd_GETX::total        23529                      
114610892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Fwd_GETS |       13255     56.66%     56.66% |       10137     43.34%    100.00%
114710892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M.Fwd_GETS::total        23392                      
114810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
114910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total            4                      
115010892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.Data_Exclusive |      252712     19.73%     19.73% |     1028027     80.27%    100.00%
115110892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1280739                      
115210892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.DataS_fromL1 |       11346     44.32%     44.32% |       14255     55.68%    100.00%
115310892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.DataS_fromL1::total        25601                      
115410892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.Data_all_Acks |      348962     38.75%     38.75% |      551527     61.25%    100.00%
115510892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IS.Data_all_Acks::total       900489                      
115610892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IM.Data   |         818     44.46%     44.46% |        1022     55.54%    100.00%
115710892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IM.Data::total         1840                      
115810892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IM.Data_all_Acks |      230354     53.43%     53.43% |      200779     46.57%    100.00%
115910892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.IM.Data_all_Acks::total       431133                      
116010892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.SM.Ack    |       12225     54.44%     54.44% |       10230     45.56%    100.00%
116110892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.SM.Ack::total        22455                      
116210892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.SM.Ack_all |       13043     53.69%     53.69% |       11252     46.31%    100.00%
116310892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.SM.Ack_all::total        24295                      
116410645Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.Ifetch |           5     83.33%     83.33% |           1     16.67%    100.00%
116510628Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M_I.Ifetch::total            6                      
116610892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M_I.WB_Ack |      468894     27.82%     27.82% |     1216556     72.18%    100.00%
116710892Sandreas.hansson@arm.comsystem.ruby.L1Cache_Controller.M_I.WB_Ack::total      1685450                      
116810892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L1_GET_INSTR       816180      0.00%      0.00%
116910892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L1_GETS        1390821      0.00%      0.00%
117010892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L1_GETX         432975      0.00%      0.00%
117110892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L1_UPGRADE        22455      0.00%      0.00%
117210892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L1_PUTX        1685450      0.00%      0.00%
117310892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L2_Replacement        95536      0.00%      0.00%
117410892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.L2_Replacement_clean        15120      0.00%      0.00%
117510892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Mem_Data        177212      0.00%      0.00%
117610892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Mem_Ack         112431      0.00%      0.00%
117710892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.WB_Data          23764      0.00%      0.00%
117810892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.WB_Data_clean         2205      0.00%      0.00%
117910892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Ack               1487      0.00%      0.00%
118010892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Ack_all           7462      0.00%      0.00%
118110892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Unblock          25601      0.00%      0.00%
118210892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.Exclusive_Unblock      1736167      0.00%      0.00%
118310892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MEM_Inv           3550      0.00%      0.00%
118410892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.NP.L1_GET_INSTR        16316      0.00%      0.00%
118510892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.NP.L1_GETS        33914      0.00%      0.00%
118610892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.NP.L1_GETX       126982      0.00%      0.00%
118710892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L1_GET_INSTR       799834      0.00%      0.00%
118810892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L1_GETS        84313      0.00%      0.00%
118910892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L1_GETX         1944      0.00%      0.00%
119010892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L1_UPGRADE        22455      0.00%      0.00%
119110892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L2_Replacement          252      0.00%      0.00%
119210892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.L2_Replacement_clean         7120      0.00%      0.00%
119310645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.MEM_Inv            3      0.00%      0.00%
119410628Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L1_GET_INSTR           26      0.00%      0.00%
119510892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L1_GETS      1246825      0.00%      0.00%
119610892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L1_GETX       280063      0.00%      0.00%
119710892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L2_Replacement        95163      0.00%      0.00%
119810892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L2_Replacement_clean         7896      0.00%      0.00%
119910892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.MEM_Inv         1542      0.00%      0.00%
120010013Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GET_INSTR            4      0.00%      0.00%
120110892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.L1_GETS        25597      0.00%      0.00%
120210892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.L1_GETX        23984      0.00%      0.00%
120310892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.L1_PUTX      1685450      0.00%      0.00%
120410892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.L2_Replacement          121      0.00%      0.00%
120510892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.L2_Replacement_clean          104      0.00%      0.00%
120610645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.MEM_Inv          230      0.00%      0.00%
120710892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M_I.Mem_Ack       112431      0.00%      0.00%
120810892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M_I.MEM_Inv         1542      0.00%      0.00%
120910892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_I.WB_Data          308      0.00%      0.00%
121010892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_I.Ack_all           43      0.00%      0.00%
121110645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_I.MEM_Inv          230      0.00%      0.00%
121210645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MCT_I.WB_Data           60      0.00%      0.00%
121310892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MCT_I.Ack_all           44      0.00%      0.00%
121410892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.I_I.Ack           1232      0.00%      0.00%
121510892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.I_I.Ack_all         7120      0.00%      0.00%
121610892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.S_I.Ack            255      0.00%      0.00%
121710892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.S_I.Ack_all          255      0.00%      0.00%
121810645Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.S_I.MEM_Inv            3      0.00%      0.00%
121910892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.ISS.Mem_Data        33914      0.00%      0.00%
122010892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.IS.Mem_Data        16316      0.00%      0.00%
122110892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.IM.Mem_Data       126982      0.00%      0.00%
122210892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS_MB.L1_GETS          122      0.00%      0.00%
122310892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        24399      0.00%      0.00%
122410892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_MB.L1_GETS           50      0.00%      0.00%
122510892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_MB.L1_GETX            2      0.00%      0.00%
122610892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1711768      0.00%      0.00%
122710892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_IIB.WB_Data        23385      0.00%      0.00%
122810892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2205      0.00%      0.00%
122910892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_IIB.Unblock           11      0.00%      0.00%
123010892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_IB.WB_Data           11      0.00%      0.00%
123110892Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_SB.Unblock        25590      0.00%      0.00%
12328968SN/A
12338968SN/A---------- End Simulation Statistics   ----------
1234