stats.txt revision 10526
18968SN/A
28968SN/A---------- Begin Simulation Statistics ----------
310526Snilay@cs.wisc.edusim_seconds                                  5.300742                       # Number of seconds simulated
410526Snilay@cs.wisc.edusim_ticks                                5300741898500                       # Number of ticks simulated
510526Snilay@cs.wisc.edufinal_tick                               5300741898500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68968SN/Asim_freq                                 1000000000000                       # Frequency of simulated ticks
710526Snilay@cs.wisc.eduhost_inst_rate                                 150557                       # Simulator instruction rate (inst/s)
810526Snilay@cs.wisc.eduhost_op_rate                                   288657                       # Simulator op (including micro ops) rate (op/s)
910526Snilay@cs.wisc.eduhost_tick_rate                             7473061965                       # Simulator tick rate (ticks/s)
1010526Snilay@cs.wisc.eduhost_mem_usage                                 840444                       # Number of bytes of host memory used
1110526Snilay@cs.wisc.eduhost_seconds                                   709.31                       # Real time elapsed on the host
1210526Snilay@cs.wisc.edusim_insts                                   106792132                       # Number of instructions simulated
1310526Snilay@cs.wisc.edusim_ops                                     204747982                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                          1000                       # Clock period in ticks
1610526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::ruby.dir_cntrl0     11447360                       # Number of bytes read from this memory
1710526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_read::total           11447360                       # Number of bytes read from this memory
1810526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::ruby.dir_cntrl0      9142976                       # Number of bytes written to this memory
1910526Snilay@cs.wisc.edusystem.mem_ctrls.bytes_written::total         9142976                       # Number of bytes written to this memory
2010526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::ruby.dir_cntrl0       178865                       # Number of read requests responded to by this memory
2110526Snilay@cs.wisc.edusystem.mem_ctrls.num_reads::total              178865                       # Number of read requests responded to by this memory
2210526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::ruby.dir_cntrl0       142859                       # Number of write requests responded to by this memory
2310526Snilay@cs.wisc.edusystem.mem_ctrls.num_writes::total             142859                       # Number of write requests responded to by this memory
2410526Snilay@cs.wisc.edusystem.mem_ctrls.bw_read::ruby.dir_cntrl0      2159577                       # Total read bandwidth from this memory (bytes/s)
2510526Snilay@cs.wisc.edusystem.mem_ctrls.bw_read::total               2159577                       # Total read bandwidth from this memory (bytes/s)
2610526Snilay@cs.wisc.edusystem.mem_ctrls.bw_write::ruby.dir_cntrl0      1724848                       # Write bandwidth from this memory (bytes/s)
2710526Snilay@cs.wisc.edusystem.mem_ctrls.bw_write::total              1724848                       # Write bandwidth from this memory (bytes/s)
2810526Snilay@cs.wisc.edusystem.mem_ctrls.bw_total::ruby.dir_cntrl0      3884425                       # Total bandwidth to/from this memory (bytes/s)
2910526Snilay@cs.wisc.edusystem.mem_ctrls.bw_total::total              3884425                       # Total bandwidth to/from this memory (bytes/s)
3010526Snilay@cs.wisc.edusystem.mem_ctrls.readReqs                      178865                       # Number of read requests accepted
3110526Snilay@cs.wisc.edusystem.mem_ctrls.writeReqs                     142859                       # Number of write requests accepted
3210526Snilay@cs.wisc.edusystem.mem_ctrls.readBursts                    178865                       # Number of DRAM read bursts, including those serviced by the write queue
3310526Snilay@cs.wisc.edusystem.mem_ctrls.writeBursts                   142859                       # Number of DRAM write bursts, including those merged in the write queue
3410526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadDRAM               11390720                       # Total number of bytes read from DRAM
3510526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadWrQ                   56640                       # Total number of bytes read from write queue
3610526Snilay@cs.wisc.edusystem.mem_ctrls.bytesWritten                 9134848                       # Total number of bytes written to DRAM
3710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesReadSys                11447360                       # Total read bytes from the system interface side
3810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesWrittenSys              9142976                       # Total written bytes from the system interface side
3910526Snilay@cs.wisc.edusystem.mem_ctrls.servicedByWrQ                    885                       # Number of DRAM read bursts serviced by the write queue
4010526Snilay@cs.wisc.edusystem.mem_ctrls.mergedWrBursts                   106                       # Number of DRAM write bursts merged with an existing one
4110526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
4210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::0             11083                       # Per bank write bursts
4310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::1             10466                       # Per bank write bursts
4410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::2             10673                       # Per bank write bursts
4510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::3             10751                       # Per bank write bursts
4610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::4             11479                       # Per bank write bursts
4710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::5             11934                       # Per bank write bursts
4810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::6             10746                       # Per bank write bursts
4910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::7             10510                       # Per bank write bursts
5010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::8             10984                       # Per bank write bursts
5110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::9             10978                       # Per bank write bursts
5210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::10            10728                       # Per bank write bursts
5310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::11            13966                       # Per bank write bursts
5410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::12            10998                       # Per bank write bursts
5510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::13            10695                       # Per bank write bursts
5610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::14            11146                       # Per bank write bursts
5710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankRdBursts::15            10843                       # Per bank write bursts
5810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::0              9192                       # Per bank write bursts
5910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::1              8887                       # Per bank write bursts
6010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::2              8721                       # Per bank write bursts
6110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::3              8884                       # Per bank write bursts
6210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::4              9584                       # Per bank write bursts
6310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::5              9646                       # Per bank write bursts
6410526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::6              8803                       # Per bank write bursts
6510526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::7              8544                       # Per bank write bursts
6610526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::8              8749                       # Per bank write bursts
6710526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::9              8837                       # Per bank write bursts
6810526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::10             8942                       # Per bank write bursts
6910526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::11             8982                       # Per bank write bursts
7010526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::12             8616                       # Per bank write bursts
7110526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::13             8535                       # Per bank write bursts
7210526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::14             8942                       # Per bank write bursts
7310526Snilay@cs.wisc.edusystem.mem_ctrls.perBankWrBursts::15             8868                       # Per bank write bursts
7410526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
7510526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
7610526Snilay@cs.wisc.edusystem.mem_ctrls.totGap                  5300741764000                       # Total gap between requests
7710526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
8310526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::6                178865                       # Read request sizes (log2)
8410526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
9010526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::6               142859                       # Write request sizes (log2)
9110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::0                  177944                       # What read queue length does an incoming req see
9210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::1                      36                       # What read queue length does an incoming req see
9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
12310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
13810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::15                   2042                       # What write queue length does an incoming req see
13910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::16                   2762                       # What write queue length does an incoming req see
14010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::17                   8528                       # What write queue length does an incoming req see
14110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::18                   9126                       # What write queue length does an incoming req see
14210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::19                   8582                       # What write queue length does an incoming req see
14310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::20                   9159                       # What write queue length does an incoming req see
14410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::21                   9214                       # What write queue length does an incoming req see
14510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::22                   8343                       # What write queue length does an incoming req see
14610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::23                   9016                       # What write queue length does an incoming req see
14710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::24                   9104                       # What write queue length does an incoming req see
14810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::25                   8438                       # What write queue length does an incoming req see
14910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::26                   8502                       # What write queue length does an incoming req see
15010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::27                   8352                       # What write queue length does an incoming req see
15110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::28                   8474                       # What write queue length does an incoming req see
15210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::29                   8065                       # What write queue length does an incoming req see
15310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::30                   8107                       # What write queue length does an incoming req see
15410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::31                   8180                       # What write queue length does an incoming req see
15510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::32                   7958                       # What write queue length does an incoming req see
15610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::33                    136                       # What write queue length does an incoming req see
15710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::34                    116                       # What write queue length does an incoming req see
15810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::35                    100                       # What write queue length does an incoming req see
15910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::36                     96                       # What write queue length does an incoming req see
16010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::37                     84                       # What write queue length does an incoming req see
16110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::38                     72                       # What write queue length does an incoming req see
16210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::39                     61                       # What write queue length does an incoming req see
16310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::40                     49                       # What write queue length does an incoming req see
16410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::41                     32                       # What write queue length does an incoming req see
16510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::42                     21                       # What write queue length does an incoming req see
16610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::43                     11                       # What write queue length does an incoming req see
16710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::44                      5                       # What write queue length does an incoming req see
16810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::45                      2                       # What write queue length does an incoming req see
16910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::46                      1                       # What write queue length does an incoming req see
17010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
18710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::samples        60353                       # Bytes accessed per row activation
18810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::mean    340.090865                       # Bytes accessed per row activation
18910526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::gmean   200.552614                       # Bytes accessed per row activation
19010526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::stdev   345.449556                       # Bytes accessed per row activation
19110526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::0-127        20341     33.70%     33.70% # Bytes accessed per row activation
19210526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::128-255        14451     23.94%     57.65% # Bytes accessed per row activation
19310526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::256-383         6322     10.48%     68.12% # Bytes accessed per row activation
19410526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::384-511         3381      5.60%     73.72% # Bytes accessed per row activation
19510526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::512-639         2729      4.52%     78.25% # Bytes accessed per row activation
19610526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::640-767         1822      3.02%     81.27% # Bytes accessed per row activation
19710526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::768-895         1379      2.28%     83.55% # Bytes accessed per row activation
19810526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::896-1023         1383      2.29%     85.84% # Bytes accessed per row activation
19910526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::1024-1151         8545     14.16%    100.00% # Bytes accessed per row activation
20010526Snilay@cs.wisc.edusystem.mem_ctrls.bytesPerActivate::total        60353                       # Bytes accessed per row activation
20110526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::samples         7902                       # Reads before turning the bus around for writes
20210526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::mean      22.522399                       # Reads before turning the bus around for writes
20310526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::stdev    318.068462                       # Reads before turning the bus around for writes
20410526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::0-1023         7896     99.92%     99.92% # Reads before turning the bus around for writes
20510526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::1024-2047            2      0.03%     99.95% # Reads before turning the bus around for writes
20610526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::2048-3071            2      0.03%     99.97% # Reads before turning the bus around for writes
20710526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::10240-11263            1      0.01%     99.99% # Reads before turning the bus around for writes
20810526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
20910526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::total          7902                       # Reads before turning the bus around for writes
21010526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::samples         7902                       # Writes before turning the bus around for reads
21110526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::mean      18.062769                       # Writes before turning the bus around for reads
21210526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::gmean     17.701265                       # Writes before turning the bus around for reads
21310526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::stdev      4.160598                       # Writes before turning the bus around for reads
21410526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::16             5817     73.61%     73.61% # Writes before turning the bus around for reads
21510526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::17                9      0.11%     73.73% # Writes before turning the bus around for reads
21610526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::18              164      2.08%     75.80% # Writes before turning the bus around for reads
21710526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::19               13      0.16%     75.97% # Writes before turning the bus around for reads
21810526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::20               44      0.56%     76.52% # Writes before turning the bus around for reads
21910526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::21              510      6.45%     82.98% # Writes before turning the bus around for reads
22010526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::22              151      1.91%     84.89% # Writes before turning the bus around for reads
22110526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::23               32      0.40%     85.29% # Writes before turning the bus around for reads
22210526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::24              635      8.04%     93.33% # Writes before turning the bus around for reads
22310526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::25              115      1.46%     94.79% # Writes before turning the bus around for reads
22410526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::26                6      0.08%     94.86% # Writes before turning the bus around for reads
22510526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::27               14      0.18%     95.04% # Writes before turning the bus around for reads
22610526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::28              297      3.76%     98.80% # Writes before turning the bus around for reads
22710526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::29                8      0.10%     98.90% # Writes before turning the bus around for reads
22810526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::30                4      0.05%     98.95% # Writes before turning the bus around for reads
22910526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::31                6      0.08%     99.03% # Writes before turning the bus around for reads
23010526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::32                6      0.08%     99.10% # Writes before turning the bus around for reads
23110526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::33                6      0.08%     99.18% # Writes before turning the bus around for reads
23210526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::34                2      0.03%     99.20% # Writes before turning the bus around for reads
23310526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::35                4      0.05%     99.25% # Writes before turning the bus around for reads
23410526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::36                1      0.01%     99.27% # Writes before turning the bus around for reads
23510526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::37                1      0.01%     99.28% # Writes before turning the bus around for reads
23610526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::38                5      0.06%     99.34% # Writes before turning the bus around for reads
23710526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::39                3      0.04%     99.38% # Writes before turning the bus around for reads
23810526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::40                6      0.08%     99.46% # Writes before turning the bus around for reads
23910526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::41                9      0.11%     99.57% # Writes before turning the bus around for reads
24010526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::42                6      0.08%     99.65% # Writes before turning the bus around for reads
24110526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::43                4      0.05%     99.70% # Writes before turning the bus around for reads
24210526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::44                5      0.06%     99.76% # Writes before turning the bus around for reads
24310526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::45                3      0.04%     99.80% # Writes before turning the bus around for reads
24410526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::46                2      0.03%     99.82% # Writes before turning the bus around for reads
24510526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::48                5      0.06%     99.89% # Writes before turning the bus around for reads
24610526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::51                9      0.11%    100.00% # Writes before turning the bus around for reads
24710526Snilay@cs.wisc.edusystem.mem_ctrls.wrPerTurnAround::total          7902                       # Writes before turning the bus around for reads
24810526Snilay@cs.wisc.edusystem.mem_ctrls.totQLat                   1958460749                       # Total ticks spent queuing
24910526Snilay@cs.wisc.edusystem.mem_ctrls.totMemAccLat              5295585749                       # Total ticks spent from burst creation until serviced by the DRAM
25010526Snilay@cs.wisc.edusystem.mem_ctrls.totBusLat                  889900000                       # Total ticks spent in databus transfers
25110526Snilay@cs.wisc.edusystem.mem_ctrls.avgQLat                     11003.82                       # Average queueing delay per DRAM burst
25210526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
25310526Snilay@cs.wisc.edusystem.mem_ctrls.avgMemAccLat                29753.82                       # Average memory access latency per DRAM burst
25410526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdBW                         2.15                       # Average DRAM read bandwidth in MiByte/s
25510526Snilay@cs.wisc.edusystem.mem_ctrls.avgWrBW                         1.72                       # Average achieved write bandwidth in MiByte/s
25610526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdBWSys                      2.16                       # Average system read bandwidth in MiByte/s
25710526Snilay@cs.wisc.edusystem.mem_ctrls.avgWrBWSys                      1.72                       # Average system write bandwidth in MiByte/s
25810526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
25910526Snilay@cs.wisc.edusystem.mem_ctrls.busUtil                         0.03                       # Data bus utilization in percentage
26010526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilRead                     0.02                       # Data bus utilization in percentage for reads
26110526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilWrite                    0.01                       # Data bus utilization in percentage for writes
26210526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
26310526Snilay@cs.wisc.edusystem.mem_ctrls.avgWrQLen                      27.88                       # Average write queue length when enqueuing
26410526Snilay@cs.wisc.edusystem.mem_ctrls.readRowHits                   142054                       # Number of row buffer hits during reads
26510526Snilay@cs.wisc.edusystem.mem_ctrls.writeRowHits                  118304                       # Number of row buffer hits during writes
26610526Snilay@cs.wisc.edusystem.mem_ctrls.readRowHitRate                 79.81                       # Row buffer hit rate for reads
26710526Snilay@cs.wisc.edusystem.mem_ctrls.writeRowHitRate                82.87                       # Row buffer hit rate for writes
26810526Snilay@cs.wisc.edusystem.mem_ctrls.avgGap                   16476053.28                       # Average gap between requests
26910526Snilay@cs.wisc.edusystem.mem_ctrls.pageHitRate                    81.18                       # Row buffer hit rate, read and write combined
27010526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::IDLE   5045112796500                       # Time in different power states
27110526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::REF    177003320000                       # Time in different power states
27210526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
27310526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::ACT     78625657500                       # Time in different power states
27410526Snilay@cs.wisc.edusystem.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
27510526Snilay@cs.wisc.edusystem.mem_ctrls.actEnergy::0               223791120                       # Energy for activate commands per rank (pJ)
27610526Snilay@cs.wisc.edusystem.mem_ctrls.actEnergy::1               232477560                       # Energy for activate commands per rank (pJ)
27710526Snilay@cs.wisc.edusystem.mem_ctrls.preEnergy::0               122108250                       # Energy for precharge commands per rank (pJ)
27810526Snilay@cs.wisc.edusystem.mem_ctrls.preEnergy::1               126847875                       # Energy for precharge commands per rank (pJ)
27910526Snilay@cs.wisc.edusystem.mem_ctrls.readEnergy::0              683599800                       # Energy for read commands per rank (pJ)
28010526Snilay@cs.wisc.edusystem.mem_ctrls.readEnergy::1              704636400                       # Energy for read commands per rank (pJ)
28110526Snilay@cs.wisc.edusystem.mem_ctrls.writeEnergy::0             468251280                       # Energy for write commands per rank (pJ)
28210526Snilay@cs.wisc.edusystem.mem_ctrls.writeEnergy::1             456652080                       # Energy for write commands per rank (pJ)
28310526Snilay@cs.wisc.edusystem.mem_ctrls.refreshEnergy::0        346218493920                       # Energy for refresh commands per rank (pJ)
28410526Snilay@cs.wisc.edusystem.mem_ctrls.refreshEnergy::1        346218493920                       # Energy for refresh commands per rank (pJ)
28510526Snilay@cs.wisc.edusystem.mem_ctrls.actBackEnergy::0        148888594485                       # Energy for active background per rank (pJ)
28610526Snilay@cs.wisc.edusystem.mem_ctrls.actBackEnergy::1        149563929060                       # Energy for active background per rank (pJ)
28710526Snilay@cs.wisc.edusystem.mem_ctrls.preBackEnergy::0        3049839426000                       # Energy for precharge background per rank (pJ)
28810526Snilay@cs.wisc.edusystem.mem_ctrls.preBackEnergy::1        3049247027250                       # Energy for precharge background per rank (pJ)
28910526Snilay@cs.wisc.edusystem.mem_ctrls.totalEnergy::0          3546444264855                       # Total energy per rank (pJ)
29010526Snilay@cs.wisc.edusystem.mem_ctrls.totalEnergy::1          3546550064145                       # Total energy per rank (pJ)
29110526Snilay@cs.wisc.edusystem.mem_ctrls.averagePower::0           669.047128                       # Core power per rank (mW)
29210526Snilay@cs.wisc.edusystem.mem_ctrls.averagePower::1           669.067087                       # Core power per rank (mW)
29310036SAli.Saidi@ARM.comsystem.ruby.clk_domain.clock                      500                       # Clock period in ticks
29410229Snilay@cs.wisc.edusystem.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
29510229Snilay@cs.wisc.edusystem.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
29610526Snilay@cs.wisc.edusystem.ruby.delayHist::samples               10900696                       # delay histogram for all message
29710526Snilay@cs.wisc.edusystem.ruby.delayHist::mean                  0.442840                       # delay histogram for all message
29810526Snilay@cs.wisc.edusystem.ruby.delayHist::stdev                 1.830682                       # delay histogram for all message
29910526Snilay@cs.wisc.edusystem.ruby.delayHist                    |    10297724     94.47%     94.47% |        1479      0.01%     94.48% |      601064      5.51%    100.00% |         150      0.00%    100.00% |         222      0.00%    100.00% |          14      0.00%    100.00% |          41      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
30010526Snilay@cs.wisc.edusystem.ruby.delayHist::total                 10900696                       # delay histogram for all message
30110013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::bucket_size            1                      
30210013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::max_bucket            9                      
30310526Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::samples    152128630                      
30410013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::mean       1.000112                      
30510013Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::gmean      1.000078                      
30610526Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::stdev      0.010605                      
30710526Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist         |           0      0.00%      0.00% |   152111520     99.99%     99.99% |       17110      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
30810526Snilay@cs.wisc.edusystem.ruby.outstanding_req_hist::total     152128630                      
30910526Snilay@cs.wisc.edusystem.ruby.latency_hist::bucket_size             256                      
31010526Snilay@cs.wisc.edusystem.ruby.latency_hist::max_bucket             2559                      
31110526Snilay@cs.wisc.edusystem.ruby.latency_hist::samples           152128629                      
31210526Snilay@cs.wisc.edusystem.ruby.latency_hist::mean               3.436815                      
31310526Snilay@cs.wisc.edusystem.ruby.latency_hist::gmean              3.107877                      
31410526Snilay@cs.wisc.edusystem.ruby.latency_hist::stdev              5.781267                      
31510526Snilay@cs.wisc.edusystem.ruby.latency_hist                 |   152119575     99.99%     99.99% |        6193      0.00%    100.00% |        2797      0.00%    100.00% |          28      0.00%    100.00% |          34      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
31610526Snilay@cs.wisc.edusystem.ruby.latency_hist::total             152128629                      
31710013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::bucket_size            1                      
31810013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::max_bucket            9                      
31910526Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::samples       149464039                      
32010013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::mean                  3                      
32110013Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::gmean          3.000000                      
32210526Snilay@cs.wisc.edusystem.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   149464039    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
32310526Snilay@cs.wisc.edusystem.ruby.hit_latency_hist::total         149464039                      
32410526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::bucket_size          256                      
32510526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::max_bucket         2559                      
32610526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::samples        2664590                      
32710526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::mean         27.938944                      
32810526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::gmean        22.546119                      
32910526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::stdev        36.016044                      
33010526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist            |     2655536     99.66%     99.66% |        6193      0.23%     99.89% |        2797      0.10%    100.00% |          28      0.00%    100.00% |          34      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
33110526Snilay@cs.wisc.edusystem.ruby.miss_latency_hist::total          2664590                      
33210526Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Dcache.demand_hits     10684802                       # Number of cache demand hits
33310526Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Dcache.demand_misses       518536                       # Number of cache demand misses
33410526Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Dcache.demand_accesses     11203338                       # Number of cache demand accesses
33510526Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Icache.demand_hits     67461431                       # Number of cache demand hits
33610526Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Icache.demand_misses       317291                       # Number of cache demand misses
33710526Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.L1Icache.demand_accesses     67778722                       # Number of cache demand accesses
33810315Snilay@cs.wisc.edusystem.cpu_clk_domain.clock                       500                       # Clock period in ticks
3399803SN/Asystem.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
3409803SN/Asystem.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
3419803SN/Asystem.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
3429803SN/Asystem.ruby.l1_cntrl0.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
3439803SN/Asystem.ruby.l1_cntrl0.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
3449803SN/Asystem.ruby.l1_cntrl0.prefetcher.hits               0                       # number of prefetched blocks accessed
3459803SN/Asystem.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
3469803SN/Asystem.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
3479803SN/Asystem.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
34810526Snilay@cs.wisc.edusystem.ruby.l1_cntrl0.fully_busy_cycles            12                       # cycles for which number of transistions == max transitions
34910526Snilay@cs.wisc.edusystem.ruby.network.routers0.percent_links_utilized     0.029331                      
35010526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Control::0       835827                      
35110526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Request_Control::2        42905                      
35210526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Data::1       863889                      
35310526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Control::1       496114                      
35410526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Response_Control::2       492544                      
35510526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Data::0       292440                      
35610526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Data::1          167                      
35710526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_count.Writeback_Control::0       162044                      
35810526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Control::0      6686616                      
35910526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Request_Control::2       343240                      
36010526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Data::1     62200008                      
36110526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Control::1      3968912                      
36210526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Response_Control::2      3940352                      
36310526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Data::0     21055680                      
36410526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Data::1        12024                      
36510526Snilay@cs.wisc.edusystem.ruby.network.routers0.msg_bytes.Writeback_Control::0      1296352                      
36610526Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Dcache.demand_hits     13058053                       # Number of cache demand hits
36710526Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Dcache.demand_misses      1328322                       # Number of cache demand misses
36810526Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Dcache.demand_accesses     14386375                       # Number of cache demand accesses
36910526Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Icache.demand_hits     58259753                       # Number of cache demand hits
37010526Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Icache.demand_misses       500441                       # Number of cache demand misses
37110526Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.L1Icache.demand_accesses     58760194                       # Number of cache demand accesses
3729803SN/Asystem.ruby.l1_cntrl1.prefetcher.miss_observed            0                       # number of misses observed
3739803SN/Asystem.ruby.l1_cntrl1.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
3749803SN/Asystem.ruby.l1_cntrl1.prefetcher.prefetches_requested            0                       # number of prefetch requests made
3759803SN/Asystem.ruby.l1_cntrl1.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
3769803SN/Asystem.ruby.l1_cntrl1.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
3779803SN/Asystem.ruby.l1_cntrl1.prefetcher.hits               0                       # number of prefetched blocks accessed
3789803SN/Asystem.ruby.l1_cntrl1.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
3799803SN/Asystem.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
3809803SN/Asystem.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
38110526Snilay@cs.wisc.edusystem.ruby.l1_cntrl1.fully_busy_cycles            12                       # cycles for which number of transistions == max transitions
38210526Snilay@cs.wisc.edusystem.ruby.network.routers1.percent_links_utilized     0.057975                      
38310526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Control::0      1828763                      
38410526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Request_Control::2        40586                      
38510526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Data::1      1853208                      
38610526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Control::1      1269894                      
38710526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Response_Control::2      1269686                      
38810526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Data::0       282914                      
38910526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Data::1          208                      
39010526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_count.Writeback_Control::0       948886                      
39110526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Control::0     14630104                      
39210526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Request_Control::2       324688                      
39310526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Data::1    133430976                      
39410526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Control::1     10159152                      
39510526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Response_Control::2     10157488                      
39610526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Data::0     20369808                      
39710526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Data::1        14976                      
39810526Snilay@cs.wisc.edusystem.ruby.network.routers1.msg_bytes.Writeback_Control::0      7591088                      
39910526Snilay@cs.wisc.edusystem.ruby.l2_cntrl0.L2cache.demand_hits      2436707                       # Number of cache demand hits
40010526Snilay@cs.wisc.edusystem.ruby.l2_cntrl0.L2cache.demand_misses       227883                       # Number of cache demand misses
40110526Snilay@cs.wisc.edusystem.ruby.l2_cntrl0.L2cache.demand_accesses      2664590                       # Number of cache demand accesses
40210526Snilay@cs.wisc.edusystem.ruby.network.routers2.percent_links_utilized     0.091680                      
40310526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Control::0      2843003                      
40410526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Request_Control::2        81677                      
40510526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Data::1      2894271                      
40610526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Control::1      1849723                      
40710526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Response_Control::2      1762230                      
40810526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Data::0       575354                      
40910526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Data::1          375                      
41010526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_count.Writeback_Control::0      1110930                      
41110526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Control::0     22744024                      
41210526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Request_Control::2       653416                      
41310526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Data::1    208387512                      
41410526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Control::1     14797784                      
41510526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Response_Control::2     14097840                      
41610526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Data::0     41425488                      
41710526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Data::1        27000                      
41810526Snilay@cs.wisc.edusystem.ruby.network.routers2.msg_bytes.Writeback_Control::0      8887440                      
41910526Snilay@cs.wisc.edusystem.ruby.network.routers3.percent_links_utilized     0.006831                      
42010526Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Control::0       178413                      
42110526Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Response_Data::1       276928                      
42210526Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Response_Control::1       131535                      
42310526Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Writeback_Control::0        47550                      
42410526Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_count.Writeback_Control::1        46736                      
42510526Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Control::0      1427304                      
42610526Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Response_Data::1     19938816                      
42710526Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Response_Control::1      1052280                      
42810526Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Writeback_Control::0       380400                      
42910526Snilay@cs.wisc.edusystem.ruby.network.routers3.msg_bytes.Writeback_Control::1       373888                      
43010526Snilay@cs.wisc.edusystem.ruby.network.routers4.percent_links_utilized     0.000240                      
43110526Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_count.Response_Data::1          814                      
43210526Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_count.Writeback_Control::0        47550                      
43310526Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_count.Writeback_Control::1        46736                      
43410526Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_bytes.Response_Data::1        58608                      
43510526Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_bytes.Writeback_Control::0       380400                      
43610526Snilay@cs.wisc.edusystem.ruby.network.routers4.msg_bytes.Writeback_Control::1       373888                      
43710526Snilay@cs.wisc.edusystem.ruby.network.routers5.percent_links_utilized            0                      
43810526Snilay@cs.wisc.edusystem.ruby.network.routers6.percent_links_utilized     0.031010                      
43910526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Control::0      2843003                      
44010526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Request_Control::2        83491                      
44110526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Response_Data::1      2944555                      
44210526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Response_Control::1      1873633                      
44310526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Response_Control::2      1762230                      
44410526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Writeback_Data::0       575354                      
44510526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Writeback_Data::1          375                      
44610526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Writeback_Control::0      1158480                      
44710526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_count.Writeback_Control::1        46736                      
44810526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Control::0     22744024                      
44910526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Request_Control::2       667928                      
45010526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Response_Data::1    212007960                      
45110526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Response_Control::1     14989064                      
45210526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Response_Control::2     14097840                      
45310526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Writeback_Data::0     41425488                      
45410526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Writeback_Data::1        27000                      
45510526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Writeback_Control::0      9267840                      
45610526Snilay@cs.wisc.edusystem.ruby.network.routers6.msg_bytes.Writeback_Control::1       373888                      
45710526Snilay@cs.wisc.edusystem.ruby.network.msg_count.Control         8529009                      
45810526Snilay@cs.wisc.edusystem.ruby.network.msg_count.Request_Control       248659                      
45910526Snilay@cs.wisc.edusystem.ruby.network.msg_count.Response_Data      8833665                      
46010526Snilay@cs.wisc.edusystem.ruby.network.msg_count.Response_Control     10907589                      
46110526Snilay@cs.wisc.edusystem.ruby.network.msg_count.Writeback_Data      1727187                      
46210526Snilay@cs.wisc.edusystem.ruby.network.msg_count.Writeback_Control      3615648                      
46310526Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Control         68232072                      
46410526Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Request_Control      1989272                      
46510526Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Response_Data    636023880                      
46610526Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Response_Control     87260712                      
46710526Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Writeback_Data    124357464                      
46810526Snilay@cs.wisc.edusystem.ruby.network.msg_byte.Writeback_Control     28925184                      
46910036SAli.Saidi@ARM.comsystem.ruby.memctrl_clk_domain.clock             1500                       # Clock period in ticks
4708968SN/Asystem.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
4718974SN/Asystem.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
4728974SN/Asystem.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
4738968SN/Asystem.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
4748974SN/Asystem.pc.south_bridge.ide.disks0.dma_write_bytes      2987008                       # Number of bytes transfered via DMA writes.
4759998SN/Asystem.pc.south_bridge.ide.disks0.dma_write_txs          813                       # Number of DMA write transactions.
4768968SN/Asystem.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
4778968SN/Asystem.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
4788968SN/Asystem.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
4798968SN/Asystem.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
4808968SN/Asystem.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
4818968SN/Asystem.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
48210526Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadReq               857926                       # Transaction distribution
48310526Snilay@cs.wisc.edusystem.iobus.trans_dist::ReadResp              857926                       # Transaction distribution
48410526Snilay@cs.wisc.edusystem.iobus.trans_dist::WriteReq               36569                       # Transaction distribution
48510526Snilay@cs.wisc.edusystem.iobus.trans_dist::WriteResp              36569                       # Transaction distribution
48610526Snilay@cs.wisc.edusystem.iobus.trans_dist::MessageReq              1919                       # Transaction distribution
48710526Snilay@cs.wisc.edusystem.iobus.trans_dist::MessageResp             1919                       # Transaction distribution
48810526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1700                       # Packet count per connected master and slave (bytes)
48910526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1642                       # Packet count per connected master and slave (bytes)
49010526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3342                       # Packet count per connected master and slave (bytes)
49110220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
49210526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4780                       # Packet count per connected master and slave (bytes)
49310220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           88                       # Packet count per connected master and slave (bytes)
49410526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio         1048                       # Packet count per connected master and slave (bytes)
49510451Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           82                       # Packet count per connected master and slave (bytes)
49610526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           42                       # Packet count per connected master and slave (bytes)
49710220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
49810220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       934582                       # Packet count per connected master and slave (bytes)
49910451Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          990                       # Packet count per connected master and slave (bytes)
50010220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio           90                       # Packet count per connected master and slave (bytes)
50110220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
50210526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        16892                       # Packet count per connected master and slave (bytes)
50310526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       743276                       # Packet count per connected master and slave (bytes)
50410526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          296                       # Packet count per connected master and slave (bytes)
50510220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         2126                       # Packet count per connected master and slave (bytes)
50610526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1704360                       # Packet count per connected master and slave (bytes)
50710220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           16                       # Packet count per connected master and slave (bytes)
50810220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
50910526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         6262                       # Packet count per connected master and slave (bytes)
51010220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           92                       # Packet count per connected master and slave (bytes)
51110526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          316                       # Packet count per connected master and slave (bytes)
51210451Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           12                       # Packet count per connected master and slave (bytes)
51310526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           12                       # Packet count per connected master and slave (bytes)
51410526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        31164                       # Packet count per connected master and slave (bytes)
51510526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          364                       # Packet count per connected master and slave (bytes)
51610526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio        31252                       # Packet count per connected master and slave (bytes)
51710526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        10236                       # Packet count per connected master and slave (bytes)
51810220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
51910220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
52010220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
52110220Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
52210526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          200                       # Packet count per connected master and slave (bytes)
52310526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         5148                       # Packet count per connected master and slave (bytes)
52410526Snilay@cs.wisc.edusystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        85126                       # Packet count per connected master and slave (bytes)
52510526Snilay@cs.wisc.edusystem.iobus.pkt_count::total                 1792828                       # Packet count per connected master and slave (bytes)
52610526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3400                       # Cumulative packet size per connected master and slave (bytes)
52710526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3284                       # Cumulative packet size per connected master and slave (bytes)
52810526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6684                       # Cumulative packet size per connected master and slave (bytes)
52910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
53010526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         2696                       # Cumulative packet size per connected master and slave (bytes)
53110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf          149                       # Cumulative packet size per connected master and slave (bytes)
53210526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          524                       # Cumulative packet size per connected master and slave (bytes)
53310451Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           41                       # Cumulative packet size per connected master and slave (bytes)
53410526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           21                       # Cumulative packet size per connected master and slave (bytes)
53510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
53610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       467291                       # Cumulative packet size per connected master and slave (bytes)
53710451Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1980                       # Cumulative packet size per connected master and slave (bytes)
53810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio           45                       # Cumulative packet size per connected master and slave (bytes)
53910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
54010526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         8446                       # Cumulative packet size per connected master and slave (bytes)
54110526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1486546                       # Cumulative packet size per connected master and slave (bytes)
54210526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          592                       # Cumulative packet size per connected master and slave (bytes)
54310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio         4252                       # Cumulative packet size per connected master and slave (bytes)
54410526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1972617                       # Cumulative packet size per connected master and slave (bytes)
54510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio            8                       # Cumulative packet size per connected master and slave (bytes)
54610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
54710526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3964                       # Cumulative packet size per connected master and slave (bytes)
54810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf           72                       # Cumulative packet size per connected master and slave (bytes)
54910526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          158                       # Cumulative packet size per connected master and slave (bytes)
55010451Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            6                       # Cumulative packet size per connected master and slave (bytes)
55110526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
55210526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        15582                       # Cumulative packet size per connected master and slave (bytes)
55310526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          728                       # Cumulative packet size per connected master and slave (bytes)
55410526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio        15626                       # Cumulative packet size per connected master and slave (bytes)
55510526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         5118                       # Cumulative packet size per connected master and slave (bytes)
55610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
55710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
55810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
55910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
56010526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          400                       # Cumulative packet size per connected master and slave (bytes)
56110526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port        10293                       # Cumulative packet size per connected master and slave (bytes)
56210526Snilay@cs.wisc.edusystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        51987                       # Cumulative packet size per connected master and slave (bytes)
56310526Snilay@cs.wisc.edusystem.iobus.pkt_size::total                  2031288                       # Cumulative packet size per connected master and slave (bytes)
56410526Snilay@cs.wisc.edusystem.iobus.reqLayer0.occupancy                51000                       # Layer occupancy (ticks)
56510220Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
56610315Snilay@cs.wisc.edusystem.iobus.reqLayer1.occupancy                 6500                       # Layer occupancy (ticks)
56710220Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
56810526Snilay@cs.wisc.edusystem.iobus.reqLayer2.occupancy             10161500                       # Layer occupancy (ticks)
56910220Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
57010526Snilay@cs.wisc.edusystem.iobus.reqLayer3.occupancy               144000                       # Layer occupancy (ticks)
57110220Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
57210526Snilay@cs.wisc.edusystem.iobus.reqLayer4.occupancy              1080000                       # Layer occupancy (ticks)
57310220Sandreas.hansson@arm.comsystem.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
57410526Snilay@cs.wisc.edusystem.iobus.reqLayer5.occupancy                94000                       # Layer occupancy (ticks)
57510220Sandreas.hansson@arm.comsystem.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
57610526Snilay@cs.wisc.edusystem.iobus.reqLayer6.occupancy                59500                       # Layer occupancy (ticks)
57710220Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
57810526Snilay@cs.wisc.edusystem.iobus.reqLayer7.occupancy             20808000                       # Layer occupancy (ticks)
57910220Sandreas.hansson@arm.comsystem.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
58010526Snilay@cs.wisc.edusystem.iobus.reqLayer8.occupancy            700937500                       # Layer occupancy (ticks)
58110220Sandreas.hansson@arm.comsystem.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
58210526Snilay@cs.wisc.edusystem.iobus.reqLayer9.occupancy              1385500                       # Layer occupancy (ticks)
58310220Sandreas.hansson@arm.comsystem.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
58410526Snilay@cs.wisc.edusystem.iobus.reqLayer10.occupancy            31365000                       # Layer occupancy (ticks)
58510220Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
58610526Snilay@cs.wisc.edusystem.iobus.reqLayer11.occupancy                2500                       # Layer occupancy (ticks)
58710220Sandreas.hansson@arm.comsystem.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
58810526Snilay@cs.wisc.edusystem.iobus.reqLayer12.occupancy            23203000                       # Layer occupancy (ticks)
58910220Sandreas.hansson@arm.comsystem.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
59010409Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
59110220Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
59210526Snilay@cs.wisc.edusystem.iobus.reqLayer14.occupancy                9000                       # Layer occupancy (ticks)
59310220Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
59410451Snilay@cs.wisc.edusystem.iobus.reqLayer15.occupancy               12000                       # Layer occupancy (ticks)
59510220Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
59610526Snilay@cs.wisc.edusystem.iobus.reqLayer16.occupancy               11000                       # Layer occupancy (ticks)
59710220Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
59810526Snilay@cs.wisc.edusystem.iobus.reqLayer17.occupancy           469007612                       # Layer occupancy (ticks)
59910220Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
60010526Snilay@cs.wisc.edusystem.iobus.reqLayer18.occupancy             8240496                       # Layer occupancy (ticks)
60110220Sandreas.hansson@arm.comsystem.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
60210526Snilay@cs.wisc.edusystem.iobus.reqLayer20.occupancy             1330000                       # Layer occupancy (ticks)
60310220Sandreas.hansson@arm.comsystem.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
60410526Snilay@cs.wisc.edusystem.iobus.respLayer0.occupancy             2404108                       # Layer occupancy (ticks)
60510220Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
60610526Snilay@cs.wisc.edusystem.iobus.respLayer2.occupancy          2025089500                       # Layer occupancy (ticks)
60710220Sandreas.hansson@arm.comsystem.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
60810526Snilay@cs.wisc.edusystem.iobus.respLayer4.occupancy            59993000                       # Layer occupancy (ticks)
60910220Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
61010036SAli.Saidi@ARM.comsystem.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
61110526Snilay@cs.wisc.edusystem.cpu0.numCycles                     10600620667                       # number of cpu cycles simulated
6128968SN/Asystem.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
6138968SN/Asystem.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
61410526Snilay@cs.wisc.edusystem.cpu0.committedInsts                   58326751                       # Number of instructions committed
61510526Snilay@cs.wisc.edusystem.cpu0.committedOps                    112208544                       # Number of ops (including micro ops) committed
61610526Snilay@cs.wisc.edusystem.cpu0.num_int_alu_accesses            105142610                       # Number of integer alu accesses
6178968SN/Asystem.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
61810526Snilay@cs.wisc.edusystem.cpu0.num_func_calls                     999393                       # number of times a function call or return occured
61910526Snilay@cs.wisc.edusystem.cpu0.num_conditional_control_insts      9968022                       # number of instructions that are conditional controls
62010526Snilay@cs.wisc.edusystem.cpu0.num_int_insts                   105142610                       # number of integer instructions
6218968SN/Asystem.cpu0.num_fp_insts                            0                       # number of float instructions
62210526Snilay@cs.wisc.edusystem.cpu0.num_int_register_reads          198014063                       # number of times the integer registers were read
62310526Snilay@cs.wisc.edusystem.cpu0.num_int_register_writes          89363011                       # number of times the integer registers were written
6248968SN/Asystem.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
6258968SN/Asystem.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
62610526Snilay@cs.wisc.edusystem.cpu0.num_cc_register_reads            60260543                       # number of times the CC registers were read
62710526Snilay@cs.wisc.edusystem.cpu0.num_cc_register_writes           43624365                       # number of times the CC registers were written
62810526Snilay@cs.wisc.edusystem.cpu0.num_mem_refs                     12030075                       # number of memory refs
62910526Snilay@cs.wisc.edusystem.cpu0.num_load_insts                    7288332                       # Number of load instructions
63010526Snilay@cs.wisc.edusystem.cpu0.num_store_insts                   4741743                       # Number of store instructions
63110526Snilay@cs.wisc.edusystem.cpu0.num_idle_cycles              10084773874.270475                       # Number of idle cycles
63210526Snilay@cs.wisc.edusystem.cpu0.num_busy_cycles              515846792.729524                       # Number of busy cycles
63310526Snilay@cs.wisc.edusystem.cpu0.not_idle_fraction                0.048662                       # Percentage of non-idle cycles
63410526Snilay@cs.wisc.edusystem.cpu0.idle_fraction                    0.951338                       # Percentage of idle cycles
63510526Snilay@cs.wisc.edusystem.cpu0.Branches                         11302630                       # Number of branches fetched
63610526Snilay@cs.wisc.edusystem.cpu0.op_class::No_OpClass               132692      0.12%      0.12% # Class of executed instruction
63710526Snilay@cs.wisc.edusystem.cpu0.op_class::IntAlu                 99906926     89.04%     89.15% # Class of executed instruction
63810526Snilay@cs.wisc.edusystem.cpu0.op_class::IntMult                   87661      0.08%     89.23% # Class of executed instruction
63910526Snilay@cs.wisc.edusystem.cpu0.op_class::IntDiv                    51849      0.05%     89.28% # Class of executed instruction
64010526Snilay@cs.wisc.edusystem.cpu0.op_class::FloatAdd                      0      0.00%     89.28% # Class of executed instruction
64110526Snilay@cs.wisc.edusystem.cpu0.op_class::FloatCmp                      0      0.00%     89.28% # Class of executed instruction
64210526Snilay@cs.wisc.edusystem.cpu0.op_class::FloatCvt                      0      0.00%     89.28% # Class of executed instruction
64310526Snilay@cs.wisc.edusystem.cpu0.op_class::FloatMult                     0      0.00%     89.28% # Class of executed instruction
64410526Snilay@cs.wisc.edusystem.cpu0.op_class::FloatDiv                      0      0.00%     89.28% # Class of executed instruction
64510526Snilay@cs.wisc.edusystem.cpu0.op_class::FloatSqrt                     0      0.00%     89.28% # Class of executed instruction
64610526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdAdd                       0      0.00%     89.28% # Class of executed instruction
64710526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdAddAcc                    0      0.00%     89.28% # Class of executed instruction
64810526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdAlu                       0      0.00%     89.28% # Class of executed instruction
64910526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdCmp                       0      0.00%     89.28% # Class of executed instruction
65010526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdCvt                       0      0.00%     89.28% # Class of executed instruction
65110526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdMisc                      0      0.00%     89.28% # Class of executed instruction
65210526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdMult                      0      0.00%     89.28% # Class of executed instruction
65310526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdMultAcc                   0      0.00%     89.28% # Class of executed instruction
65410526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdShift                     0      0.00%     89.28% # Class of executed instruction
65510526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdShiftAcc                  0      0.00%     89.28% # Class of executed instruction
65610526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdSqrt                      0      0.00%     89.28% # Class of executed instruction
65710526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatAdd                  0      0.00%     89.28% # Class of executed instruction
65810526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatAlu                  0      0.00%     89.28% # Class of executed instruction
65910526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatCmp                  0      0.00%     89.28% # Class of executed instruction
66010526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatCvt                  0      0.00%     89.28% # Class of executed instruction
66110526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatDiv                  0      0.00%     89.28% # Class of executed instruction
66210526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatMisc                 0      0.00%     89.28% # Class of executed instruction
66310526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatMult                 0      0.00%     89.28% # Class of executed instruction
66410526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatMultAcc              0      0.00%     89.28% # Class of executed instruction
66510526Snilay@cs.wisc.edusystem.cpu0.op_class::SimdFloatSqrt                 0      0.00%     89.28% # Class of executed instruction
66610526Snilay@cs.wisc.edusystem.cpu0.op_class::MemRead                 7288332      6.50%     95.77% # Class of executed instruction
66710526Snilay@cs.wisc.edusystem.cpu0.op_class::MemWrite                4741743      4.23%    100.00% # Class of executed instruction
66810220Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
66910220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
67010526Snilay@cs.wisc.edusystem.cpu0.op_class::total                 112209203                       # Class of executed instruction
6718968SN/Asystem.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
6728968SN/Asystem.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
67310036SAli.Saidi@ARM.comsystem.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
67410526Snilay@cs.wisc.edusystem.cpu1.numCycles                     10601483797                       # number of cpu cycles simulated
6758968SN/Asystem.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
6768968SN/Asystem.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
67710526Snilay@cs.wisc.edusystem.cpu1.committedInsts                   48465381                       # Number of instructions committed
67810526Snilay@cs.wisc.edusystem.cpu1.committedOps                     92539438                       # Number of ops (including micro ops) committed
67910526Snilay@cs.wisc.edusystem.cpu1.num_int_alu_accesses             88910462                       # Number of integer alu accesses
6808968SN/Asystem.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
68110526Snilay@cs.wisc.edusystem.cpu1.num_func_calls                    1744945                       # number of times a function call or return occured
68210526Snilay@cs.wisc.edusystem.cpu1.num_conditional_control_insts      8275238                       # number of instructions that are conditional controls
68310526Snilay@cs.wisc.edusystem.cpu1.num_int_insts                    88910462                       # number of integer instructions
6848968SN/Asystem.cpu1.num_fp_insts                            0                       # number of float instructions
68510526Snilay@cs.wisc.edusystem.cpu1.num_int_register_reads          172623141                       # number of times the integer registers were read
68610526Snilay@cs.wisc.edusystem.cpu1.num_int_register_writes          73500216                       # number of times the integer registers were written
6878968SN/Asystem.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
6888968SN/Asystem.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
68910526Snilay@cs.wisc.edusystem.cpu1.num_cc_register_reads            51257305                       # number of times the CC registers were read
69010526Snilay@cs.wisc.edusystem.cpu1.num_cc_register_writes           33029139                       # number of times the CC registers were written
69110526Snilay@cs.wisc.edusystem.cpu1.num_mem_refs                     14403882                       # number of memory refs
69210526Snilay@cs.wisc.edusystem.cpu1.num_load_insts                    9271822                       # Number of load instructions
69310526Snilay@cs.wisc.edusystem.cpu1.num_store_insts                   5132060                       # Number of store instructions
69410526Snilay@cs.wisc.edusystem.cpu1.num_idle_cycles              10262330670.974064                       # Number of idle cycles
69510526Snilay@cs.wisc.edusystem.cpu1.num_busy_cycles              339153126.025936                       # Number of busy cycles
69610526Snilay@cs.wisc.edusystem.cpu1.not_idle_fraction                0.031991                       # Percentage of non-idle cycles
69710526Snilay@cs.wisc.edusystem.cpu1.idle_fraction                    0.968009                       # Percentage of idle cycles
69810526Snilay@cs.wisc.edusystem.cpu1.Branches                         10623766                       # Number of branches fetched
69910526Snilay@cs.wisc.edusystem.cpu1.op_class::No_OpClass               173936      0.19%      0.19% # Class of executed instruction
70010526Snilay@cs.wisc.edusystem.cpu1.op_class::IntAlu                 77788975     84.06%     84.25% # Class of executed instruction
70110526Snilay@cs.wisc.edusystem.cpu1.op_class::IntMult                   96916      0.10%     84.35% # Class of executed instruction
70210526Snilay@cs.wisc.edusystem.cpu1.op_class::IntDiv                    76680      0.08%     84.44% # Class of executed instruction
70310526Snilay@cs.wisc.edusystem.cpu1.op_class::FloatAdd                      0      0.00%     84.44% # Class of executed instruction
70410526Snilay@cs.wisc.edusystem.cpu1.op_class::FloatCmp                      0      0.00%     84.44% # Class of executed instruction
70510526Snilay@cs.wisc.edusystem.cpu1.op_class::FloatCvt                      0      0.00%     84.44% # Class of executed instruction
70610526Snilay@cs.wisc.edusystem.cpu1.op_class::FloatMult                     0      0.00%     84.44% # Class of executed instruction
70710526Snilay@cs.wisc.edusystem.cpu1.op_class::FloatDiv                      0      0.00%     84.44% # Class of executed instruction
70810526Snilay@cs.wisc.edusystem.cpu1.op_class::FloatSqrt                     0      0.00%     84.44% # Class of executed instruction
70910526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAdd                       0      0.00%     84.44% # Class of executed instruction
71010526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAddAcc                    0      0.00%     84.44% # Class of executed instruction
71110526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdAlu                       0      0.00%     84.44% # Class of executed instruction
71210526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdCmp                       0      0.00%     84.44% # Class of executed instruction
71310526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdCvt                       0      0.00%     84.44% # Class of executed instruction
71410526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMisc                      0      0.00%     84.44% # Class of executed instruction
71510526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMult                      0      0.00%     84.44% # Class of executed instruction
71610526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdMultAcc                   0      0.00%     84.44% # Class of executed instruction
71710526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdShift                     0      0.00%     84.44% # Class of executed instruction
71810526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdShiftAcc                  0      0.00%     84.44% # Class of executed instruction
71910526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdSqrt                      0      0.00%     84.44% # Class of executed instruction
72010526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatAdd                  0      0.00%     84.44% # Class of executed instruction
72110526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatAlu                  0      0.00%     84.44% # Class of executed instruction
72210526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatCmp                  0      0.00%     84.44% # Class of executed instruction
72310526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatCvt                  0      0.00%     84.44% # Class of executed instruction
72410526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatDiv                  0      0.00%     84.44% # Class of executed instruction
72510526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMisc                 0      0.00%     84.44% # Class of executed instruction
72610526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMult                 0      0.00%     84.44% # Class of executed instruction
72710526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatMultAcc              0      0.00%     84.44% # Class of executed instruction
72810526Snilay@cs.wisc.edusystem.cpu1.op_class::SimdFloatSqrt                 0      0.00%     84.44% # Class of executed instruction
72910526Snilay@cs.wisc.edusystem.cpu1.op_class::MemRead                 9271822     10.02%     94.45% # Class of executed instruction
73010526Snilay@cs.wisc.edusystem.cpu1.op_class::MemWrite                5132060      5.55%    100.00% # Class of executed instruction
73110220Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
73210220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
73310526Snilay@cs.wisc.edusystem.cpu1.op_class::total                  92540389                       # Class of executed instruction
7348968SN/Asystem.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
7358968SN/Asystem.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
73610526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.link_utilization     0.037422                      
73710526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Request_Control::2        42905                      
73810526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Data::1       823544                      
73910526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_count.Response_Control::1       479708                      
74010526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2       343240                      
74110526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1     59295168                      
74210526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1      3837664                      
74310526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.link_utilization     0.021239                      
74410526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Control::0       835827                      
74510526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Response_Data::1        40345                      
74610526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Response_Control::1        16406                      
74710526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Response_Control::2       492544                      
74810526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0       292440                      
74910526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1          167                      
75010526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0       162044                      
75110526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Control::0      6686616                      
75210526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1      2904840                      
75310526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1       131248                      
75410526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2      3940352                      
75510526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0     21055680                      
75610526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        12024                      
75710526Snilay@cs.wisc.edusystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0      1296352                      
75810526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.link_utilization     0.083305                      
75910526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Request_Control::2        40586                      
76010526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Response_Data::1      1818878                      
76110526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_count.Response_Control::1      1252654                      
76210526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2       324688                      
76310526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1    130959216                      
76410526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1     10021232                      
76510526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.link_utilization     0.032645                      
76610526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Control::0      1828763                      
76710526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Data::1        34330                      
76810526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Control::1        17240                      
76910526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Response_Control::2      1269686                      
77010526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0       282914                      
77110526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1          208                      
77210526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0       948886                      
77310526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Control::0     14630104                      
77410526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1      2471760                      
77510526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1       137920                      
77610526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2     10157488                      
77710526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0     20369808                      
77810526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1        14976                      
77910526Snilay@cs.wisc.edusystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0      7591088                      
78010526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.link_utilization     0.059790                      
78110526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Control::0      2664590                      
78210526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Data::1       203618                      
78310526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Control::1       125324                      
78410526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Response_Control::2      1762230                      
78510526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0       575354                      
78610526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1          375                      
78710526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0      1110930                      
78810526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Control::0     21316720                      
78910526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1     14660496                      
79010526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1      1002592                      
79110526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2     14097840                      
79210526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0     41425488                      
79310526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1        27000                      
79410526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0      8887440                      
79510526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.link_utilization     0.123569                      
79610526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Control::0       178413                      
79710526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Request_Control::2        81677                      
79810526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Response_Data::1      2690653                      
79910526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_count.Response_Control::1      1724399                      
80010526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Control::0      1427304                      
80110526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2       653416                      
80210526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1    193727016                      
80310526Snilay@cs.wisc.edusystem.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1     13795192                      
80410526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.link_utilization     0.005288                      
80510526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Control::0       178413                      
80610526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Response_Data::1        97701                      
80710526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Response_Control::1        15947                      
80810526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0        47550                      
80910526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Control::0      1427304                      
81010526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1      7034472                      
81110526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1       127576                      
81210526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0       380400                      
81310526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.link_utilization     0.008373                      
81410526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_count.Response_Data::1       179227                      
81510526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_count.Response_Control::1       115588                      
8169978SN/Asystem.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1        46736                      
81710526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1     12904344                      
81810526Snilay@cs.wisc.edusystem.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1       924704                      
8199978SN/Asystem.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1       373888                      
82010526Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.link_utilization     0.000255                      
82110526Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.msg_count.Response_Data::1          814                      
8229978SN/Asystem.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1        46736                      
82310526Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1        58608                      
8249978SN/Asystem.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1       373888                      
8259978SN/Asystem.ruby.network.routers4.throttle1.link_utilization     0.000224                      
82610526Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0        47550                      
82710526Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0       380400                      
82810526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle0.link_utilization            0                      
82910526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle1.link_utilization            0                      
83010526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.link_utilization     0.037422                      
83110526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_count.Request_Control::2        42905                      
83210526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_count.Response_Data::1       823544                      
83310526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_count.Response_Control::1       479708                      
83410526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2       343240                      
83510526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1     59295168                      
83610526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1      3837664                      
83710526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.link_utilization     0.083305                      
83810526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_count.Request_Control::2        40586                      
83910526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_count.Response_Data::1      1818878                      
84010526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_count.Response_Control::1      1252654                      
84110526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2       324688                      
84210526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1    130959216                      
84310526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1     10021232                      
84410526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.link_utilization     0.059790                      
84510526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Control::0      2664590                      
84610526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Response_Data::1       203618                      
84710526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Response_Control::1       125324                      
84810526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Response_Control::2      1762230                      
84910526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0       575354                      
85010526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1          375                      
85110526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0      1110930                      
85210526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Control::0     21316720                      
85310526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1     14660496                      
85410526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1      1002592                      
85510526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2     14097840                      
85610526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0     41425488                      
85710526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1        27000                      
85810526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0      8887440                      
85910526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.link_utilization     0.005288                      
86010526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Control::0       178413                      
86110526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Response_Data::1        97701                      
86210526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Response_Control::1        15947                      
86310526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0        47550                      
86410526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Control::0      1427304                      
86510526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1      7034472                      
86610526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1       127576                      
86710526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0       380400                      
86810526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.link_utilization     0.000255                      
86910526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_count.Response_Data::1          814                      
87010526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1        46736                      
87110526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1        58608                      
87210526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1       373888                      
87310526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle5.link_utilization            0                      
87410229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
87510229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
87610526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::samples       6113104                       # delay histogram for vnet_0
87710526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::mean         0.754972                       # delay histogram for vnet_0
87810526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::stdev        2.341149                       # delay histogram for vnet_0
87910526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0           |     5536836     90.57%     90.57% |         424      0.01%     90.58% |      575424      9.41%     99.99% |         146      0.00%    100.00% |         217      0.00%    100.00% |          14      0.00%    100.00% |          41      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
88010526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::total         6113104                       # delay histogram for vnet_0
88110229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
88210229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
88310526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::samples       4704101                       # delay histogram for vnet_1
88410526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::mean         0.045072                       # delay histogram for vnet_1
88510526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::stdev        0.595912                       # delay histogram for vnet_1
88610526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1           |     4676918     99.42%     99.42% |         479      0.01%     99.43% |         405      0.01%     99.44% |         650      0.01%     99.45% |       25495      0.54%    100.00% |         145      0.00%    100.00% |           4      0.00%    100.00% |           0      0.00%    100.00% |           2      0.00%    100.00% |           3      0.00%    100.00% # delay histogram for vnet_1
88710526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::total         4704101                       # delay histogram for vnet_1
88810315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
88910315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
89010526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::samples         83491                       # delay histogram for vnet_2
89110526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::mean         0.000264                       # delay histogram for vnet_2
89210526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::stdev        0.022955                       # delay histogram for vnet_2
89310526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2           |       83480     99.99%     99.99% |           0      0.00%     99.99% |          11      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
89410526Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::total           83491                       # delay histogram for vnet_2
89510526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::bucket_size          256                      
89610526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::max_bucket          2559                      
89710526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::samples         14918164                      
89810526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::mean            4.885826                      
89910526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::gmean           3.596048                      
90010526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::stdev           9.349489                      
90110526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist              |    14916026     99.99%     99.99% |        1637      0.01%    100.00% |         485      0.00%    100.00% |          10      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
90210526Snilay@cs.wisc.edusystem.ruby.LD.latency_hist::total           14918164                      
90310013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::bucket_size            1                      
90410013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::max_bucket            9                      
90510526Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::samples     13527451                      
90610013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::mean               3                      
90710013Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::gmean       3.000000                      
90810526Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |    13527451    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
90910526Snilay@cs.wisc.edusystem.ruby.LD.hit_latency_hist::total       13527451                      
91010526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::bucket_size          256                      
91110526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::max_bucket         2559                      
91210526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::samples      1390713                      
91310526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::mean      23.229241                      
91410526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::gmean     20.959487                      
91510526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::stdev     23.803463                      
91610526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist         |     1388575     99.85%     99.85% |        1637      0.12%     99.96% |         485      0.03%    100.00% |          10      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
91710526Snilay@cs.wisc.edusystem.ruby.LD.miss_latency_hist::total       1390713                      
91810526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::bucket_size          256                      
91910526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::max_bucket          2559                      
92010526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::samples          9498200                      
92110526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::mean            5.193739                      
92210526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::gmean           3.303046                      
92310526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::stdev          17.710522                      
92410526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist              |     9492386     99.94%     99.94% |        3703      0.04%     99.98% |        2069      0.02%    100.00% |          12      0.00%    100.00% |          29      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
92510526Snilay@cs.wisc.edusystem.ruby.ST.latency_hist::total            9498200                      
92610013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::bucket_size            1                      
92710013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::max_bucket            9                      
92810526Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::samples      9146403                      
92910013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::mean               3                      
93010013Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::gmean       3.000000                      
93110526Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist          |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |     9146403    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
93210526Snilay@cs.wisc.edusystem.ruby.ST.hit_latency_hist::total        9146403                      
93310526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::bucket_size          256                      
93410526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::max_bucket         2559                      
93510526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::samples       351797                      
93610526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::mean      62.228953                      
93710526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::gmean     40.318436                      
93810526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::stdev     71.347621                      
93910526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist         |      345983     98.35%     98.35% |        3703      1.05%     99.40% |        2069      0.59%     99.99% |          12      0.00%     99.99% |          29      0.01%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
94010526Snilay@cs.wisc.edusystem.ruby.ST.miss_latency_hist::total        351797                      
94110526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::bucket_size          128                      
94210526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::max_bucket         1279                      
94310526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::samples    126538916                      
94410526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::mean        3.120095                      
94510526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::gmean       3.036786                      
94610526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::stdev       2.265582                      
94710526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist          |   126532168     99.99%     99.99% |        5703      0.00%    100.00% |         492      0.00%    100.00% |         323      0.00%    100.00% |         160      0.00%    100.00% |          64      0.00%    100.00% |           0      0.00%    100.00% |           6      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
94810526Snilay@cs.wisc.edusystem.ruby.IFETCH.latency_hist::total      126538916                      
94910013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
95010013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::max_bucket            9                      
95110526Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::samples    125721184                      
95210013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::mean            3                      
95310013Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::gmean     3.000000                      
95410526Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist      |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |   125721184    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
95510526Snilay@cs.wisc.edusystem.ruby.IFETCH.hit_latency_hist::total    125721184                      
95610526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::bucket_size          128                      
95710526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::max_bucket         1279                      
95810526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::samples       817732                      
95910526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::mean    21.583892                      
96010526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::gmean    19.777346                      
96110526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::stdev    21.240290                      
96210526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist     |      810984     99.17%     99.17% |        5703      0.70%     99.87% |         492      0.06%     99.93% |         323      0.04%     99.97% |         160      0.02%     99.99% |          64      0.01%    100.00% |           0      0.00%    100.00% |           6      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
96310526Snilay@cs.wisc.edusystem.ruby.IFETCH.miss_latency_hist::total       817732                      
96410526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::bucket_size          128                      
96510526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::max_bucket         1279                      
96610526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::samples       494265                      
96710526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::mean      6.023605                      
96810526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::gmean     3.954302                      
96910526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::stdev    10.239189                      
97010526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist        |      494082     99.96%     99.96% |         137      0.03%     99.99% |          14      0.00%     99.99% |          17      0.00%    100.00% |          10      0.00%    100.00% |           5      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
97110526Snilay@cs.wisc.edusystem.ruby.RMW_Read.latency_hist::total       494265                      
97210013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::bucket_size            1                      
97310013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::max_bucket            9                      
97410526Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::samples       428815                      
97510013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::mean            3                      
97610013Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::gmean     3.000000                      
97710526Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist    |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      428815    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
97810526Snilay@cs.wisc.edusystem.ruby.RMW_Read.hit_latency_hist::total       428815                      
97910526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::bucket_size          128                      
98010526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::max_bucket         1279                      
98110526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::samples        65450                      
98210526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::mean    25.833644                      
98310526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::gmean    24.151736                      
98410526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::stdev    18.422970                      
98510526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist   |       65267     99.72%     99.72% |         137      0.21%     99.93% |          14      0.02%     99.95% |          17      0.03%     99.98% |          10      0.02%     99.99% |           5      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
98610526Snilay@cs.wisc.edusystem.ruby.RMW_Read.miss_latency_hist::total        65450                      
98710526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::bucket_size          128                      
98810526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::max_bucket         1279                      
98910526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::samples       339542                      
99010526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::mean     5.330551                      
99110526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::gmean     3.775845                      
99210526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::stdev     8.064390                      
99310526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist |      339293     99.93%     99.93% |         238      0.07%    100.00% |           4      0.00%    100.00% |           3      0.00%    100.00% |           1      0.00%    100.00% |           3      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
99410526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.latency_hist::total       339542                      
99510013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size            1                      
99610013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket            9                      
99710526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::samples       300644                      
99810013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::mean            3                      
99910013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::gmean     3.000000                      
100010526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      300644    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
100110526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.hit_latency_hist::total       300644                      
100210526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size          128                      
100310526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket         1279                      
100410526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::samples        38898                      
100510526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::mean    23.343462                      
100610526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::gmean    22.340350                      
100710526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::stdev    14.186116                      
100810526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist |       38649     99.36%     99.36% |         238      0.61%     99.97% |           4      0.01%     99.98% |           3      0.01%     99.99% |           1      0.00%     99.99% |           3      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
100910526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Read.miss_latency_hist::total        38898                      
101010013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::bucket_size            1                      
101110013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::max_bucket            9                      
101210526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::samples       339542                      
101310013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::mean            3                      
101410013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::gmean     3.000000                      
101510526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339542    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
101610526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.latency_hist::total       339542                      
101710013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size            1                      
101810013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket            9                      
101910526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::samples       339542                      
102010013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::mean            3                      
102110013Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::gmean     3.000000                      
102210526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |      339542    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
102310526Snilay@cs.wisc.edusystem.ruby.Locked_RMW_Write.hit_latency_hist::total       339542                      
102410526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load      |     6037097     40.47%     40.47% |     8881067     59.53%    100.00%
102510526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Load::total     14918164                      
102610526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch    |    67778726     53.56%     53.56% |    58760197     46.44%    100.00%
102710526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ifetch::total    126538923                      
102810526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store     |     5166241     48.41%     48.41% |     5505308     51.59%    100.00%
102910526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Store::total     10671549                      
103010526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Inv       |       16573     48.71%     48.71% |       17448     51.29%    100.00%
103110526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Inv::total        34021                      
103210526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.L1_Replacement |      807951     30.97%     30.97% |     1801234     69.03%    100.00%
103310526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.L1_Replacement::total      2609185                      
103410526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETX  |       12319     50.77%     50.77% |       11946     49.23%    100.00%
103510526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETX::total        24265                      
103610526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETS  |       14009     55.59%     55.59% |       11192     44.41%    100.00%
103710526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GETS::total        25201                      
103810013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
103910013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR::total            4                      
104010526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data      |         658     37.77%     37.77% |        1084     62.23%    100.00%
104110526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data::total         1742                      
104210526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_Exclusive |      243874     19.04%     19.04% |     1037006     80.96%    100.00%
104310526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_Exclusive::total      1280880                      
104410526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.DataS_fromL1 |       11192     44.40%     44.40% |       14013     55.60%    100.00%
104510526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.DataS_fromL1::total        25205                      
104610526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_all_Acks |      567820     42.55%     42.55% |      766775     57.45%    100.00%
104710526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Data_all_Acks::total      1334595                      
104810526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack       |       12283     55.41%     55.41% |        9885     44.59%    100.00%
104910526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack::total        22168                      
105010526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack_all   |       12941     54.12%     54.12% |       10969     45.88%    100.00%
105110526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Ack_all::total        23910                      
105210526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.WB_Ack    |      454484     26.95%     26.95% |     1231800     73.05%    100.00%
105310526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.WB_Ack::total      1686284                      
105410526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Load   |      272421     19.86%     19.86% |     1099369     80.14%    100.00%
105510526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Load::total      1371790                      
105610526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Ifetch |      317175     38.82%     38.82% |      499890     61.18%    100.00%
105710526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Ifetch::total       817065                      
105810526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Store  |      219379     51.94%     51.94% |      202999     48.06%    100.00%
105910526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Store::total       422378                      
106010526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Inv    |        5530     57.31%     57.31% |        4119     42.69%    100.00%
106110526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.NP.Inv::total         9649                      
106210526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load    |        8637     45.64%     45.64% |       10286     54.36%    100.00%
106310526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Load::total        18923                      
106410526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch  |         116     17.39%     17.39% |         551     82.61%    100.00%
106510526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Ifetch::total          667                      
106610526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store   |        5816     50.14%     50.14% |        5783     49.86%    100.00%
106710526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.Store::total        11599                      
106810526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.L1_Replacement |        8686     50.09%     50.09% |        8655     49.91%    100.00%
106910526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.I.L1_Replacement::total        17341                      
107010526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Load    |      551952     52.35%     52.35% |      502332     47.65%    100.00%
107110526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Load::total      1054284                      
107210526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Ifetch  |    67461431     53.66%     53.66% |    58259753     46.34%    100.00%
107310526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Ifetch::total    125721184                      
107410526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Store   |       12283     55.41%     55.41% |        9885     44.59%    100.00%
107510526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Store::total        22168                      
107610526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Inv     |       10821     45.28%     45.28% |       13078     54.72%    100.00%
107710526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.Inv::total        23899                      
107810526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.L1_Replacement |      344781     38.07%     38.07% |      560779     61.93%    100.00%
107910526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.S.L1_Replacement::total       905560                      
108010526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Load    |     1077334     27.76%     27.76% |     2803511     72.24%    100.00%
108110526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Load::total      3880845                      
108210526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Store   |       80360     48.21%     48.21% |       86332     51.79%    100.00%
108310526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Store::total       166692                      
108410526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Inv     |          55     56.12%     56.12% |          43     43.88%    100.00%
108510526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Inv::total           98                      
108610526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.L1_Replacement |      162044     14.59%     14.59% |      948886     85.41%    100.00%
108710526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.L1_Replacement::total      1110930                      
108810526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETX |         433     65.81%     65.81% |         225     34.19%    100.00%
108910526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETX::total          658                      
109010526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETS |         907     40.65%     40.65% |        1324     59.35%    100.00%
109110526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.E.Fwd_GETS::total         2231                      
109210526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load    |     4126753     48.03%     48.03% |     4465569     51.97%    100.00%
109310526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Load::total      8592322                      
109410526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store   |     4848403     48.25%     48.25% |     5200309     51.75%    100.00%
109510526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Store::total     10048712                      
109610526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Inv     |         167     44.53%     44.53% |         208     55.47%    100.00%
109710526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Inv::total          375                      
109810526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.L1_Replacement |      292440     50.83%     50.83% |      282914     49.17%    100.00%
109910526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.L1_Replacement::total       575354                      
110010526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETX |       11886     50.35%     50.35% |       11721     49.65%    100.00%
110110526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETX::total        23607                      
110210526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETS |       13102     57.04%     57.04% |        9868     42.96%    100.00%
110310526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GETS::total        22970                      
110410013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
110510013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total            4                      
110610526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_Exclusive |      243874     19.04%     19.04% |     1037006     80.96%    100.00%
110710526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1280880                      
110810526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.DataS_fromL1 |       11192     44.40%     44.40% |       14013     55.60%    100.00%
110910526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.DataS_fromL1::total        25205                      
111010526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_all_Acks |      343283     38.04%     38.04% |      559077     61.96%    100.00%
111110526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IS.Data_all_Acks::total       902360                      
111210526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data   |         658     37.77%     37.77% |        1084     62.23%    100.00%
111310526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data::total         1742                      
111410526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data_all_Acks |      224537     51.95%     51.95% |      207698     48.05%    100.00%
111510526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.IM.Data_all_Acks::total       432235                      
111610526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack    |       12283     55.41%     55.41% |        9885     44.59%    100.00%
111710526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack::total        22168                      
111810526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack_all |       12941     54.12%     54.12% |       10969     45.88%    100.00%
111910526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.SM.Ack_all::total        23910                      
112010526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.Ifetch |           4     57.14%     57.14% |           3     42.86%    100.00%
112110451Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.Ifetch::total            7                      
112210526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.WB_Ack |      454484     26.95%     26.95% |     1231800     73.05%    100.00%
112310526Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M_I.WB_Ack::total      1686284                      
112410526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_GET_INSTR       817732      0.00%      0.00%
112510526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_GETS        1390884      0.00%      0.00%
112610526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_GETX         433978      0.00%      0.00%
112710526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_UPGRADE        22168      0.00%      0.00%
112810526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L1_PUTX        1686284      0.00%      0.00%
112910526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L2_Replacement        95716      0.00%      0.00%
113010526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.L2_Replacement_clean        15992      0.00%      0.00%
113110526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Mem_Data        178413      0.00%      0.00%
113210526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Mem_Ack         113648      0.00%      0.00%
113310526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.WB_Data          23349      0.00%      0.00%
113410526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.WB_Data_clean         2231      0.00%      0.00%
113510526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Ack               1814      0.00%      0.00%
113610526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Ack_all           7922      0.00%      0.00%
113710526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Unblock          25205      0.00%      0.00%
113810526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.Exclusive_Unblock      1737025      0.00%      0.00%
113910526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MEM_Inv           3880      0.00%      0.00%
114010526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.NP.L1_GET_INSTR        16558      0.00%      0.00%
114110526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.NP.L1_GETS        34140      0.00%      0.00%
114210526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.NP.L1_GETX       127715      0.00%      0.00%
114310526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_GET_INSTR       801143      0.00%      0.00%
114410526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_GETS        84632      0.00%      0.00%
114510526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_GETX         1919      0.00%      0.00%
114610526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L1_UPGRADE        22168      0.00%      0.00%
114710526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L2_Replacement          243      0.00%      0.00%
114810526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.L2_Replacement_clean         7577      0.00%      0.00%
114910526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS.MEM_Inv            4      0.00%      0.00%
115010526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L1_GET_INSTR           27      0.00%      0.00%
115110526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L1_GETS      1246740      0.00%      0.00%
115210526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L1_GETX       280078      0.00%      0.00%
115310526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L2_Replacement        95328      0.00%      0.00%
115410526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.L2_Replacement_clean         8315      0.00%      0.00%
115510526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M.MEM_Inv         1708      0.00%      0.00%
115610013Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GET_INSTR            4      0.00%      0.00%
115710526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GETS        25201      0.00%      0.00%
115810526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GETX        24265      0.00%      0.00%
115910526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_PUTX      1686284      0.00%      0.00%
116010526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L2_Replacement          145      0.00%      0.00%
116110526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L2_Replacement_clean          100      0.00%      0.00%
116210526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.MEM_Inv          228      0.00%      0.00%
116310526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M_I.Mem_Ack       113648      0.00%      0.00%
116410526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.M_I.MEM_Inv         1708      0.00%      0.00%
116510526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_I.WB_Data          330      0.00%      0.00%
116610526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_I.Ack_all           43      0.00%      0.00%
116710526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_I.MEM_Inv          228      0.00%      0.00%
116810526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MCT_I.WB_Data           45      0.00%      0.00%
116910526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MCT_I.Ack_all           55      0.00%      0.00%
117010526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.I_I.Ack           1567      0.00%      0.00%
117110526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.I_I.Ack_all         7577      0.00%      0.00%
117210526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.S_I.Ack            247      0.00%      0.00%
117310526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.S_I.Ack_all          247      0.00%      0.00%
117410526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.S_I.MEM_Inv            4      0.00%      0.00%
117510526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.ISS.Mem_Data        34140      0.00%      0.00%
117610526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.IS.Mem_Data        16558      0.00%      0.00%
117710526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.IM.Mem_Data       127715      0.00%      0.00%
117810526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS_MB.L1_GETS          125      0.00%      0.00%
117910526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        24087      0.00%      0.00%
118010526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_MB.L1_GETS           46      0.00%      0.00%
118110409Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_MB.L1_GETX            1      0.00%      0.00%
118210526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1712938      0.00%      0.00%
118310526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IIB.WB_Data        22969      0.00%      0.00%
118410526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2231      0.00%      0.00%
118510526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IIB.Unblock            5      0.00%      0.00%
118610451Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_IB.WB_Data            5      0.00%      0.00%
118710526Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT_SB.Unblock        25200      0.00%      0.00%
118810526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.ReadRequest   |         814    100.00%    100.00% |           0      0.00%    100.00%
118910526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.ReadRequest::total          814                      
119010526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.WriteRequest  |       46736    100.00%    100.00% |           0      0.00%    100.00%
119110526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.WriteRequest::total        46736                      
119210526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.Data          |         814    100.00%    100.00% |           0      0.00%    100.00%
119310526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.Data::total            814                      
119410526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.Ack           |       46736    100.00%    100.00% |           0      0.00%    100.00%
119510526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.Ack::total           46736                      
119610526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.READY.ReadRequest |         814    100.00%    100.00% |           0      0.00%    100.00%
119710526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.READY.ReadRequest::total          814                      
119810526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.READY.WriteRequest |       46736    100.00%    100.00% |           0      0.00%    100.00%
119910526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.READY.WriteRequest::total        46736                      
120010526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.BUSY_RD.Data  |         814    100.00%    100.00% |           0      0.00%    100.00%
120110526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.BUSY_RD.Data::total          814                      
120210526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.BUSY_WR.Ack   |       46736    100.00%    100.00% |           0      0.00%    100.00%
120310526Snilay@cs.wisc.edusystem.ruby.DMA_Controller.BUSY_WR.Ack::total        46736                      
120410526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Fetch         178413      0.00%      0.00%
120510526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Data           97701      0.00%      0.00%
120610526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Data       178865      0.00%      0.00%
120710526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.Memory_Ack       142859      0.00%      0.00%
120810526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.DMA_READ          814      0.00%      0.00%
120910013Snilay@cs.wisc.edusystem.ruby.Directory_Controller.DMA_WRITE        46736      0.00%      0.00%
121010526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.CleanReplacement        15947      0.00%      0.00%
121110526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.Fetch       178413      0.00%      0.00%
121210526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.DMA_READ          452      0.00%      0.00%
121310526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.I.DMA_WRITE        45158      0.00%      0.00%
121410526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.ID.Memory_Data          452      0.00%      0.00%
121510526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.ID_W.Memory_Ack        45158      0.00%      0.00%
121610526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.Data         95761      0.00%      0.00%
121710526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.DMA_READ          362      0.00%      0.00%
121810526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.DMA_WRITE         1578      0.00%      0.00%
121910526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M.CleanReplacement        15947      0.00%      0.00%
122010526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.IM.Memory_Data       178413      0.00%      0.00%
122110526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.MI.Memory_Ack        95761      0.00%      0.00%
122210526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DRD.Data          362      0.00%      0.00%
122310526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DRDI.Memory_Ack          362      0.00%      0.00%
122410526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DWR.Data         1578      0.00%      0.00%
122510526Snilay@cs.wisc.edusystem.ruby.Directory_Controller.M_DWRI.Memory_Ack         1578      0.00%      0.00%
12268968SN/A
12278968SN/A---------- End Simulation Statistics   ----------
1228