18968SN/A
28968SN/A---------- Begin Simulation Statistics ----------
311374Ssteve.reinhardt@amd.comsim_seconds                                  5.220167                       # Number of seconds simulated
411374Ssteve.reinhardt@amd.comsim_ticks                                5220166723500                       # Number of ticks simulated
511374Ssteve.reinhardt@amd.comfinal_tick                               5220166723500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68968SN/Asim_freq                                 1000000000000                       # Frequency of simulated ticks
711502SCurtis.Dunham@arm.comhost_inst_rate                                 281505                       # Simulator instruction rate (inst/s)
811502SCurtis.Dunham@arm.comhost_op_rate                                   546613                       # Simulator op (including micro ops) rate (op/s)
911502SCurtis.Dunham@arm.comhost_tick_rate                             9727443238                       # Simulator tick rate (ticks/s)
1011502SCurtis.Dunham@arm.comhost_mem_usage                                 784792                       # Number of bytes of host memory used
1111502SCurtis.Dunham@arm.comhost_seconds                                   536.64                       # Real time elapsed on the host
1211374Ssteve.reinhardt@amd.comsim_insts                                   151067812                       # Number of instructions simulated
1311374Ssteve.reinhardt@amd.comsim_ops                                     293336428                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                          1000                       # Clock period in ticks
1611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_read::ruby.dir_cntrl0     11621312                       # Number of bytes read from this memory
1711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_read::total           11621312                       # Number of bytes read from this memory
1811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_written::ruby.dir_cntrl0      9422976                       # Number of bytes written to this memory
1911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytes_written::total         9422976                       # Number of bytes written to this memory
2011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_reads::ruby.dir_cntrl0       181583                       # Number of read requests responded to by this memory
2111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_reads::total              181583                       # Number of read requests responded to by this memory
2211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_writes::ruby.dir_cntrl0       147234                       # Number of write requests responded to by this memory
2311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.num_writes::total             147234                       # Number of write requests responded to by this memory
2411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_read::ruby.dir_cntrl0      2226234                       # Total read bandwidth from this memory (bytes/s)
2511374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_read::total               2226234                       # Total read bandwidth from this memory (bytes/s)
2611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_write::ruby.dir_cntrl0      1805110                       # Write bandwidth from this memory (bytes/s)
2711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_write::total              1805110                       # Write bandwidth from this memory (bytes/s)
2811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_total::ruby.dir_cntrl0      4031344                       # Total bandwidth to/from this memory (bytes/s)
2911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bw_total::total              4031344                       # Total bandwidth to/from this memory (bytes/s)
3011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.readReqs                      181583                       # Number of read requests accepted
3111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.writeReqs                     147234                       # Number of write requests accepted
3211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.readBursts                    181583                       # Number of DRAM read bursts, including those serviced by the write queue
3311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.writeBursts                   147234                       # Number of DRAM write bursts, including those merged in the write queue
3411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesReadDRAM               11591808                       # Total number of bytes read from DRAM
3511374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesReadWrQ                   29504                       # Total number of bytes read from write queue
3611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesWritten                 9419008                       # Total number of bytes written to DRAM
3711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesReadSys                11621312                       # Total read bytes from the system interface side
3811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesWrittenSys              9422976                       # Total written bytes from the system interface side
3911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.servicedByWrQ                    461                       # Number of DRAM read bursts serviced by the write queue
4011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.mergedWrBursts                    33                       # Number of DRAM write bursts merged with an existing one
4110526Snilay@cs.wisc.edusystem.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
4211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::0             11329                       # Per bank write bursts
4311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::1             10774                       # Per bank write bursts
4411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::2             10935                       # Per bank write bursts
4511374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::3             11505                       # Per bank write bursts
4611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::4             11170                       # Per bank write bursts
4711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::5             10899                       # Per bank write bursts
4811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::6             11836                       # Per bank write bursts
4911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::7             10884                       # Per bank write bursts
5011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::8             12484                       # Per bank write bursts
5111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::9             12159                       # Per bank write bursts
5211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::10            11756                       # Per bank write bursts
5311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::11            12007                       # Per bank write bursts
5411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::12            11147                       # Per bank write bursts
5511374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::13            10761                       # Per bank write bursts
5611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::14            10863                       # Per bank write bursts
5711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankRdBursts::15            10613                       # Per bank write bursts
5811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::0             10067                       # Per bank write bursts
5911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::1              9205                       # Per bank write bursts
6011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::2              8897                       # Per bank write bursts
6111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::3              9266                       # Per bank write bursts
6211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::4              9038                       # Per bank write bursts
6311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::5              9160                       # Per bank write bursts
6411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::6              9230                       # Per bank write bursts
6511201Sandreas.hansson@arm.comsystem.mem_ctrls.perBankWrBursts::7              8385                       # Per bank write bursts
6611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::8              9312                       # Per bank write bursts
6711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::9              9251                       # Per bank write bursts
6811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::10             9047                       # Per bank write bursts
6911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::11             9790                       # Per bank write bursts
7011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::12             9121                       # Per bank write bursts
7111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::13             9097                       # Per bank write bursts
7211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::14             9389                       # Per bank write bursts
7311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.perBankWrBursts::15             8917                       # Per bank write bursts
7410526Snilay@cs.wisc.edusystem.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
7510526Snilay@cs.wisc.edusystem.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
7611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.totGap                  5220166614000                       # Total gap between requests
7710526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
7810526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
7910526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
8010526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
8110526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
8210526Snilay@cs.wisc.edusystem.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
8311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.readPktSize::6                181583                       # Read request sizes (log2)
8410526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
8510526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
8610526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
8710526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
8810526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
8910526Snilay@cs.wisc.edusystem.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
9011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.writePktSize::6               147234                       # Write request sizes (log2)
9111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::0                  181021                       # What read queue length does an incoming req see
9211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdQLenPdf::1                     101                       # What read queue length does an incoming req see
9310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::2                       0                       # What read queue length does an incoming req see
9410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
9510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
9610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
9710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
9810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
9910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
10010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
10110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
10210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
10310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
10410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
10510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
10610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
10710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
10810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
10910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
11010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
11110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
11210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
11310526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
11410526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
11510526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
11610526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
11710526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
11810526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
11910526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
12010526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
12110526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
12210526Snilay@cs.wisc.edusystem.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
12310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
12410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
12510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
12610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
12710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
12810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
12910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
13010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
13110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
13210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
13310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
13410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
13510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
13610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
13710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
13811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::15                   2012                       # What write queue length does an incoming req see
13911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::16                   2729                       # What write queue length does an incoming req see
14011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::17                   8785                       # What write queue length does an incoming req see
14111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::18                   9320                       # What write queue length does an incoming req see
14211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::19                   8843                       # What write queue length does an incoming req see
14311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::20                   9495                       # What write queue length does an incoming req see
14411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::21                   9462                       # What write queue length does an incoming req see
14511374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::22                   8653                       # What write queue length does an incoming req see
14611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::23                   9363                       # What write queue length does an incoming req see
14711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::24                   9364                       # What write queue length does an incoming req see
14811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::25                   8726                       # What write queue length does an incoming req see
14911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::26                   8830                       # What write queue length does an incoming req see
15011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::27                   8641                       # What write queue length does an incoming req see
15111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::28                   8729                       # What write queue length does an incoming req see
15211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::29                   8351                       # What write queue length does an incoming req see
15311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::30                   8407                       # What write queue length does an incoming req see
15411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::31                   8469                       # What write queue length does an incoming req see
15511374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::32                   8257                       # What write queue length does an incoming req see
15611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::33                    137                       # What write queue length does an incoming req see
15711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::34                    112                       # What write queue length does an incoming req see
15811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::35                     95                       # What write queue length does an incoming req see
15911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::36                     89                       # What write queue length does an incoming req see
16011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::37                     83                       # What write queue length does an incoming req see
16111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::38                     61                       # What write queue length does an incoming req see
16211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::39                     57                       # What write queue length does an incoming req see
16311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::40                     44                       # What write queue length does an incoming req see
16411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::41                     32                       # What write queue length does an incoming req see
16511201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::42                     21                       # What write queue length does an incoming req see
16611201Sandreas.hansson@arm.comsystem.mem_ctrls.wrQLenPdf::43                     12                       # What write queue length does an incoming req see
16711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::44                      7                       # What write queue length does an incoming req see
16811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
16911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
17011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
17110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
17210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
17310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
17410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
17510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
17610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
17710526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
17810526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
17910526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
18010526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
18110526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
18210526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
18310526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
18410526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
18510526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
18610526Snilay@cs.wisc.edusystem.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
18711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::samples        59923                       # Bytes accessed per row activation
18811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::mean    350.629174                       # Bytes accessed per row activation
18911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::gmean   206.226666                       # Bytes accessed per row activation
19011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::stdev   350.561474                       # Bytes accessed per row activation
19111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::0-127        19936     33.27%     33.27% # Bytes accessed per row activation
19211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::128-255        13794     23.02%     56.29% # Bytes accessed per row activation
19311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::256-383         6108     10.19%     66.48% # Bytes accessed per row activation
19411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::384-511         3634      6.06%     72.55% # Bytes accessed per row activation
19511374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::512-639         2579      4.30%     76.85% # Bytes accessed per row activation
19611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::640-767         1995      3.33%     80.18% # Bytes accessed per row activation
19711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::768-895         1624      2.71%     82.89% # Bytes accessed per row activation
19811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::896-1023         1412      2.36%     85.25% # Bytes accessed per row activation
19911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::1024-1151         8841     14.75%    100.00% # Bytes accessed per row activation
20011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.bytesPerActivate::total        59923                       # Bytes accessed per row activation
20111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdPerTurnAround::samples         8207                       # Reads before turning the bus around for writes
20211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdPerTurnAround::mean      22.065919                       # Reads before turning the bus around for writes
20311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdPerTurnAround::stdev    311.578267                       # Reads before turning the bus around for writes
20411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdPerTurnAround::0-1023         8201     99.93%     99.93% # Reads before turning the bus around for writes
20510892Sandreas.hansson@arm.comsystem.mem_ctrls.rdPerTurnAround::1024-2047            3      0.04%     99.96% # Reads before turning the bus around for writes
20611026Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
20710526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::10240-11263            1      0.01%     99.99% # Reads before turning the bus around for writes
20810526Snilay@cs.wisc.edusystem.mem_ctrls.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
20911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.rdPerTurnAround::total          8207                       # Reads before turning the bus around for writes
21011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::samples         8207                       # Writes before turning the bus around for reads
21111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::mean      17.932497                       # Writes before turning the bus around for reads
21211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::gmean     17.599692                       # Writes before turning the bus around for reads
21311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::stdev      3.953739                       # Writes before turning the bus around for reads
21411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::16             6146     74.89%     74.89% # Writes before turning the bus around for reads
21511374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::17               20      0.24%     75.13% # Writes before turning the bus around for reads
21611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::18              127      1.55%     76.68% # Writes before turning the bus around for reads
21711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::19               26      0.32%     77.00% # Writes before turning the bus around for reads
21811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::20               39      0.48%     77.47% # Writes before turning the bus around for reads
21911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::21              486      5.92%     83.39% # Writes before turning the bus around for reads
22011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::22              193      2.35%     85.74% # Writes before turning the bus around for reads
22111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::23               58      0.71%     86.45% # Writes before turning the bus around for reads
22211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::24              617      7.52%     93.97% # Writes before turning the bus around for reads
22311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::25              104      1.27%     95.24% # Writes before turning the bus around for reads
22411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::26                8      0.10%     95.33% # Writes before turning the bus around for reads
22511374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::27               15      0.18%     95.52% # Writes before turning the bus around for reads
22611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::28              293      3.57%     99.09% # Writes before turning the bus around for reads
22711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::29                4      0.05%     99.13% # Writes before turning the bus around for reads
22811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::30                1      0.01%     99.15% # Writes before turning the bus around for reads
22911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::31                3      0.04%     99.18% # Writes before turning the bus around for reads
23011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::32               10      0.12%     99.31% # Writes before turning the bus around for reads
23111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::33                5      0.06%     99.37% # Writes before turning the bus around for reads
23211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::34                2      0.02%     99.39% # Writes before turning the bus around for reads
23311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::35                2      0.02%     99.42% # Writes before turning the bus around for reads
23411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::36                5      0.06%     99.48% # Writes before turning the bus around for reads
23511374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::37                1      0.01%     99.49% # Writes before turning the bus around for reads
23611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::38                5      0.06%     99.55% # Writes before turning the bus around for reads
23711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::39                2      0.02%     99.57% # Writes before turning the bus around for reads
23811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::40                3      0.04%     99.61% # Writes before turning the bus around for reads
23911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::41                5      0.06%     99.67% # Writes before turning the bus around for reads
24011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::42                2      0.02%     99.70% # Writes before turning the bus around for reads
24111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::43                3      0.04%     99.73% # Writes before turning the bus around for reads
24211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::44                3      0.04%     99.77% # Writes before turning the bus around for reads
24311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::45                5      0.06%     99.83% # Writes before turning the bus around for reads
24411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::46                2      0.02%     99.85% # Writes before turning the bus around for reads
24511374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::47                1      0.01%     99.87% # Writes before turning the bus around for reads
24611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::48                4      0.05%     99.91% # Writes before turning the bus around for reads
24711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::49                2      0.02%     99.94% # Writes before turning the bus around for reads
24811201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::50                1      0.01%     99.95% # Writes before turning the bus around for reads
24911201Sandreas.hansson@arm.comsystem.mem_ctrls.wrPerTurnAround::51                4      0.05%    100.00% # Writes before turning the bus around for reads
25011374Ssteve.reinhardt@amd.comsystem.mem_ctrls.wrPerTurnAround::total          8207                       # Writes before turning the bus around for reads
25111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.totQLat                   1926054246                       # Total ticks spent queuing
25211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.totMemAccLat              5322091746                       # Total ticks spent from burst creation until serviced by the DRAM
25311374Ssteve.reinhardt@amd.comsystem.mem_ctrls.totBusLat                  905610000                       # Total ticks spent in databus transfers
25411374Ssteve.reinhardt@amd.comsystem.mem_ctrls.avgQLat                     10634.02                       # Average queueing delay per DRAM burst
25510526Snilay@cs.wisc.edusystem.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
25611374Ssteve.reinhardt@amd.comsystem.mem_ctrls.avgMemAccLat                29384.02                       # Average memory access latency per DRAM burst
25711026Snilay@cs.wisc.edusystem.mem_ctrls.avgRdBW                         2.22                       # Average DRAM read bandwidth in MiByte/s
25811201Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrBW                         1.80                       # Average achieved write bandwidth in MiByte/s
25911201Sandreas.hansson@arm.comsystem.mem_ctrls.avgRdBWSys                      2.23                       # Average system read bandwidth in MiByte/s
26011201Sandreas.hansson@arm.comsystem.mem_ctrls.avgWrBWSys                      1.81                       # Average system write bandwidth in MiByte/s
26110526Snilay@cs.wisc.edusystem.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
26210526Snilay@cs.wisc.edusystem.mem_ctrls.busUtil                         0.03                       # Data bus utilization in percentage
26310526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilRead                     0.02                       # Data bus utilization in percentage for reads
26410526Snilay@cs.wisc.edusystem.mem_ctrls.busUtilWrite                    0.01                       # Data bus utilization in percentage for writes
26510526Snilay@cs.wisc.edusystem.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
26611281Sstever@gmail.comsystem.mem_ctrls.avgWrQLen                      25.93                       # Average write queue length when enqueuing
26711374Ssteve.reinhardt@amd.comsystem.mem_ctrls.readRowHits                   146815                       # Number of row buffer hits during reads
26811374Ssteve.reinhardt@amd.comsystem.mem_ctrls.writeRowHits                  121555                       # Number of row buffer hits during writes
26911374Ssteve.reinhardt@amd.comsystem.mem_ctrls.readRowHitRate                 81.06                       # Row buffer hit rate for reads
27011201Sandreas.hansson@arm.comsystem.mem_ctrls.writeRowHitRate                82.58                       # Row buffer hit rate for writes
27111374Ssteve.reinhardt@amd.comsystem.mem_ctrls.avgGap                   15875598.32                       # Average gap between requests
27211374Ssteve.reinhardt@amd.comsystem.mem_ctrls.pageHitRate                    81.74                       # Row buffer hit rate, read and write combined
27311374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.actEnergy                222014520                       # Energy for activate commands per rank (pJ)
27411374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.preEnergy                121138875                       # Energy for precharge commands per rank (pJ)
27511374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.readEnergy               696781800                       # Energy for read commands per rank (pJ)
27611374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.writeEnergy              474647040                       # Energy for write commands per rank (pJ)
27711374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.refreshEnergy         340955406480                       # Energy for refresh commands per rank (pJ)
27811374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.actBackEnergy         139500530325                       # Energy for active background per rank (pJ)
27911374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.preBackEnergy         3009726629250                       # Energy for precharge background per rank (pJ)
28011374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.totalEnergy           3491697148290                       # Total energy per rank (pJ)
28111374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.averagePower            668.887101                       # Core power per rank (mW)
28211374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.memoryStateTime::IDLE 5006844557250                       # Time in different power states
28311374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.memoryStateTime::REF  174312580000                       # Time in different power states
28410628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
28511374Ssteve.reinhardt@amd.comsystem.mem_ctrls_0.memoryStateTime::ACT   39009485750                       # Time in different power states
28610628Sandreas.hansson@arm.comsystem.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
28711374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.actEnergy                231003360                       # Energy for activate commands per rank (pJ)
28811374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.preEnergy                126043500                       # Energy for precharge commands per rank (pJ)
28911374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.readEnergy               715962000                       # Energy for read commands per rank (pJ)
29011374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.writeEnergy              479027520                       # Energy for write commands per rank (pJ)
29111374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.refreshEnergy         340955406480                       # Energy for refresh commands per rank (pJ)
29211374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.actBackEnergy         139411599210                       # Energy for active background per rank (pJ)
29311374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.preBackEnergy         3009804639000                       # Energy for precharge background per rank (pJ)
29411374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.totalEnergy           3491723681070                       # Total energy per rank (pJ)
29511374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.averagePower            668.892184                       # Core power per rank (mW)
29611374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.memoryStateTime::IDLE 5006961679500                       # Time in different power states
29711374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.memoryStateTime::REF  174312580000                       # Time in different power states
29810628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
29911374Ssteve.reinhardt@amd.comsystem.mem_ctrls_1.memoryStateTime::ACT   38884946750                       # Time in different power states
30010628Sandreas.hansson@arm.comsystem.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
30110315Snilay@cs.wisc.edusystem.cpu_clk_domain.clock                       500                       # Clock period in ticks
30210036SAli.Saidi@ARM.comsystem.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
30311374Ssteve.reinhardt@amd.comsystem.cpu0.numCycles                     10440333447                       # number of cpu cycles simulated
3048968SN/Asystem.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
3058968SN/Asystem.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
30611201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
30711201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
30811374Ssteve.reinhardt@amd.comsystem.cpu0.committedInsts                  100619599                       # Number of instructions committed
30911374Ssteve.reinhardt@amd.comsystem.cpu0.committedOps                    194912227                       # Number of ops (including micro ops) committed
31011374Ssteve.reinhardt@amd.comsystem.cpu0.num_int_alu_accesses            182208047                       # Number of integer alu accesses
31110645Snilay@cs.wisc.edusystem.cpu0.num_fp_alu_accesses                    48                       # Number of float alu accesses
31211374Ssteve.reinhardt@amd.comsystem.cpu0.num_func_calls                    1789060                       # number of times a function call or return occured
31311374Ssteve.reinhardt@amd.comsystem.cpu0.num_conditional_control_insts     17876463                       # number of instructions that are conditional controls
31411374Ssteve.reinhardt@amd.comsystem.cpu0.num_int_insts                   182208047                       # number of integer instructions
31510645Snilay@cs.wisc.edusystem.cpu0.num_fp_insts                           48                       # number of float instructions
31611374Ssteve.reinhardt@amd.comsystem.cpu0.num_int_register_reads          340866599                       # number of times the integer registers were read
31711374Ssteve.reinhardt@amd.comsystem.cpu0.num_int_register_writes         155423898                       # number of times the integer registers were written
31810645Snilay@cs.wisc.edusystem.cpu0.num_fp_register_reads                  48                       # number of times the floating registers were read
3198968SN/Asystem.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
32011374Ssteve.reinhardt@amd.comsystem.cpu0.num_cc_register_reads           104641558                       # number of times the CC registers were read
32111374Ssteve.reinhardt@amd.comsystem.cpu0.num_cc_register_writes           75150612                       # number of times the CC registers were written
32211374Ssteve.reinhardt@amd.comsystem.cpu0.num_mem_refs                     18466644                       # number of memory refs
32311374Ssteve.reinhardt@amd.comsystem.cpu0.num_load_insts                   11577076                       # Number of load instructions
32411374Ssteve.reinhardt@amd.comsystem.cpu0.num_store_insts                   6889568                       # Number of store instructions
32511374Ssteve.reinhardt@amd.comsystem.cpu0.num_idle_cycles              9942379374.520096                       # Number of idle cycles
32611374Ssteve.reinhardt@amd.comsystem.cpu0.num_busy_cycles              497954072.479905                       # Number of busy cycles
32711374Ssteve.reinhardt@amd.comsystem.cpu0.not_idle_fraction                0.047695                       # Percentage of non-idle cycles
32811374Ssteve.reinhardt@amd.comsystem.cpu0.idle_fraction                    0.952305                       # Percentage of idle cycles
32911374Ssteve.reinhardt@amd.comsystem.cpu0.Branches                         20277624                       # Number of branches fetched
33011374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::No_OpClass               187137      0.10%      0.10% # Class of executed instruction
33111374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::IntAlu                176059705     90.33%     90.42% # Class of executed instruction
33211374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::IntMult                  119089      0.06%     90.48% # Class of executed instruction
33311374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::IntDiv                    84733      0.04%     90.53% # Class of executed instruction
33411374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatAdd                      0      0.00%     90.53% # Class of executed instruction
33511374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatCmp                      0      0.00%     90.53% # Class of executed instruction
33611374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatCvt                     16      0.00%     90.53% # Class of executed instruction
33711374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatMult                     0      0.00%     90.53% # Class of executed instruction
33811374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatDiv                      0      0.00%     90.53% # Class of executed instruction
33911374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::FloatSqrt                     0      0.00%     90.53% # Class of executed instruction
34011374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdAdd                       0      0.00%     90.53% # Class of executed instruction
34111374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdAddAcc                    0      0.00%     90.53% # Class of executed instruction
34211374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdAlu                       0      0.00%     90.53% # Class of executed instruction
34311374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdCmp                       0      0.00%     90.53% # Class of executed instruction
34411374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdCvt                       0      0.00%     90.53% # Class of executed instruction
34511374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdMisc                      0      0.00%     90.53% # Class of executed instruction
34611374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdMult                      0      0.00%     90.53% # Class of executed instruction
34711374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdMultAcc                   0      0.00%     90.53% # Class of executed instruction
34811374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdShift                     0      0.00%     90.53% # Class of executed instruction
34911374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.53% # Class of executed instruction
35011374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdSqrt                      0      0.00%     90.53% # Class of executed instruction
35111374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.53% # Class of executed instruction
35211374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.53% # Class of executed instruction
35311374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.53% # Class of executed instruction
35411374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.53% # Class of executed instruction
35511374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.53% # Class of executed instruction
35611374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.53% # Class of executed instruction
35711374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatMult                 0      0.00%     90.53% # Class of executed instruction
35811374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.53% # Class of executed instruction
35911374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.53% # Class of executed instruction
36011374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::MemRead                11572910      5.94%     96.47% # Class of executed instruction
36111374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::MemWrite                6889568      3.53%    100.00% # Class of executed instruction
36210220Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
36310220Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
36411374Ssteve.reinhardt@amd.comsystem.cpu0.op_class::total                 194913158                       # Class of executed instruction
36510036SAli.Saidi@ARM.comsystem.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
36611374Ssteve.reinhardt@amd.comsystem.cpu1.numCycles                     10439192066                       # number of cpu cycles simulated
3678968SN/Asystem.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
3688968SN/Asystem.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
36911201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
37011201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
37111374Ssteve.reinhardt@amd.comsystem.cpu1.committedInsts                   50448213                       # Number of instructions committed
37211374Ssteve.reinhardt@amd.comsystem.cpu1.committedOps                     98424201                       # Number of ops (including micro ops) committed
37311374Ssteve.reinhardt@amd.comsystem.cpu1.num_int_alu_accesses             91824874                       # Number of integer alu accesses
37410645Snilay@cs.wisc.edusystem.cpu1.num_fp_alu_accesses                    48                       # Number of float alu accesses
37511374Ssteve.reinhardt@amd.comsystem.cpu1.num_func_calls                     991908                       # number of times a function call or return occured
37611374Ssteve.reinhardt@amd.comsystem.cpu1.num_conditional_control_insts      9137643                       # number of instructions that are conditional controls
37711374Ssteve.reinhardt@amd.comsystem.cpu1.num_int_insts                    91824874                       # number of integer instructions
37810645Snilay@cs.wisc.edusystem.cpu1.num_fp_insts                           48                       # number of float instructions
37911374Ssteve.reinhardt@amd.comsystem.cpu1.num_int_register_reads          171791517                       # number of times the integer registers were read
38011374Ssteve.reinhardt@amd.comsystem.cpu1.num_int_register_writes          78447804                       # number of times the integer registers were written
38110645Snilay@cs.wisc.edusystem.cpu1.num_fp_register_reads                  48                       # number of times the floating registers were read
3828968SN/Asystem.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
38311374Ssteve.reinhardt@amd.comsystem.cpu1.num_cc_register_reads            52143431                       # number of times the CC registers were read
38411374Ssteve.reinhardt@amd.comsystem.cpu1.num_cc_register_writes           36991088                       # number of times the CC registers were written
38511374Ssteve.reinhardt@amd.comsystem.cpu1.num_mem_refs                      8627580                       # number of memory refs
38611374Ssteve.reinhardt@amd.comsystem.cpu1.num_load_insts                    5530314                       # Number of load instructions
38711374Ssteve.reinhardt@amd.comsystem.cpu1.num_store_insts                   3097266                       # Number of store instructions
38811374Ssteve.reinhardt@amd.comsystem.cpu1.num_idle_cycles              10278680276.738028                       # Number of idle cycles
38911374Ssteve.reinhardt@amd.comsystem.cpu1.num_busy_cycles              160511789.261972                       # Number of busy cycles
39011374Ssteve.reinhardt@amd.comsystem.cpu1.not_idle_fraction                0.015376                       # Percentage of non-idle cycles
39111374Ssteve.reinhardt@amd.comsystem.cpu1.idle_fraction                    0.984624                       # Percentage of idle cycles
39211374Ssteve.reinhardt@amd.comsystem.cpu1.Branches                         10492962                       # Number of branches fetched
39311374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::No_OpClass               118368      0.12%      0.12% # Class of executed instruction
39411374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::IntAlu                 89576077     91.01%     91.13% # Class of executed instruction
39511374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::IntMult                   66940      0.07%     91.20% # Class of executed instruction
39611374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::IntDiv                    40064      0.04%     91.24% # Class of executed instruction
39711374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatAdd                      0      0.00%     91.24% # Class of executed instruction
39811374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatCmp                      0      0.00%     91.24% # Class of executed instruction
39911374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatCvt                     16      0.00%     91.24% # Class of executed instruction
40011374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatMult                     0      0.00%     91.24% # Class of executed instruction
40111374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatDiv                      0      0.00%     91.24% # Class of executed instruction
40211374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::FloatSqrt                     0      0.00%     91.24% # Class of executed instruction
40311374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdAdd                       0      0.00%     91.24% # Class of executed instruction
40411374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdAddAcc                    0      0.00%     91.24% # Class of executed instruction
40511374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdAlu                       0      0.00%     91.24% # Class of executed instruction
40611374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdCmp                       0      0.00%     91.24% # Class of executed instruction
40711374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdCvt                       0      0.00%     91.24% # Class of executed instruction
40811374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdMisc                      0      0.00%     91.24% # Class of executed instruction
40911374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdMult                      0      0.00%     91.24% # Class of executed instruction
41011374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdMultAcc                   0      0.00%     91.24% # Class of executed instruction
41111374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdShift                     0      0.00%     91.24% # Class of executed instruction
41211374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdShiftAcc                  0      0.00%     91.24% # Class of executed instruction
41311374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdSqrt                      0      0.00%     91.24% # Class of executed instruction
41411374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatAdd                  0      0.00%     91.24% # Class of executed instruction
41511374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatAlu                  0      0.00%     91.24% # Class of executed instruction
41611374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatCmp                  0      0.00%     91.24% # Class of executed instruction
41711374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatCvt                  0      0.00%     91.24% # Class of executed instruction
41811374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatDiv                  0      0.00%     91.24% # Class of executed instruction
41911374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatMisc                 0      0.00%     91.24% # Class of executed instruction
42011374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatMult                 0      0.00%     91.24% # Class of executed instruction
42111374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatMultAcc              0      0.00%     91.24% # Class of executed instruction
42211374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::SimdFloatSqrt                 0      0.00%     91.24% # Class of executed instruction
42311374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::MemRead                 5526131      5.61%     96.85% # Class of executed instruction
42411374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::MemWrite                3097266      3.15%    100.00% # Class of executed instruction
42510220Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
42610220Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
42711374Ssteve.reinhardt@amd.comsystem.cpu1.op_class::total                  98424862                       # Class of executed instruction
42811374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::ReadReq               883871                       # Transaction distribution
42911374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::ReadResp              883871                       # Transaction distribution
43011374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::WriteReq               36792                       # Transaction distribution
43111374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::WriteResp              36792                       # Transaction distribution
43211374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::MessageReq              1835                       # Transaction distribution
43311374Ssteve.reinhardt@amd.comsystem.iobus.trans_dist::MessageResp             1835                       # Transaction distribution
43411201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         1736                       # Packet count per connected master and slave (bytes)
43511201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         1682                       # Packet count per connected master and slave (bytes)
43611201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3418                       # Packet count per connected master and slave (bytes)
43711201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
43811374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         6166                       # Packet count per connected master and slave (bytes)
43911201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          712                       # Packet count per connected master and slave (bytes)
44011201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           74                       # Packet count per connected master and slave (bytes)
44111201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           38                       # Packet count per connected master and slave (bytes)
44210560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
44311201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       917434                       # Packet count per connected master and slave (bytes)
44411374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1234                       # Packet count per connected master and slave (bytes)
44511201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           90                       # Packet count per connected master and slave (bytes)
44610560Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
44711374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio        14088                       # Packet count per connected master and slave (bytes)
44811374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port       811278                       # Packet count per connected master and slave (bytes)
44911374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          180                       # Packet count per connected master and slave (bytes)
45011281Sstever@gmail.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pci_host.pio         2214                       # Packet count per connected master and slave (bytes)
45111374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      1753576                       # Packet count per connected master and slave (bytes)
45211201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           16                       # Packet count per connected master and slave (bytes)
45311201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
45411374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         4922                       # Packet count per connected master and slave (bytes)
45511201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          652                       # Packet count per connected master and slave (bytes)
45611201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           12                       # Packet count per connected master and slave (bytes)
45711201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
45811201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        31650                       # Packet count per connected master and slave (bytes)
45911374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio          876                       # Packet count per connected master and slave (bytes)
46011201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        31738                       # Packet count per connected master and slave (bytes)
46111374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio        13284                       # Packet count per connected master and slave (bytes)
46211201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
46311201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
46411201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
46511201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
46611374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port           72                       # Packet count per connected master and slave (bytes)
46711374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         4620                       # Packet count per connected master and slave (bytes)
46811281Sstever@gmail.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.pci_host.pio           92                       # Packet count per connected master and slave (bytes)
46911374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        88002                       # Packet count per connected master and slave (bytes)
47011374Ssteve.reinhardt@amd.comsystem.iobus.pkt_count::total                 1844996                       # Packet count per connected master and slave (bytes)
47111201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port         3472                       # Cumulative packet size per connected master and slave (bytes)
47211201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port         3364                       # Cumulative packet size per connected master and slave (bytes)
47311201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6836                       # Cumulative packet size per connected master and slave (bytes)
47411201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
47511374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3506                       # Cumulative packet size per connected master and slave (bytes)
47611201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          356                       # Cumulative packet size per connected master and slave (bytes)
47711201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio           37                       # Cumulative packet size per connected master and slave (bytes)
47811201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio           19                       # Cumulative packet size per connected master and slave (bytes)
47910560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
48011201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio       458717                       # Cumulative packet size per connected master and slave (bytes)
48111374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         2468                       # Cumulative packet size per connected master and slave (bytes)
48211201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio           45                       # Cumulative packet size per connected master and slave (bytes)
48310560Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
48411374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio         7044                       # Cumulative packet size per connected master and slave (bytes)
48511374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port      1622550                       # Cumulative packet size per connected master and slave (bytes)
48611374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port          360                       # Cumulative packet size per connected master and slave (bytes)
48711281Sstever@gmail.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pci_host.pio         4401                       # Cumulative packet size per connected master and slave (bytes)
48811374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total      2099537                       # Cumulative packet size per connected master and slave (bytes)
48911201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio            8                       # Cumulative packet size per connected master and slave (bytes)
49011201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
49111374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio         3180                       # Cumulative packet size per connected master and slave (bytes)
49211201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio          326                       # Cumulative packet size per connected master and slave (bytes)
49311201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio            6                       # Cumulative packet size per connected master and slave (bytes)
49411201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
49511201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio        15825                       # Cumulative packet size per connected master and slave (bytes)
49611374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio         1752                       # Cumulative packet size per connected master and slave (bytes)
49711201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio        15869                       # Cumulative packet size per connected master and slave (bytes)
49811374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio         6642                       # Cumulative packet size per connected master and slave (bytes)
49911201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50011201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50111201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
50211201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
50311374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port          144                       # Cumulative packet size per connected master and slave (bytes)
50411374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port         9237                       # Cumulative packet size per connected master and slave (bytes)
50511281Sstever@gmail.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.pci_host.pio           72                       # Cumulative packet size per connected master and slave (bytes)
50611374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total        53095                       # Cumulative packet size per connected master and slave (bytes)
50711374Ssteve.reinhardt@amd.comsystem.iobus.pkt_size::total                  2159468                       # Cumulative packet size per connected master and slave (bytes)
50811201Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy                43000                       # Layer occupancy (ticks)
50910560Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
51011201Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy                 7500                       # Layer occupancy (ticks)
51110560Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
51211374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer2.occupancy              9083500                       # Layer occupancy (ticks)
51310560Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
51411281Sstever@gmail.comsystem.iobus.reqLayer3.occupancy               944500                       # Layer occupancy (ticks)
51510560Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
51611281Sstever@gmail.comsystem.iobus.reqLayer4.occupancy                84500                       # Layer occupancy (ticks)
51710560Sandreas.hansson@arm.comsystem.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
51811281Sstever@gmail.comsystem.iobus.reqLayer5.occupancy                51500                       # Layer occupancy (ticks)
51910560Sandreas.hansson@arm.comsystem.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
52011281Sstever@gmail.comsystem.iobus.reqLayer6.occupancy             21127500                       # Layer occupancy (ticks)
52110560Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
52211281Sstever@gmail.comsystem.iobus.reqLayer7.occupancy            458718000                       # Layer occupancy (ticks)
52310560Sandreas.hansson@arm.comsystem.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
52411374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer8.occupancy              1783484                       # Layer occupancy (ticks)
52510560Sandreas.hansson@arm.comsystem.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
52611281Sstever@gmail.comsystem.iobus.reqLayer9.occupancy             31828500                       # Layer occupancy (ticks)
52710560Sandreas.hansson@arm.comsystem.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
52811281Sstever@gmail.comsystem.iobus.reqLayer11.occupancy                2500                       # Layer occupancy (ticks)
52911281Sstever@gmail.comsystem.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
53011281Sstever@gmail.comsystem.iobus.reqLayer12.occupancy            20524000                       # Layer occupancy (ticks)
53110560Sandreas.hansson@arm.comsystem.iobus.reqLayer12.utilization               0.0                       # Layer utilization (%)
53211281Sstever@gmail.comsystem.iobus.reqLayer13.occupancy                9000                       # Layer occupancy (ticks)
53310560Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
53411201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
53510560Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
53610892Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
53710560Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
53811281Sstever@gmail.comsystem.iobus.reqLayer16.occupancy               11500                       # Layer occupancy (ticks)
53910560Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
54011374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer17.occupancy           410414499                       # Layer occupancy (ticks)
54110560Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
54211374Ssteve.reinhardt@amd.comsystem.iobus.reqLayer18.occupancy             7700146                       # Layer occupancy (ticks)
54310560Sandreas.hansson@arm.comsystem.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
54411281Sstever@gmail.comsystem.iobus.reqLayer20.occupancy             1751500                       # Layer occupancy (ticks)
54511281Sstever@gmail.comsystem.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
54611374Ssteve.reinhardt@amd.comsystem.iobus.respLayer0.occupancy             2638190                       # Layer occupancy (ticks)
54710560Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
54811374Ssteve.reinhardt@amd.comsystem.iobus.respLayer2.occupancy          1947717500                       # Layer occupancy (ticks)
54910560Sandreas.hansson@arm.comsystem.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
55011374Ssteve.reinhardt@amd.comsystem.iobus.respLayer4.occupancy            60917000                       # Layer occupancy (ticks)
55110560Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
55210560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
55310560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
55411374Ssteve.reinhardt@amd.comsystem.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
55510560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
55610560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_bytes      2987008                       # Number of bytes transfered via DMA writes.
55711201Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
55810560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
55910560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
56010560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
56110560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
56210560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
56310560Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
56410560Sandreas.hansson@arm.comsystem.ruby.clk_domain.clock                      500                       # Clock period in ticks
56510560Sandreas.hansson@arm.comsystem.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
56610560Sandreas.hansson@arm.comsystem.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
56711374Ssteve.reinhardt@amd.comsystem.ruby.delayHist::samples               11184165                       # delay histogram for all message
56811374Ssteve.reinhardt@amd.comsystem.ruby.delayHist::mean                  0.431974                       # delay histogram for all message
56911374Ssteve.reinhardt@amd.comsystem.ruby.delayHist::stdev                 1.810021                       # delay histogram for all message
57011374Ssteve.reinhardt@amd.comsystem.ruby.delayHist                    |    10580766     94.60%     94.60% |        2101      0.02%     94.62% |      600708      5.37%     99.99% |         188      0.00%    100.00% |         323      0.00%    100.00% |           9      0.00%    100.00% |          67      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
57111374Ssteve.reinhardt@amd.comsystem.ruby.delayHist::total                 11184165                       # delay histogram for all message
57211336Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist_seqr::bucket_size            1                      
57311336Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist_seqr::max_bucket            9                      
57411374Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_seqr::samples    197976054                      
57511336Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist_seqr::mean     1.000129                      
57611336Sandreas.hansson@arm.comsystem.ruby.outstanding_req_hist_seqr::gmean     1.000089                      
57711374Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_seqr::stdev     0.011359                      
57811374Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_seqr    |           0      0.00%      0.00% |   197950506     99.99%     99.99% |       25548      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
57911374Ssteve.reinhardt@amd.comsystem.ruby.outstanding_req_hist_seqr::total    197976054                      
58011336Sandreas.hansson@arm.comsystem.ruby.latency_hist_seqr::bucket_size          128                      
58111336Sandreas.hansson@arm.comsystem.ruby.latency_hist_seqr::max_bucket         1279                      
58211374Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_seqr::samples      197976053                      
58311374Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_seqr::mean          1.340875                      
58411374Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_seqr::gmean         1.042170                      
58511374Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_seqr::stdev         5.085216                      
58611374Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_seqr            |   197940485     99.98%     99.98% |       26707      0.01%    100.00% |        2933      0.00%    100.00% |        3350      0.00%    100.00% |        1606      0.00%    100.00% |         905      0.00%    100.00% |           4      0.00%    100.00% |          34      0.00%    100.00% |          22      0.00%    100.00% |           7      0.00%    100.00%
58711374Ssteve.reinhardt@amd.comsystem.ruby.latency_hist_seqr::total        197976053                      
58811336Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist_seqr::bucket_size            1                      
58911336Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist_seqr::max_bucket            9                      
59011374Ssteve.reinhardt@amd.comsystem.ruby.hit_latency_hist_seqr::samples    195263006                      
59111336Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist_seqr::mean             1                      
59211336Sandreas.hansson@arm.comsystem.ruby.hit_latency_hist_seqr::gmean            1                      
59311374Ssteve.reinhardt@amd.comsystem.ruby.hit_latency_hist_seqr        |           0      0.00%      0.00% |   195263006    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
59411374Ssteve.reinhardt@amd.comsystem.ruby.hit_latency_hist_seqr::total    195263006                      
59511336Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist_seqr::bucket_size          128                      
59611336Sandreas.hansson@arm.comsystem.ruby.miss_latency_hist_seqr::max_bucket         1279                      
59711374Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_seqr::samples      2713047                      
59811374Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_seqr::mean    25.874270                      
59911374Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_seqr::gmean    20.370607                      
60011374Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_seqr::stdev    35.731774                      
60111374Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_seqr       |     2677479     98.69%     98.69% |       26707      0.98%     99.67% |        2933      0.11%     99.78% |        3350      0.12%     99.90% |        1606      0.06%     99.96% |         905      0.03%    100.00% |           4      0.00%    100.00% |          34      0.00%    100.00% |          22      0.00%    100.00% |           7      0.00%    100.00%
60211374Ssteve.reinhardt@amd.comsystem.ruby.miss_latency_hist_seqr::total      2713047                      
60311374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.L1Dcache.demand_hits     16414226                       # Number of cache demand hits
60411374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.L1Dcache.demand_misses      1206044                       # Number of cache demand misses
60511374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.L1Dcache.demand_accesses     17620270                       # Number of cache demand accesses
60611374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.L1Icache.demand_hits    114568727                       # Number of cache demand hits
60711374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.L1Icache.demand_misses       549758                       # Number of cache demand misses
60811374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.L1Icache.demand_accesses    115118485                       # Number of cache demand accesses
60910560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
61010560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
61110560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
61210560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
61310560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
61410560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.hits               0                       # number of prefetched blocks accessed
61510560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
61610560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
61710560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
61811374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl0.fully_busy_cycles            13                       # cycles for which number of transistions == max transitions
61911374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl1.L1Dcache.demand_hits      7924165                       # Number of cache demand hits
62011374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl1.L1Dcache.demand_misses       686474                       # Number of cache demand misses
62111374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl1.L1Dcache.demand_accesses      8610639                       # Number of cache demand accesses
62211374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl1.L1Icache.demand_hits     56355888                       # Number of cache demand hits
62311374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl1.L1Icache.demand_misses       270771                       # Number of cache demand misses
62411374Ssteve.reinhardt@amd.comsystem.ruby.l1_cntrl1.L1Icache.demand_accesses     56626659                       # Number of cache demand accesses
62510560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.miss_observed            0                       # number of misses observed
62610560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
62710560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.prefetches_requested            0                       # number of prefetch requests made
62810560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
62910560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
63010560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.hits               0                       # number of prefetched blocks accessed
63110560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
63210560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.pages_crossed            0                       # number of prefetches across pages
63310560Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
63411201Sandreas.hansson@arm.comsystem.ruby.l1_cntrl1.fully_busy_cycles            14                       # cycles for which number of transistions == max transitions
63511374Ssteve.reinhardt@amd.comsystem.ruby.l2_cntrl0.L2cache.demand_hits      2479845                       # Number of cache demand hits
63611374Ssteve.reinhardt@amd.comsystem.ruby.l2_cntrl0.L2cache.demand_misses       233202                       # Number of cache demand misses
63711374Ssteve.reinhardt@amd.comsystem.ruby.l2_cntrl0.L2cache.demand_accesses      2713047                       # Number of cache demand accesses
63810560Sandreas.hansson@arm.comsystem.ruby.memctrl_clk_domain.clock             1500                       # Clock period in ticks
63911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.percent_links_utilized     0.058980                      
64011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Control::0      1755802                      
64111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Request_Control::2        45794                      
64211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Response_Data::1      1784920                      
64311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Response_Control::1      1171907                      
64411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Response_Control::2      1168239                      
64511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Writeback_Data::0       411948                      
64611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Writeback_Data::1          195                      
64711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_count.Writeback_Control::0       715361                      
64811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Control::0     14046416                      
64911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Request_Control::2       366352                      
65011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Response_Data::1    128514240                      
65111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Response_Control::1      9375256                      
65211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Response_Control::2      9345912                      
65311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Writeback_Data::0     29660256                      
65411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Writeback_Data::1        14040                      
65511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.msg_bytes.Writeback_Control::0      5722888                      
65611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.percent_links_utilized     0.031273                      
65711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Control::0       957245                      
65811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Request_Control::2        41954                      
65911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Response_Data::1       983466                      
66011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Response_Control::1       655818                      
66111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Response_Control::2       654857                      
66211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Writeback_Data::0       160205                      
66311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Writeback_Data::1          305                      
66411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_count.Writeback_Control::0       454250                      
66511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Control::0      7657960                      
66611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Request_Control::2       335632                      
66711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Response_Data::1     70809552                      
66811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Response_Control::1      5246544                      
66911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Response_Control::2      5238856                      
67011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Writeback_Data::0     11534760                      
67111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Writeback_Data::1        21960                      
67211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.msg_bytes.Writeback_Control::0      3634000                      
67311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.percent_links_utilized     0.094749                      
67411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Control::0      2894160                      
67511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Request_Control::2        85903                      
67611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Response_Data::1      2948232                      
67711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Response_Control::1      1907805                      
67811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Response_Control::2      1823096                      
67911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Writeback_Data::0       572153                      
68011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Writeback_Data::1          500                      
68111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_count.Writeback_Control::0      1169611                      
68211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Control::0     23153280                      
68311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Request_Control::2       687224                      
68411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Response_Data::1    212272704                      
68511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Response_Control::1     15262440                      
68611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Response_Control::2     14584768                      
68711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Writeback_Data::0     41195016                      
68811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Writeback_Data::1        36000                      
68911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.msg_bytes.Writeback_Control::0      9356888                      
69011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.percent_links_utilized     0.007115                      
69111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.msg_count.Control::0       181113                      
69211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.msg_count.Response_Data::1       284840                      
69311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.msg_count.Response_Control::1       132538                      
69411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.msg_count.Writeback_Control::0        47552                      
69510560Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_count.Writeback_Control::1        46736                      
69611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.msg_bytes.Control::0      1448904                      
69711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.msg_bytes.Response_Data::1     20508480                      
69811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.msg_bytes.Response_Control::1      1060304                      
69911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.msg_bytes.Writeback_Control::0       380416                      
70010560Sandreas.hansson@arm.comsystem.ruby.network.routers3.msg_bytes.Writeback_Control::1       373888                      
70111026Snilay@cs.wisc.edusystem.ruby.network.routers4.percent_links_utilized     0.000243                      
70211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers4.msg_count.Response_Data::1          816                      
70311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers4.msg_count.Writeback_Control::0        47552                      
70410560Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_count.Writeback_Control::1        46736                      
70511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers4.msg_bytes.Response_Data::1        58752                      
70611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers4.msg_bytes.Writeback_Control::0       380416                      
70710560Sandreas.hansson@arm.comsystem.ruby.network.routers4.msg_bytes.Writeback_Control::1       373888                      
70810560Sandreas.hansson@arm.comsystem.ruby.network.routers5.percent_links_utilized            0                      
70911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.percent_links_utilized     0.032061                      
71011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_count.Control::0      2894160                      
71111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_count.Request_Control::2        87748                      
71211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_count.Response_Data::1      3001137                      
71311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_count.Response_Control::1      1934034                      
71411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_count.Response_Control::2      1823096                      
71511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_count.Writeback_Data::0       572153                      
71611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_count.Writeback_Data::1          500                      
71711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_count.Writeback_Control::0      1217163                      
71810560Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_count.Writeback_Control::1        46736                      
71911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_bytes.Control::0     23153280                      
72011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_bytes.Request_Control::2       701984                      
72111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_bytes.Response_Data::1    216081864                      
72211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_bytes.Response_Control::1     15472272                      
72311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_bytes.Response_Control::2     14584768                      
72411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_bytes.Writeback_Data::0     41195016                      
72511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_bytes.Writeback_Data::1        36000                      
72611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.msg_bytes.Writeback_Control::0      9737304                      
72710560Sandreas.hansson@arm.comsystem.ruby.network.routers6.msg_bytes.Writeback_Control::1       373888                      
72811374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Control         8682480                      
72911374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Request_Control       261399                      
73011374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Response_Data      9003411                      
73111374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Response_Control     11271390                      
73211374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Writeback_Data      1717959                      
73311374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_count.Writeback_Control      3791697                      
73411374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Control         69459840                      
73511374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Request_Control      2091192                      
73611374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Response_Data    648245592                      
73711374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Response_Control     90171120                      
73811374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Writeback_Data    123693048                      
73911374Ssteve.reinhardt@amd.comsystem.ruby.network.msg_byte.Writeback_Control     30333576                      
74011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.link_utilization     0.080870                      
74111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_count.Request_Control::2        45794                      
74211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_count.Response_Data::1      1742990                      
74311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_count.Response_Control::1      1153454                      
74411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2       366352                      
74511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1    125495280                      
74611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1      9227632                      
74711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.link_utilization     0.037089                      
74811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_count.Control::0      1755802                      
74911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_count.Response_Data::1        41930                      
75011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_count.Response_Control::1        18453                      
75111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_count.Response_Control::2      1168239                      
75211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0       411948                      
75311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1          195                      
75411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0       715361                      
75511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_bytes.Control::0     14046416                      
75611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1      3018960                      
75711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1       147624                      
75811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2      9345912                      
75911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0     29660256                      
76011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1        14040                      
76111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0      5722888                      
76211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.link_utilization     0.044014                      
76311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_count.Request_Control::2        41954                      
76411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_count.Response_Data::1       945484                      
76511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_count.Response_Control::1       639112                      
76611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2       335632                      
76711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1     68074848                      
76811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1      5112896                      
76911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.link_utilization     0.018531                      
77011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_count.Control::0       957245                      
77111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Data::1        37982                      
77211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Control::1        16706                      
77311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_count.Response_Control::2       654857                      
77411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0       160205                      
77511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1          305                      
77611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0       454250                      
77711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_bytes.Control::0      7657960                      
77811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1      2734704                      
77911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1       133648                      
78011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2      5238856                      
78111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0     11534760                      
78211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1        21960                      
78311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0      3634000                      
78411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.link_utilization     0.061627                      
78511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_count.Control::0      2713047                      
78611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Data::1       208936                      
78711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Control::1       128034                      
78811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_count.Response_Control::2      1823096                      
78911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0       572153                      
79011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1          500                      
79111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0      1169611                      
79211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_bytes.Control::0     21704376                      
79311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1     15043392                      
79411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1      1024272                      
79511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2     14584768                      
79611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0     41195016                      
79711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1        36000                      
79811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0      9356888                      
79911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.link_utilization     0.127872                      
80011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_count.Control::0       181113                      
80111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_count.Request_Control::2        85903                      
80211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_count.Response_Data::1      2739296                      
80311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_count.Response_Control::1      1779771                      
80411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_bytes.Control::0      1448904                      
80511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2       687224                      
80611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1    197229312                      
80711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1     14238168                      
80811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle0.link_utilization     0.005595                      
80911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle0.msg_count.Control::0       181113                      
81011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle0.msg_count.Response_Data::1       102911                      
81111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle0.msg_count.Response_Control::1        13434                      
81211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0        47552                      
81311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle0.msg_bytes.Control::0      1448904                      
81411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1      7409592                      
81511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1       107472                      
81611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0       380416                      
81711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle1.link_utilization     0.008636                      
81811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle1.msg_count.Response_Data::1       181929                      
81911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle1.msg_count.Response_Control::1       119104                      
8209978SN/Asystem.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1        46736                      
82111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1     13098888                      
82211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1       952832                      
8239978SN/Asystem.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1       373888                      
82411026Snilay@cs.wisc.edusystem.ruby.network.routers4.throttle0.link_utilization     0.000259                      
82511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers4.throttle0.msg_count.Response_Data::1          816                      
8269978SN/Asystem.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1        46736                      
82711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1        58752                      
8289978SN/Asystem.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1       373888                      
82911201Sandreas.hansson@arm.comsystem.ruby.network.routers4.throttle1.link_utilization     0.000228                      
83011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0        47552                      
83111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0       380416                      
83210526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle0.link_utilization            0                      
83310526Snilay@cs.wisc.edusystem.ruby.network.routers5.throttle1.link_utilization            0                      
83411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle0.link_utilization     0.080870                      
83511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle0.msg_count.Request_Control::2        45794                      
83611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle0.msg_count.Response_Data::1      1742990                      
83711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle0.msg_count.Response_Control::1      1153454                      
83811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2       366352                      
83911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1    125495280                      
84011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1      9227632                      
84111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle1.link_utilization     0.044014                      
84211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle1.msg_count.Request_Control::2        41954                      
84311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle1.msg_count.Response_Data::1       945484                      
84411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle1.msg_count.Response_Control::1       639112                      
84511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2       335632                      
84611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1     68074848                      
84711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1      5112896                      
84811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.link_utilization     0.061627                      
84911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_count.Control::0      2713047                      
85011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_count.Response_Data::1       208936                      
85111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_count.Response_Control::1       128034                      
85211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_count.Response_Control::2      1823096                      
85311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0       572153                      
85411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1          500                      
85511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0      1169611                      
85611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_bytes.Control::0     21704376                      
85711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1     15043392                      
85811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1      1024272                      
85911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2     14584768                      
86011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0     41195016                      
86111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1        36000                      
86211374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0      9356888                      
86311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle3.link_utilization     0.005595                      
86411374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle3.msg_count.Control::0       181113                      
86511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle3.msg_count.Response_Data::1       102911                      
86611374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle3.msg_count.Response_Control::1        13434                      
86711374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0        47552                      
86811374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle3.msg_bytes.Control::0      1448904                      
86911374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1      7409592                      
87011374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1       107472                      
87111374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0       380416                      
87211026Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.link_utilization     0.000259                      
87311374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle4.msg_count.Response_Data::1          816                      
87410526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1        46736                      
87511374Ssteve.reinhardt@amd.comsystem.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1        58752                      
87610526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1       373888                      
87710526Snilay@cs.wisc.edusystem.ruby.network.routers6.throttle5.link_utilization            0                      
87810229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::bucket_size            4                       # delay histogram for vnet_0
87910229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_0::max_bucket           39                       # delay histogram for vnet_0
88011374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_0::samples       6277907                       # delay histogram for vnet_0
88111374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_0::mean         0.731657                       # delay histogram for vnet_0
88211374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_0::stdev        2.309527                       # delay histogram for vnet_0
88311374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_0           |     5704590     90.87%     90.87% |         579      0.01%     90.88% |      572160      9.11%     99.99% |         182      0.00%     99.99% |         317      0.01%    100.00% |           9      0.00%    100.00% |          67      0.00%    100.00% |           2      0.00%    100.00% |           1      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_0
88411374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_0::total         6277907                       # delay histogram for vnet_0
88510229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::bucket_size            2                       # delay histogram for vnet_1
88610229Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_1::max_bucket           19                       # delay histogram for vnet_1
88711374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_1::samples       4818510                       # delay histogram for vnet_1
88811374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_1::mean         0.049390                       # delay histogram for vnet_1
88911374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_1::stdev        0.622960                       # delay histogram for vnet_1
89011374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_1           |     4787836     99.36%     99.36% |         592      0.01%     99.38% |         677      0.01%     99.39% |         845      0.02%     99.41% |       28317      0.59%     99.99% |         231      0.00%    100.00% |           4      0.00%    100.00% |           2      0.00%    100.00% |           3      0.00%    100.00% |           3      0.00%    100.00% # delay histogram for vnet_1
89111374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_1::total         4818510                       # delay histogram for vnet_1
89210315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::bucket_size            1                       # delay histogram for vnet_2
89310315Snilay@cs.wisc.edusystem.ruby.delayVCHist.vnet_2::max_bucket            9                       # delay histogram for vnet_2
89411374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_2::samples         87748                       # delay histogram for vnet_2
89511374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_2::mean         0.000137                       # delay histogram for vnet_2
89611374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_2::stdev        0.016538                       # delay histogram for vnet_2
89711374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_2           |       87742     99.99%     99.99% |           0      0.00%     99.99% |           6      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for vnet_2
89811374Ssteve.reinhardt@amd.comsystem.ruby.delayVCHist.vnet_2::total           87748                       # delay histogram for vnet_2
89911336Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist_seqr::bucket_size          128                      
90011336Sandreas.hansson@arm.comsystem.ruby.LD.latency_hist_seqr::max_bucket         1279                      
90111374Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr::samples     15434919                      
90211374Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr::mean       2.853771                      
90311374Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr::gmean      1.313299                      
90411374Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr::stdev      9.010453                      
90511374Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr         |    15420072     99.90%     99.90% |       12855      0.08%     99.99% |         824      0.01%     99.99% |         752      0.00%    100.00% |         311      0.00%    100.00% |          93      0.00%    100.00% |           1      0.00%    100.00% |           6      0.00%    100.00% |           3      0.00%    100.00% |           2      0.00%    100.00%
90611374Ssteve.reinhardt@amd.comsystem.ruby.LD.latency_hist_seqr::total      15434919                      
90711336Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist_seqr::bucket_size            1                      
90811336Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist_seqr::max_bucket            9                      
90911374Ssteve.reinhardt@amd.comsystem.ruby.LD.hit_latency_hist_seqr::samples     14000797                      
91011336Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist_seqr::mean            1                      
91111336Sandreas.hansson@arm.comsystem.ruby.LD.hit_latency_hist_seqr::gmean            1                      
91211374Ssteve.reinhardt@amd.comsystem.ruby.LD.hit_latency_hist_seqr     |           0      0.00%      0.00% |    14000797    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
91311374Ssteve.reinhardt@amd.comsystem.ruby.LD.hit_latency_hist_seqr::total     14000797                      
91411336Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist_seqr::bucket_size          128                      
91511336Sandreas.hansson@arm.comsystem.ruby.LD.miss_latency_hist_seqr::max_bucket         1279                      
91611374Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr::samples      1434122                      
91711374Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr::mean    20.951441                      
91811374Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr::gmean    18.789020                      
91911374Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr::stdev    22.643422                      
92011374Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr    |     1419275     98.96%     98.96% |       12855      0.90%     99.86% |         824      0.06%     99.92% |         752      0.05%     99.97% |         311      0.02%     99.99% |          93      0.01%    100.00% |           1      0.00%    100.00% |           6      0.00%    100.00% |           3      0.00%    100.00% |           2      0.00%    100.00%
92111374Ssteve.reinhardt@amd.comsystem.ruby.LD.miss_latency_hist_seqr::total      1434122                      
92211336Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist_seqr::bucket_size          128                      
92311336Sandreas.hansson@arm.comsystem.ruby.ST.latency_hist_seqr::max_bucket         1279                      
92411374Ssteve.reinhardt@amd.comsystem.ruby.ST.latency_hist_seqr::samples      9614411                      
92511374Ssteve.reinhardt@amd.comsystem.ruby.ST.latency_hist_seqr::mean       3.236789                      
92611374Ssteve.reinhardt@amd.comsystem.ruby.ST.latency_hist_seqr::gmean      1.144007                      
92711374Ssteve.reinhardt@amd.comsystem.ruby.ST.latency_hist_seqr::stdev     17.965589                      
92811374Ssteve.reinhardt@amd.comsystem.ruby.ST.latency_hist_seqr         |     9599857     99.85%     99.85% |        8650      0.09%     99.94% |        1610      0.02%     99.96% |        2319      0.02%     99.98% |        1166      0.01%     99.99% |         762      0.01%    100.00% |           3      0.00%    100.00% |          22      0.00%    100.00% |          17      0.00%    100.00% |           5      0.00%    100.00%
92911374Ssteve.reinhardt@amd.comsystem.ruby.ST.latency_hist_seqr::total       9614411                      
93011336Sandreas.hansson@arm.comsystem.ruby.ST.hit_latency_hist_seqr::bucket_size            1                      
93111336Sandreas.hansson@arm.comsystem.ruby.ST.hit_latency_hist_seqr::max_bucket            9                      
93211374Ssteve.reinhardt@amd.comsystem.ruby.ST.hit_latency_hist_seqr::samples      9260487                      
93311336Sandreas.hansson@arm.comsystem.ruby.ST.hit_latency_hist_seqr::mean            1                      
93411336Sandreas.hansson@arm.comsystem.ruby.ST.hit_latency_hist_seqr::gmean            1                      
93511374Ssteve.reinhardt@amd.comsystem.ruby.ST.hit_latency_hist_seqr     |           0      0.00%      0.00% |     9260487    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
93611374Ssteve.reinhardt@amd.comsystem.ruby.ST.hit_latency_hist_seqr::total      9260487                      
93711336Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist_seqr::bucket_size          128                      
93811336Sandreas.hansson@arm.comsystem.ruby.ST.miss_latency_hist_seqr::max_bucket         1279                      
93911374Ssteve.reinhardt@amd.comsystem.ruby.ST.miss_latency_hist_seqr::samples       353924                      
94011374Ssteve.reinhardt@amd.comsystem.ruby.ST.miss_latency_hist_seqr::mean    61.762782                      
94111374Ssteve.reinhardt@amd.comsystem.ruby.ST.miss_latency_hist_seqr::gmean    38.656662                      
94211374Ssteve.reinhardt@amd.comsystem.ruby.ST.miss_latency_hist_seqr::stdev    72.192186                      
94311374Ssteve.reinhardt@amd.comsystem.ruby.ST.miss_latency_hist_seqr    |      339370     95.89%     95.89% |        8650      2.44%     98.33% |        1610      0.45%     98.79% |        2319      0.66%     99.44% |        1166      0.33%     99.77% |         762      0.22%     99.99% |           3      0.00%     99.99% |          22      0.01%     99.99% |          17      0.00%    100.00% |           5      0.00%    100.00%
94411374Ssteve.reinhardt@amd.comsystem.ruby.ST.miss_latency_hist_seqr::total       353924                      
94511336Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist_seqr::bucket_size          128                      
94611336Sandreas.hansson@arm.comsystem.ruby.IFETCH.latency_hist_seqr::max_bucket         1279                      
94711374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.latency_hist_seqr::samples    171745144                      
94811374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.latency_hist_seqr::mean     1.087707                      
94911374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.latency_hist_seqr::gmean     1.013816                      
95011374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.latency_hist_seqr::stdev     1.870223                      
95111374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.latency_hist_seqr     |   171739420    100.00%    100.00% |        4825      0.00%    100.00% |         474      0.00%    100.00% |         262      0.00%    100.00% |         112      0.00%    100.00% |          43      0.00%    100.00% |           0      0.00%    100.00% |           6      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
95211374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.latency_hist_seqr::total    171745144                      
95311336Sandreas.hansson@arm.comsystem.ruby.IFETCH.hit_latency_hist_seqr::bucket_size            1                      
95411336Sandreas.hansson@arm.comsystem.ruby.IFETCH.hit_latency_hist_seqr::max_bucket            9                      
95511374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::samples    170924615                      
95611336Sandreas.hansson@arm.comsystem.ruby.IFETCH.hit_latency_hist_seqr::mean            1                      
95711336Sandreas.hansson@arm.comsystem.ruby.IFETCH.hit_latency_hist_seqr::gmean            1                      
95811374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr |           0      0.00%      0.00% |   170924615    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
95911374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.hit_latency_hist_seqr::total    170924615                      
96011336Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr::bucket_size          128                      
96111336Sandreas.hansson@arm.comsystem.ruby.IFETCH.miss_latency_hist_seqr::max_bucket         1279                      
96211374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::samples       820529                      
96311374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::mean    19.358062                      
96411374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::gmean    17.674355                      
96511374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::stdev    19.917428                      
96611374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr |      814805     99.30%     99.30% |        4825      0.59%     99.89% |         474      0.06%     99.95% |         262      0.03%     99.98% |         112      0.01%     99.99% |          43      0.01%    100.00% |           0      0.00%    100.00% |           6      0.00%    100.00% |           2      0.00%    100.00% |           0      0.00%    100.00%
96711374Ssteve.reinhardt@amd.comsystem.ruby.IFETCH.miss_latency_hist_seqr::total       820529                      
96811336Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist_seqr::bucket_size          128                      
96911336Sandreas.hansson@arm.comsystem.ruby.RMW_Read.latency_hist_seqr::max_bucket         1279                      
97011374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::samples       500947                      
97111374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::mean     4.014067                      
97211374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::gmean     1.503920                      
97311374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::stdev    10.213309                      
97411374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.latency_hist_seqr   |      500762     99.96%     99.96% |         143      0.03%     99.99% |          15      0.00%     99.99% |          11      0.00%    100.00% |           9      0.00%    100.00% |           7      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
97511374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.latency_hist_seqr::total       500947                      
97611336Sandreas.hansson@arm.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size            1                      
97711336Sandreas.hansson@arm.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket            9                      
97811374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::samples       434941                      
97911336Sandreas.hansson@arm.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::mean            1                      
98011336Sandreas.hansson@arm.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::gmean            1                      
98111374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr |           0      0.00%      0.00% |      434941    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
98211374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.hit_latency_hist_seqr::total       434941                      
98311336Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size          128                      
98411336Sandreas.hansson@arm.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket         1279                      
98511374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::samples        66006                      
98611374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::mean    23.875011                      
98711374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::gmean    22.132571                      
98811374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::stdev    18.367061                      
98911374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr |       65821     99.72%     99.72% |         143      0.22%     99.94% |          15      0.02%     99.96% |          11      0.02%     99.98% |           9      0.01%     99.99% |           7      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
99011374Ssteve.reinhardt@amd.comsystem.ruby.RMW_Read.miss_latency_hist_seqr::total        66006                      
99111336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size           64                      
99211336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket          639                      
99311374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::samples       340316                      
99411374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::mean     3.332085                      
99511374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::gmean     1.406714                      
99611374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::stdev     8.468226                      
99711374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr |      339968     99.90%     99.90% |          90      0.03%     99.92% |         233      0.07%     99.99% |           1      0.00%     99.99% |           3      0.00%     99.99% |           7      0.00%    100.00% |           5      0.00%    100.00% |           1      0.00%    100.00% |           2      0.00%    100.00% |           6      0.00%    100.00%
99811374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.latency_hist_seqr::total       340316                      
99911336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.hit_latency_hist_seqr::bucket_size            1                      
100011336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.hit_latency_hist_seqr::max_bucket            9                      
100111374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.hit_latency_hist_seqr::samples       301850                      
100211336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.hit_latency_hist_seqr::mean            1                      
100311336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.hit_latency_hist_seqr::gmean            1                      
100411374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.hit_latency_hist_seqr |           0      0.00%      0.00% |      301850    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
100511374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.hit_latency_hist_seqr::total       301850                      
100611336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size           64                      
100711336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket          639                      
100811374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples        38466                      
100911374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean    21.632403                      
101011374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean    20.474141                      
101111374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::stdev    16.027002                      
101211374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr |       38118     99.10%     99.10% |          90      0.23%     99.33% |         233      0.61%     99.94% |           1      0.00%     99.94% |           3      0.01%     99.95% |           7      0.02%     99.96% |           5      0.01%     99.98% |           1      0.00%     99.98% |           2      0.01%     99.98% |           6      0.02%    100.00%
101311374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total        38466                      
101411336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size            1                      
101511336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket            9                      
101611374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::samples       340316                      
101711336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::mean            1                      
101811336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::gmean            1                      
101911374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr |           0      0.00%      0.00% |      340316    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
102011374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Write.latency_hist_seqr::total       340316                      
102111336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.hit_latency_hist_seqr::bucket_size            1                      
102211336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.hit_latency_hist_seqr::max_bucket            9                      
102311374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Write.hit_latency_hist_seqr::samples       340316                      
102411336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.hit_latency_hist_seqr::mean            1                      
102511336Sandreas.hansson@arm.comsystem.ruby.Locked_RMW_Write.hit_latency_hist_seqr::gmean            1                      
102611374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Write.hit_latency_hist_seqr |           0      0.00%      0.00% |      340316    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
102711374Ssteve.reinhardt@amd.comsystem.ruby.Locked_RMW_Write.hit_latency_hist_seqr::total       340316                      
102811374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.Fetch         181113      0.00%      0.00%
102911374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.Data          102911      0.00%      0.00%
103011374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.Memory_Data       181583      0.00%      0.00%
103111374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.Memory_Ack       147234      0.00%      0.00%
103211374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.DMA_READ          816      0.00%      0.00%
103310560Sandreas.hansson@arm.comsystem.ruby.Directory_Controller.DMA_WRITE        46736      0.00%      0.00%
103411374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.CleanReplacement        13434      0.00%      0.00%
103511374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.I.Fetch       181113      0.00%      0.00%
103611374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.I.DMA_READ          470      0.00%      0.00%
103711374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.I.DMA_WRITE        44323      0.00%      0.00%
103811374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.ID.Memory_Data          470      0.00%      0.00%
103911374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.ID_W.Memory_Ack        44323      0.00%      0.00%
104011374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.M.Data        100152      0.00%      0.00%
104111374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.M.DMA_READ          346      0.00%      0.00%
104211374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.M.DMA_WRITE         2413      0.00%      0.00%
104311374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.M.CleanReplacement        13434      0.00%      0.00%
104411374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.IM.Memory_Data       181113      0.00%      0.00%
104511374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.MI.Memory_Ack       100152      0.00%      0.00%
104611374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.M_DRD.Data          346      0.00%      0.00%
104711374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.M_DRDI.Memory_Ack          346      0.00%      0.00%
104811374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.M_DWR.Data         2413      0.00%      0.00%
104911374Ssteve.reinhardt@amd.comsystem.ruby.Directory_Controller.M_DWRI.Memory_Ack         2413      0.00%      0.00%
105011374Ssteve.reinhardt@amd.comsystem.ruby.DMA_Controller.ReadRequest   |         816    100.00%    100.00% |           0      0.00%    100.00%
105111374Ssteve.reinhardt@amd.comsystem.ruby.DMA_Controller.ReadRequest::total          816                      
105210560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.WriteRequest  |       46736    100.00%    100.00% |           0      0.00%    100.00%
105310560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.WriteRequest::total        46736                      
105411374Ssteve.reinhardt@amd.comsystem.ruby.DMA_Controller.Data          |         816    100.00%    100.00% |           0      0.00%    100.00%
105511374Ssteve.reinhardt@amd.comsystem.ruby.DMA_Controller.Data::total            816                      
105610560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Ack           |       46736    100.00%    100.00% |           0      0.00%    100.00%
105710560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.Ack::total           46736                      
105811374Ssteve.reinhardt@amd.comsystem.ruby.DMA_Controller.READY.ReadRequest |         816    100.00%    100.00% |           0      0.00%    100.00%
105911374Ssteve.reinhardt@amd.comsystem.ruby.DMA_Controller.READY.ReadRequest::total          816                      
106010560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.WriteRequest |       46736    100.00%    100.00% |           0      0.00%    100.00%
106110560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.READY.WriteRequest::total        46736                      
106211374Ssteve.reinhardt@amd.comsystem.ruby.DMA_Controller.BUSY_RD.Data  |         816    100.00%    100.00% |           0      0.00%    100.00%
106311374Ssteve.reinhardt@amd.comsystem.ruby.DMA_Controller.BUSY_RD.Data::total          816                      
106410560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_WR.Ack   |       46736    100.00%    100.00% |           0      0.00%    100.00%
106510560Sandreas.hansson@arm.comsystem.ruby.DMA_Controller.BUSY_WR.Ack::total        46736                      
106611374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Load      |    10174731     65.92%     65.92% |     5260188     34.08%    100.00%
106711374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Load::total     15434919                      
106811374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Ifetch    |   115118489     67.03%     67.03% |    56626661     32.97%    100.00%
106911374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Ifetch::total    171745150                      
107011374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Store     |     7445539     68.97%     68.97% |     3350451     31.03%    100.00%
107111374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Store::total     10795990                      
107211374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Inv       |       18648     52.30%     52.30% |       17011     47.70%    100.00%
107311374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Inv::total        35659                      
107411374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.L1_Replacement |     1725795     65.05%     65.05% |      927205     34.95%    100.00%
107511374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.L1_Replacement::total      2653000                      
107611374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Fwd_GETX  |       12362     50.94%     50.94% |       11904     49.06%    100.00%
107711374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Fwd_GETX::total        24266                      
107811374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Fwd_GETS  |       14780     53.13%     53.13% |       13039     46.87%    100.00%
107911374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Fwd_GETS::total        27819                      
108010013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
108110013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.Fwd_GET_INSTR::total            4                      
108211374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Data      |         521     31.46%     31.46% |        1135     68.54%    100.00%
108311374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Data::total         1656                      
108411374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Data_Exclusive |      836671     62.58%     62.58% |      500206     37.42%    100.00%
108511374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Data_Exclusive::total      1336877                      
108611374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.DataS_fromL1 |       13039     46.86%     46.86% |       14784     53.14%    100.00%
108711374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.DataS_fromL1::total        27823                      
108811374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Data_all_Acks |      892759     67.52%     67.52% |      429359     32.48%    100.00%
108911374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Data_all_Acks::total      1322118                      
109011374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Ack       |       12812     52.14%     52.14% |       11761     47.86%    100.00%
109111374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Ack::total        24573                      
109211374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Ack_all   |       13333     50.83%     50.83% |       12896     49.17%    100.00%
109311374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.Ack_all::total        26229                      
109411374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.WB_Ack    |     1127309     64.72%     64.72% |      614455     35.28%    100.00%
109511374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.WB_Ack::total      1741764                      
109611374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.NP.Load   |      877314     62.10%     62.10% |      535446     37.90%    100.00%
109711374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.NP.Load::total      1412760                      
109811374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.NP.Ifetch |      549594     67.01%     67.01% |      270630     32.99%    100.00%
109911374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.NP.Ifetch::total       820224                      
110011374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.NP.Store  |      299910     71.06%     71.06% |      122153     28.94%    100.00%
110111374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.NP.Store::total       422063                      
110211374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.NP.Inv    |        5790     62.89%     62.89% |        3417     37.11%    100.00%
110311374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.NP.Inv::total         9207                      
110411374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.I.Load    |       10201     47.75%     47.75% |       11161     52.25%    100.00%
110511374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.I.Load::total        21362                      
110611374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.I.Ifetch  |         164     53.77%     53.77% |         141     46.23%    100.00%
110711374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.I.Ifetch::total          305                      
110811374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.I.Store   |        5805     49.38%     49.38% |        5950     50.62%    100.00%
110911374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.I.Store::total        11755                      
111011374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.I.L1_Replacement |        9048     52.68%     52.68% |        8128     47.32%    100.00%
111111374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.I.L1_Replacement::total        17176                      
111211374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.S.Load    |      854922     63.25%     63.25% |      496689     36.75%    100.00%
111311374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.S.Load::total      1351611                      
111411374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.S.Ifetch  |   114568727     67.03%     67.03% |    56355888     32.97%    100.00%
111511374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.S.Ifetch::total    170924615                      
111611374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.S.Store   |       12814     52.14%     52.14% |       11764     47.86%    100.00%
111711374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.S.Store::total        24578                      
111811374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.S.Inv     |       12592     48.75%     48.75% |       13236     51.25%    100.00%
111911374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.S.Inv::total        25828                      
112011374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.S.L1_Replacement |      589438     65.93%     65.93% |      304622     34.07%    100.00%
112111374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.S.L1_Replacement::total       894060                      
112211374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.Load    |     2373511     63.51%     63.51% |     1363700     36.49%    100.00%
112311374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.Load::total      3737211                      
112411374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.Store   |      119848     72.96%     72.96% |       44409     27.04%    100.00%
112511374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.Store::total       164257                      
112611374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.Inv     |          68     57.63%     57.63% |          50     42.37%    100.00%
112711374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.Inv::total          118                      
112811374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.L1_Replacement |      715361     61.16%     61.16% |      454250     38.84%    100.00%
112911374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.L1_Replacement::total      1169611                      
113011374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.Fwd_GETX |         230     60.05%     60.05% |         153     39.95%    100.00%
113111374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.Fwd_GETX::total          383                      
113211374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.Fwd_GETS |         951     42.97%     42.97% |        1262     57.03%    100.00%
113311374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.E.Fwd_GETS::total         2213                      
113411374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Load    |     6058783     67.98%     67.98% |     2853192     32.02%    100.00%
113511374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Load::total      8911975                      
113611374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Store   |     7007162     68.88%     68.88% |     3166175     31.12%    100.00%
113711374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Store::total     10173337                      
113811374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Inv     |         195     39.00%     39.00% |         305     61.00%    100.00%
113911374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Inv::total          500                      
114011374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.L1_Replacement |      411948     72.00%     72.00% |      160205     28.00%    100.00%
114111374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.L1_Replacement::total       572153                      
114211374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Fwd_GETX |       12132     50.80%     50.80% |       11750     49.20%    100.00%
114311374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Fwd_GETX::total        23882                      
114411374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Fwd_GETS |       13829     54.01%     54.01% |       11777     45.99%    100.00%
114511374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M.Fwd_GETS::total        25606                      
114610013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR |           4    100.00%    100.00% |           0      0.00%    100.00%
114710013Snilay@cs.wisc.edusystem.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total            4                      
114811374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS.Inv    |           1    100.00%    100.00% |           0      0.00%    100.00%
114911374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS.Inv::total            1                      
115011374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS.Data_Exclusive |      836671     62.58%     62.58% |      500206     37.42%    100.00%
115111374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS.Data_Exclusive::total      1336877                      
115211374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS.DataS_fromL1 |       13038     46.86%     46.86% |       14784     53.14%    100.00%
115311374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS.DataS_fromL1::total        27822                      
115411374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS.Data_all_Acks |      587563     66.02%     66.02% |      302388     33.98%    100.00%
115511374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS.Data_all_Acks::total       889951                      
115611374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IM.Data   |         521     31.46%     31.46% |        1135     68.54%    100.00%
115711374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IM.Data::total         1656                      
115811374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IM.Data_all_Acks |      305196     70.62%     70.62% |      126971     29.38%    100.00%
115911374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IM.Data_all_Acks::total       432167                      
116011374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.SM.Inv    |           2     40.00%     40.00% |           3     60.00%    100.00%
116111374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.SM.Inv::total            5                      
116211374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.SM.Ack    |       12812     52.14%     52.14% |       11761     47.86%    100.00%
116311374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.SM.Ack::total        24573                      
116411374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.SM.Ack_all |       13333     50.83%     50.83% |       12896     49.17%    100.00%
116511374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.SM.Ack_all::total        26229                      
116611374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS_I.DataS_fromL1 |           1    100.00%    100.00% |           0      0.00%    100.00%
116711374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.IS_I.DataS_fromL1::total            1                      
116811374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M_I.Ifetch |           4     66.67%     66.67% |           2     33.33%    100.00%
116911374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M_I.Ifetch::total            6                      
117011374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M_I.Fwd_GETX |           0      0.00%      0.00% |           1    100.00%    100.00%
117111374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M_I.Fwd_GETX::total            1                      
117211374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M_I.WB_Ack |     1127309     64.72%     64.72% |      614454     35.28%    100.00%
117311374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.M_I.WB_Ack::total      1741763                      
117411374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack |           0      0.00%      0.00% |           1    100.00%    100.00%
117511374Ssteve.reinhardt@amd.comsystem.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total            1                      
117611374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.L1_GET_INSTR       820529      0.00%      0.00%
117711374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.L1_GETS        1434524      0.00%      0.00%
117811374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.L1_GETX         433826      0.00%      0.00%
117911374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.L1_UPGRADE        24578      0.00%      0.00%
118011374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.L1_PUTX        1741764      0.00%      0.00%
118111374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.L1_PUTX_old            1      0.00%      0.00%
118211374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.L2_Replacement       100099      0.00%      0.00%
118311374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.L2_Replacement_clean        13487      0.00%      0.00%
118411374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.Mem_Data        181113      0.00%      0.00%
118511374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.Mem_Ack         116345      0.00%      0.00%
118611374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.WB_Data          26110      0.00%      0.00%
118711374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.WB_Data_clean         2213      0.00%      0.00%
118811374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.Ack               1845      0.00%      0.00%
118911374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.Ack_all           7085      0.00%      0.00%
119011374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.Unblock          27823      0.00%      0.00%
119111374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.Exclusive_Unblock      1795273      0.00%      0.00%
119211374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MEM_Inv           5518      0.00%      0.00%
119311374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.NP.L1_GET_INSTR        15422      0.00%      0.00%
119411374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.NP.L1_GETS        32337      0.00%      0.00%
119511374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.NP.L1_GETX       133354      0.00%      0.00%
119611374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.SS.L1_GET_INSTR       805077      0.00%      0.00%
119711374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.SS.L1_GETS        69426      0.00%      0.00%
119811374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.SS.L1_GETX         1949      0.00%      0.00%
119911374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.SS.L1_UPGRADE        24573      0.00%      0.00%
120011374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.SS.L2_Replacement          290      0.00%      0.00%
120111374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.SS.L2_Replacement_clean         6672      0.00%      0.00%
120211201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS.MEM_Inv            5      0.00%      0.00%
120311201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.M.L1_GET_INSTR           26      0.00%      0.00%
120411374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.M.L1_GETS      1304540      0.00%      0.00%
120511374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.M.L1_GETX       274254      0.00%      0.00%
120611374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.M.L2_Replacement        99553      0.00%      0.00%
120711374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.M.L2_Replacement_clean         6682      0.00%      0.00%
120811374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.M.MEM_Inv         2525      0.00%      0.00%
120910013Snilay@cs.wisc.edusystem.ruby.L2Cache_Controller.MT.L1_GET_INSTR            4      0.00%      0.00%
121011374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT.L1_GETS        27819      0.00%      0.00%
121111374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT.L1_GETX        24266      0.00%      0.00%
121211374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT.L1_PUTX      1741763      0.00%      0.00%
121311374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT.L1_PUTX_old            1      0.00%      0.00%
121411374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT.L2_Replacement          256      0.00%      0.00%
121511374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT.L2_Replacement_clean          133      0.00%      0.00%
121611201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT.MEM_Inv          229      0.00%      0.00%
121711374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.M_I.Mem_Ack       116345      0.00%      0.00%
121811374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.M_I.MEM_Inv         2525      0.00%      0.00%
121911374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT_I.WB_Data          447      0.00%      0.00%
122011201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_I.Ack_all           38      0.00%      0.00%
122111201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_I.MEM_Inv          229      0.00%      0.00%
122211374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MCT_I.WB_Data           53      0.00%      0.00%
122311374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MCT_I.Ack_all           80      0.00%      0.00%
122411374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.I_I.Ack           1551      0.00%      0.00%
122511374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.I_I.Ack_all         6672      0.00%      0.00%
122611374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.S_I.Ack            294      0.00%      0.00%
122711374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.S_I.Ack_all          295      0.00%      0.00%
122811201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.S_I.MEM_Inv            5      0.00%      0.00%
122911374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.ISS.Mem_Data        32337      0.00%      0.00%
123011374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.IS.Mem_Data        15422      0.00%      0.00%
123111374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.IM.Mem_Data       133354      0.00%      0.00%
123211374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.SS_MB.L1_GETS          237      0.00%      0.00%
123311201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.SS_MB.L1_GETX            1      0.00%      0.00%
123411374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE            5      0.00%      0.00%
123511374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock        26522      0.00%      0.00%
123611374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT_MB.L1_GETS          165      0.00%      0.00%
123711201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_MB.L1_GETX            2      0.00%      0.00%
123811374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT_MB.L1_PUTX            1      0.00%      0.00%
123911374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock      1768751      0.00%      0.00%
124011374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT_IIB.WB_Data        25603      0.00%      0.00%
124111374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean         2212      0.00%      0.00%
124211374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT_IIB.Unblock            8      0.00%      0.00%
124311374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT_IB.WB_Data            7      0.00%      0.00%
124411201Sandreas.hansson@arm.comsystem.ruby.L2Cache_Controller.MT_IB.WB_Data_clean            1      0.00%      0.00%
124511374Ssteve.reinhardt@amd.comsystem.ruby.L2Cache_Controller.MT_SB.Unblock        27815      0.00%      0.00%
12468968SN/A
12478968SN/A---------- End Simulation Statistics   ----------
1248