stats.txt revision 9702:094d0280e481
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.140938 # Number of seconds simulated 4sim_ticks 5140937585000 # Number of ticks simulated 5final_tick 5140937585000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 121697 # Simulator instruction rate (inst/s) 8host_op_rate 240559 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1534230705 # Simulator tick rate (ticks/s) 10host_mem_usage 773616 # Number of bytes of host memory used 11host_seconds 3350.82 # Real time elapsed on the host 12sim_insts 407786881 # Number of instructions simulated 13sim_ops 806071515 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2479872 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 1026240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10765120 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14275328 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1026240 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1026240 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9536256 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9536256 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38748 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 16035 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 168205 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 223052 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 149004 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 149004 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 482377 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 722 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 199621 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2093999 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2776795 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 199621 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 199621 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1854964 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1854964 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1854964 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 482377 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 722 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 199621 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2093999 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4631759 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 223052 # Total number of read requests seen 50system.physmem.writeReqs 149004 # Total number of write requests seen 51system.physmem.cpureqs 373790 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14275328 # Total number of bytes read from memory 53system.physmem.bytesWritten 9536256 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14275328 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9536256 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q 57system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed 58system.physmem.perBankRdReqs::0 13636 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 12914 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 13124 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 16345 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13470 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 13111 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 13382 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 16266 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13519 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 13235 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 13394 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 15885 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 13088 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 12601 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 13202 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 15809 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 8837 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 8387 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 8583 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 11810 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 8818 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 8522 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8723 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 11661 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 8790 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 8601 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 8761 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 11230 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 8431 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 8093 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 8583 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 11174 # Track writes on a per bank basis 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 91system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5140937531500 # Total gap between requests 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes 99system.physmem.readPktSize::6 223052 # Categorize read packet sizes 100system.physmem.writePktSize::0 0 # Categorize write packet sizes 101system.physmem.writePktSize::1 0 # Categorize write packet sizes 102system.physmem.writePktSize::2 0 # Categorize write packet sizes 103system.physmem.writePktSize::3 0 # Categorize write packet sizes 104system.physmem.writePktSize::4 0 # Categorize write packet sizes 105system.physmem.writePktSize::5 0 # Categorize write packet sizes 106system.physmem.writePktSize::6 149004 # Categorize write packet sizes 107system.physmem.rdQLenPdf::0 172997 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::1 18175 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 7573 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 3487 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 3011 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::5 2422 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::6 1913 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1861 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1763 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::9 1672 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::10 1114 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::11 1019 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::12 962 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::13 902 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::14 823 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::15 817 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::16 907 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::17 865 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::18 412 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::19 253 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::20 31 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 139system.physmem.wrQLenPdf::0 5326 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::1 5675 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::2 6279 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::3 6374 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::4 6421 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::5 6454 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::6 6466 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::7 6470 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 6471 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::9 6479 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 6478 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 6478 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 6478 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 6478 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 6478 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::15 6478 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 6478 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 6478 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 6478 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 6478 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6478 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 6478 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 6478 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::23 1153 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 804 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 200 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 105 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 58 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 25 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see 171system.physmem.totQLat 4794975750 # Total cycles spent in queuing delays 172system.physmem.totMemAccLat 9301923250 # Sum of mem lat for all requests 173system.physmem.totBusLat 1114905000 # Total cycles spent in databus access 174system.physmem.totBankLat 3392042500 # Total cycles spent in bank access 175system.physmem.avgQLat 21503.97 # Average queueing delay per request 176system.physmem.avgBankLat 15212.25 # Average bank access latency per request 177system.physmem.avgBusLat 5000.00 # Average bus latency per request 178system.physmem.avgMemAccLat 41716.21 # Average memory access latency 179system.physmem.avgRdBW 2.78 # Average achieved read bandwidth in MB/s 180system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s 181system.physmem.avgConsumedRdBW 2.78 # Average consumed read bandwidth in MB/s 182system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s 183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 184system.physmem.busUtil 0.04 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.00 # Average read queue length over time 186system.physmem.avgWrQLen 15.58 # Average write queue length over time 187system.physmem.readRowHits 191257 # Number of row buffer hits during reads 188system.physmem.writeRowHits 105612 # Number of row buffer hits during writes 189system.physmem.readRowHitRate 85.77 # Row buffer hit rate for reads 190system.physmem.writeRowHitRate 70.88 # Row buffer hit rate for writes 191system.physmem.avgGap 13817644.47 # Average gap between requests 192system.iocache.replacements 47576 # number of replacements 193system.iocache.tagsinuse 0.128763 # Cycle average of tags in use 194system.iocache.total_refs 0 # Total number of references to valid blocks. 195system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. 196system.iocache.avg_refs 0 # Average number of references to valid blocks. 197system.iocache.warmup_cycle 4991974997000 # Cycle when the warmup percentage was hit. 198system.iocache.occ_blocks::pc.south_bridge.ide 0.128763 # Average occupied blocks per requestor 199system.iocache.occ_percent::pc.south_bridge.ide 0.008048 # Average percentage of cache occupancy 200system.iocache.occ_percent::total 0.008048 # Average percentage of cache occupancy 201system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses 202system.iocache.ReadReq_misses::total 911 # number of ReadReq misses 203system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 204system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 205system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses 206system.iocache.demand_misses::total 47631 # number of demand (read+write) misses 207system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses 208system.iocache.overall_misses::total 47631 # number of overall misses 209system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147497397 # number of ReadReq miss cycles 210system.iocache.ReadReq_miss_latency::total 147497397 # number of ReadReq miss cycles 211system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10072244306 # number of WriteReq miss cycles 212system.iocache.WriteReq_miss_latency::total 10072244306 # number of WriteReq miss cycles 213system.iocache.demand_miss_latency::pc.south_bridge.ide 10219741703 # number of demand (read+write) miss cycles 214system.iocache.demand_miss_latency::total 10219741703 # number of demand (read+write) miss cycles 215system.iocache.overall_miss_latency::pc.south_bridge.ide 10219741703 # number of overall miss cycles 216system.iocache.overall_miss_latency::total 10219741703 # number of overall miss cycles 217system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) 218system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) 219system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 220system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 221system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses 222system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses 223system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses 224system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses 225system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 226system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 227system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 228system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 229system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 230system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 231system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 232system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 233system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 161907.131723 # average ReadReq miss latency 234system.iocache.ReadReq_avg_miss_latency::total 161907.131723 # average ReadReq miss latency 235system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215587.420933 # average WriteReq miss latency 236system.iocache.WriteReq_avg_miss_latency::total 215587.420933 # average WriteReq miss latency 237system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency 238system.iocache.demand_avg_miss_latency::total 214560.721022 # average overall miss latency 239system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency 240system.iocache.overall_avg_miss_latency::total 214560.721022 # average overall miss latency 241system.iocache.blocked_cycles::no_mshrs 139153 # number of cycles access was blocked 242system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 243system.iocache.blocked::no_mshrs 12645 # number of cycles access was blocked 244system.iocache.blocked::no_targets 0 # number of cycles access was blocked 245system.iocache.avg_blocked_cycles::no_mshrs 11.004587 # average number of cycles each access was blocked 246system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247system.iocache.fast_writes 0 # number of fast writes performed 248system.iocache.cache_copies 0 # number of cache copies performed 249system.iocache.writebacks::writebacks 46667 # number of writebacks 250system.iocache.writebacks::total 46667 # number of writebacks 251system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 252system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses 253system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 254system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 255system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses 256system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses 257system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses 258system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses 259system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100104427 # number of ReadReq MSHR miss cycles 260system.iocache.ReadReq_mshr_miss_latency::total 100104427 # number of ReadReq MSHR miss cycles 261system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7641446543 # number of WriteReq MSHR miss cycles 262system.iocache.WriteReq_mshr_miss_latency::total 7641446543 # number of WriteReq MSHR miss cycles 263system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of demand (read+write) MSHR miss cycles 264system.iocache.demand_mshr_miss_latency::total 7741550970 # number of demand (read+write) MSHR miss cycles 265system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of overall MSHR miss cycles 266system.iocache.overall_mshr_miss_latency::total 7741550970 # number of overall MSHR miss cycles 267system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 268system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 269system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 270system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 271system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 272system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 273system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 274system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 275system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 109884.113063 # average ReadReq mshr miss latency 276system.iocache.ReadReq_avg_mshr_miss_latency::total 109884.113063 # average ReadReq mshr miss latency 277system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163558.359225 # average WriteReq mshr miss latency 278system.iocache.WriteReq_avg_mshr_miss_latency::total 163558.359225 # average WriteReq mshr miss latency 279system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency 280system.iocache.demand_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency 281system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency 282system.iocache.overall_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency 283system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 284system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 285system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 286system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 287system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 288system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 289system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 290system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 291system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 292system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 293system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 294system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 295system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 296system.cpu.branchPred.lookups 85620726 # Number of BP lookups 297system.cpu.branchPred.condPredicted 85620726 # Number of conditional branches predicted 298system.cpu.branchPred.condIncorrect 882198 # Number of conditional branches incorrect 299system.cpu.branchPred.BTBLookups 79268619 # Number of BTB lookups 300system.cpu.branchPred.BTBHits 77534559 # Number of BTB hits 301system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 302system.cpu.branchPred.BTBHitPct 97.812426 # BTB Hit Percentage 303system.cpu.branchPred.usedRAS 1442315 # Number of times the RAS was used to get a target. 304system.cpu.branchPred.RASInCorrect 180251 # Number of incorrect RAS predictions. 305system.cpu.numCycles 447791761 # number of cpu cycles simulated 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 308system.cpu.fetch.icacheStallCycles 25559948 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 422856490 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 85620726 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 78976874 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 162677741 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 4000997 # Number of cycles fetch has spent squashing 314system.cpu.fetch.TlbCycles 98298 # Number of cycles fetch has spent waiting for tlb 315system.cpu.fetch.BlockedCycles 65919320 # Number of cycles fetch has spent blocked 316system.cpu.fetch.MiscStallCycles 43594 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 317system.cpu.fetch.PendingTrapStallCycles 86507 # Number of stall cycles due to pending traps 318system.cpu.fetch.IcacheWaitRetryStallCycles 459 # Number of stall cycles due to full MSHR 319system.cpu.fetch.CacheLines 8492083 # Number of cache lines fetched 320system.cpu.fetch.IcacheSquashes 383635 # Number of outstanding Icache misses that were squashed 321system.cpu.fetch.ItlbSquashes 2345 # Number of outstanding ITLB misses that were squashed 322system.cpu.fetch.rateDist::samples 257461374 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::mean 3.243647 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::stdev 3.415529 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::0 95198026 36.98% 36.98% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::1 1534816 0.60% 37.57% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::2 71825104 27.90% 65.47% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::3 895357 0.35% 65.82% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::4 1570607 0.61% 66.43% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::5 2391332 0.93% 67.36% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::6 1020158 0.40% 67.75% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::7 1325162 0.51% 68.27% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::8 81700812 31.73% 100.00% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::total 257461374 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.branchRate 0.191207 # Number of branch fetches per cycle 340system.cpu.fetch.rate 0.944315 # Number of inst fetches per cycle 341system.cpu.decode.IdleCycles 29461192 # Number of cycles decode is idle 342system.cpu.decode.BlockedCycles 63064302 # Number of cycles decode is blocked 343system.cpu.decode.RunCycles 158550724 # Number of cycles decode is running 344system.cpu.decode.UnblockCycles 3309649 # Number of cycles decode is unblocking 345system.cpu.decode.SquashCycles 3075507 # Number of cycles decode is squashing 346system.cpu.decode.DecodedInsts 832761340 # Number of instructions handled by decode 347system.cpu.decode.SquashedInsts 863 # Number of squashed instructions handled by decode 348system.cpu.rename.SquashCycles 3075507 # Number of cycles rename is squashing 349system.cpu.rename.IdleCycles 32153278 # Number of cycles rename is idle 350system.cpu.rename.BlockCycles 38465118 # Number of cycles rename is blocking 351system.cpu.rename.serializeStallCycles 12079112 # count of cycles rename stalled for serializing inst 352system.cpu.rename.RunCycles 158824437 # Number of cycles rename is running 353system.cpu.rename.UnblockCycles 12863922 # Number of cycles rename is unblocking 354system.cpu.rename.RenamedInsts 829829025 # Number of instructions processed by rename 355system.cpu.rename.ROBFullEvents 19879 # Number of times rename has blocked due to ROB full 356system.cpu.rename.IQFullEvents 6055166 # Number of times rename has blocked due to IQ full 357system.cpu.rename.LSQFullEvents 4924546 # Number of times rename has blocked due to LSQ full 358system.cpu.rename.FullRegisterEvents 11525 # Number of times there has been no free registers 359system.cpu.rename.RenamedOperands 991492877 # Number of destination operands rename has renamed 360system.cpu.rename.RenameLookups 1800847756 # Number of register rename lookups that rename has made 361system.cpu.rename.int_rename_lookups 1800847292 # Number of integer rename lookups 362system.cpu.rename.fp_rename_lookups 464 # Number of floating rename lookups 363system.cpu.rename.CommittedMaps 963999366 # Number of HB maps that are committed 364system.cpu.rename.UndoneMaps 27493506 # Number of HB maps that are undone due to squashing 365system.cpu.rename.serializingInsts 456551 # count of serializing insts renamed 366system.cpu.rename.tempSerializingInsts 462682 # count of temporary serializing insts renamed 367system.cpu.rename.skidInsts 29304477 # count of insts added to the skid buffer 368system.cpu.memDep0.insertedLoads 16752339 # Number of loads inserted to the mem dependence unit. 369system.cpu.memDep0.insertedStores 9837983 # Number of stores inserted to the mem dependence unit. 370system.cpu.memDep0.conflictingLoads 1099709 # Number of conflicting loads. 371system.cpu.memDep0.conflictingStores 928773 # Number of conflicting stores. 372system.cpu.iq.iqInstsAdded 825036488 # Number of instructions added to the IQ (excludes non-spec) 373system.cpu.iq.iqNonSpecInstsAdded 1186686 # Number of non-speculative instructions added to the IQ 374system.cpu.iq.iqInstsIssued 821069910 # Number of instructions issued 375system.cpu.iq.iqSquashedInstsIssued 146070 # Number of squashed instructions issued 376system.cpu.iq.iqSquashedInstsExamined 19309743 # Number of squashed instructions iterated over during squash; mainly for profiling 377system.cpu.iq.iqSquashedOperandsExamined 29357166 # Number of squashed operands that are examined and possibly removed from graph 378system.cpu.iq.iqSquashedNonSpecRemoved 131932 # Number of squashed non-spec instructions that were removed 379system.cpu.iq.issued_per_cycle::samples 257461374 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::mean 3.189099 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::stdev 2.383585 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::0 71259249 27.68% 27.68% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::1 15575755 6.05% 33.73% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::2 10479111 4.07% 37.80% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::3 7383615 2.87% 40.67% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::4 75752504 29.42% 70.09% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::5 3772068 1.47% 71.55% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::6 72307575 28.08% 99.64% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::7 782694 0.30% 99.94% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::8 148803 0.06% 100.00% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::total 257461374 # Number of insts issued each cycle 396system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 397system.cpu.iq.fu_full::IntAlu 356313 33.63% 33.63% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntMult 241 0.02% 33.66% # attempts to use FU when none available 399system.cpu.iq.fu_full::IntDiv 2452 0.23% 33.89% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.89% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemRead 547502 51.68% 85.57% # attempts to use FU when none available 427system.cpu.iq.fu_full::MemWrite 152922 14.43% 100.00% # attempts to use FU when none available 428system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 429system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 430system.cpu.iq.FU_type_0::No_OpClass 308526 0.04% 0.04% # Type of FU issued 431system.cpu.iq.FU_type_0::IntAlu 793557907 96.65% 96.69% # Type of FU issued 432system.cpu.iq.FU_type_0::IntMult 150412 0.02% 96.71% # Type of FU issued 433system.cpu.iq.FU_type_0::IntDiv 124298 0.02% 96.72% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.72% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.72% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.72% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.72% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.72% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.72% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.72% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.72% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.72% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.72% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.72% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.72% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.72% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.72% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.72% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.72% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.72% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.72% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.72% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.72% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued 460system.cpu.iq.FU_type_0::MemRead 17694567 2.16% 98.88% # Type of FU issued 461system.cpu.iq.FU_type_0::MemWrite 9234200 1.12% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 464system.cpu.iq.FU_type_0::total 821069910 # Type of FU issued 465system.cpu.iq.rate 1.833598 # Inst issue rate 466system.cpu.iq.fu_busy_cnt 1059430 # FU busy when requested 467system.cpu.iq.fu_busy_rate 0.001290 # FU busy rate (busy events/executed inst) 468system.cpu.iq.int_inst_queue_reads 1900915279 # Number of integer instruction queue reads 469system.cpu.iq.int_inst_queue_writes 845543458 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 817157785 # Number of integer instruction queue wakeup accesses 471system.cpu.iq.fp_inst_queue_reads 194 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses 474system.cpu.iq.int_alu_accesses 821820724 # Number of integer alu accesses 475system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses 476system.cpu.iew.lsq.thread0.forwLoads 1686147 # Number of loads that had data forwarded from stores 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 478system.cpu.iew.lsq.thread0.squashedLoads 2748440 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 17101 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 11930 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 1411969 # Number of stores squashed 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 484system.cpu.iew.lsq.thread0.rescheduledLoads 1931504 # Number of loads that were rescheduled 485system.cpu.iew.lsq.thread0.cacheBlocked 11624 # Number of times an access to memory failed due to the cache being blocked 486system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 487system.cpu.iew.iewSquashCycles 3075507 # Number of cycles IEW is squashing 488system.cpu.iew.iewBlockCycles 26873503 # Number of cycles IEW is blocking 489system.cpu.iew.iewUnblockCycles 2150322 # Number of cycles IEW is unblocking 490system.cpu.iew.iewDispatchedInsts 826223174 # Number of instructions dispatched to IQ 491system.cpu.iew.iewDispSquashedInsts 241070 # Number of squashed instructions skipped by dispatch 492system.cpu.iew.iewDispLoadInsts 16752339 # Number of dispatched load instructions 493system.cpu.iew.iewDispStoreInsts 9837983 # Number of dispatched store instructions 494system.cpu.iew.iewDispNonSpecInsts 692103 # Number of dispatched non-speculative instructions 495system.cpu.iew.iewIQFullEvents 1621529 # Number of times the IQ has become full, causing a stall 496system.cpu.iew.iewLSQFullEvents 12267 # Number of times the LSQ has become full, causing a stall 497system.cpu.iew.memOrderViolationEvents 11930 # Number of memory order violations 498system.cpu.iew.predictedTakenIncorrect 498132 # Number of branches that were predicted taken incorrectly 499system.cpu.iew.predictedNotTakenIncorrect 506603 # Number of branches that were predicted not taken incorrectly 500system.cpu.iew.branchMispredicts 1004735 # Number of branch mispredicts detected at execute 501system.cpu.iew.iewExecutedInsts 819660888 # Number of executed instructions 502system.cpu.iew.iewExecLoadInsts 17391685 # Number of load instructions executed 503system.cpu.iew.iewExecSquashedInsts 1409021 # Number of squashed instructions skipped in execute 504system.cpu.iew.exec_swp 0 # number of swp insts executed 505system.cpu.iew.exec_nop 0 # number of nop insts executed 506system.cpu.iew.exec_refs 26440023 # number of memory reference insts executed 507system.cpu.iew.exec_branches 83107253 # Number of branches executed 508system.cpu.iew.exec_stores 9048338 # Number of stores executed 509system.cpu.iew.exec_rate 1.830451 # Inst execution rate 510system.cpu.iew.wb_sent 819258374 # cumulative count of insts sent to commit 511system.cpu.iew.wb_count 817157837 # cumulative count of insts written-back 512system.cpu.iew.wb_producers 638799704 # num instructions producing a value 513system.cpu.iew.wb_consumers 1044337102 # num instructions consuming a value 514system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 515system.cpu.iew.wb_rate 1.824861 # insts written-back per cycle 516system.cpu.iew.wb_fanout 0.611680 # average fanout of values written-back 517system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 518system.cpu.commit.commitSquashedInsts 20042352 # The number of squashed insts skipped by commit 519system.cpu.commit.commitNonSpecStalls 1054753 # The number of times commit has been forced to stall to communicate backwards 520system.cpu.commit.branchMispredicts 891546 # The number of times a branch was mispredicted 521system.cpu.commit.committed_per_cycle::samples 254385866 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::mean 3.168696 # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::stdev 2.858566 # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::0 82972146 32.62% 32.62% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::1 11724447 4.61% 37.23% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::2 3813249 1.50% 38.72% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::3 74747378 29.38% 68.11% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::4 2384925 0.94% 69.05% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::5 1476326 0.58% 69.63% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::6 865615 0.34% 69.97% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::7 70850824 27.85% 97.82% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::8 5550956 2.18% 100.00% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::total 254385866 # Number of insts commited each cycle 538system.cpu.commit.committedInsts 407786881 # Number of instructions committed 539system.cpu.commit.committedOps 806071515 # Number of ops (including micro ops) committed 540system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 541system.cpu.commit.refs 22429911 # Number of memory references committed 542system.cpu.commit.loads 14003897 # Number of loads committed 543system.cpu.commit.membars 474463 # Number of memory barriers committed 544system.cpu.commit.branches 82163817 # Number of branches committed 545system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 546system.cpu.commit.int_insts 735061477 # Number of committed integer instructions. 547system.cpu.commit.function_calls 1156045 # Number of function calls committed. 548system.cpu.commit.bw_lim_events 5550956 # number cycles where commit BW limit reached 549system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 550system.cpu.rob.rob_reads 1074870508 # The number of ROB reads 551system.cpu.rob.rob_writes 1655318425 # The number of ROB writes 552system.cpu.timesIdled 1256763 # Number of times that the entire CPU went into an idle state and unscheduled itself 553system.cpu.idleCycles 190330387 # Total number of cycles that the CPU has spent unscheduled due to idling 554system.cpu.quiesceCycles 9834088814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 555system.cpu.committedInsts 407786881 # Number of Instructions Simulated 556system.cpu.committedOps 806071515 # Number of Ops (including micro ops) Simulated 557system.cpu.committedInsts_total 407786881 # Number of Instructions Simulated 558system.cpu.cpi 1.098102 # CPI: Cycles Per Instruction 559system.cpu.cpi_total 1.098102 # CPI: Total CPI of All Threads 560system.cpu.ipc 0.910662 # IPC: Instructions Per Cycle 561system.cpu.ipc_total 0.910662 # IPC: Total IPC of All Threads 562system.cpu.int_regfile_reads 1504614065 # number of integer regfile reads 563system.cpu.int_regfile_writes 975429838 # number of integer regfile writes 564system.cpu.fp_regfile_reads 52 # number of floating regfile reads 565system.cpu.misc_regfile_reads 264130300 # number of misc regfile reads 566system.cpu.misc_regfile_writes 403010 # number of misc regfile writes 567system.cpu.icache.replacements 955437 # number of replacements 568system.cpu.icache.tagsinuse 509.903328 # Cycle average of tags in use 569system.cpu.icache.total_refs 7482159 # Total number of references to valid blocks. 570system.cpu.icache.sampled_refs 955949 # Sample count of references to valid blocks. 571system.cpu.icache.avg_refs 7.826944 # Average number of references to valid blocks. 572system.cpu.icache.warmup_cycle 146514700000 # Cycle when the warmup percentage was hit. 573system.cpu.icache.occ_blocks::cpu.inst 509.903328 # Average occupied blocks per requestor 574system.cpu.icache.occ_percent::cpu.inst 0.995905 # Average percentage of cache occupancy 575system.cpu.icache.occ_percent::total 0.995905 # Average percentage of cache occupancy 576system.cpu.icache.ReadReq_hits::cpu.inst 7482159 # number of ReadReq hits 577system.cpu.icache.ReadReq_hits::total 7482159 # number of ReadReq hits 578system.cpu.icache.demand_hits::cpu.inst 7482159 # number of demand (read+write) hits 579system.cpu.icache.demand_hits::total 7482159 # number of demand (read+write) hits 580system.cpu.icache.overall_hits::cpu.inst 7482159 # number of overall hits 581system.cpu.icache.overall_hits::total 7482159 # number of overall hits 582system.cpu.icache.ReadReq_misses::cpu.inst 1009922 # number of ReadReq misses 583system.cpu.icache.ReadReq_misses::total 1009922 # number of ReadReq misses 584system.cpu.icache.demand_misses::cpu.inst 1009922 # number of demand (read+write) misses 585system.cpu.icache.demand_misses::total 1009922 # number of demand (read+write) misses 586system.cpu.icache.overall_misses::cpu.inst 1009922 # number of overall misses 587system.cpu.icache.overall_misses::total 1009922 # number of overall misses 588system.cpu.icache.ReadReq_miss_latency::cpu.inst 13938284992 # number of ReadReq miss cycles 589system.cpu.icache.ReadReq_miss_latency::total 13938284992 # number of ReadReq miss cycles 590system.cpu.icache.demand_miss_latency::cpu.inst 13938284992 # number of demand (read+write) miss cycles 591system.cpu.icache.demand_miss_latency::total 13938284992 # number of demand (read+write) miss cycles 592system.cpu.icache.overall_miss_latency::cpu.inst 13938284992 # number of overall miss cycles 593system.cpu.icache.overall_miss_latency::total 13938284992 # number of overall miss cycles 594system.cpu.icache.ReadReq_accesses::cpu.inst 8492081 # number of ReadReq accesses(hits+misses) 595system.cpu.icache.ReadReq_accesses::total 8492081 # number of ReadReq accesses(hits+misses) 596system.cpu.icache.demand_accesses::cpu.inst 8492081 # number of demand (read+write) accesses 597system.cpu.icache.demand_accesses::total 8492081 # number of demand (read+write) accesses 598system.cpu.icache.overall_accesses::cpu.inst 8492081 # number of overall (read+write) accesses 599system.cpu.icache.overall_accesses::total 8492081 # number of overall (read+write) accesses 600system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118925 # miss rate for ReadReq accesses 601system.cpu.icache.ReadReq_miss_rate::total 0.118925 # miss rate for ReadReq accesses 602system.cpu.icache.demand_miss_rate::cpu.inst 0.118925 # miss rate for demand accesses 603system.cpu.icache.demand_miss_rate::total 0.118925 # miss rate for demand accesses 604system.cpu.icache.overall_miss_rate::cpu.inst 0.118925 # miss rate for overall accesses 605system.cpu.icache.overall_miss_rate::total 0.118925 # miss rate for overall accesses 606system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.348017 # average ReadReq miss latency 607system.cpu.icache.ReadReq_avg_miss_latency::total 13801.348017 # average ReadReq miss latency 608system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency 609system.cpu.icache.demand_avg_miss_latency::total 13801.348017 # average overall miss latency 610system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency 611system.cpu.icache.overall_avg_miss_latency::total 13801.348017 # average overall miss latency 612system.cpu.icache.blocked_cycles::no_mshrs 8199 # number of cycles access was blocked 613system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 614system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked 615system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 616system.cpu.icache.avg_blocked_cycles::no_mshrs 40.389163 # average number of cycles each access was blocked 617system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 618system.cpu.icache.fast_writes 0 # number of fast writes performed 619system.cpu.icache.cache_copies 0 # number of cache copies performed 620system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53908 # number of ReadReq MSHR hits 621system.cpu.icache.ReadReq_mshr_hits::total 53908 # number of ReadReq MSHR hits 622system.cpu.icache.demand_mshr_hits::cpu.inst 53908 # number of demand (read+write) MSHR hits 623system.cpu.icache.demand_mshr_hits::total 53908 # number of demand (read+write) MSHR hits 624system.cpu.icache.overall_mshr_hits::cpu.inst 53908 # number of overall MSHR hits 625system.cpu.icache.overall_mshr_hits::total 53908 # number of overall MSHR hits 626system.cpu.icache.ReadReq_mshr_misses::cpu.inst 956014 # number of ReadReq MSHR misses 627system.cpu.icache.ReadReq_mshr_misses::total 956014 # number of ReadReq MSHR misses 628system.cpu.icache.demand_mshr_misses::cpu.inst 956014 # number of demand (read+write) MSHR misses 629system.cpu.icache.demand_mshr_misses::total 956014 # number of demand (read+write) MSHR misses 630system.cpu.icache.overall_mshr_misses::cpu.inst 956014 # number of overall MSHR misses 631system.cpu.icache.overall_mshr_misses::total 956014 # number of overall MSHR misses 632system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11502740492 # number of ReadReq MSHR miss cycles 633system.cpu.icache.ReadReq_mshr_miss_latency::total 11502740492 # number of ReadReq MSHR miss cycles 634system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11502740492 # number of demand (read+write) MSHR miss cycles 635system.cpu.icache.demand_mshr_miss_latency::total 11502740492 # number of demand (read+write) MSHR miss cycles 636system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11502740492 # number of overall MSHR miss cycles 637system.cpu.icache.overall_mshr_miss_latency::total 11502740492 # number of overall MSHR miss cycles 638system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112577 # mshr miss rate for ReadReq accesses 640system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for demand accesses 641system.cpu.icache.demand_mshr_miss_rate::total 0.112577 # mshr miss rate for demand accesses 642system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112577 # mshr miss rate for overall accesses 643system.cpu.icache.overall_mshr_miss_rate::total 0.112577 # mshr miss rate for overall accesses 644system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.979126 # average ReadReq mshr miss latency 645system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.979126 # average ReadReq mshr miss latency 646system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency 647system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency 648system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.979126 # average overall mshr miss latency 649system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.979126 # average overall mshr miss latency 650system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 651system.cpu.itb_walker_cache.replacements 7960 # number of replacements 652system.cpu.itb_walker_cache.tagsinuse 6.326712 # Cycle average of tags in use 653system.cpu.itb_walker_cache.total_refs 20386 # Total number of references to valid blocks. 654system.cpu.itb_walker_cache.sampled_refs 7973 # Sample count of references to valid blocks. 655system.cpu.itb_walker_cache.avg_refs 2.556879 # Average number of references to valid blocks. 656system.cpu.itb_walker_cache.warmup_cycle 5107329698000 # Cycle when the warmup percentage was hit. 657system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.326712 # Average occupied blocks per requestor 658system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.395420 # Average percentage of cache occupancy 659system.cpu.itb_walker_cache.occ_percent::total 0.395420 # Average percentage of cache occupancy 660system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20403 # number of ReadReq hits 661system.cpu.itb_walker_cache.ReadReq_hits::total 20403 # number of ReadReq hits 662system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 663system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 664system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20405 # number of demand (read+write) hits 665system.cpu.itb_walker_cache.demand_hits::total 20405 # number of demand (read+write) hits 666system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20405 # number of overall hits 667system.cpu.itb_walker_cache.overall_hits::total 20405 # number of overall hits 668system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8843 # number of ReadReq misses 669system.cpu.itb_walker_cache.ReadReq_misses::total 8843 # number of ReadReq misses 670system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8843 # number of demand (read+write) misses 671system.cpu.itb_walker_cache.demand_misses::total 8843 # number of demand (read+write) misses 672system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8843 # number of overall misses 673system.cpu.itb_walker_cache.overall_misses::total 8843 # number of overall misses 674system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 96821500 # number of ReadReq miss cycles 675system.cpu.itb_walker_cache.ReadReq_miss_latency::total 96821500 # number of ReadReq miss cycles 676system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 96821500 # number of demand (read+write) miss cycles 677system.cpu.itb_walker_cache.demand_miss_latency::total 96821500 # number of demand (read+write) miss cycles 678system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 96821500 # number of overall miss cycles 679system.cpu.itb_walker_cache.overall_miss_latency::total 96821500 # number of overall miss cycles 680system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 29246 # number of ReadReq accesses(hits+misses) 681system.cpu.itb_walker_cache.ReadReq_accesses::total 29246 # number of ReadReq accesses(hits+misses) 682system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 683system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 684system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 29248 # number of demand (read+write) accesses 685system.cpu.itb_walker_cache.demand_accesses::total 29248 # number of demand (read+write) accesses 686system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 29248 # number of overall (read+write) accesses 687system.cpu.itb_walker_cache.overall_accesses::total 29248 # number of overall (read+write) accesses 688system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.302366 # miss rate for ReadReq accesses 689system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.302366 # miss rate for ReadReq accesses 690system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.302345 # miss rate for demand accesses 691system.cpu.itb_walker_cache.demand_miss_rate::total 0.302345 # miss rate for demand accesses 692system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.302345 # miss rate for overall accesses 693system.cpu.itb_walker_cache.overall_miss_rate::total 0.302345 # miss rate for overall accesses 694system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10948.942667 # average ReadReq miss latency 695system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10948.942667 # average ReadReq miss latency 696system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10948.942667 # average overall miss latency 697system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10948.942667 # average overall miss latency 698system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10948.942667 # average overall miss latency 699system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10948.942667 # average overall miss latency 700system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 701system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 702system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 703system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 704system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 705system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 706system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 707system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 708system.cpu.itb_walker_cache.writebacks::writebacks 1394 # number of writebacks 709system.cpu.itb_walker_cache.writebacks::total 1394 # number of writebacks 710system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8843 # number of ReadReq MSHR misses 711system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8843 # number of ReadReq MSHR misses 712system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8843 # number of demand (read+write) MSHR misses 713system.cpu.itb_walker_cache.demand_mshr_misses::total 8843 # number of demand (read+write) MSHR misses 714system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8843 # number of overall MSHR misses 715system.cpu.itb_walker_cache.overall_mshr_misses::total 8843 # number of overall MSHR misses 716system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 79135500 # number of ReadReq MSHR miss cycles 717system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 79135500 # number of ReadReq MSHR miss cycles 718system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 79135500 # number of demand (read+write) MSHR miss cycles 719system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 79135500 # number of demand (read+write) MSHR miss cycles 720system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 79135500 # number of overall MSHR miss cycles 721system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 79135500 # number of overall MSHR miss cycles 722system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.302366 # mshr miss rate for ReadReq accesses 723system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.302366 # mshr miss rate for ReadReq accesses 724system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for demand accesses 725system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.302345 # mshr miss rate for demand accesses 726system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.302345 # mshr miss rate for overall accesses 727system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.302345 # mshr miss rate for overall accesses 728system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average ReadReq mshr miss latency 729system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8948.942667 # average ReadReq mshr miss latency 730system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency 731system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency 732system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8948.942667 # average overall mshr miss latency 733system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8948.942667 # average overall mshr miss latency 734system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 735system.cpu.dtb_walker_cache.replacements 67560 # number of replacements 736system.cpu.dtb_walker_cache.tagsinuse 14.837353 # Cycle average of tags in use 737system.cpu.dtb_walker_cache.total_refs 92239 # Total number of references to valid blocks. 738system.cpu.dtb_walker_cache.sampled_refs 67575 # Sample count of references to valid blocks. 739system.cpu.dtb_walker_cache.avg_refs 1.364987 # Average number of references to valid blocks. 740system.cpu.dtb_walker_cache.warmup_cycle 5100574572500 # Cycle when the warmup percentage was hit. 741system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 14.837353 # Average occupied blocks per requestor 742system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.927335 # Average percentage of cache occupancy 743system.cpu.dtb_walker_cache.occ_percent::total 0.927335 # Average percentage of cache occupancy 744system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92240 # number of ReadReq hits 745system.cpu.dtb_walker_cache.ReadReq_hits::total 92240 # number of ReadReq hits 746system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92240 # number of demand (read+write) hits 747system.cpu.dtb_walker_cache.demand_hits::total 92240 # number of demand (read+write) hits 748system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92240 # number of overall hits 749system.cpu.dtb_walker_cache.overall_hits::total 92240 # number of overall hits 750system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 68644 # number of ReadReq misses 751system.cpu.dtb_walker_cache.ReadReq_misses::total 68644 # number of ReadReq misses 752system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 68644 # number of demand (read+write) misses 753system.cpu.dtb_walker_cache.demand_misses::total 68644 # number of demand (read+write) misses 754system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 68644 # number of overall misses 755system.cpu.dtb_walker_cache.overall_misses::total 68644 # number of overall misses 756system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 852599000 # number of ReadReq miss cycles 757system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 852599000 # number of ReadReq miss cycles 758system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 852599000 # number of demand (read+write) miss cycles 759system.cpu.dtb_walker_cache.demand_miss_latency::total 852599000 # number of demand (read+write) miss cycles 760system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 852599000 # number of overall miss cycles 761system.cpu.dtb_walker_cache.overall_miss_latency::total 852599000 # number of overall miss cycles 762system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 160884 # number of ReadReq accesses(hits+misses) 763system.cpu.dtb_walker_cache.ReadReq_accesses::total 160884 # number of ReadReq accesses(hits+misses) 764system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 160884 # number of demand (read+write) accesses 765system.cpu.dtb_walker_cache.demand_accesses::total 160884 # number of demand (read+write) accesses 766system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 160884 # number of overall (read+write) accesses 767system.cpu.dtb_walker_cache.overall_accesses::total 160884 # number of overall (read+write) accesses 768system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.426668 # miss rate for ReadReq accesses 769system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.426668 # miss rate for ReadReq accesses 770system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.426668 # miss rate for demand accesses 771system.cpu.dtb_walker_cache.demand_miss_rate::total 0.426668 # miss rate for demand accesses 772system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.426668 # miss rate for overall accesses 773system.cpu.dtb_walker_cache.overall_miss_rate::total 0.426668 # miss rate for overall accesses 774system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12420.590292 # average ReadReq miss latency 775system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12420.590292 # average ReadReq miss latency 776system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency 777system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12420.590292 # average overall miss latency 778system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12420.590292 # average overall miss latency 779system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12420.590292 # average overall miss latency 780system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 781system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 782system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 783system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 784system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 785system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 786system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 787system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 788system.cpu.dtb_walker_cache.writebacks::writebacks 19876 # number of writebacks 789system.cpu.dtb_walker_cache.writebacks::total 19876 # number of writebacks 790system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 68644 # number of ReadReq MSHR misses 791system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 68644 # number of ReadReq MSHR misses 792system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 68644 # number of demand (read+write) MSHR misses 793system.cpu.dtb_walker_cache.demand_mshr_misses::total 68644 # number of demand (read+write) MSHR misses 794system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 68644 # number of overall MSHR misses 795system.cpu.dtb_walker_cache.overall_mshr_misses::total 68644 # number of overall MSHR misses 796system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 715311000 # number of ReadReq MSHR miss cycles 797system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 715311000 # number of ReadReq MSHR miss cycles 798system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 715311000 # number of demand (read+write) MSHR miss cycles 799system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 715311000 # number of demand (read+write) MSHR miss cycles 800system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 715311000 # number of overall MSHR miss cycles 801system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 715311000 # number of overall MSHR miss cycles 802system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for ReadReq accesses 803system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.426668 # mshr miss rate for ReadReq accesses 804system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for demand accesses 805system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.426668 # mshr miss rate for demand accesses 806system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.426668 # mshr miss rate for overall accesses 807system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.426668 # mshr miss rate for overall accesses 808system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average ReadReq mshr miss latency 809system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10420.590292 # average ReadReq mshr miss latency 810system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency 811system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency 812system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292 # average overall mshr miss latency 813system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10420.590292 # average overall mshr miss latency 814system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 815system.cpu.dcache.replacements 1655094 # number of replacements 816system.cpu.dcache.tagsinuse 511.995445 # Cycle average of tags in use 817system.cpu.dcache.total_refs 19021390 # Total number of references to valid blocks. 818system.cpu.dcache.sampled_refs 1655606 # Sample count of references to valid blocks. 819system.cpu.dcache.avg_refs 11.489080 # Average number of references to valid blocks. 820system.cpu.dcache.warmup_cycle 27980000 # Cycle when the warmup percentage was hit. 821system.cpu.dcache.occ_blocks::cpu.data 511.995445 # Average occupied blocks per requestor 822system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy 823system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy 824system.cpu.dcache.ReadReq_hits::cpu.data 10917270 # number of ReadReq hits 825system.cpu.dcache.ReadReq_hits::total 10917270 # number of ReadReq hits 826system.cpu.dcache.WriteReq_hits::cpu.data 8101435 # number of WriteReq hits 827system.cpu.dcache.WriteReq_hits::total 8101435 # number of WriteReq hits 828system.cpu.dcache.demand_hits::cpu.data 19018705 # number of demand (read+write) hits 829system.cpu.dcache.demand_hits::total 19018705 # number of demand (read+write) hits 830system.cpu.dcache.overall_hits::cpu.data 19018705 # number of overall hits 831system.cpu.dcache.overall_hits::total 19018705 # number of overall hits 832system.cpu.dcache.ReadReq_misses::cpu.data 2239579 # number of ReadReq misses 833system.cpu.dcache.ReadReq_misses::total 2239579 # number of ReadReq misses 834system.cpu.dcache.WriteReq_misses::cpu.data 315092 # number of WriteReq misses 835system.cpu.dcache.WriteReq_misses::total 315092 # number of WriteReq misses 836system.cpu.dcache.demand_misses::cpu.data 2554671 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 2554671 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 2554671 # number of overall misses 839system.cpu.dcache.overall_misses::total 2554671 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 31946998000 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 31946998000 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 9622210995 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 9622210995 # number of WriteReq miss cycles 844system.cpu.dcache.demand_miss_latency::cpu.data 41569208995 # number of demand (read+write) miss cycles 845system.cpu.dcache.demand_miss_latency::total 41569208995 # number of demand (read+write) miss cycles 846system.cpu.dcache.overall_miss_latency::cpu.data 41569208995 # number of overall miss cycles 847system.cpu.dcache.overall_miss_latency::total 41569208995 # number of overall miss cycles 848system.cpu.dcache.ReadReq_accesses::cpu.data 13156849 # number of ReadReq accesses(hits+misses) 849system.cpu.dcache.ReadReq_accesses::total 13156849 # number of ReadReq accesses(hits+misses) 850system.cpu.dcache.WriteReq_accesses::cpu.data 8416527 # number of WriteReq accesses(hits+misses) 851system.cpu.dcache.WriteReq_accesses::total 8416527 # number of WriteReq accesses(hits+misses) 852system.cpu.dcache.demand_accesses::cpu.data 21573376 # number of demand (read+write) accesses 853system.cpu.dcache.demand_accesses::total 21573376 # number of demand (read+write) accesses 854system.cpu.dcache.overall_accesses::cpu.data 21573376 # number of overall (read+write) accesses 855system.cpu.dcache.overall_accesses::total 21573376 # number of overall (read+write) accesses 856system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170222 # miss rate for ReadReq accesses 857system.cpu.dcache.ReadReq_miss_rate::total 0.170222 # miss rate for ReadReq accesses 858system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037437 # miss rate for WriteReq accesses 859system.cpu.dcache.WriteReq_miss_rate::total 0.037437 # miss rate for WriteReq accesses 860system.cpu.dcache.demand_miss_rate::cpu.data 0.118418 # miss rate for demand accesses 861system.cpu.dcache.demand_miss_rate::total 0.118418 # miss rate for demand accesses 862system.cpu.dcache.overall_miss_rate::cpu.data 0.118418 # miss rate for overall accesses 863system.cpu.dcache.overall_miss_rate::total 0.118418 # miss rate for overall accesses 864system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14264.733684 # average ReadReq miss latency 865system.cpu.dcache.ReadReq_avg_miss_latency::total 14264.733684 # average ReadReq miss latency 866system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30537.782600 # average WriteReq miss latency 867system.cpu.dcache.WriteReq_avg_miss_latency::total 30537.782600 # average WriteReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 16271.844396 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 16271.844396 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 16271.844396 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 16271.844396 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 387071 # number of cycles access was blocked 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 874system.cpu.dcache.blocked::no_mshrs 42390 # number of cycles access was blocked 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.131187 # average number of cycles each access was blocked 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed 880system.cpu.dcache.writebacks::writebacks 1557214 # number of writebacks 881system.cpu.dcache.writebacks::total 1557214 # number of writebacks 882system.cpu.dcache.ReadReq_mshr_hits::cpu.data 870911 # number of ReadReq MSHR hits 883system.cpu.dcache.ReadReq_mshr_hits::total 870911 # number of ReadReq MSHR hits 884system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25892 # number of WriteReq MSHR hits 885system.cpu.dcache.WriteReq_mshr_hits::total 25892 # number of WriteReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 896803 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 896803 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 896803 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 896803 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1368668 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 1368668 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289200 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 289200 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 1657868 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 1657868 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 1657868 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 1657868 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17401159000 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 17401159000 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8794383495 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 8794383495 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26195542495 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 26195542495 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26195542495 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 26195542495 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97349101500 # number of ReadReq MSHR uncacheable cycles 907system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97349101500 # number of ReadReq MSHR uncacheable cycles 908system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2522345500 # number of WriteReq MSHR uncacheable cycles 909system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2522345500 # number of WriteReq MSHR uncacheable cycles 910system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99871447000 # number of overall MSHR uncacheable cycles 911system.cpu.dcache.overall_mshr_uncacheable_latency::total 99871447000 # number of overall MSHR uncacheable cycles 912system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104027 # mshr miss rate for ReadReq accesses 913system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104027 # mshr miss rate for ReadReq accesses 914system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034361 # mshr miss rate for WriteReq accesses 915system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034361 # mshr miss rate for WriteReq accesses 916system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076848 # mshr miss rate for demand accesses 917system.cpu.dcache.demand_mshr_miss_rate::total 0.076848 # mshr miss rate for demand accesses 918system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076848 # mshr miss rate for overall accesses 919system.cpu.dcache.overall_mshr_miss_rate::total 0.076848 # mshr miss rate for overall accesses 920system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12713.937200 # average ReadReq mshr miss latency 921system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12713.937200 # average ReadReq mshr miss latency 922system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30409.348185 # average WriteReq mshr miss latency 923system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30409.348185 # average WriteReq mshr miss latency 924system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15800.740768 # average overall mshr miss latency 925system.cpu.dcache.demand_avg_mshr_miss_latency::total 15800.740768 # average overall mshr miss latency 926system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15800.740768 # average overall mshr miss latency 927system.cpu.dcache.overall_avg_mshr_miss_latency::total 15800.740768 # average overall mshr miss latency 928system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 929system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 930system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 931system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 932system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 933system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 934system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 935system.cpu.l2cache.replacements 111963 # number of replacements 936system.cpu.l2cache.tagsinuse 64818.241357 # Cycle average of tags in use 937system.cpu.l2cache.total_refs 3779325 # Total number of references to valid blocks. 938system.cpu.l2cache.sampled_refs 176193 # Sample count of references to valid blocks. 939system.cpu.l2cache.avg_refs 21.449916 # Average number of references to valid blocks. 940system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 941system.cpu.l2cache.occ_blocks::writebacks 50535.271880 # Average occupied blocks per requestor 942system.cpu.l2cache.occ_blocks::cpu.dtb.walker 14.689116 # Average occupied blocks per requestor 943system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.441967 # Average occupied blocks per requestor 944system.cpu.l2cache.occ_blocks::cpu.inst 3088.733265 # Average occupied blocks per requestor 945system.cpu.l2cache.occ_blocks::cpu.data 11179.105128 # Average occupied blocks per requestor 946system.cpu.l2cache.occ_percent::writebacks 0.771107 # Average percentage of cache occupancy 947system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000224 # Average percentage of cache occupancy 948system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy 949system.cpu.l2cache.occ_percent::cpu.inst 0.047130 # Average percentage of cache occupancy 950system.cpu.l2cache.occ_percent::cpu.data 0.170580 # Average percentage of cache occupancy 951system.cpu.l2cache.occ_percent::total 0.989048 # Average percentage of cache occupancy 952system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63019 # number of ReadReq hits 953system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 6673 # number of ReadReq hits 954system.cpu.l2cache.ReadReq_hits::cpu.inst 939861 # number of ReadReq hits 955system.cpu.l2cache.ReadReq_hits::cpu.data 1331810 # number of ReadReq hits 956system.cpu.l2cache.ReadReq_hits::total 2341363 # number of ReadReq hits 957system.cpu.l2cache.Writeback_hits::writebacks 1578484 # number of Writeback hits 958system.cpu.l2cache.Writeback_hits::total 1578484 # number of Writeback hits 959system.cpu.l2cache.UpgradeReq_hits::cpu.data 313 # number of UpgradeReq hits 960system.cpu.l2cache.UpgradeReq_hits::total 313 # number of UpgradeReq hits 961system.cpu.l2cache.ReadExReq_hits::cpu.data 154035 # number of ReadExReq hits 962system.cpu.l2cache.ReadExReq_hits::total 154035 # number of ReadExReq hits 963system.cpu.l2cache.demand_hits::cpu.dtb.walker 63019 # number of demand (read+write) hits 964system.cpu.l2cache.demand_hits::cpu.itb.walker 6673 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.inst 939861 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::cpu.data 1485845 # number of demand (read+write) hits 967system.cpu.l2cache.demand_hits::total 2495398 # number of demand (read+write) hits 968system.cpu.l2cache.overall_hits::cpu.dtb.walker 63019 # number of overall hits 969system.cpu.l2cache.overall_hits::cpu.itb.walker 6673 # number of overall hits 970system.cpu.l2cache.overall_hits::cpu.inst 939861 # number of overall hits 971system.cpu.l2cache.overall_hits::cpu.data 1485845 # number of overall hits 972system.cpu.l2cache.overall_hits::total 2495398 # number of overall hits 973system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 58 # number of ReadReq misses 974system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses 975system.cpu.l2cache.ReadReq_misses::cpu.inst 16036 # number of ReadReq misses 976system.cpu.l2cache.ReadReq_misses::cpu.data 36136 # number of ReadReq misses 977system.cpu.l2cache.ReadReq_misses::total 52236 # number of ReadReq misses 978system.cpu.l2cache.UpgradeReq_misses::cpu.data 1469 # number of UpgradeReq misses 979system.cpu.l2cache.UpgradeReq_misses::total 1469 # number of UpgradeReq misses 980system.cpu.l2cache.ReadExReq_misses::cpu.data 133013 # number of ReadExReq misses 981system.cpu.l2cache.ReadExReq_misses::total 133013 # number of ReadExReq misses 982system.cpu.l2cache.demand_misses::cpu.dtb.walker 58 # number of demand (read+write) misses 983system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 984system.cpu.l2cache.demand_misses::cpu.inst 16036 # number of demand (read+write) misses 985system.cpu.l2cache.demand_misses::cpu.data 169149 # number of demand (read+write) misses 986system.cpu.l2cache.demand_misses::total 185249 # number of demand (read+write) misses 987system.cpu.l2cache.overall_misses::cpu.dtb.walker 58 # number of overall misses 988system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses 989system.cpu.l2cache.overall_misses::cpu.inst 16036 # number of overall misses 990system.cpu.l2cache.overall_misses::cpu.data 169149 # number of overall misses 991system.cpu.l2cache.overall_misses::total 185249 # number of overall misses 992system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4739500 # number of ReadReq miss cycles 993system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 386000 # number of ReadReq miss cycles 994system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1102660000 # number of ReadReq miss cycles 995system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2500024999 # number of ReadReq miss cycles 996system.cpu.l2cache.ReadReq_miss_latency::total 3607810499 # number of ReadReq miss cycles 997system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 18004500 # number of UpgradeReq miss cycles 998system.cpu.l2cache.UpgradeReq_miss_latency::total 18004500 # number of UpgradeReq miss cycles 999system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6917223500 # number of ReadExReq miss cycles 1000system.cpu.l2cache.ReadExReq_miss_latency::total 6917223500 # number of ReadExReq miss cycles 1001system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4739500 # number of demand (read+write) miss cycles 1002system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 386000 # number of demand (read+write) miss cycles 1003system.cpu.l2cache.demand_miss_latency::cpu.inst 1102660000 # number of demand (read+write) miss cycles 1004system.cpu.l2cache.demand_miss_latency::cpu.data 9417248499 # number of demand (read+write) miss cycles 1005system.cpu.l2cache.demand_miss_latency::total 10525033999 # number of demand (read+write) miss cycles 1006system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4739500 # number of overall miss cycles 1007system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 386000 # number of overall miss cycles 1008system.cpu.l2cache.overall_miss_latency::cpu.inst 1102660000 # number of overall miss cycles 1009system.cpu.l2cache.overall_miss_latency::cpu.data 9417248499 # number of overall miss cycles 1010system.cpu.l2cache.overall_miss_latency::total 10525033999 # number of overall miss cycles 1011system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 63077 # number of ReadReq accesses(hits+misses) 1012system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 6679 # number of ReadReq accesses(hits+misses) 1013system.cpu.l2cache.ReadReq_accesses::cpu.inst 955897 # number of ReadReq accesses(hits+misses) 1014system.cpu.l2cache.ReadReq_accesses::cpu.data 1367946 # number of ReadReq accesses(hits+misses) 1015system.cpu.l2cache.ReadReq_accesses::total 2393599 # number of ReadReq accesses(hits+misses) 1016system.cpu.l2cache.Writeback_accesses::writebacks 1578484 # number of Writeback accesses(hits+misses) 1017system.cpu.l2cache.Writeback_accesses::total 1578484 # number of Writeback accesses(hits+misses) 1018system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1782 # number of UpgradeReq accesses(hits+misses) 1019system.cpu.l2cache.UpgradeReq_accesses::total 1782 # number of UpgradeReq accesses(hits+misses) 1020system.cpu.l2cache.ReadExReq_accesses::cpu.data 287048 # number of ReadExReq accesses(hits+misses) 1021system.cpu.l2cache.ReadExReq_accesses::total 287048 # number of ReadExReq accesses(hits+misses) 1022system.cpu.l2cache.demand_accesses::cpu.dtb.walker 63077 # number of demand (read+write) accesses 1023system.cpu.l2cache.demand_accesses::cpu.itb.walker 6679 # number of demand (read+write) accesses 1024system.cpu.l2cache.demand_accesses::cpu.inst 955897 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::cpu.data 1654994 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::total 2680647 # number of demand (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.dtb.walker 63077 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::cpu.itb.walker 6679 # number of overall (read+write) accesses 1029system.cpu.l2cache.overall_accesses::cpu.inst 955897 # number of overall (read+write) accesses 1030system.cpu.l2cache.overall_accesses::cpu.data 1654994 # number of overall (read+write) accesses 1031system.cpu.l2cache.overall_accesses::total 2680647 # number of overall (read+write) accesses 1032system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses 1033system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000898 # miss rate for ReadReq accesses 1034system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016776 # miss rate for ReadReq accesses 1035system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026416 # miss rate for ReadReq accesses 1036system.cpu.l2cache.ReadReq_miss_rate::total 0.021823 # miss rate for ReadReq accesses 1037system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.824355 # miss rate for UpgradeReq accesses 1038system.cpu.l2cache.UpgradeReq_miss_rate::total 0.824355 # miss rate for UpgradeReq accesses 1039system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463382 # miss rate for ReadExReq accesses 1040system.cpu.l2cache.ReadExReq_miss_rate::total 0.463382 # miss rate for ReadExReq accesses 1041system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses 1042system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000898 # miss rate for demand accesses 1043system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016776 # miss rate for demand accesses 1044system.cpu.l2cache.demand_miss_rate::cpu.data 0.102205 # miss rate for demand accesses 1045system.cpu.l2cache.demand_miss_rate::total 0.069106 # miss rate for demand accesses 1046system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses 1047system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000898 # miss rate for overall accesses 1048system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016776 # miss rate for overall accesses 1049system.cpu.l2cache.overall_miss_rate::cpu.data 0.102205 # miss rate for overall accesses 1050system.cpu.l2cache.overall_miss_rate::total 0.069106 # miss rate for overall accesses 1051system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81715.517241 # average ReadReq miss latency 1052system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64333.333333 # average ReadReq miss latency 1053system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68761.536543 # average ReadReq miss latency 1054system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69183.777922 # average ReadReq miss latency 1055system.cpu.l2cache.ReadReq_avg_miss_latency::total 69067.510893 # average ReadReq miss latency 1056system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12256.296801 # average UpgradeReq miss latency 1057system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12256.296801 # average UpgradeReq miss latency 1058system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.116139 # average ReadExReq miss latency 1059system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.116139 # average ReadExReq miss latency 1060system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81715.517241 # average overall miss latency 1061system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64333.333333 # average overall miss latency 1062system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68761.536543 # average overall miss latency 1063system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55674.278293 # average overall miss latency 1064system.cpu.l2cache.demand_avg_miss_latency::total 56815.604937 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81715.517241 # average overall miss latency 1066system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64333.333333 # average overall miss latency 1067system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68761.536543 # average overall miss latency 1068system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55674.278293 # average overall miss latency 1069system.cpu.l2cache.overall_avg_miss_latency::total 56815.604937 # average overall miss latency 1070system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1077system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1078system.cpu.l2cache.writebacks::writebacks 102337 # number of writebacks 1079system.cpu.l2cache.writebacks::total 102337 # number of writebacks 1080system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1081system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1082system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1083system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1084system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1085system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 1086system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 58 # number of ReadReq MSHR misses 1087system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses 1088system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16035 # number of ReadReq MSHR misses 1089system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36136 # number of ReadReq MSHR misses 1090system.cpu.l2cache.ReadReq_mshr_misses::total 52235 # number of ReadReq MSHR misses 1091system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1469 # number of UpgradeReq MSHR misses 1092system.cpu.l2cache.UpgradeReq_mshr_misses::total 1469 # number of UpgradeReq MSHR misses 1093system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133013 # number of ReadExReq MSHR misses 1094system.cpu.l2cache.ReadExReq_mshr_misses::total 133013 # number of ReadExReq MSHR misses 1095system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 58 # number of demand (read+write) MSHR misses 1096system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 1097system.cpu.l2cache.demand_mshr_misses::cpu.inst 16035 # number of demand (read+write) MSHR misses 1098system.cpu.l2cache.demand_mshr_misses::cpu.data 169149 # number of demand (read+write) MSHR misses 1099system.cpu.l2cache.demand_mshr_misses::total 185248 # number of demand (read+write) MSHR misses 1100system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 58 # number of overall MSHR misses 1101system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 1102system.cpu.l2cache.overall_mshr_misses::cpu.inst 16035 # number of overall MSHR misses 1103system.cpu.l2cache.overall_mshr_misses::cpu.data 169149 # number of overall MSHR misses 1104system.cpu.l2cache.overall_mshr_misses::total 185248 # number of overall MSHR misses 1105system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4016555 # number of ReadReq MSHR miss cycles 1106system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 310006 # number of ReadReq MSHR miss cycles 1107system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 903103756 # number of ReadReq MSHR miss cycles 1108system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2050826327 # number of ReadReq MSHR miss cycles 1109system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2958256644 # number of ReadReq MSHR miss cycles 1110system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15725947 # number of UpgradeReq MSHR miss cycles 1111system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15725947 # number of UpgradeReq MSHR miss cycles 1112system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5276958842 # number of ReadExReq MSHR miss cycles 1113system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5276958842 # number of ReadExReq MSHR miss cycles 1114system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4016555 # number of demand (read+write) MSHR miss cycles 1115system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 310006 # number of demand (read+write) MSHR miss cycles 1116system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 903103756 # number of demand (read+write) MSHR miss cycles 1117system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327785169 # number of demand (read+write) MSHR miss cycles 1118system.cpu.l2cache.demand_mshr_miss_latency::total 8235215486 # number of demand (read+write) MSHR miss cycles 1119system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4016555 # number of overall MSHR miss cycles 1120system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 310006 # number of overall MSHR miss cycles 1121system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 903103756 # number of overall MSHR miss cycles 1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327785169 # number of overall MSHR miss cycles 1123system.cpu.l2cache.overall_mshr_miss_latency::total 8235215486 # number of overall MSHR miss cycles 1124system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89236811500 # number of ReadReq MSHR uncacheable cycles 1125system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236811500 # number of ReadReq MSHR uncacheable cycles 1126system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2357396500 # number of WriteReq MSHR uncacheable cycles 1127system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2357396500 # number of WriteReq MSHR uncacheable cycles 1128system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91594208000 # number of overall MSHR uncacheable cycles 1129system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91594208000 # number of overall MSHR uncacheable cycles 1130system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000920 # mshr miss rate for ReadReq accesses 1131system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000898 # mshr miss rate for ReadReq accesses 1132system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016775 # mshr miss rate for ReadReq accesses 1133system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026416 # mshr miss rate for ReadReq accesses 1134system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021823 # mshr miss rate for ReadReq accesses 1135system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.824355 # mshr miss rate for UpgradeReq accesses 1136system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.824355 # mshr miss rate for UpgradeReq accesses 1137system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463382 # mshr miss rate for ReadExReq accesses 1138system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463382 # mshr miss rate for ReadExReq accesses 1139system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000920 # mshr miss rate for demand accesses 1140system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000898 # mshr miss rate for demand accesses 1141system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016775 # mshr miss rate for demand accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102205 # mshr miss rate for demand accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::total 0.069106 # mshr miss rate for demand accesses 1144system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000920 # mshr miss rate for overall accesses 1145system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000898 # mshr miss rate for overall accesses 1146system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016775 # mshr miss rate for overall accesses 1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102205 # mshr miss rate for overall accesses 1148system.cpu.l2cache.overall_mshr_miss_rate::total 0.069106 # mshr miss rate for overall accesses 1149system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276 # average ReadReq mshr miss latency 1150system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average ReadReq mshr miss latency 1151system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56320.783037 # average ReadReq mshr miss latency 1152system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56752.997758 # average ReadReq mshr miss latency 1153system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56633.610491 # average ReadReq mshr miss latency 1154system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10705.205582 # average UpgradeReq mshr miss latency 1155system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10705.205582 # average UpgradeReq mshr miss latency 1156system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39672.504507 # average ReadExReq mshr miss latency 1157system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39672.504507 # average ReadExReq mshr miss latency 1158system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276 # average overall mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average overall mshr miss latency 1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56320.783037 # average overall mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43321.480878 # average overall mshr miss latency 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44455.084460 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 51667.666667 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56320.783037 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43321.480878 # average overall mshr miss latency 1167system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44455.084460 # average overall mshr miss latency 1168system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1169system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1170system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1171system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1172system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1173system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1174system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1175system.cpu.kern.inst.arm 0 # number of arm instructions executed 1176system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1177 1178---------- End Simulation Statistics ---------- 1179