stats.txt revision 9615:daa8a14ec85e
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.136865 # Number of seconds simulated 4sim_ticks 5136864508000 # Number of ticks simulated 5final_tick 5136864508000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 157360 # Simulator instruction rate (inst/s) 8host_op_rate 311060 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1981722494 # Simulator tick rate (ticks/s) 10host_mem_usage 783288 # Number of bytes of host memory used 11host_seconds 2592.12 # Real time elapsed on the host 12sim_insts 407895398 # Number of instructions simulated 13sim_ops 806304609 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2499136 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 1076928 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10801024 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14380480 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1076928 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1076928 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9561920 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9561920 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 39049 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 16827 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 168766 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 224695 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 149405 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 149405 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 486510 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 586 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 209647 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2102649 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2799466 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 209647 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 209647 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1861431 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1861431 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1861431 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 486510 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 586 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 209647 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2102649 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4660898 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 224695 # Total number of read requests seen 50system.physmem.writeReqs 149405 # Total number of write requests seen 51system.physmem.cpureqs 378068 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14380480 # Total number of bytes read from memory 53system.physmem.bytesWritten 9561920 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14380480 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9561920 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 102 # Number of read reqs serviced by write Q 57system.physmem.neitherReadNorWrite 3959 # Reqs where no action is needed 58system.physmem.perBankRdReqs::0 14159 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 13042 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 13152 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 16282 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13746 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 13201 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 13511 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 16248 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13928 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 13310 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 13277 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 15618 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 13156 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 12636 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 13394 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 15933 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 9055 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 8495 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 8476 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 11557 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 8862 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 8626 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8868 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 11671 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 8971 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 8652 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 8710 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 11130 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 8376 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 8093 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 8654 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 11209 # Track writes on a per bank basis 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 91system.physmem.numWrRetry 9 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5136864456000 # Total gap between requests 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes 99system.physmem.readPktSize::6 224695 # Categorize read packet sizes 100system.physmem.writePktSize::0 0 # Categorize write packet sizes 101system.physmem.writePktSize::1 0 # Categorize write packet sizes 102system.physmem.writePktSize::2 0 # Categorize write packet sizes 103system.physmem.writePktSize::3 0 # Categorize write packet sizes 104system.physmem.writePktSize::4 0 # Categorize write packet sizes 105system.physmem.writePktSize::5 0 # Categorize write packet sizes 106system.physmem.writePktSize::6 149405 # Categorize write packet sizes 107system.physmem.rdQLenPdf::0 173100 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::1 19795 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::2 7560 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::3 3484 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::4 3025 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::5 2399 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::6 1873 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::7 1799 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::8 1771 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::9 1716 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::10 1128 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::11 1029 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::12 947 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::14 817 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::15 811 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::16 909 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::17 868 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::18 395 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::19 255 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::20 27 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 139system.physmem.wrQLenPdf::0 5333 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::1 5688 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::2 6308 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::3 6389 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::4 6439 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::5 6471 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::6 6482 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::7 6485 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::8 6486 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::9 6496 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::10 6496 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::11 6496 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::12 6496 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::13 6496 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::14 6496 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::15 6496 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::16 6496 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::17 6496 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::18 6496 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::19 6496 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::20 6495 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::22 6495 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::23 1163 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::24 808 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::25 188 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::26 107 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::27 57 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::28 25 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see 171system.physmem.totQLat 4766626250 # Total cycles spent in queuing delays 172system.physmem.totMemAccLat 9279378750 # Sum of mem lat for all requests 173system.physmem.totBusLat 1122965000 # Total cycles spent in databus access 174system.physmem.totBankLat 3389787500 # Total cycles spent in bank access 175system.physmem.avgQLat 21223.40 # Average queueing delay per request 176system.physmem.avgBankLat 15093.02 # Average bank access latency per request 177system.physmem.avgBusLat 5000.00 # Average bus latency per request 178system.physmem.avgMemAccLat 41316.42 # Average memory access latency 179system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s 180system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s 181system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s 182system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s 183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 184system.physmem.busUtil 0.04 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.00 # Average read queue length over time 186system.physmem.avgWrQLen 11.02 # Average write queue length over time 187system.physmem.readRowHits 193644 # Number of row buffer hits during reads 188system.physmem.writeRowHits 105706 # Number of row buffer hits during writes 189system.physmem.readRowHitRate 86.22 # Row buffer hit rate for reads 190system.physmem.writeRowHitRate 70.75 # Row buffer hit rate for writes 191system.physmem.avgGap 13731260.24 # Average gap between requests 192system.iocache.replacements 47574 # number of replacements 193system.iocache.tagsinuse 0.116323 # Cycle average of tags in use 194system.iocache.total_refs 0 # Total number of references to valid blocks. 195system.iocache.sampled_refs 47590 # Sample count of references to valid blocks. 196system.iocache.avg_refs 0 # Average number of references to valid blocks. 197system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit. 198system.iocache.occ_blocks::pc.south_bridge.ide 0.116323 # Average occupied blocks per requestor 199system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy 200system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy 201system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses 202system.iocache.ReadReq_misses::total 909 # number of ReadReq misses 203system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 204system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 205system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses 206system.iocache.demand_misses::total 47629 # number of demand (read+write) misses 207system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses 208system.iocache.overall_misses::total 47629 # number of overall misses 209system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144901871 # number of ReadReq miss cycles 210system.iocache.ReadReq_miss_latency::total 144901871 # number of ReadReq miss cycles 211system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10053199611 # number of WriteReq miss cycles 212system.iocache.WriteReq_miss_latency::total 10053199611 # number of WriteReq miss cycles 213system.iocache.demand_miss_latency::pc.south_bridge.ide 10198101482 # number of demand (read+write) miss cycles 214system.iocache.demand_miss_latency::total 10198101482 # number of demand (read+write) miss cycles 215system.iocache.overall_miss_latency::pc.south_bridge.ide 10198101482 # number of overall miss cycles 216system.iocache.overall_miss_latency::total 10198101482 # number of overall miss cycles 217system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) 218system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) 219system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 220system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 221system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses 222system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses 223system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses 224system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses 225system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 226system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 227system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 228system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 229system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 230system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 231system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 232system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 233system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 159407.998900 # average ReadReq miss latency 234system.iocache.ReadReq_avg_miss_latency::total 159407.998900 # average ReadReq miss latency 235system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215179.786194 # average WriteReq miss latency 236system.iocache.WriteReq_avg_miss_latency::total 215179.786194 # average WriteReq miss latency 237system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214115.381007 # average overall miss latency 238system.iocache.demand_avg_miss_latency::total 214115.381007 # average overall miss latency 239system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214115.381007 # average overall miss latency 240system.iocache.overall_avg_miss_latency::total 214115.381007 # average overall miss latency 241system.iocache.blocked_cycles::no_mshrs 138033 # number of cycles access was blocked 242system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 243system.iocache.blocked::no_mshrs 12531 # number of cycles access was blocked 244system.iocache.blocked::no_targets 0 # number of cycles access was blocked 245system.iocache.avg_blocked_cycles::no_mshrs 11.015322 # average number of cycles each access was blocked 246system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247system.iocache.fast_writes 0 # number of fast writes performed 248system.iocache.cache_copies 0 # number of cache copies performed 249system.iocache.writebacks::writebacks 46667 # number of writebacks 250system.iocache.writebacks::total 46667 # number of writebacks 251system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses 252system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses 253system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 254system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 255system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses 256system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses 257system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses 258system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses 259system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97611900 # number of ReadReq MSHR miss cycles 260system.iocache.ReadReq_mshr_miss_latency::total 97611900 # number of ReadReq MSHR miss cycles 261system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7622412826 # number of WriteReq MSHR miss cycles 262system.iocache.WriteReq_mshr_miss_latency::total 7622412826 # number of WriteReq MSHR miss cycles 263system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7720024726 # number of demand (read+write) MSHR miss cycles 264system.iocache.demand_mshr_miss_latency::total 7720024726 # number of demand (read+write) MSHR miss cycles 265system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7720024726 # number of overall MSHR miss cycles 266system.iocache.overall_mshr_miss_latency::total 7720024726 # number of overall MSHR miss cycles 267system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 268system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 269system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 270system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 271system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 272system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 273system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 274system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 275system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107383.828383 # average ReadReq mshr miss latency 276system.iocache.ReadReq_avg_mshr_miss_latency::total 107383.828383 # average ReadReq mshr miss latency 277system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163150.959461 # average WriteReq mshr miss latency 278system.iocache.WriteReq_avg_mshr_miss_latency::total 163150.959461 # average WriteReq mshr miss latency 279system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162086.643138 # average overall mshr miss latency 280system.iocache.demand_avg_mshr_miss_latency::total 162086.643138 # average overall mshr miss latency 281system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162086.643138 # average overall mshr miss latency 282system.iocache.overall_avg_mshr_miss_latency::total 162086.643138 # average overall mshr miss latency 283system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 284system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 285system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 286system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). 287system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 288system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 289system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 290system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 291system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 292system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 293system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 294system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 295system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 296system.cpu.branchPred.lookups 86192778 # Number of BP lookups 297system.cpu.branchPred.condPredicted 86192778 # Number of conditional branches predicted 298system.cpu.branchPred.condIncorrect 1105969 # Number of conditional branches incorrect 299system.cpu.branchPred.BTBLookups 81285940 # Number of BTB lookups 300system.cpu.branchPred.BTBHits 79207876 # Number of BTB hits 301system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 302system.cpu.branchPred.BTBHitPct 97.443514 # BTB Hit Percentage 303system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 304system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 305system.cpu.numCycles 448117283 # number of cpu cycles simulated 306system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 307system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 308system.cpu.fetch.icacheStallCycles 27407295 # Number of cycles fetch is stalled on an Icache miss 309system.cpu.fetch.Insts 425903825 # Number of instructions fetch has processed 310system.cpu.fetch.Branches 86192778 # Number of branches that fetch encountered 311system.cpu.fetch.predictedBranches 79207876 # Number of branches that fetch has predicted taken 312system.cpu.fetch.Cycles 163564309 # Number of cycles fetch has run and was not squashing or blocked 313system.cpu.fetch.SquashCycles 4697150 # Number of cycles fetch has spent squashing 314system.cpu.fetch.TlbCycles 125610 # Number of cycles fetch has spent waiting for tlb 315system.cpu.fetch.BlockedCycles 63070837 # Number of cycles fetch has spent blocked 316system.cpu.fetch.MiscStallCycles 35658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 317system.cpu.fetch.PendingTrapStallCycles 51192 # Number of stall cycles due to pending traps 318system.cpu.fetch.IcacheWaitRetryStallCycles 380 # Number of stall cycles due to full MSHR 319system.cpu.fetch.CacheLines 9007924 # Number of cache lines fetched 320system.cpu.fetch.IcacheSquashes 482953 # Number of outstanding Icache misses that were squashed 321system.cpu.fetch.ItlbSquashes 2789 # Number of outstanding ITLB misses that were squashed 322system.cpu.fetch.rateDist::samples 257808166 # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::mean 3.261396 # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::stdev 3.418051 # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::0 94670555 36.72% 36.72% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::1 1565511 0.61% 37.33% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::2 71913522 27.89% 65.22% # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::3 935622 0.36% 65.59% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::4 1598852 0.62% 66.21% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::5 2418850 0.94% 67.14% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::6 1070189 0.42% 67.56% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::7 1376236 0.53% 68.09% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::8 82258829 31.91% 100.00% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::total 257808166 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.branchRate 0.192344 # Number of branch fetches per cycle 340system.cpu.fetch.rate 0.950429 # Number of inst fetches per cycle 341system.cpu.decode.IdleCycles 31124176 # Number of cycles decode is idle 342system.cpu.decode.BlockedCycles 60511588 # Number of cycles decode is blocked 343system.cpu.decode.RunCycles 159357091 # Number of cycles decode is running 344system.cpu.decode.UnblockCycles 3262426 # Number of cycles decode is unblocking 345system.cpu.decode.SquashCycles 3552885 # Number of cycles decode is squashing 346system.cpu.decode.DecodedInsts 837683480 # Number of instructions handled by decode 347system.cpu.decode.SquashedInsts 953 # Number of squashed instructions handled by decode 348system.cpu.rename.SquashCycles 3552885 # Number of cycles rename is squashing 349system.cpu.rename.IdleCycles 33860427 # Number of cycles rename is idle 350system.cpu.rename.BlockCycles 37375460 # Number of cycles rename is blocking 351system.cpu.rename.serializeStallCycles 11010468 # count of cycles rename stalled for serializing inst 352system.cpu.rename.RunCycles 159557932 # Number of cycles rename is running 353system.cpu.rename.UnblockCycles 12450994 # Number of cycles rename is unblocking 354system.cpu.rename.RenamedInsts 834052267 # Number of instructions processed by rename 355system.cpu.rename.ROBFullEvents 19515 # Number of times rename has blocked due to ROB full 356system.cpu.rename.IQFullEvents 5867687 # Number of times rename has blocked due to IQ full 357system.cpu.rename.LSQFullEvents 4751018 # Number of times rename has blocked due to LSQ full 358system.cpu.rename.FullRegisterEvents 8643 # Number of times there has been no free registers 359system.cpu.rename.RenamedOperands 995567635 # Number of destination operands rename has renamed 360system.cpu.rename.RenameLookups 1810525606 # Number of register rename lookups that rename has made 361system.cpu.rename.int_rename_lookups 1810524958 # Number of integer rename lookups 362system.cpu.rename.fp_rename_lookups 648 # Number of floating rename lookups 363system.cpu.rename.CommittedMaps 964273740 # Number of HB maps that are committed 364system.cpu.rename.UndoneMaps 31293888 # Number of HB maps that are undone due to squashing 365system.cpu.rename.serializingInsts 458980 # count of serializing insts renamed 366system.cpu.rename.tempSerializingInsts 466833 # count of temporary serializing insts renamed 367system.cpu.rename.skidInsts 28792477 # count of insts added to the skid buffer 368system.cpu.memDep0.insertedLoads 17053482 # Number of loads inserted to the mem dependence unit. 369system.cpu.memDep0.insertedStores 10121038 # Number of stores inserted to the mem dependence unit. 370system.cpu.memDep0.conflictingLoads 1248085 # Number of conflicting loads. 371system.cpu.memDep0.conflictingStores 996765 # Number of conflicting stores. 372system.cpu.iq.iqInstsAdded 827936036 # Number of instructions added to the IQ (excludes non-spec) 373system.cpu.iq.iqNonSpecInstsAdded 1250306 # Number of non-speculative instructions added to the IQ 374system.cpu.iq.iqInstsIssued 823005910 # Number of instructions issued 375system.cpu.iq.iqSquashedInstsIssued 148163 # Number of squashed instructions issued 376system.cpu.iq.iqSquashedInstsExamined 21984013 # Number of squashed instructions iterated over during squash; mainly for profiling 377system.cpu.iq.iqSquashedOperandsExamined 33436004 # Number of squashed operands that are examined and possibly removed from graph 378system.cpu.iq.iqSquashedNonSpecRemoved 197912 # Number of squashed non-spec instructions that were removed 379system.cpu.iq.issued_per_cycle::samples 257808166 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::mean 3.192319 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::stdev 2.383919 # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::0 71353106 27.68% 27.68% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::1 15525279 6.02% 33.70% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::2 10289212 3.99% 37.69% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::3 7463811 2.90% 40.58% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::4 75897283 29.44% 70.02% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::5 3839331 1.49% 71.51% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::6 72507991 28.12% 99.64% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::7 780183 0.30% 99.94% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::8 151970 0.06% 100.00% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::total 257808166 # Number of insts issued each cycle 396system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 397system.cpu.iq.fu_full::IntAlu 363662 34.07% 34.07% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntMult 0 0.00% 34.07% # attempts to use FU when none available 399system.cpu.iq.fu_full::IntDiv 0 0.00% 34.07% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.07% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.07% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.07% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatMult 0 0.00% 34.07% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.07% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.07% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.07% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.07% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.07% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.07% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.07% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.07% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMult 0 0.00% 34.07% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.07% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShift 0 0.00% 34.07% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.07% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.07% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.07% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.07% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.07% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.07% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.07% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.07% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.07% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.07% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.07% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemRead 553259 51.83% 85.89% # attempts to use FU when none available 427system.cpu.iq.fu_full::MemWrite 150581 14.11% 100.00% # attempts to use FU when none available 428system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 429system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 430system.cpu.iq.FU_type_0::No_OpClass 310965 0.04% 0.04% # Type of FU issued 431system.cpu.iq.FU_type_0::IntAlu 795485356 96.66% 96.69% # Type of FU issued 432system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued 433system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued 460system.cpu.iq.FU_type_0::MemRead 17833485 2.17% 98.86% # Type of FU issued 461system.cpu.iq.FU_type_0::MemWrite 9376104 1.14% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 464system.cpu.iq.FU_type_0::total 823005910 # Type of FU issued 465system.cpu.iq.rate 1.836586 # Inst issue rate 466system.cpu.iq.fu_busy_cnt 1067502 # FU busy when requested 467system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) 468system.cpu.iq.int_inst_queue_reads 1905165811 # Number of integer instruction queue reads 469system.cpu.iq.int_inst_queue_writes 851180208 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 818537057 # Number of integer instruction queue wakeup accesses 471system.cpu.iq.fp_inst_queue_reads 213 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 302 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 58 # Number of floating instruction queue wakeup accesses 474system.cpu.iq.int_alu_accesses 823762347 # Number of integer alu accesses 475system.cpu.iq.fp_alu_accesses 100 # Number of floating point alu accesses 476system.cpu.iew.lsq.thread0.forwLoads 1638684 # Number of loads that had data forwarded from stores 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 478system.cpu.iew.lsq.thread0.squashedLoads 3078529 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 22784 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 11411 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 1710138 # Number of stores squashed 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 484system.cpu.iew.lsq.thread0.rescheduledLoads 1932419 # Number of loads that were rescheduled 485system.cpu.iew.lsq.thread0.cacheBlocked 12218 # Number of times an access to memory failed due to the cache being blocked 486system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 487system.cpu.iew.iewSquashCycles 3552885 # Number of cycles IEW is squashing 488system.cpu.iew.iewBlockCycles 26109999 # Number of cycles IEW is blocking 489system.cpu.iew.iewUnblockCycles 2115264 # Number of cycles IEW is unblocking 490system.cpu.iew.iewDispatchedInsts 829186342 # Number of instructions dispatched to IQ 491system.cpu.iew.iewDispSquashedInsts 321096 # Number of squashed instructions skipped by dispatch 492system.cpu.iew.iewDispLoadInsts 17053482 # Number of dispatched load instructions 493system.cpu.iew.iewDispStoreInsts 10121038 # Number of dispatched store instructions 494system.cpu.iew.iewDispNonSpecInsts 718511 # Number of dispatched non-speculative instructions 495system.cpu.iew.iewIQFullEvents 1615692 # Number of times the IQ has become full, causing a stall 496system.cpu.iew.iewLSQFullEvents 10262 # Number of times the LSQ has become full, causing a stall 497system.cpu.iew.memOrderViolationEvents 11411 # Number of memory order violations 498system.cpu.iew.predictedTakenIncorrect 648780 # Number of branches that were predicted taken incorrectly 499system.cpu.iew.predictedNotTakenIncorrect 593291 # Number of branches that were predicted not taken incorrectly 500system.cpu.iew.branchMispredicts 1242071 # Number of branch mispredicts detected at execute 501system.cpu.iew.iewExecutedInsts 821133450 # Number of executed instructions 502system.cpu.iew.iewExecLoadInsts 17423083 # Number of load instructions executed 503system.cpu.iew.iewExecSquashedInsts 1872459 # Number of squashed instructions skipped in execute 504system.cpu.iew.exec_swp 0 # number of swp insts executed 505system.cpu.iew.exec_nop 0 # number of nop insts executed 506system.cpu.iew.exec_refs 26567058 # number of memory reference insts executed 507system.cpu.iew.exec_branches 83190955 # Number of branches executed 508system.cpu.iew.exec_stores 9143975 # Number of stores executed 509system.cpu.iew.exec_rate 1.832407 # Inst execution rate 510system.cpu.iew.wb_sent 820672114 # cumulative count of insts sent to commit 511system.cpu.iew.wb_count 818537115 # cumulative count of insts written-back 512system.cpu.iew.wb_producers 639752264 # num instructions producing a value 513system.cpu.iew.wb_consumers 1045484939 # num instructions consuming a value 514system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 515system.cpu.iew.wb_rate 1.826614 # insts written-back per cycle 516system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back 517system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 518system.cpu.commit.commitSquashedInsts 22773726 # The number of squashed insts skipped by commit 519system.cpu.commit.commitNonSpecStalls 1052392 # The number of times commit has been forced to stall to communicate backwards 520system.cpu.commit.branchMispredicts 1110510 # The number of times a branch was mispredicted 521system.cpu.commit.committed_per_cycle::samples 254255281 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::mean 3.171240 # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::stdev 2.853929 # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::0 82490050 32.44% 32.44% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::1 11810591 4.65% 37.09% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::2 3912535 1.54% 38.63% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::3 74936309 29.47% 68.10% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::4 2436608 0.96% 69.06% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::5 1481517 0.58% 69.64% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::6 940613 0.37% 70.01% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::7 70914138 27.89% 97.90% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::8 5332920 2.10% 100.00% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::total 254255281 # Number of insts commited each cycle 538system.cpu.commit.committedInsts 407895398 # Number of instructions committed 539system.cpu.commit.committedOps 806304609 # Number of ops (including micro ops) committed 540system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 541system.cpu.commit.refs 22385850 # Number of memory references committed 542system.cpu.commit.loads 13974950 # Number of loads committed 543system.cpu.commit.membars 473369 # Number of memory barriers committed 544system.cpu.commit.branches 82185287 # Number of branches committed 545system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 546system.cpu.commit.int_insts 735250581 # Number of committed integer instructions. 547system.cpu.commit.function_calls 0 # Number of function calls committed. 548system.cpu.commit.bw_lim_events 5332920 # number cycles where commit BW limit reached 549system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 550system.cpu.rob.rob_reads 1077922480 # The number of ROB reads 551system.cpu.rob.rob_writes 1661728217 # The number of ROB writes 552system.cpu.timesIdled 1219694 # Number of times that the entire CPU went into an idle state and unscheduled itself 553system.cpu.idleCycles 190309117 # Total number of cycles that the CPU has spent unscheduled due to idling 554system.cpu.quiesceCycles 9825609154 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 555system.cpu.committedInsts 407895398 # Number of Instructions Simulated 556system.cpu.committedOps 806304609 # Number of Ops (including micro ops) Simulated 557system.cpu.committedInsts_total 407895398 # Number of Instructions Simulated 558system.cpu.cpi 1.098608 # CPI: Cycles Per Instruction 559system.cpu.cpi_total 1.098608 # CPI: Total CPI of All Threads 560system.cpu.ipc 0.910243 # IPC: Instructions Per Cycle 561system.cpu.ipc_total 0.910243 # IPC: Total IPC of All Threads 562system.cpu.int_regfile_reads 1506572228 # number of integer regfile reads 563system.cpu.int_regfile_writes 976715078 # number of integer regfile writes 564system.cpu.fp_regfile_reads 58 # number of floating regfile reads 565system.cpu.misc_regfile_reads 264599077 # number of misc regfile reads 566system.cpu.misc_regfile_writes 402085 # number of misc regfile writes 567system.cpu.icache.replacements 1045531 # number of replacements 568system.cpu.icache.tagsinuse 510.125027 # Cycle average of tags in use 569system.cpu.icache.total_refs 7898981 # Total number of references to valid blocks. 570system.cpu.icache.sampled_refs 1046043 # Sample count of references to valid blocks. 571system.cpu.icache.avg_refs 7.551297 # Average number of references to valid blocks. 572system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. 573system.cpu.icache.occ_blocks::cpu.inst 510.125027 # Average occupied blocks per requestor 574system.cpu.icache.occ_percent::cpu.inst 0.996338 # Average percentage of cache occupancy 575system.cpu.icache.occ_percent::total 0.996338 # Average percentage of cache occupancy 576system.cpu.icache.ReadReq_hits::cpu.inst 7898981 # number of ReadReq hits 577system.cpu.icache.ReadReq_hits::total 7898981 # number of ReadReq hits 578system.cpu.icache.demand_hits::cpu.inst 7898981 # number of demand (read+write) hits 579system.cpu.icache.demand_hits::total 7898981 # number of demand (read+write) hits 580system.cpu.icache.overall_hits::cpu.inst 7898981 # number of overall hits 581system.cpu.icache.overall_hits::total 7898981 # number of overall hits 582system.cpu.icache.ReadReq_misses::cpu.inst 1108941 # number of ReadReq misses 583system.cpu.icache.ReadReq_misses::total 1108941 # number of ReadReq misses 584system.cpu.icache.demand_misses::cpu.inst 1108941 # number of demand (read+write) misses 585system.cpu.icache.demand_misses::total 1108941 # number of demand (read+write) misses 586system.cpu.icache.overall_misses::cpu.inst 1108941 # number of overall misses 587system.cpu.icache.overall_misses::total 1108941 # number of overall misses 588system.cpu.icache.ReadReq_miss_latency::cpu.inst 15254214993 # number of ReadReq miss cycles 589system.cpu.icache.ReadReq_miss_latency::total 15254214993 # number of ReadReq miss cycles 590system.cpu.icache.demand_miss_latency::cpu.inst 15254214993 # number of demand (read+write) miss cycles 591system.cpu.icache.demand_miss_latency::total 15254214993 # number of demand (read+write) miss cycles 592system.cpu.icache.overall_miss_latency::cpu.inst 15254214993 # number of overall miss cycles 593system.cpu.icache.overall_miss_latency::total 15254214993 # number of overall miss cycles 594system.cpu.icache.ReadReq_accesses::cpu.inst 9007922 # number of ReadReq accesses(hits+misses) 595system.cpu.icache.ReadReq_accesses::total 9007922 # number of ReadReq accesses(hits+misses) 596system.cpu.icache.demand_accesses::cpu.inst 9007922 # number of demand (read+write) accesses 597system.cpu.icache.demand_accesses::total 9007922 # number of demand (read+write) accesses 598system.cpu.icache.overall_accesses::cpu.inst 9007922 # number of overall (read+write) accesses 599system.cpu.icache.overall_accesses::total 9007922 # number of overall (read+write) accesses 600system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123107 # miss rate for ReadReq accesses 601system.cpu.icache.ReadReq_miss_rate::total 0.123107 # miss rate for ReadReq accesses 602system.cpu.icache.demand_miss_rate::cpu.inst 0.123107 # miss rate for demand accesses 603system.cpu.icache.demand_miss_rate::total 0.123107 # miss rate for demand accesses 604system.cpu.icache.overall_miss_rate::cpu.inst 0.123107 # miss rate for overall accesses 605system.cpu.icache.overall_miss_rate::total 0.123107 # miss rate for overall accesses 606system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13755.659673 # average ReadReq miss latency 607system.cpu.icache.ReadReq_avg_miss_latency::total 13755.659673 # average ReadReq miss latency 608system.cpu.icache.demand_avg_miss_latency::cpu.inst 13755.659673 # average overall miss latency 609system.cpu.icache.demand_avg_miss_latency::total 13755.659673 # average overall miss latency 610system.cpu.icache.overall_avg_miss_latency::cpu.inst 13755.659673 # average overall miss latency 611system.cpu.icache.overall_avg_miss_latency::total 13755.659673 # average overall miss latency 612system.cpu.icache.blocked_cycles::no_mshrs 11697 # number of cycles access was blocked 613system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 614system.cpu.icache.blocked::no_mshrs 280 # number of cycles access was blocked 615system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 616system.cpu.icache.avg_blocked_cycles::no_mshrs 41.775000 # average number of cycles each access was blocked 617system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 618system.cpu.icache.fast_writes 0 # number of fast writes performed 619system.cpu.icache.cache_copies 0 # number of cache copies performed 620system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60573 # number of ReadReq MSHR hits 621system.cpu.icache.ReadReq_mshr_hits::total 60573 # number of ReadReq MSHR hits 622system.cpu.icache.demand_mshr_hits::cpu.inst 60573 # number of demand (read+write) MSHR hits 623system.cpu.icache.demand_mshr_hits::total 60573 # number of demand (read+write) MSHR hits 624system.cpu.icache.overall_mshr_hits::cpu.inst 60573 # number of overall MSHR hits 625system.cpu.icache.overall_mshr_hits::total 60573 # number of overall MSHR hits 626system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048368 # number of ReadReq MSHR misses 627system.cpu.icache.ReadReq_mshr_misses::total 1048368 # number of ReadReq MSHR misses 628system.cpu.icache.demand_mshr_misses::cpu.inst 1048368 # number of demand (read+write) MSHR misses 629system.cpu.icache.demand_mshr_misses::total 1048368 # number of demand (read+write) MSHR misses 630system.cpu.icache.overall_mshr_misses::cpu.inst 1048368 # number of overall MSHR misses 631system.cpu.icache.overall_mshr_misses::total 1048368 # number of overall MSHR misses 632system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12562155993 # number of ReadReq MSHR miss cycles 633system.cpu.icache.ReadReq_mshr_miss_latency::total 12562155993 # number of ReadReq MSHR miss cycles 634system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12562155993 # number of demand (read+write) MSHR miss cycles 635system.cpu.icache.demand_mshr_miss_latency::total 12562155993 # number of demand (read+write) MSHR miss cycles 636system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12562155993 # number of overall MSHR miss cycles 637system.cpu.icache.overall_mshr_miss_latency::total 12562155993 # number of overall MSHR miss cycles 638system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116383 # mshr miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116383 # mshr miss rate for ReadReq accesses 640system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116383 # mshr miss rate for demand accesses 641system.cpu.icache.demand_mshr_miss_rate::total 0.116383 # mshr miss rate for demand accesses 642system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116383 # mshr miss rate for overall accesses 643system.cpu.icache.overall_mshr_miss_rate::total 0.116383 # mshr miss rate for overall accesses 644system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11982.582445 # average ReadReq mshr miss latency 645system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11982.582445 # average ReadReq mshr miss latency 646system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11982.582445 # average overall mshr miss latency 647system.cpu.icache.demand_avg_mshr_miss_latency::total 11982.582445 # average overall mshr miss latency 648system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11982.582445 # average overall mshr miss latency 649system.cpu.icache.overall_avg_mshr_miss_latency::total 11982.582445 # average overall mshr miss latency 650system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 651system.cpu.itb_walker_cache.replacements 9623 # number of replacements 652system.cpu.itb_walker_cache.tagsinuse 6.015619 # Cycle average of tags in use 653system.cpu.itb_walker_cache.total_refs 25274 # Total number of references to valid blocks. 654system.cpu.itb_walker_cache.sampled_refs 9637 # Sample count of references to valid blocks. 655system.cpu.itb_walker_cache.avg_refs 2.622600 # Average number of references to valid blocks. 656system.cpu.itb_walker_cache.warmup_cycle 5103989981500 # Cycle when the warmup percentage was hit. 657system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.015619 # Average occupied blocks per requestor 658system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375976 # Average percentage of cache occupancy 659system.cpu.itb_walker_cache.occ_percent::total 0.375976 # Average percentage of cache occupancy 660system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25281 # number of ReadReq hits 661system.cpu.itb_walker_cache.ReadReq_hits::total 25281 # number of ReadReq hits 662system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 663system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 664system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25283 # number of demand (read+write) hits 665system.cpu.itb_walker_cache.demand_hits::total 25283 # number of demand (read+write) hits 666system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25283 # number of overall hits 667system.cpu.itb_walker_cache.overall_hits::total 25283 # number of overall hits 668system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10506 # number of ReadReq misses 669system.cpu.itb_walker_cache.ReadReq_misses::total 10506 # number of ReadReq misses 670system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10506 # number of demand (read+write) misses 671system.cpu.itb_walker_cache.demand_misses::total 10506 # number of demand (read+write) misses 672system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10506 # number of overall misses 673system.cpu.itb_walker_cache.overall_misses::total 10506 # number of overall misses 674system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 117420000 # number of ReadReq miss cycles 675system.cpu.itb_walker_cache.ReadReq_miss_latency::total 117420000 # number of ReadReq miss cycles 676system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 117420000 # number of demand (read+write) miss cycles 677system.cpu.itb_walker_cache.demand_miss_latency::total 117420000 # number of demand (read+write) miss cycles 678system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 117420000 # number of overall miss cycles 679system.cpu.itb_walker_cache.overall_miss_latency::total 117420000 # number of overall miss cycles 680system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 35787 # number of ReadReq accesses(hits+misses) 681system.cpu.itb_walker_cache.ReadReq_accesses::total 35787 # number of ReadReq accesses(hits+misses) 682system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 683system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 684system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 35789 # number of demand (read+write) accesses 685system.cpu.itb_walker_cache.demand_accesses::total 35789 # number of demand (read+write) accesses 686system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 35789 # number of overall (read+write) accesses 687system.cpu.itb_walker_cache.overall_accesses::total 35789 # number of overall (read+write) accesses 688system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.293570 # miss rate for ReadReq accesses 689system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.293570 # miss rate for ReadReq accesses 690system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.293554 # miss rate for demand accesses 691system.cpu.itb_walker_cache.demand_miss_rate::total 0.293554 # miss rate for demand accesses 692system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.293554 # miss rate for overall accesses 693system.cpu.itb_walker_cache.overall_miss_rate::total 0.293554 # miss rate for overall accesses 694system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11176.470588 # average ReadReq miss latency 695system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11176.470588 # average ReadReq miss latency 696system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11176.470588 # average overall miss latency 697system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11176.470588 # average overall miss latency 698system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11176.470588 # average overall miss latency 699system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11176.470588 # average overall miss latency 700system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 701system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 702system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 703system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 704system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 705system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 706system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 707system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 708system.cpu.itb_walker_cache.writebacks::writebacks 1917 # number of writebacks 709system.cpu.itb_walker_cache.writebacks::total 1917 # number of writebacks 710system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10506 # number of ReadReq MSHR misses 711system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10506 # number of ReadReq MSHR misses 712system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10506 # number of demand (read+write) MSHR misses 713system.cpu.itb_walker_cache.demand_mshr_misses::total 10506 # number of demand (read+write) MSHR misses 714system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10506 # number of overall MSHR misses 715system.cpu.itb_walker_cache.overall_mshr_misses::total 10506 # number of overall MSHR misses 716system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96408000 # number of ReadReq MSHR miss cycles 717system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96408000 # number of ReadReq MSHR miss cycles 718system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96408000 # number of demand (read+write) MSHR miss cycles 719system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96408000 # number of demand (read+write) MSHR miss cycles 720system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96408000 # number of overall MSHR miss cycles 721system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96408000 # number of overall MSHR miss cycles 722system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.293570 # mshr miss rate for ReadReq accesses 723system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.293570 # mshr miss rate for ReadReq accesses 724system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.293554 # mshr miss rate for demand accesses 725system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.293554 # mshr miss rate for demand accesses 726system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.293554 # mshr miss rate for overall accesses 727system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.293554 # mshr miss rate for overall accesses 728system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average ReadReq mshr miss latency 729system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9176.470588 # average ReadReq mshr miss latency 730system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average overall mshr miss latency 731system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9176.470588 # average overall mshr miss latency 732system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average overall mshr miss latency 733system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9176.470588 # average overall mshr miss latency 734system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 735system.cpu.dtb_walker_cache.replacements 107366 # number of replacements 736system.cpu.dtb_walker_cache.tagsinuse 12.959117 # Cycle average of tags in use 737system.cpu.dtb_walker_cache.total_refs 135123 # Total number of references to valid blocks. 738system.cpu.dtb_walker_cache.sampled_refs 107381 # Sample count of references to valid blocks. 739system.cpu.dtb_walker_cache.avg_refs 1.258351 # Average number of references to valid blocks. 740system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit. 741system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.959117 # Average occupied blocks per requestor 742system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809945 # Average percentage of cache occupancy 743system.cpu.dtb_walker_cache.occ_percent::total 0.809945 # Average percentage of cache occupancy 744system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135139 # number of ReadReq hits 745system.cpu.dtb_walker_cache.ReadReq_hits::total 135139 # number of ReadReq hits 746system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135139 # number of demand (read+write) hits 747system.cpu.dtb_walker_cache.demand_hits::total 135139 # number of demand (read+write) hits 748system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135139 # number of overall hits 749system.cpu.dtb_walker_cache.overall_hits::total 135139 # number of overall hits 750system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108408 # number of ReadReq misses 751system.cpu.dtb_walker_cache.ReadReq_misses::total 108408 # number of ReadReq misses 752system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108408 # number of demand (read+write) misses 753system.cpu.dtb_walker_cache.demand_misses::total 108408 # number of demand (read+write) misses 754system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108408 # number of overall misses 755system.cpu.dtb_walker_cache.overall_misses::total 108408 # number of overall misses 756system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1365628000 # number of ReadReq miss cycles 757system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1365628000 # number of ReadReq miss cycles 758system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1365628000 # number of demand (read+write) miss cycles 759system.cpu.dtb_walker_cache.demand_miss_latency::total 1365628000 # number of demand (read+write) miss cycles 760system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1365628000 # number of overall miss cycles 761system.cpu.dtb_walker_cache.overall_miss_latency::total 1365628000 # number of overall miss cycles 762system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243547 # number of ReadReq accesses(hits+misses) 763system.cpu.dtb_walker_cache.ReadReq_accesses::total 243547 # number of ReadReq accesses(hits+misses) 764system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243547 # number of demand (read+write) accesses 765system.cpu.dtb_walker_cache.demand_accesses::total 243547 # number of demand (read+write) accesses 766system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243547 # number of overall (read+write) accesses 767system.cpu.dtb_walker_cache.overall_accesses::total 243547 # number of overall (read+write) accesses 768system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.445121 # miss rate for ReadReq accesses 769system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.445121 # miss rate for ReadReq accesses 770system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.445121 # miss rate for demand accesses 771system.cpu.dtb_walker_cache.demand_miss_rate::total 0.445121 # miss rate for demand accesses 772system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.445121 # miss rate for overall accesses 773system.cpu.dtb_walker_cache.overall_miss_rate::total 0.445121 # miss rate for overall accesses 774system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12597.114604 # average ReadReq miss latency 775system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12597.114604 # average ReadReq miss latency 776system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12597.114604 # average overall miss latency 777system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12597.114604 # average overall miss latency 778system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12597.114604 # average overall miss latency 779system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12597.114604 # average overall miss latency 780system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 781system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 782system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 783system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 784system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 785system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 786system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 787system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 788system.cpu.dtb_walker_cache.writebacks::writebacks 35267 # number of writebacks 789system.cpu.dtb_walker_cache.writebacks::total 35267 # number of writebacks 790system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108408 # number of ReadReq MSHR misses 791system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108408 # number of ReadReq MSHR misses 792system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108408 # number of demand (read+write) MSHR misses 793system.cpu.dtb_walker_cache.demand_mshr_misses::total 108408 # number of demand (read+write) MSHR misses 794system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108408 # number of overall MSHR misses 795system.cpu.dtb_walker_cache.overall_mshr_misses::total 108408 # number of overall MSHR misses 796system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of ReadReq MSHR miss cycles 797system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1148812000 # number of ReadReq MSHR miss cycles 798system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of demand (read+write) MSHR miss cycles 799system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1148812000 # number of demand (read+write) MSHR miss cycles 800system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of overall MSHR miss cycles 801system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1148812000 # number of overall MSHR miss cycles 802system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for ReadReq accesses 803system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.445121 # mshr miss rate for ReadReq accesses 804system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for demand accesses 805system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.445121 # mshr miss rate for demand accesses 806system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for overall accesses 807system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.445121 # mshr miss rate for overall accesses 808system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604 # average ReadReq mshr miss latency 809system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10597.114604 # average ReadReq mshr miss latency 810system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604 # average overall mshr miss latency 811system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10597.114604 # average overall mshr miss latency 812system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604 # average overall mshr miss latency 813system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10597.114604 # average overall mshr miss latency 814system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 815system.cpu.dcache.replacements 1660204 # number of replacements 816system.cpu.dcache.tagsinuse 511.993130 # Cycle average of tags in use 817system.cpu.dcache.total_refs 19074634 # Total number of references to valid blocks. 818system.cpu.dcache.sampled_refs 1660716 # Sample count of references to valid blocks. 819system.cpu.dcache.avg_refs 11.485789 # Average number of references to valid blocks. 820system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. 821system.cpu.dcache.occ_blocks::cpu.data 511.993130 # Average occupied blocks per requestor 822system.cpu.dcache.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy 823system.cpu.dcache.occ_percent::total 0.999987 # Average percentage of cache occupancy 824system.cpu.dcache.ReadReq_hits::cpu.data 10985848 # number of ReadReq hits 825system.cpu.dcache.ReadReq_hits::total 10985848 # number of ReadReq hits 826system.cpu.dcache.WriteReq_hits::cpu.data 8083807 # number of WriteReq hits 827system.cpu.dcache.WriteReq_hits::total 8083807 # number of WriteReq hits 828system.cpu.dcache.demand_hits::cpu.data 19069655 # number of demand (read+write) hits 829system.cpu.dcache.demand_hits::total 19069655 # number of demand (read+write) hits 830system.cpu.dcache.overall_hits::cpu.data 19069655 # number of overall hits 831system.cpu.dcache.overall_hits::total 19069655 # number of overall hits 832system.cpu.dcache.ReadReq_misses::cpu.data 2236198 # number of ReadReq misses 833system.cpu.dcache.ReadReq_misses::total 2236198 # number of ReadReq misses 834system.cpu.dcache.WriteReq_misses::cpu.data 317897 # number of WriteReq misses 835system.cpu.dcache.WriteReq_misses::total 317897 # number of WriteReq misses 836system.cpu.dcache.demand_misses::cpu.data 2554095 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 2554095 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 2554095 # number of overall misses 839system.cpu.dcache.overall_misses::total 2554095 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 32136809500 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 32136809500 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 9657348993 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 9657348993 # number of WriteReq miss cycles 844system.cpu.dcache.demand_miss_latency::cpu.data 41794158493 # number of demand (read+write) miss cycles 845system.cpu.dcache.demand_miss_latency::total 41794158493 # number of demand (read+write) miss cycles 846system.cpu.dcache.overall_miss_latency::cpu.data 41794158493 # number of overall miss cycles 847system.cpu.dcache.overall_miss_latency::total 41794158493 # number of overall miss cycles 848system.cpu.dcache.ReadReq_accesses::cpu.data 13222046 # number of ReadReq accesses(hits+misses) 849system.cpu.dcache.ReadReq_accesses::total 13222046 # number of ReadReq accesses(hits+misses) 850system.cpu.dcache.WriteReq_accesses::cpu.data 8401704 # number of WriteReq accesses(hits+misses) 851system.cpu.dcache.WriteReq_accesses::total 8401704 # number of WriteReq accesses(hits+misses) 852system.cpu.dcache.demand_accesses::cpu.data 21623750 # number of demand (read+write) accesses 853system.cpu.dcache.demand_accesses::total 21623750 # number of demand (read+write) accesses 854system.cpu.dcache.overall_accesses::cpu.data 21623750 # number of overall (read+write) accesses 855system.cpu.dcache.overall_accesses::total 21623750 # number of overall (read+write) accesses 856system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169126 # miss rate for ReadReq accesses 857system.cpu.dcache.ReadReq_miss_rate::total 0.169126 # miss rate for ReadReq accesses 858system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037837 # miss rate for WriteReq accesses 859system.cpu.dcache.WriteReq_miss_rate::total 0.037837 # miss rate for WriteReq accesses 860system.cpu.dcache.demand_miss_rate::cpu.data 0.118115 # miss rate for demand accesses 861system.cpu.dcache.demand_miss_rate::total 0.118115 # miss rate for demand accesses 862system.cpu.dcache.overall_miss_rate::cpu.data 0.118115 # miss rate for overall accesses 863system.cpu.dcache.overall_miss_rate::total 0.118115 # miss rate for overall accesses 864system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14371.182471 # average ReadReq miss latency 865system.cpu.dcache.ReadReq_avg_miss_latency::total 14371.182471 # average ReadReq miss latency 866system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30378.861685 # average WriteReq miss latency 867system.cpu.dcache.WriteReq_avg_miss_latency::total 30378.861685 # average WriteReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 16363.588078 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 16363.588078 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 16363.588078 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 16363.588078 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 398738 # number of cycles access was blocked 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 874system.cpu.dcache.blocked::no_mshrs 42519 # number of cycles access was blocked 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.377878 # average number of cycles each access was blocked 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed 880system.cpu.dcache.writebacks::writebacks 1561580 # number of writebacks 881system.cpu.dcache.writebacks::total 1561580 # number of writebacks 882system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863817 # number of ReadReq MSHR hits 883system.cpu.dcache.ReadReq_mshr_hits::total 863817 # number of ReadReq MSHR hits 884system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25014 # number of WriteReq MSHR hits 885system.cpu.dcache.WriteReq_mshr_hits::total 25014 # number of WriteReq MSHR hits 886system.cpu.dcache.demand_mshr_hits::cpu.data 888831 # number of demand (read+write) MSHR hits 887system.cpu.dcache.demand_mshr_hits::total 888831 # number of demand (read+write) MSHR hits 888system.cpu.dcache.overall_mshr_hits::cpu.data 888831 # number of overall MSHR hits 889system.cpu.dcache.overall_mshr_hits::total 888831 # number of overall MSHR hits 890system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1372381 # number of ReadReq MSHR misses 891system.cpu.dcache.ReadReq_mshr_misses::total 1372381 # number of ReadReq MSHR misses 892system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292883 # number of WriteReq MSHR misses 893system.cpu.dcache.WriteReq_mshr_misses::total 292883 # number of WriteReq MSHR misses 894system.cpu.dcache.demand_mshr_misses::cpu.data 1665264 # number of demand (read+write) MSHR misses 895system.cpu.dcache.demand_mshr_misses::total 1665264 # number of demand (read+write) MSHR misses 896system.cpu.dcache.overall_mshr_misses::cpu.data 1665264 # number of overall MSHR misses 897system.cpu.dcache.overall_mshr_misses::total 1665264 # number of overall MSHR misses 898system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17480696000 # number of ReadReq MSHR miss cycles 899system.cpu.dcache.ReadReq_mshr_miss_latency::total 17480696000 # number of ReadReq MSHR miss cycles 900system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8813584993 # number of WriteReq MSHR miss cycles 901system.cpu.dcache.WriteReq_mshr_miss_latency::total 8813584993 # number of WriteReq MSHR miss cycles 902system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26294280993 # number of demand (read+write) MSHR miss cycles 903system.cpu.dcache.demand_mshr_miss_latency::total 26294280993 # number of demand (read+write) MSHR miss cycles 904system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26294280993 # number of overall MSHR miss cycles 905system.cpu.dcache.overall_mshr_miss_latency::total 26294280993 # number of overall MSHR miss cycles 906system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97294541500 # number of ReadReq MSHR uncacheable cycles 907system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97294541500 # number of ReadReq MSHR uncacheable cycles 908system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2465874000 # number of WriteReq MSHR uncacheable cycles 909system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2465874000 # number of WriteReq MSHR uncacheable cycles 910system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99760415500 # number of overall MSHR uncacheable cycles 911system.cpu.dcache.overall_mshr_uncacheable_latency::total 99760415500 # number of overall MSHR uncacheable cycles 912system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103795 # mshr miss rate for ReadReq accesses 913system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103795 # mshr miss rate for ReadReq accesses 914system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034860 # mshr miss rate for WriteReq accesses 915system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034860 # mshr miss rate for WriteReq accesses 916system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077011 # mshr miss rate for demand accesses 917system.cpu.dcache.demand_mshr_miss_rate::total 0.077011 # mshr miss rate for demand accesses 918system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077011 # mshr miss rate for overall accesses 919system.cpu.dcache.overall_mshr_miss_rate::total 0.077011 # mshr miss rate for overall accesses 920system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12737.494908 # average ReadReq mshr miss latency 921system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12737.494908 # average ReadReq mshr miss latency 922system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30092.511320 # average WriteReq mshr miss latency 923system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30092.511320 # average WriteReq mshr miss latency 924system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15789.857340 # average overall mshr miss latency 925system.cpu.dcache.demand_avg_mshr_miss_latency::total 15789.857340 # average overall mshr miss latency 926system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15789.857340 # average overall mshr miss latency 927system.cpu.dcache.overall_avg_mshr_miss_latency::total 15789.857340 # average overall mshr miss latency 928system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 929system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 930system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 931system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 932system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 933system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 934system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 935system.cpu.l2cache.replacements 113491 # number of replacements 936system.cpu.l2cache.tagsinuse 64842.078955 # Cycle average of tags in use 937system.cpu.l2cache.total_refs 3927958 # Total number of references to valid blocks. 938system.cpu.l2cache.sampled_refs 177583 # Sample count of references to valid blocks. 939system.cpu.l2cache.avg_refs 22.118998 # Average number of references to valid blocks. 940system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 941system.cpu.l2cache.occ_blocks::writebacks 50032.816197 # Average occupied blocks per requestor 942system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.886318 # Average occupied blocks per requestor 943system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133448 # Average occupied blocks per requestor 944system.cpu.l2cache.occ_blocks::cpu.inst 3280.359245 # Average occupied blocks per requestor 945system.cpu.l2cache.occ_blocks::cpu.data 11517.883747 # Average occupied blocks per requestor 946system.cpu.l2cache.occ_percent::writebacks 0.763440 # Average percentage of cache occupancy 947system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000166 # Average percentage of cache occupancy 948system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 949system.cpu.l2cache.occ_percent::cpu.inst 0.050054 # Average percentage of cache occupancy 950system.cpu.l2cache.occ_percent::cpu.data 0.175749 # Average percentage of cache occupancy 951system.cpu.l2cache.occ_percent::total 0.989412 # Average percentage of cache occupancy 952system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 101572 # number of ReadReq hits 953system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8137 # number of ReadReq hits 954system.cpu.l2cache.ReadReq_hits::cpu.inst 1029165 # number of ReadReq hits 955system.cpu.l2cache.ReadReq_hits::cpu.data 1334330 # number of ReadReq hits 956system.cpu.l2cache.ReadReq_hits::total 2473204 # number of ReadReq hits 957system.cpu.l2cache.Writeback_hits::writebacks 1598764 # number of Writeback hits 958system.cpu.l2cache.Writeback_hits::total 1598764 # number of Writeback hits 959system.cpu.l2cache.UpgradeReq_hits::cpu.data 341 # number of UpgradeReq hits 960system.cpu.l2cache.UpgradeReq_hits::total 341 # number of UpgradeReq hits 961system.cpu.l2cache.ReadExReq_hits::cpu.data 156095 # number of ReadExReq hits 962system.cpu.l2cache.ReadExReq_hits::total 156095 # number of ReadExReq hits 963system.cpu.l2cache.demand_hits::cpu.dtb.walker 101572 # number of demand (read+write) hits 964system.cpu.l2cache.demand_hits::cpu.itb.walker 8137 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.inst 1029165 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::cpu.data 1490425 # number of demand (read+write) hits 967system.cpu.l2cache.demand_hits::total 2629299 # number of demand (read+write) hits 968system.cpu.l2cache.overall_hits::cpu.dtb.walker 101572 # number of overall hits 969system.cpu.l2cache.overall_hits::cpu.itb.walker 8137 # number of overall hits 970system.cpu.l2cache.overall_hits::cpu.inst 1029165 # number of overall hits 971system.cpu.l2cache.overall_hits::cpu.data 1490425 # number of overall hits 972system.cpu.l2cache.overall_hits::total 2629299 # number of overall hits 973system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 47 # number of ReadReq misses 974system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses 975system.cpu.l2cache.ReadReq_misses::cpu.inst 16828 # number of ReadReq misses 976system.cpu.l2cache.ReadReq_misses::cpu.data 36875 # number of ReadReq misses 977system.cpu.l2cache.ReadReq_misses::total 53756 # number of ReadReq misses 978system.cpu.l2cache.UpgradeReq_misses::cpu.data 3686 # number of UpgradeReq misses 979system.cpu.l2cache.UpgradeReq_misses::total 3686 # number of UpgradeReq misses 980system.cpu.l2cache.ReadExReq_misses::cpu.data 132834 # number of ReadExReq misses 981system.cpu.l2cache.ReadExReq_misses::total 132834 # number of ReadExReq misses 982system.cpu.l2cache.demand_misses::cpu.dtb.walker 47 # number of demand (read+write) misses 983system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 984system.cpu.l2cache.demand_misses::cpu.inst 16828 # number of demand (read+write) misses 985system.cpu.l2cache.demand_misses::cpu.data 169709 # number of demand (read+write) misses 986system.cpu.l2cache.demand_misses::total 186590 # number of demand (read+write) misses 987system.cpu.l2cache.overall_misses::cpu.dtb.walker 47 # number of overall misses 988system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses 989system.cpu.l2cache.overall_misses::cpu.inst 16828 # number of overall misses 990system.cpu.l2cache.overall_misses::cpu.data 169709 # number of overall misses 991system.cpu.l2cache.overall_misses::total 186590 # number of overall misses 992system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6046500 # number of ReadReq miss cycles 993system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles 994system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1168943500 # number of ReadReq miss cycles 995system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2535282000 # number of ReadReq miss cycles 996system.cpu.l2cache.ReadReq_miss_latency::total 3710661500 # number of ReadReq miss cycles 997system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17110500 # number of UpgradeReq miss cycles 998system.cpu.l2cache.UpgradeReq_miss_latency::total 17110500 # number of UpgradeReq miss cycles 999system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6867635000 # number of ReadExReq miss cycles 1000system.cpu.l2cache.ReadExReq_miss_latency::total 6867635000 # number of ReadExReq miss cycles 1001system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6046500 # number of demand (read+write) miss cycles 1002system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles 1003system.cpu.l2cache.demand_miss_latency::cpu.inst 1168943500 # number of demand (read+write) miss cycles 1004system.cpu.l2cache.demand_miss_latency::cpu.data 9402917000 # number of demand (read+write) miss cycles 1005system.cpu.l2cache.demand_miss_latency::total 10578296500 # number of demand (read+write) miss cycles 1006system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6046500 # number of overall miss cycles 1007system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles 1008system.cpu.l2cache.overall_miss_latency::cpu.inst 1168943500 # number of overall miss cycles 1009system.cpu.l2cache.overall_miss_latency::cpu.data 9402917000 # number of overall miss cycles 1010system.cpu.l2cache.overall_miss_latency::total 10578296500 # number of overall miss cycles 1011system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 101619 # number of ReadReq accesses(hits+misses) 1012system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8143 # number of ReadReq accesses(hits+misses) 1013system.cpu.l2cache.ReadReq_accesses::cpu.inst 1045993 # number of ReadReq accesses(hits+misses) 1014system.cpu.l2cache.ReadReq_accesses::cpu.data 1371205 # number of ReadReq accesses(hits+misses) 1015system.cpu.l2cache.ReadReq_accesses::total 2526960 # number of ReadReq accesses(hits+misses) 1016system.cpu.l2cache.Writeback_accesses::writebacks 1598764 # number of Writeback accesses(hits+misses) 1017system.cpu.l2cache.Writeback_accesses::total 1598764 # number of Writeback accesses(hits+misses) 1018system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4027 # number of UpgradeReq accesses(hits+misses) 1019system.cpu.l2cache.UpgradeReq_accesses::total 4027 # number of UpgradeReq accesses(hits+misses) 1020system.cpu.l2cache.ReadExReq_accesses::cpu.data 288929 # number of ReadExReq accesses(hits+misses) 1021system.cpu.l2cache.ReadExReq_accesses::total 288929 # number of ReadExReq accesses(hits+misses) 1022system.cpu.l2cache.demand_accesses::cpu.dtb.walker 101619 # number of demand (read+write) accesses 1023system.cpu.l2cache.demand_accesses::cpu.itb.walker 8143 # number of demand (read+write) accesses 1024system.cpu.l2cache.demand_accesses::cpu.inst 1045993 # number of demand (read+write) accesses 1025system.cpu.l2cache.demand_accesses::cpu.data 1660134 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::total 2815889 # number of demand (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.dtb.walker 101619 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::cpu.itb.walker 8143 # number of overall (read+write) accesses 1029system.cpu.l2cache.overall_accesses::cpu.inst 1045993 # number of overall (read+write) accesses 1030system.cpu.l2cache.overall_accesses::cpu.data 1660134 # number of overall (read+write) accesses 1031system.cpu.l2cache.overall_accesses::total 2815889 # number of overall (read+write) accesses 1032system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000463 # miss rate for ReadReq accesses 1033system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000737 # miss rate for ReadReq accesses 1034system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016088 # miss rate for ReadReq accesses 1035system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026892 # miss rate for ReadReq accesses 1036system.cpu.l2cache.ReadReq_miss_rate::total 0.021273 # miss rate for ReadReq accesses 1037system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.915322 # miss rate for UpgradeReq accesses 1038system.cpu.l2cache.UpgradeReq_miss_rate::total 0.915322 # miss rate for UpgradeReq accesses 1039system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459746 # miss rate for ReadExReq accesses 1040system.cpu.l2cache.ReadExReq_miss_rate::total 0.459746 # miss rate for ReadExReq accesses 1041system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000463 # miss rate for demand accesses 1042system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000737 # miss rate for demand accesses 1043system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016088 # miss rate for demand accesses 1044system.cpu.l2cache.demand_miss_rate::cpu.data 0.102226 # miss rate for demand accesses 1045system.cpu.l2cache.demand_miss_rate::total 0.066263 # miss rate for demand accesses 1046system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000463 # miss rate for overall accesses 1047system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000737 # miss rate for overall accesses 1048system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016088 # miss rate for overall accesses 1049system.cpu.l2cache.overall_miss_rate::cpu.data 0.102226 # miss rate for overall accesses 1050system.cpu.l2cache.overall_miss_rate::total 0.066263 # miss rate for overall accesses 1051system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 128648.936170 # average ReadReq miss latency 1052system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency 1053system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69464.196577 # average ReadReq miss latency 1054system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68753.410169 # average ReadReq miss latency 1055system.cpu.l2cache.ReadReq_avg_miss_latency::total 69027.857355 # average ReadReq miss latency 1056system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4642.023874 # average UpgradeReq miss latency 1057system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4642.023874 # average UpgradeReq miss latency 1058system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51700.882304 # average ReadExReq miss latency 1059system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51700.882304 # average ReadExReq miss latency 1060system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 128648.936170 # average overall miss latency 1061system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency 1062system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69464.196577 # average overall miss latency 1063system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55406.118709 # average overall miss latency 1064system.cpu.l2cache.demand_avg_miss_latency::total 56692.730050 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 128648.936170 # average overall miss latency 1066system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency 1067system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69464.196577 # average overall miss latency 1068system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55406.118709 # average overall miss latency 1069system.cpu.l2cache.overall_avg_miss_latency::total 56692.730050 # average overall miss latency 1070system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1071system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1072system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1073system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1074system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1075system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1076system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1077system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1078system.cpu.l2cache.writebacks::writebacks 102738 # number of writebacks 1079system.cpu.l2cache.writebacks::total 102738 # number of writebacks 1080system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1081system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1082system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 1083system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1084system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1085system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 1086system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1087system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1088system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits 1089system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 47 # number of ReadReq MSHR misses 1090system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses 1091system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16827 # number of ReadReq MSHR misses 1092system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36874 # number of ReadReq MSHR misses 1093system.cpu.l2cache.ReadReq_mshr_misses::total 53754 # number of ReadReq MSHR misses 1094system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3686 # number of UpgradeReq MSHR misses 1095system.cpu.l2cache.UpgradeReq_mshr_misses::total 3686 # number of UpgradeReq MSHR misses 1096system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132834 # number of ReadExReq MSHR misses 1097system.cpu.l2cache.ReadExReq_mshr_misses::total 132834 # number of ReadExReq MSHR misses 1098system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 47 # number of demand (read+write) MSHR misses 1099system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 1100system.cpu.l2cache.demand_mshr_misses::cpu.inst 16827 # number of demand (read+write) MSHR misses 1101system.cpu.l2cache.demand_mshr_misses::cpu.data 169708 # number of demand (read+write) MSHR misses 1102system.cpu.l2cache.demand_mshr_misses::total 186588 # number of demand (read+write) MSHR misses 1103system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 47 # number of overall MSHR misses 1104system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 1105system.cpu.l2cache.overall_mshr_misses::cpu.inst 16827 # number of overall MSHR misses 1106system.cpu.l2cache.overall_mshr_misses::cpu.data 169708 # number of overall MSHR misses 1107system.cpu.l2cache.overall_mshr_misses::total 186588 # number of overall MSHR misses 1108system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5461043 # number of ReadReq MSHR miss cycles 1109system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles 1110system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 959626979 # number of ReadReq MSHR miss cycles 1111system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2076990471 # number of ReadReq MSHR miss cycles 1112system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3042392748 # number of ReadReq MSHR miss cycles 1113system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37820166 # number of UpgradeReq MSHR miss cycles 1114system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37820166 # number of UpgradeReq MSHR miss cycles 1115system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5229334603 # number of ReadExReq MSHR miss cycles 1116system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5229334603 # number of ReadExReq MSHR miss cycles 1117system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5461043 # number of demand (read+write) MSHR miss cycles 1118system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles 1119system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 959626979 # number of demand (read+write) MSHR miss cycles 1120system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7306325074 # number of demand (read+write) MSHR miss cycles 1121system.cpu.l2cache.demand_mshr_miss_latency::total 8271727351 # number of demand (read+write) MSHR miss cycles 1122system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5461043 # number of overall MSHR miss cycles 1123system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles 1124system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 959626979 # number of overall MSHR miss cycles 1125system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7306325074 # number of overall MSHR miss cycles 1126system.cpu.l2cache.overall_mshr_miss_latency::total 8271727351 # number of overall MSHR miss cycles 1127system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89185441500 # number of ReadReq MSHR uncacheable cycles 1128system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89185441500 # number of ReadReq MSHR uncacheable cycles 1129system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2304074500 # number of WriteReq MSHR uncacheable cycles 1130system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2304074500 # number of WriteReq MSHR uncacheable cycles 1131system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91489516000 # number of overall MSHR uncacheable cycles 1132system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91489516000 # number of overall MSHR uncacheable cycles 1133system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000463 # mshr miss rate for ReadReq accesses 1134system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000737 # mshr miss rate for ReadReq accesses 1135system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016087 # mshr miss rate for ReadReq accesses 1136system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026892 # mshr miss rate for ReadReq accesses 1137system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021272 # mshr miss rate for ReadReq accesses 1138system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.915322 # mshr miss rate for UpgradeReq accesses 1139system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.915322 # mshr miss rate for UpgradeReq accesses 1140system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459746 # mshr miss rate for ReadExReq accesses 1141system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459746 # mshr miss rate for ReadExReq accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000463 # mshr miss rate for demand accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000737 # mshr miss rate for demand accesses 1144system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016087 # mshr miss rate for demand accesses 1145system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102225 # mshr miss rate for demand accesses 1146system.cpu.l2cache.demand_mshr_miss_rate::total 0.066263 # mshr miss rate for demand accesses 1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000463 # mshr miss rate for overall accesses 1148system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000737 # mshr miss rate for overall accesses 1149system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016087 # mshr miss rate for overall accesses 1150system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102225 # mshr miss rate for overall accesses 1151system.cpu.l2cache.overall_mshr_miss_rate::total 0.066263 # mshr miss rate for overall accesses 1152system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255 # average ReadReq mshr miss latency 1153system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency 1154system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57028.999762 # average ReadReq mshr miss latency 1155system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56326.692819 # average ReadReq mshr miss latency 1156system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56598.443800 # average ReadReq mshr miss latency 1157system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10260.489962 # average UpgradeReq mshr miss latency 1158system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10260.489962 # average UpgradeReq mshr miss latency 1159system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39367.440588 # average ReadExReq mshr miss latency 1160system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39367.440588 # average ReadExReq mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255 # average overall mshr miss latency 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency 1163system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57028.999762 # average overall mshr miss latency 1164system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43052.331499 # average overall mshr miss latency 1165system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44331.507659 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255 # average overall mshr miss latency 1167system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency 1168system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57028.999762 # average overall mshr miss latency 1169system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43052.331499 # average overall mshr miss latency 1170system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44331.507659 # average overall mshr miss latency 1171system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1172system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1173system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1174system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1175system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1176system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1177system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1178system.cpu.kern.inst.arm 0 # number of arm instructions executed 1179system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1180 1181---------- End Simulation Statistics ---------- 1182