stats.txt revision 9490:e6a09d97bdc9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.136862 # Number of seconds simulated 4sim_ticks 5136862311000 # Number of ticks simulated 5final_tick 5136862311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 202420 # Simulator instruction rate (inst/s) 8host_op_rate 400133 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2548945395 # Simulator tick rate (ticks/s) 10host_mem_usage 760276 # Number of bytes of host memory used 11host_seconds 2015.29 # Real time elapsed on the host 12sim_insts 407935752 # Number of instructions simulated 13sim_ops 806383618 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2490880 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 1078272 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10788032 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14361024 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1078272 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1078272 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9547840 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9547840 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38920 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 16848 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 168563 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 224391 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 149185 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 149185 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 484903 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 660 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 209909 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2100121 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2795680 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 209909 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 209909 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1858691 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1858691 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1858691 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 484903 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 660 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 209909 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2100121 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4654371 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 224391 # Total number of read requests seen 50system.physmem.writeReqs 149185 # Total number of write requests seen 51system.physmem.cpureqs 388105 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14361024 # Total number of bytes read from memory 53system.physmem.bytesWritten 9547840 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14361024 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9547840 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 135 # Number of read reqs serviced by write Q 57system.physmem.neitherReadNorWrite 3903 # Reqs where no action is needed 58system.physmem.perBankRdReqs::0 14157 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 13127 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 13393 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 16573 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13535 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 12962 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 13580 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 16342 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13760 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 13186 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 13242 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 15501 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 13187 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 12719 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 13259 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 15733 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 9129 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 8570 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 8702 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 11948 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 8746 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 8430 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8914 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 11741 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 8779 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 8505 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 8628 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 10975 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 8406 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 8212 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 8505 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 10995 # Track writes on a per bank basis 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 91system.physmem.numWrRetry 794 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5136862258500 # Total gap between requests 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes 99system.physmem.readPktSize::6 224391 # Categorize read packet sizes 100system.physmem.readPktSize::7 0 # Categorize read packet sizes 101system.physmem.readPktSize::8 0 # Categorize read packet sizes 102system.physmem.writePktSize::0 0 # categorize write packet sizes 103system.physmem.writePktSize::1 0 # categorize write packet sizes 104system.physmem.writePktSize::2 0 # categorize write packet sizes 105system.physmem.writePktSize::3 0 # categorize write packet sizes 106system.physmem.writePktSize::4 0 # categorize write packet sizes 107system.physmem.writePktSize::5 0 # categorize write packet sizes 108system.physmem.writePktSize::6 149979 # categorize write packet sizes 109system.physmem.writePktSize::7 0 # categorize write packet sizes 110system.physmem.writePktSize::8 0 # categorize write packet sizes 111system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 112system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 113system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::6 3903 # categorize neither packet sizes 118system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 120system.physmem.rdQLenPdf::0 173046 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::1 19422 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::2 7578 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::3 3497 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::4 3020 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::5 2415 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::6 1930 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::7 1866 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::8 1777 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::9 1691 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::10 1133 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::11 1016 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::12 933 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::13 874 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::14 828 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::15 817 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::16 915 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::17 867 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::18 384 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::19 221 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 153system.physmem.wrQLenPdf::0 5322 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::1 5660 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::2 6306 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::3 6395 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::4 6433 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::5 6455 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::6 6463 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::7 6468 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::8 6472 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::9 6486 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::10 6486 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::11 6486 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::12 6486 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::13 6486 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::14 6486 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::15 6486 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::16 6486 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::17 6486 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::18 6486 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::19 6486 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::20 6486 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::21 6486 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::22 6486 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::23 1165 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::24 827 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::25 181 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::26 92 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::28 32 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 186system.physmem.totQLat 4730288859 # Total cycles spent in queuing delays 187system.physmem.totMemAccLat 9241012609 # Sum of mem lat for all requests 188system.physmem.totBusLat 1121280000 # Total cycles spent in databus access 189system.physmem.totBankLat 3389443750 # Total cycles spent in bank access 190system.physmem.avgQLat 21093.25 # Average queueing delay per request 191system.physmem.avgBankLat 15114.17 # Average bank access latency per request 192system.physmem.avgBusLat 5000.00 # Average bus latency per request 193system.physmem.avgMemAccLat 41207.43 # Average memory access latency 194system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s 195system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s 196system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s 197system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s 198system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 199system.physmem.busUtil 0.04 # Data bus utilization in percentage 200system.physmem.avgRdQLen 0.00 # Average read queue length over time 201system.physmem.avgWrQLen 12.83 # Average write queue length over time 202system.physmem.readRowHits 193267 # Number of row buffer hits during reads 203system.physmem.writeRowHits 105785 # Number of row buffer hits during writes 204system.physmem.readRowHitRate 86.18 # Row buffer hit rate for reads 205system.physmem.writeRowHitRate 70.91 # Row buffer hit rate for writes 206system.physmem.avgGap 13750514.64 # Average gap between requests 207system.iocache.replacements 47583 # number of replacements 208system.iocache.tagsinuse 0.137403 # Cycle average of tags in use 209system.iocache.total_refs 0 # Total number of references to valid blocks. 210system.iocache.sampled_refs 47599 # Sample count of references to valid blocks. 211system.iocache.avg_refs 0 # Average number of references to valid blocks. 212system.iocache.warmup_cycle 4991910569000 # Cycle when the warmup percentage was hit. 213system.iocache.occ_blocks::pc.south_bridge.ide 0.137403 # Average occupied blocks per requestor 214system.iocache.occ_percent::pc.south_bridge.ide 0.008588 # Average percentage of cache occupancy 215system.iocache.occ_percent::total 0.008588 # Average percentage of cache occupancy 216system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses 217system.iocache.ReadReq_misses::total 912 # number of ReadReq misses 218system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 219system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 220system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses 221system.iocache.demand_misses::total 47632 # number of demand (read+write) misses 222system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses 223system.iocache.overall_misses::total 47632 # number of overall misses 224system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144324932 # number of ReadReq miss cycles 225system.iocache.ReadReq_miss_latency::total 144324932 # number of ReadReq miss cycles 226system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10020383160 # number of WriteReq miss cycles 227system.iocache.WriteReq_miss_latency::total 10020383160 # number of WriteReq miss cycles 228system.iocache.demand_miss_latency::pc.south_bridge.ide 10164708092 # number of demand (read+write) miss cycles 229system.iocache.demand_miss_latency::total 10164708092 # number of demand (read+write) miss cycles 230system.iocache.overall_miss_latency::pc.south_bridge.ide 10164708092 # number of overall miss cycles 231system.iocache.overall_miss_latency::total 10164708092 # number of overall miss cycles 232system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses) 233system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses) 234system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 235system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 236system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses 237system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses 238system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses 239system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses 240system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 241system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 242system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 243system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 244system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 245system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 246system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 247system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 248system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158251.021930 # average ReadReq miss latency 249system.iocache.ReadReq_avg_miss_latency::total 158251.021930 # average ReadReq miss latency 250system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214477.379281 # average WriteReq miss latency 251system.iocache.WriteReq_avg_miss_latency::total 214477.379281 # average WriteReq miss latency 252system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213400.824908 # average overall miss latency 253system.iocache.demand_avg_miss_latency::total 213400.824908 # average overall miss latency 254system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213400.824908 # average overall miss latency 255system.iocache.overall_avg_miss_latency::total 213400.824908 # average overall miss latency 256system.iocache.blocked_cycles::no_mshrs 133472 # number of cycles access was blocked 257system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 258system.iocache.blocked::no_mshrs 12161 # number of cycles access was blocked 259system.iocache.blocked::no_targets 0 # number of cycles access was blocked 260system.iocache.avg_blocked_cycles::no_mshrs 10.975413 # average number of cycles each access was blocked 261system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 262system.iocache.fast_writes 0 # number of fast writes performed 263system.iocache.cache_copies 0 # number of cache copies performed 264system.iocache.writebacks::writebacks 46673 # number of writebacks 265system.iocache.writebacks::total 46673 # number of writebacks 266system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses 267system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses 268system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 269system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 270system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses 271system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses 272system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses 273system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses 274system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96878242 # number of ReadReq MSHR miss cycles 275system.iocache.ReadReq_mshr_miss_latency::total 96878242 # number of ReadReq MSHR miss cycles 276system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7589579568 # number of WriteReq MSHR miss cycles 277system.iocache.WriteReq_mshr_miss_latency::total 7589579568 # number of WriteReq MSHR miss cycles 278system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7686457810 # number of demand (read+write) MSHR miss cycles 279system.iocache.demand_mshr_miss_latency::total 7686457810 # number of demand (read+write) MSHR miss cycles 280system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7686457810 # number of overall MSHR miss cycles 281system.iocache.overall_mshr_miss_latency::total 7686457810 # number of overall MSHR miss cycles 282system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 283system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 284system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 285system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 286system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 287system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 288system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 289system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 290system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106226.142544 # average ReadReq mshr miss latency 291system.iocache.ReadReq_avg_mshr_miss_latency::total 106226.142544 # average ReadReq mshr miss latency 292system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162448.192808 # average WriteReq mshr miss latency 293system.iocache.WriteReq_avg_mshr_miss_latency::total 162448.192808 # average WriteReq mshr miss latency 294system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161371.720902 # average overall mshr miss latency 295system.iocache.demand_avg_mshr_miss_latency::total 161371.720902 # average overall mshr miss latency 296system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161371.720902 # average overall mshr miss latency 297system.iocache.overall_avg_mshr_miss_latency::total 161371.720902 # average overall mshr miss latency 298system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 299system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 300system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 301system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 302system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 303system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 304system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 305system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 306system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 307system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 308system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 309system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 310system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 311system.cpu.branchPred.lookups 86190273 # Number of BP lookups 312system.cpu.branchPred.condPredicted 86190273 # Number of conditional branches predicted 313system.cpu.branchPred.condIncorrect 1107531 # Number of conditional branches incorrect 314system.cpu.branchPred.BTBLookups 81286866 # Number of BTB lookups 315system.cpu.branchPred.BTBHits 79207834 # Number of BTB hits 316system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 317system.cpu.branchPred.BTBHitPct 97.442352 # BTB Hit Percentage 318system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 319system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 320system.cpu.numCycles 448143159 # number of cpu cycles simulated 321system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 322system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 323system.cpu.fetch.icacheStallCycles 27503051 # Number of cycles fetch is stalled on an Icache miss 324system.cpu.fetch.Insts 425930482 # Number of instructions fetch has processed 325system.cpu.fetch.Branches 86190273 # Number of branches that fetch encountered 326system.cpu.fetch.predictedBranches 79207834 # Number of branches that fetch has predicted taken 327system.cpu.fetch.Cycles 163575255 # Number of cycles fetch has run and was not squashing or blocked 328system.cpu.fetch.SquashCycles 4699027 # Number of cycles fetch has spent squashing 329system.cpu.fetch.TlbCycles 119359 # Number of cycles fetch has spent waiting for tlb 330system.cpu.fetch.BlockedCycles 63002200 # Number of cycles fetch has spent blocked 331system.cpu.fetch.MiscStallCycles 36275 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 332system.cpu.fetch.PendingTrapStallCycles 56191 # Number of stall cycles due to pending traps 333system.cpu.fetch.IcacheWaitRetryStallCycles 501 # Number of stall cycles due to full MSHR 334system.cpu.fetch.CacheLines 9012986 # Number of cache lines fetched 335system.cpu.fetch.IcacheSquashes 485449 # Number of outstanding Icache misses that were squashed 336system.cpu.fetch.ItlbSquashes 3601 # Number of outstanding ITLB misses that were squashed 337system.cpu.fetch.rateDist::samples 257845073 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::mean 3.261142 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::stdev 3.418049 # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::0 94696195 36.73% 36.73% # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::1 1566516 0.61% 37.33% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::2 71918479 27.89% 65.23% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::3 936665 0.36% 65.59% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::4 1597376 0.62% 66.21% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::5 2419164 0.94% 67.15% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::6 1071712 0.42% 67.56% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::7 1371295 0.53% 68.09% # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::8 82267671 31.91% 100.00% # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.rateDist::total 257845073 # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.branchRate 0.192328 # Number of branch fetches per cycle 355system.cpu.fetch.rate 0.950434 # Number of inst fetches per cycle 356system.cpu.decode.IdleCycles 31188651 # Number of cycles decode is idle 357system.cpu.decode.BlockedCycles 60472166 # Number of cycles decode is blocked 358system.cpu.decode.RunCycles 159373926 # Number of cycles decode is running 359system.cpu.decode.UnblockCycles 3258089 # Number of cycles decode is unblocking 360system.cpu.decode.SquashCycles 3552241 # Number of cycles decode is squashing 361system.cpu.decode.DecodedInsts 837743575 # Number of instructions handled by decode 362system.cpu.decode.SquashedInsts 790 # Number of squashed instructions handled by decode 363system.cpu.rename.SquashCycles 3552241 # Number of cycles rename is squashing 364system.cpu.rename.IdleCycles 33924496 # Number of cycles rename is idle 365system.cpu.rename.BlockCycles 37350938 # Number of cycles rename is blocking 366system.cpu.rename.serializeStallCycles 11010617 # count of cycles rename stalled for serializing inst 367system.cpu.rename.RunCycles 159571112 # Number of cycles rename is running 368system.cpu.rename.UnblockCycles 12435669 # Number of cycles rename is unblocking 369system.cpu.rename.RenamedInsts 834099694 # Number of instructions processed by rename 370system.cpu.rename.ROBFullEvents 18960 # Number of times rename has blocked due to ROB full 371system.cpu.rename.IQFullEvents 5861549 # Number of times rename has blocked due to IQ full 372system.cpu.rename.LSQFullEvents 4743149 # Number of times rename has blocked due to LSQ full 373system.cpu.rename.FullRegisterEvents 8341 # Number of times there has been no free registers 374system.cpu.rename.RenamedOperands 995593221 # Number of destination operands rename has renamed 375system.cpu.rename.RenameLookups 1810589255 # Number of register rename lookups that rename has made 376system.cpu.rename.int_rename_lookups 1810588751 # Number of integer rename lookups 377system.cpu.rename.fp_rename_lookups 504 # Number of floating rename lookups 378system.cpu.rename.CommittedMaps 964361742 # Number of HB maps that are committed 379system.cpu.rename.UndoneMaps 31231472 # Number of HB maps that are undone due to squashing 380system.cpu.rename.serializingInsts 459351 # count of serializing insts renamed 381system.cpu.rename.tempSerializingInsts 467339 # count of temporary serializing insts renamed 382system.cpu.rename.skidInsts 28773559 # count of insts added to the skid buffer 383system.cpu.memDep0.insertedLoads 17056832 # Number of loads inserted to the mem dependence unit. 384system.cpu.memDep0.insertedStores 10125853 # Number of stores inserted to the mem dependence unit. 385system.cpu.memDep0.conflictingLoads 1239786 # Number of conflicting loads. 386system.cpu.memDep0.conflictingStores 991765 # Number of conflicting stores. 387system.cpu.iq.iqInstsAdded 827988990 # Number of instructions added to the IQ (excludes non-spec) 388system.cpu.iq.iqNonSpecInstsAdded 1249374 # Number of non-speculative instructions added to the IQ 389system.cpu.iq.iqInstsIssued 823075347 # Number of instructions issued 390system.cpu.iq.iqSquashedInstsIssued 149433 # Number of squashed instructions issued 391system.cpu.iq.iqSquashedInstsExamined 21943198 # Number of squashed instructions iterated over during squash; mainly for profiling 392system.cpu.iq.iqSquashedOperandsExamined 33340930 # Number of squashed operands that are examined and possibly removed from graph 393system.cpu.iq.iqSquashedNonSpecRemoved 196529 # Number of squashed non-spec instructions that were removed 394system.cpu.iq.issued_per_cycle::samples 257845073 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::mean 3.192131 # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::stdev 2.383978 # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::0 71377289 27.68% 27.68% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::1 15522092 6.02% 33.70% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::2 10290654 3.99% 37.69% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::3 7462079 2.89% 40.59% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::4 75909573 29.44% 70.03% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::5 3836908 1.49% 71.52% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::6 72514603 28.12% 99.64% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::7 779740 0.30% 99.94% # Number of insts issued each cycle 406system.cpu.iq.issued_per_cycle::8 152135 0.06% 100.00% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 409system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 410system.cpu.iq.issued_per_cycle::total 257845073 # Number of insts issued each cycle 411system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 412system.cpu.iq.fu_full::IntAlu 361447 33.94% 33.94% # attempts to use FU when none available 413system.cpu.iq.fu_full::IntMult 0 0.00% 33.94% # attempts to use FU when none available 414system.cpu.iq.fu_full::IntDiv 0 0.00% 33.94% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.94% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.94% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.94% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatMult 0 0.00% 33.94% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.94% # attempts to use FU when none available 420system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.94% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.94% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.94% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.94% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.94% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.94% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.94% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdMult 0 0.00% 33.94% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.94% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdShift 0 0.00% 33.94% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.94% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.94% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.94% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.94% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.94% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.94% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.94% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.94% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.94% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.94% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.94% # attempts to use FU when none available 441system.cpu.iq.fu_full::MemRead 553013 51.93% 85.87% # attempts to use FU when none available 442system.cpu.iq.fu_full::MemWrite 150537 14.13% 100.00% # attempts to use FU when none available 443system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 444system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 445system.cpu.iq.FU_type_0::No_OpClass 311265 0.04% 0.04% # Type of FU issued 446system.cpu.iq.FU_type_0::IntAlu 795546265 96.66% 96.69% # Type of FU issued 447system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued 448system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued 454system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued 475system.cpu.iq.FU_type_0::MemRead 17838711 2.17% 98.86% # Type of FU issued 476system.cpu.iq.FU_type_0::MemWrite 9379106 1.14% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 478system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 479system.cpu.iq.FU_type_0::total 823075347 # Type of FU issued 480system.cpu.iq.rate 1.836635 # Inst issue rate 481system.cpu.iq.fu_busy_cnt 1064997 # FU busy when requested 482system.cpu.iq.fu_busy_rate 0.001294 # FU busy rate (busy events/executed inst) 483system.cpu.iq.int_inst_queue_reads 1905340193 # Number of integer instruction queue reads 484system.cpu.iq.int_inst_queue_writes 851191548 # Number of integer instruction queue writes 485system.cpu.iq.int_inst_queue_wakeup_accesses 818612199 # Number of integer instruction queue wakeup accesses 486system.cpu.iq.fp_inst_queue_reads 185 # Number of floating instruction queue reads 487system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes 488system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses 489system.cpu.iq.int_alu_accesses 823828994 # Number of integer alu accesses 490system.cpu.iq.fp_alu_accesses 85 # Number of floating point alu accesses 491system.cpu.iew.lsq.thread0.forwLoads 1638396 # Number of loads that had data forwarded from stores 492system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 493system.cpu.iew.lsq.thread0.squashedLoads 3078783 # Number of loads squashed 494system.cpu.iew.lsq.thread0.ignoredResponses 22684 # Number of memory responses ignored because the instruction is squashed 495system.cpu.iew.lsq.thread0.memOrderViolation 11490 # Number of memory ordering violations 496system.cpu.iew.lsq.thread0.squashedStores 1711608 # Number of stores squashed 497system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 498system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 499system.cpu.iew.lsq.thread0.rescheduledLoads 1932396 # Number of loads that were rescheduled 500system.cpu.iew.lsq.thread0.cacheBlocked 11890 # Number of times an access to memory failed due to the cache being blocked 501system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 502system.cpu.iew.iewSquashCycles 3552241 # Number of cycles IEW is squashing 503system.cpu.iew.iewBlockCycles 26088999 # Number of cycles IEW is blocking 504system.cpu.iew.iewUnblockCycles 2114690 # Number of cycles IEW is unblocking 505system.cpu.iew.iewDispatchedInsts 829238364 # Number of instructions dispatched to IQ 506system.cpu.iew.iewDispSquashedInsts 319607 # Number of squashed instructions skipped by dispatch 507system.cpu.iew.iewDispLoadInsts 17056832 # Number of dispatched load instructions 508system.cpu.iew.iewDispStoreInsts 10125853 # Number of dispatched store instructions 509system.cpu.iew.iewDispNonSpecInsts 718701 # Number of dispatched non-speculative instructions 510system.cpu.iew.iewIQFullEvents 1615260 # Number of times the IQ has become full, causing a stall 511system.cpu.iew.iewLSQFullEvents 11047 # Number of times the LSQ has become full, causing a stall 512system.cpu.iew.memOrderViolationEvents 11490 # Number of memory order violations 513system.cpu.iew.predictedTakenIncorrect 650165 # Number of branches that were predicted taken incorrectly 514system.cpu.iew.predictedNotTakenIncorrect 594804 # Number of branches that were predicted not taken incorrectly 515system.cpu.iew.branchMispredicts 1244969 # Number of branch mispredicts detected at execute 516system.cpu.iew.iewExecutedInsts 821209157 # Number of executed instructions 517system.cpu.iew.iewExecLoadInsts 17428424 # Number of load instructions executed 518system.cpu.iew.iewExecSquashedInsts 1866189 # Number of squashed instructions skipped in execute 519system.cpu.iew.exec_swp 0 # number of swp insts executed 520system.cpu.iew.exec_nop 0 # number of nop insts executed 521system.cpu.iew.exec_refs 26576192 # number of memory reference insts executed 522system.cpu.iew.exec_branches 83198528 # Number of branches executed 523system.cpu.iew.exec_stores 9147768 # Number of stores executed 524system.cpu.iew.exec_rate 1.832471 # Inst execution rate 525system.cpu.iew.wb_sent 820748086 # cumulative count of insts sent to commit 526system.cpu.iew.wb_count 818612249 # cumulative count of insts written-back 527system.cpu.iew.wb_producers 639805768 # num instructions producing a value 528system.cpu.iew.wb_consumers 1045573656 # num instructions consuming a value 529system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 530system.cpu.iew.wb_rate 1.826676 # insts written-back per cycle 531system.cpu.iew.wb_fanout 0.611918 # average fanout of values written-back 532system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 533system.cpu.commit.commitSquashedInsts 22746956 # The number of squashed insts skipped by commit 534system.cpu.commit.commitNonSpecStalls 1052843 # The number of times commit has been forced to stall to communicate backwards 535system.cpu.commit.branchMispredicts 1113134 # The number of times a branch was mispredicted 536system.cpu.commit.committed_per_cycle::samples 254292832 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::mean 3.171083 # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::stdev 2.853965 # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::0 82512721 32.45% 32.45% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::1 11810250 4.64% 37.09% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::2 3911409 1.54% 38.63% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::3 74946899 29.47% 68.10% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::4 2433458 0.96% 69.06% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::5 1482000 0.58% 69.64% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::6 941049 0.37% 70.01% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::7 70920641 27.89% 97.90% # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::8 5334405 2.10% 100.00% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 552system.cpu.commit.committed_per_cycle::total 254292832 # Number of insts commited each cycle 553system.cpu.commit.committedInsts 407935752 # Number of instructions committed 554system.cpu.commit.committedOps 806383618 # Number of ops (including micro ops) committed 555system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 556system.cpu.commit.refs 22392291 # Number of memory references committed 557system.cpu.commit.loads 13978046 # Number of loads committed 558system.cpu.commit.membars 473511 # Number of memory barriers committed 559system.cpu.commit.branches 82192705 # Number of branches committed 560system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 561system.cpu.commit.int_insts 735323034 # Number of committed integer instructions. 562system.cpu.commit.function_calls 0 # Number of function calls committed. 563system.cpu.commit.bw_lim_events 5334405 # number cycles where commit BW limit reached 564system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 565system.cpu.rob.rob_reads 1078010714 # The number of ROB reads 566system.cpu.rob.rob_writes 1661832245 # The number of ROB writes 567system.cpu.timesIdled 1221118 # Number of times that the entire CPU went into an idle state and unscheduled itself 568system.cpu.idleCycles 190298086 # Total number of cycles that the CPU has spent unscheduled due to idling 569system.cpu.quiesceCycles 9825578883 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 570system.cpu.committedInsts 407935752 # Number of Instructions Simulated 571system.cpu.committedOps 806383618 # Number of Ops (including micro ops) Simulated 572system.cpu.committedInsts_total 407935752 # Number of Instructions Simulated 573system.cpu.cpi 1.098563 # CPI: Cycles Per Instruction 574system.cpu.cpi_total 1.098563 # CPI: Total CPI of All Threads 575system.cpu.ipc 0.910280 # IPC: Instructions Per Cycle 576system.cpu.ipc_total 0.910280 # IPC: Total IPC of All Threads 577system.cpu.int_regfile_reads 1506729750 # number of integer regfile reads 578system.cpu.int_regfile_writes 976791944 # number of integer regfile writes 579system.cpu.fp_regfile_reads 50 # number of floating regfile reads 580system.cpu.misc_regfile_reads 264623965 # number of misc regfile reads 581system.cpu.misc_regfile_writes 402412 # number of misc regfile writes 582system.cpu.icache.replacements 1049766 # number of replacements 583system.cpu.icache.tagsinuse 510.907265 # Cycle average of tags in use 584system.cpu.icache.total_refs 7899601 # Total number of references to valid blocks. 585system.cpu.icache.sampled_refs 1050278 # Sample count of references to valid blocks. 586system.cpu.icache.avg_refs 7.521438 # Average number of references to valid blocks. 587system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. 588system.cpu.icache.occ_blocks::cpu.inst 510.907265 # Average occupied blocks per requestor 589system.cpu.icache.occ_percent::cpu.inst 0.997866 # Average percentage of cache occupancy 590system.cpu.icache.occ_percent::total 0.997866 # Average percentage of cache occupancy 591system.cpu.icache.ReadReq_hits::cpu.inst 7899601 # number of ReadReq hits 592system.cpu.icache.ReadReq_hits::total 7899601 # number of ReadReq hits 593system.cpu.icache.demand_hits::cpu.inst 7899601 # number of demand (read+write) hits 594system.cpu.icache.demand_hits::total 7899601 # number of demand (read+write) hits 595system.cpu.icache.overall_hits::cpu.inst 7899601 # number of overall hits 596system.cpu.icache.overall_hits::total 7899601 # number of overall hits 597system.cpu.icache.ReadReq_misses::cpu.inst 1113380 # number of ReadReq misses 598system.cpu.icache.ReadReq_misses::total 1113380 # number of ReadReq misses 599system.cpu.icache.demand_misses::cpu.inst 1113380 # number of demand (read+write) misses 600system.cpu.icache.demand_misses::total 1113380 # number of demand (read+write) misses 601system.cpu.icache.overall_misses::cpu.inst 1113380 # number of overall misses 602system.cpu.icache.overall_misses::total 1113380 # number of overall misses 603system.cpu.icache.ReadReq_miss_latency::cpu.inst 15333448488 # number of ReadReq miss cycles 604system.cpu.icache.ReadReq_miss_latency::total 15333448488 # number of ReadReq miss cycles 605system.cpu.icache.demand_miss_latency::cpu.inst 15333448488 # number of demand (read+write) miss cycles 606system.cpu.icache.demand_miss_latency::total 15333448488 # number of demand (read+write) miss cycles 607system.cpu.icache.overall_miss_latency::cpu.inst 15333448488 # number of overall miss cycles 608system.cpu.icache.overall_miss_latency::total 15333448488 # number of overall miss cycles 609system.cpu.icache.ReadReq_accesses::cpu.inst 9012981 # number of ReadReq accesses(hits+misses) 610system.cpu.icache.ReadReq_accesses::total 9012981 # number of ReadReq accesses(hits+misses) 611system.cpu.icache.demand_accesses::cpu.inst 9012981 # number of demand (read+write) accesses 612system.cpu.icache.demand_accesses::total 9012981 # number of demand (read+write) accesses 613system.cpu.icache.overall_accesses::cpu.inst 9012981 # number of overall (read+write) accesses 614system.cpu.icache.overall_accesses::total 9012981 # number of overall (read+write) accesses 615system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123531 # miss rate for ReadReq accesses 616system.cpu.icache.ReadReq_miss_rate::total 0.123531 # miss rate for ReadReq accesses 617system.cpu.icache.demand_miss_rate::cpu.inst 0.123531 # miss rate for demand accesses 618system.cpu.icache.demand_miss_rate::total 0.123531 # miss rate for demand accesses 619system.cpu.icache.overall_miss_rate::cpu.inst 0.123531 # miss rate for overall accesses 620system.cpu.icache.overall_miss_rate::total 0.123531 # miss rate for overall accesses 621system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13771.981253 # average ReadReq miss latency 622system.cpu.icache.ReadReq_avg_miss_latency::total 13771.981253 # average ReadReq miss latency 623system.cpu.icache.demand_avg_miss_latency::cpu.inst 13771.981253 # average overall miss latency 624system.cpu.icache.demand_avg_miss_latency::total 13771.981253 # average overall miss latency 625system.cpu.icache.overall_avg_miss_latency::cpu.inst 13771.981253 # average overall miss latency 626system.cpu.icache.overall_avg_miss_latency::total 13771.981253 # average overall miss latency 627system.cpu.icache.blocked_cycles::no_mshrs 13782 # number of cycles access was blocked 628system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 629system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked 630system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 631system.cpu.icache.avg_blocked_cycles::no_mshrs 45.485149 # average number of cycles each access was blocked 632system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 633system.cpu.icache.fast_writes 0 # number of fast writes performed 634system.cpu.icache.cache_copies 0 # number of cache copies performed 635system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60842 # number of ReadReq MSHR hits 636system.cpu.icache.ReadReq_mshr_hits::total 60842 # number of ReadReq MSHR hits 637system.cpu.icache.demand_mshr_hits::cpu.inst 60842 # number of demand (read+write) MSHR hits 638system.cpu.icache.demand_mshr_hits::total 60842 # number of demand (read+write) MSHR hits 639system.cpu.icache.overall_mshr_hits::cpu.inst 60842 # number of overall MSHR hits 640system.cpu.icache.overall_mshr_hits::total 60842 # number of overall MSHR hits 641system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1052538 # number of ReadReq MSHR misses 642system.cpu.icache.ReadReq_mshr_misses::total 1052538 # number of ReadReq MSHR misses 643system.cpu.icache.demand_mshr_misses::cpu.inst 1052538 # number of demand (read+write) MSHR misses 644system.cpu.icache.demand_mshr_misses::total 1052538 # number of demand (read+write) MSHR misses 645system.cpu.icache.overall_mshr_misses::cpu.inst 1052538 # number of overall MSHR misses 646system.cpu.icache.overall_mshr_misses::total 1052538 # number of overall MSHR misses 647system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12613347488 # number of ReadReq MSHR miss cycles 648system.cpu.icache.ReadReq_mshr_miss_latency::total 12613347488 # number of ReadReq MSHR miss cycles 649system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12613347488 # number of demand (read+write) MSHR miss cycles 650system.cpu.icache.demand_mshr_miss_latency::total 12613347488 # number of demand (read+write) MSHR miss cycles 651system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12613347488 # number of overall MSHR miss cycles 652system.cpu.icache.overall_mshr_miss_latency::total 12613347488 # number of overall MSHR miss cycles 653system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for ReadReq accesses 654system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116780 # mshr miss rate for ReadReq accesses 655system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for demand accesses 656system.cpu.icache.demand_mshr_miss_rate::total 0.116780 # mshr miss rate for demand accesses 657system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for overall accesses 658system.cpu.icache.overall_mshr_miss_rate::total 0.116780 # mshr miss rate for overall accesses 659system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.745469 # average ReadReq mshr miss latency 660system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11983.745469 # average ReadReq mshr miss latency 661system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.745469 # average overall mshr miss latency 662system.cpu.icache.demand_avg_mshr_miss_latency::total 11983.745469 # average overall mshr miss latency 663system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.745469 # average overall mshr miss latency 664system.cpu.icache.overall_avg_mshr_miss_latency::total 11983.745469 # average overall mshr miss latency 665system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 666system.cpu.itb_walker_cache.replacements 9783 # number of replacements 667system.cpu.itb_walker_cache.tagsinuse 6.014217 # Cycle average of tags in use 668system.cpu.itb_walker_cache.total_refs 28141 # Total number of references to valid blocks. 669system.cpu.itb_walker_cache.sampled_refs 9798 # Sample count of references to valid blocks. 670system.cpu.itb_walker_cache.avg_refs 2.872117 # Average number of references to valid blocks. 671system.cpu.itb_walker_cache.warmup_cycle 5106728958500 # Cycle when the warmup percentage was hit. 672system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.014217 # Average occupied blocks per requestor 673system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375889 # Average percentage of cache occupancy 674system.cpu.itb_walker_cache.occ_percent::total 0.375889 # Average percentage of cache occupancy 675system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28140 # number of ReadReq hits 676system.cpu.itb_walker_cache.ReadReq_hits::total 28140 # number of ReadReq hits 677system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 678system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 679system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28142 # number of demand (read+write) hits 680system.cpu.itb_walker_cache.demand_hits::total 28142 # number of demand (read+write) hits 681system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28142 # number of overall hits 682system.cpu.itb_walker_cache.overall_hits::total 28142 # number of overall hits 683system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10689 # number of ReadReq misses 684system.cpu.itb_walker_cache.ReadReq_misses::total 10689 # number of ReadReq misses 685system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10689 # number of demand (read+write) misses 686system.cpu.itb_walker_cache.demand_misses::total 10689 # number of demand (read+write) misses 687system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10689 # number of overall misses 688system.cpu.itb_walker_cache.overall_misses::total 10689 # number of overall misses 689system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 118046500 # number of ReadReq miss cycles 690system.cpu.itb_walker_cache.ReadReq_miss_latency::total 118046500 # number of ReadReq miss cycles 691system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 118046500 # number of demand (read+write) miss cycles 692system.cpu.itb_walker_cache.demand_miss_latency::total 118046500 # number of demand (read+write) miss cycles 693system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 118046500 # number of overall miss cycles 694system.cpu.itb_walker_cache.overall_miss_latency::total 118046500 # number of overall miss cycles 695system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38829 # number of ReadReq accesses(hits+misses) 696system.cpu.itb_walker_cache.ReadReq_accesses::total 38829 # number of ReadReq accesses(hits+misses) 697system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 698system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 699system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38831 # number of demand (read+write) accesses 700system.cpu.itb_walker_cache.demand_accesses::total 38831 # number of demand (read+write) accesses 701system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38831 # number of overall (read+write) accesses 702system.cpu.itb_walker_cache.overall_accesses::total 38831 # number of overall (read+write) accesses 703system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275284 # miss rate for ReadReq accesses 704system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275284 # miss rate for ReadReq accesses 705system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275270 # miss rate for demand accesses 706system.cpu.itb_walker_cache.demand_miss_rate::total 0.275270 # miss rate for demand accesses 707system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275270 # miss rate for overall accesses 708system.cpu.itb_walker_cache.overall_miss_rate::total 0.275270 # miss rate for overall accesses 709system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11043.736552 # average ReadReq miss latency 710system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11043.736552 # average ReadReq miss latency 711system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11043.736552 # average overall miss latency 712system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11043.736552 # average overall miss latency 713system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11043.736552 # average overall miss latency 714system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11043.736552 # average overall miss latency 715system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 716system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 717system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 718system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 719system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 720system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 721system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 722system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 723system.cpu.itb_walker_cache.writebacks::writebacks 1993 # number of writebacks 724system.cpu.itb_walker_cache.writebacks::total 1993 # number of writebacks 725system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10689 # number of ReadReq MSHR misses 726system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10689 # number of ReadReq MSHR misses 727system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10689 # number of demand (read+write) MSHR misses 728system.cpu.itb_walker_cache.demand_mshr_misses::total 10689 # number of demand (read+write) MSHR misses 729system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10689 # number of overall MSHR misses 730system.cpu.itb_walker_cache.overall_mshr_misses::total 10689 # number of overall MSHR misses 731system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96668500 # number of ReadReq MSHR miss cycles 732system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96668500 # number of ReadReq MSHR miss cycles 733system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96668500 # number of demand (read+write) MSHR miss cycles 734system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96668500 # number of demand (read+write) MSHR miss cycles 735system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96668500 # number of overall MSHR miss cycles 736system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96668500 # number of overall MSHR miss cycles 737system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275284 # mshr miss rate for ReadReq accesses 738system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275284 # mshr miss rate for ReadReq accesses 739system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275270 # mshr miss rate for demand accesses 740system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275270 # mshr miss rate for demand accesses 741system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275270 # mshr miss rate for overall accesses 742system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275270 # mshr miss rate for overall accesses 743system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average ReadReq mshr miss latency 744system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9043.736552 # average ReadReq mshr miss latency 745system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average overall mshr miss latency 746system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9043.736552 # average overall mshr miss latency 747system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average overall mshr miss latency 748system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9043.736552 # average overall mshr miss latency 749system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 750system.cpu.dtb_walker_cache.replacements 108113 # number of replacements 751system.cpu.dtb_walker_cache.tagsinuse 13.301181 # Cycle average of tags in use 752system.cpu.dtb_walker_cache.total_refs 134692 # Total number of references to valid blocks. 753system.cpu.dtb_walker_cache.sampled_refs 108129 # Sample count of references to valid blocks. 754system.cpu.dtb_walker_cache.avg_refs 1.245660 # Average number of references to valid blocks. 755system.cpu.dtb_walker_cache.warmup_cycle 5100502305500 # Cycle when the warmup percentage was hit. 756system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.301181 # Average occupied blocks per requestor 757system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.831324 # Average percentage of cache occupancy 758system.cpu.dtb_walker_cache.occ_percent::total 0.831324 # Average percentage of cache occupancy 759system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134692 # number of ReadReq hits 760system.cpu.dtb_walker_cache.ReadReq_hits::total 134692 # number of ReadReq hits 761system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134692 # number of demand (read+write) hits 762system.cpu.dtb_walker_cache.demand_hits::total 134692 # number of demand (read+write) hits 763system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134692 # number of overall hits 764system.cpu.dtb_walker_cache.overall_hits::total 134692 # number of overall hits 765system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109183 # number of ReadReq misses 766system.cpu.dtb_walker_cache.ReadReq_misses::total 109183 # number of ReadReq misses 767system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109183 # number of demand (read+write) misses 768system.cpu.dtb_walker_cache.demand_misses::total 109183 # number of demand (read+write) misses 769system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109183 # number of overall misses 770system.cpu.dtb_walker_cache.overall_misses::total 109183 # number of overall misses 771system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1366356000 # number of ReadReq miss cycles 772system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1366356000 # number of ReadReq miss cycles 773system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1366356000 # number of demand (read+write) miss cycles 774system.cpu.dtb_walker_cache.demand_miss_latency::total 1366356000 # number of demand (read+write) miss cycles 775system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1366356000 # number of overall miss cycles 776system.cpu.dtb_walker_cache.overall_miss_latency::total 1366356000 # number of overall miss cycles 777system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243875 # number of ReadReq accesses(hits+misses) 778system.cpu.dtb_walker_cache.ReadReq_accesses::total 243875 # number of ReadReq accesses(hits+misses) 779system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243875 # number of demand (read+write) accesses 780system.cpu.dtb_walker_cache.demand_accesses::total 243875 # number of demand (read+write) accesses 781system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243875 # number of overall (read+write) accesses 782system.cpu.dtb_walker_cache.overall_accesses::total 243875 # number of overall (read+write) accesses 783system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447701 # miss rate for ReadReq accesses 784system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447701 # miss rate for ReadReq accesses 785system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447701 # miss rate for demand accesses 786system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447701 # miss rate for demand accesses 787system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447701 # miss rate for overall accesses 788system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447701 # miss rate for overall accesses 789system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12514.365790 # average ReadReq miss latency 790system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12514.365790 # average ReadReq miss latency 791system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12514.365790 # average overall miss latency 792system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12514.365790 # average overall miss latency 793system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12514.365790 # average overall miss latency 794system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12514.365790 # average overall miss latency 795system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 796system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 797system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 798system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 799system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 800system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 801system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 802system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 803system.cpu.dtb_walker_cache.writebacks::writebacks 35577 # number of writebacks 804system.cpu.dtb_walker_cache.writebacks::total 35577 # number of writebacks 805system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109183 # number of ReadReq MSHR misses 806system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109183 # number of ReadReq MSHR misses 807system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109183 # number of demand (read+write) MSHR misses 808system.cpu.dtb_walker_cache.demand_mshr_misses::total 109183 # number of demand (read+write) MSHR misses 809system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109183 # number of overall MSHR misses 810system.cpu.dtb_walker_cache.overall_mshr_misses::total 109183 # number of overall MSHR misses 811system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of ReadReq MSHR miss cycles 812system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1147990000 # number of ReadReq MSHR miss cycles 813system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of demand (read+write) MSHR miss cycles 814system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1147990000 # number of demand (read+write) MSHR miss cycles 815system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of overall MSHR miss cycles 816system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1147990000 # number of overall MSHR miss cycles 817system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for ReadReq accesses 818system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447701 # mshr miss rate for ReadReq accesses 819system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for demand accesses 820system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447701 # mshr miss rate for demand accesses 821system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for overall accesses 822system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447701 # mshr miss rate for overall accesses 823system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average ReadReq mshr miss latency 824system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10514.365790 # average ReadReq mshr miss latency 825system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average overall mshr miss latency 826system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10514.365790 # average overall mshr miss latency 827system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average overall mshr miss latency 828system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10514.365790 # average overall mshr miss latency 829system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 830system.cpu.dcache.replacements 1659590 # number of replacements 831system.cpu.dcache.tagsinuse 511.997640 # Cycle average of tags in use 832system.cpu.dcache.total_refs 19085008 # Total number of references to valid blocks. 833system.cpu.dcache.sampled_refs 1660102 # Sample count of references to valid blocks. 834system.cpu.dcache.avg_refs 11.496286 # Average number of references to valid blocks. 835system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. 836system.cpu.dcache.occ_blocks::cpu.data 511.997640 # Average occupied blocks per requestor 837system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy 838system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy 839system.cpu.dcache.ReadReq_hits::cpu.data 10993134 # number of ReadReq hits 840system.cpu.dcache.ReadReq_hits::total 10993134 # number of ReadReq hits 841system.cpu.dcache.WriteReq_hits::cpu.data 8086930 # number of WriteReq hits 842system.cpu.dcache.WriteReq_hits::total 8086930 # number of WriteReq hits 843system.cpu.dcache.demand_hits::cpu.data 19080064 # number of demand (read+write) hits 844system.cpu.dcache.demand_hits::total 19080064 # number of demand (read+write) hits 845system.cpu.dcache.overall_hits::cpu.data 19080064 # number of overall hits 846system.cpu.dcache.overall_hits::total 19080064 # number of overall hits 847system.cpu.dcache.ReadReq_misses::cpu.data 2235074 # number of ReadReq misses 848system.cpu.dcache.ReadReq_misses::total 2235074 # number of ReadReq misses 849system.cpu.dcache.WriteReq_misses::cpu.data 318068 # number of WriteReq misses 850system.cpu.dcache.WriteReq_misses::total 318068 # number of WriteReq misses 851system.cpu.dcache.demand_misses::cpu.data 2553142 # number of demand (read+write) misses 852system.cpu.dcache.demand_misses::total 2553142 # number of demand (read+write) misses 853system.cpu.dcache.overall_misses::cpu.data 2553142 # number of overall misses 854system.cpu.dcache.overall_misses::total 2553142 # number of overall misses 855system.cpu.dcache.ReadReq_miss_latency::cpu.data 32122708000 # number of ReadReq miss cycles 856system.cpu.dcache.ReadReq_miss_latency::total 32122708000 # number of ReadReq miss cycles 857system.cpu.dcache.WriteReq_miss_latency::cpu.data 9628285992 # number of WriteReq miss cycles 858system.cpu.dcache.WriteReq_miss_latency::total 9628285992 # number of WriteReq miss cycles 859system.cpu.dcache.demand_miss_latency::cpu.data 41750993992 # number of demand (read+write) miss cycles 860system.cpu.dcache.demand_miss_latency::total 41750993992 # number of demand (read+write) miss cycles 861system.cpu.dcache.overall_miss_latency::cpu.data 41750993992 # number of overall miss cycles 862system.cpu.dcache.overall_miss_latency::total 41750993992 # number of overall miss cycles 863system.cpu.dcache.ReadReq_accesses::cpu.data 13228208 # number of ReadReq accesses(hits+misses) 864system.cpu.dcache.ReadReq_accesses::total 13228208 # number of ReadReq accesses(hits+misses) 865system.cpu.dcache.WriteReq_accesses::cpu.data 8404998 # number of WriteReq accesses(hits+misses) 866system.cpu.dcache.WriteReq_accesses::total 8404998 # number of WriteReq accesses(hits+misses) 867system.cpu.dcache.demand_accesses::cpu.data 21633206 # number of demand (read+write) accesses 868system.cpu.dcache.demand_accesses::total 21633206 # number of demand (read+write) accesses 869system.cpu.dcache.overall_accesses::cpu.data 21633206 # number of overall (read+write) accesses 870system.cpu.dcache.overall_accesses::total 21633206 # number of overall (read+write) accesses 871system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168963 # miss rate for ReadReq accesses 872system.cpu.dcache.ReadReq_miss_rate::total 0.168963 # miss rate for ReadReq accesses 873system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037843 # miss rate for WriteReq accesses 874system.cpu.dcache.WriteReq_miss_rate::total 0.037843 # miss rate for WriteReq accesses 875system.cpu.dcache.demand_miss_rate::cpu.data 0.118020 # miss rate for demand accesses 876system.cpu.dcache.demand_miss_rate::total 0.118020 # miss rate for demand accesses 877system.cpu.dcache.overall_miss_rate::cpu.data 0.118020 # miss rate for overall accesses 878system.cpu.dcache.overall_miss_rate::total 0.118020 # miss rate for overall accesses 879system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14372.100432 # average ReadReq miss latency 880system.cpu.dcache.ReadReq_avg_miss_latency::total 14372.100432 # average ReadReq miss latency 881system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30271.155828 # average WriteReq miss latency 882system.cpu.dcache.WriteReq_avg_miss_latency::total 30271.155828 # average WriteReq miss latency 883system.cpu.dcache.demand_avg_miss_latency::cpu.data 16352.789618 # average overall miss latency 884system.cpu.dcache.demand_avg_miss_latency::total 16352.789618 # average overall miss latency 885system.cpu.dcache.overall_avg_miss_latency::cpu.data 16352.789618 # average overall miss latency 886system.cpu.dcache.overall_avg_miss_latency::total 16352.789618 # average overall miss latency 887system.cpu.dcache.blocked_cycles::no_mshrs 398716 # number of cycles access was blocked 888system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 889system.cpu.dcache.blocked::no_mshrs 42426 # number of cycles access was blocked 890system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 891system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.397916 # average number of cycles each access was blocked 892system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 893system.cpu.dcache.fast_writes 0 # number of fast writes performed 894system.cpu.dcache.cache_copies 0 # number of cache copies performed 895system.cpu.dcache.writebacks::writebacks 1560986 # number of writebacks 896system.cpu.dcache.writebacks::total 1560986 # number of writebacks 897system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863566 # number of ReadReq MSHR hits 898system.cpu.dcache.ReadReq_mshr_hits::total 863566 # number of ReadReq MSHR hits 899system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25004 # number of WriteReq MSHR hits 900system.cpu.dcache.WriteReq_mshr_hits::total 25004 # number of WriteReq MSHR hits 901system.cpu.dcache.demand_mshr_hits::cpu.data 888570 # number of demand (read+write) MSHR hits 902system.cpu.dcache.demand_mshr_hits::total 888570 # number of demand (read+write) MSHR hits 903system.cpu.dcache.overall_mshr_hits::cpu.data 888570 # number of overall MSHR hits 904system.cpu.dcache.overall_mshr_hits::total 888570 # number of overall MSHR hits 905system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371508 # number of ReadReq MSHR misses 906system.cpu.dcache.ReadReq_mshr_misses::total 1371508 # number of ReadReq MSHR misses 907system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293064 # number of WriteReq MSHR misses 908system.cpu.dcache.WriteReq_mshr_misses::total 293064 # number of WriteReq MSHR misses 909system.cpu.dcache.demand_mshr_misses::cpu.data 1664572 # number of demand (read+write) MSHR misses 910system.cpu.dcache.demand_mshr_misses::total 1664572 # number of demand (read+write) MSHR misses 911system.cpu.dcache.overall_mshr_misses::cpu.data 1664572 # number of overall MSHR misses 912system.cpu.dcache.overall_mshr_misses::total 1664572 # number of overall MSHR misses 913system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17458468000 # number of ReadReq MSHR miss cycles 914system.cpu.dcache.ReadReq_mshr_miss_latency::total 17458468000 # number of ReadReq MSHR miss cycles 915system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8785727992 # number of WriteReq MSHR miss cycles 916system.cpu.dcache.WriteReq_mshr_miss_latency::total 8785727992 # number of WriteReq MSHR miss cycles 917system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26244195992 # number of demand (read+write) MSHR miss cycles 918system.cpu.dcache.demand_mshr_miss_latency::total 26244195992 # number of demand (read+write) MSHR miss cycles 919system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26244195992 # number of overall MSHR miss cycles 920system.cpu.dcache.overall_mshr_miss_latency::total 26244195992 # number of overall MSHR miss cycles 921system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97297948500 # number of ReadReq MSHR uncacheable cycles 922system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97297948500 # number of ReadReq MSHR uncacheable cycles 923system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2473076000 # number of WriteReq MSHR uncacheable cycles 924system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2473076000 # number of WriteReq MSHR uncacheable cycles 925system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99771024500 # number of overall MSHR uncacheable cycles 926system.cpu.dcache.overall_mshr_uncacheable_latency::total 99771024500 # number of overall MSHR uncacheable cycles 927system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103681 # mshr miss rate for ReadReq accesses 928system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103681 # mshr miss rate for ReadReq accesses 929system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034868 # mshr miss rate for WriteReq accesses 930system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034868 # mshr miss rate for WriteReq accesses 931system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076945 # mshr miss rate for demand accesses 932system.cpu.dcache.demand_mshr_miss_rate::total 0.076945 # mshr miss rate for demand accesses 933system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076945 # mshr miss rate for overall accesses 934system.cpu.dcache.overall_mshr_miss_rate::total 0.076945 # mshr miss rate for overall accesses 935system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12729.395673 # average ReadReq mshr miss latency 936system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12729.395673 # average ReadReq mshr miss latency 937system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29978.871482 # average WriteReq mshr miss latency 938system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29978.871482 # average WriteReq mshr miss latency 939system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15766.332722 # average overall mshr miss latency 940system.cpu.dcache.demand_avg_mshr_miss_latency::total 15766.332722 # average overall mshr miss latency 941system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15766.332722 # average overall mshr miss latency 942system.cpu.dcache.overall_avg_mshr_miss_latency::total 15766.332722 # average overall mshr miss latency 943system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 944system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 945system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 946system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 947system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 948system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 949system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 950system.cpu.l2cache.replacements 113184 # number of replacements 951system.cpu.l2cache.tagsinuse 64838.652063 # Cycle average of tags in use 952system.cpu.l2cache.total_refs 3931021 # Total number of references to valid blocks. 953system.cpu.l2cache.sampled_refs 177284 # Sample count of references to valid blocks. 954system.cpu.l2cache.avg_refs 22.173580 # Average number of references to valid blocks. 955system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 956system.cpu.l2cache.occ_blocks::writebacks 50168.170279 # Average occupied blocks per requestor 957system.cpu.l2cache.occ_blocks::cpu.dtb.walker 13.493195 # Average occupied blocks per requestor 958system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133179 # Average occupied blocks per requestor 959system.cpu.l2cache.occ_blocks::cpu.inst 3227.427363 # Average occupied blocks per requestor 960system.cpu.l2cache.occ_blocks::cpu.data 11429.428047 # Average occupied blocks per requestor 961system.cpu.l2cache.occ_percent::writebacks 0.765506 # Average percentage of cache occupancy 962system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000206 # Average percentage of cache occupancy 963system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 964system.cpu.l2cache.occ_percent::cpu.inst 0.049247 # Average percentage of cache occupancy 965system.cpu.l2cache.occ_percent::cpu.data 0.174399 # Average percentage of cache occupancy 966system.cpu.l2cache.occ_percent::total 0.989359 # Average percentage of cache occupancy 967system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 101466 # number of ReadReq hits 968system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8114 # number of ReadReq hits 969system.cpu.l2cache.ReadReq_hits::cpu.inst 1033385 # number of ReadReq hits 970system.cpu.l2cache.ReadReq_hits::cpu.data 1333616 # number of ReadReq hits 971system.cpu.l2cache.ReadReq_hits::total 2476581 # number of ReadReq hits 972system.cpu.l2cache.Writeback_hits::writebacks 1598556 # number of Writeback hits 973system.cpu.l2cache.Writeback_hits::total 1598556 # number of Writeback hits 974system.cpu.l2cache.UpgradeReq_hits::cpu.data 335 # number of UpgradeReq hits 975system.cpu.l2cache.UpgradeReq_hits::total 335 # number of UpgradeReq hits 976system.cpu.l2cache.ReadExReq_hits::cpu.data 156370 # number of ReadExReq hits 977system.cpu.l2cache.ReadExReq_hits::total 156370 # number of ReadExReq hits 978system.cpu.l2cache.demand_hits::cpu.dtb.walker 101466 # number of demand (read+write) hits 979system.cpu.l2cache.demand_hits::cpu.itb.walker 8114 # number of demand (read+write) hits 980system.cpu.l2cache.demand_hits::cpu.inst 1033385 # number of demand (read+write) hits 981system.cpu.l2cache.demand_hits::cpu.data 1489986 # number of demand (read+write) hits 982system.cpu.l2cache.demand_hits::total 2632951 # number of demand (read+write) hits 983system.cpu.l2cache.overall_hits::cpu.dtb.walker 101466 # number of overall hits 984system.cpu.l2cache.overall_hits::cpu.itb.walker 8114 # number of overall hits 985system.cpu.l2cache.overall_hits::cpu.inst 1033385 # number of overall hits 986system.cpu.l2cache.overall_hits::cpu.data 1489986 # number of overall hits 987system.cpu.l2cache.overall_hits::total 2632951 # number of overall hits 988system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 53 # number of ReadReq misses 989system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses 990system.cpu.l2cache.ReadReq_misses::cpu.inst 16850 # number of ReadReq misses 991system.cpu.l2cache.ReadReq_misses::cpu.data 36691 # number of ReadReq misses 992system.cpu.l2cache.ReadReq_misses::total 53601 # number of ReadReq misses 993system.cpu.l2cache.UpgradeReq_misses::cpu.data 3625 # number of UpgradeReq misses 994system.cpu.l2cache.UpgradeReq_misses::total 3625 # number of UpgradeReq misses 995system.cpu.l2cache.ReadExReq_misses::cpu.data 132809 # number of ReadExReq misses 996system.cpu.l2cache.ReadExReq_misses::total 132809 # number of ReadExReq misses 997system.cpu.l2cache.demand_misses::cpu.dtb.walker 53 # number of demand (read+write) misses 998system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses 999system.cpu.l2cache.demand_misses::cpu.inst 16850 # number of demand (read+write) misses 1000system.cpu.l2cache.demand_misses::cpu.data 169500 # number of demand (read+write) misses 1001system.cpu.l2cache.demand_misses::total 186410 # number of demand (read+write) misses 1002system.cpu.l2cache.overall_misses::cpu.dtb.walker 53 # number of overall misses 1003system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses 1004system.cpu.l2cache.overall_misses::cpu.inst 16850 # number of overall misses 1005system.cpu.l2cache.overall_misses::cpu.data 169500 # number of overall misses 1006system.cpu.l2cache.overall_misses::total 186410 # number of overall misses 1007system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4666500 # number of ReadReq miss cycles 1008system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 459000 # number of ReadReq miss cycles 1009system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1174285000 # number of ReadReq miss cycles 1010system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2521513999 # number of ReadReq miss cycles 1011system.cpu.l2cache.ReadReq_miss_latency::total 3700924499 # number of ReadReq miss cycles 1012system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17158500 # number of UpgradeReq miss cycles 1013system.cpu.l2cache.UpgradeReq_miss_latency::total 17158500 # number of UpgradeReq miss cycles 1014system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6838563000 # number of ReadExReq miss cycles 1015system.cpu.l2cache.ReadExReq_miss_latency::total 6838563000 # number of ReadExReq miss cycles 1016system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4666500 # number of demand (read+write) miss cycles 1017system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 459000 # number of demand (read+write) miss cycles 1018system.cpu.l2cache.demand_miss_latency::cpu.inst 1174285000 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.demand_miss_latency::cpu.data 9360076999 # number of demand (read+write) miss cycles 1020system.cpu.l2cache.demand_miss_latency::total 10539487499 # number of demand (read+write) miss cycles 1021system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4666500 # number of overall miss cycles 1022system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 459000 # number of overall miss cycles 1023system.cpu.l2cache.overall_miss_latency::cpu.inst 1174285000 # number of overall miss cycles 1024system.cpu.l2cache.overall_miss_latency::cpu.data 9360076999 # number of overall miss cycles 1025system.cpu.l2cache.overall_miss_latency::total 10539487499 # number of overall miss cycles 1026system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 101519 # number of ReadReq accesses(hits+misses) 1027system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8121 # number of ReadReq accesses(hits+misses) 1028system.cpu.l2cache.ReadReq_accesses::cpu.inst 1050235 # number of ReadReq accesses(hits+misses) 1029system.cpu.l2cache.ReadReq_accesses::cpu.data 1370307 # number of ReadReq accesses(hits+misses) 1030system.cpu.l2cache.ReadReq_accesses::total 2530182 # number of ReadReq accesses(hits+misses) 1031system.cpu.l2cache.Writeback_accesses::writebacks 1598556 # number of Writeback accesses(hits+misses) 1032system.cpu.l2cache.Writeback_accesses::total 1598556 # number of Writeback accesses(hits+misses) 1033system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3960 # number of UpgradeReq accesses(hits+misses) 1034system.cpu.l2cache.UpgradeReq_accesses::total 3960 # number of UpgradeReq accesses(hits+misses) 1035system.cpu.l2cache.ReadExReq_accesses::cpu.data 289179 # number of ReadExReq accesses(hits+misses) 1036system.cpu.l2cache.ReadExReq_accesses::total 289179 # number of ReadExReq accesses(hits+misses) 1037system.cpu.l2cache.demand_accesses::cpu.dtb.walker 101519 # number of demand (read+write) accesses 1038system.cpu.l2cache.demand_accesses::cpu.itb.walker 8121 # number of demand (read+write) accesses 1039system.cpu.l2cache.demand_accesses::cpu.inst 1050235 # number of demand (read+write) accesses 1040system.cpu.l2cache.demand_accesses::cpu.data 1659486 # number of demand (read+write) accesses 1041system.cpu.l2cache.demand_accesses::total 2819361 # number of demand (read+write) accesses 1042system.cpu.l2cache.overall_accesses::cpu.dtb.walker 101519 # number of overall (read+write) accesses 1043system.cpu.l2cache.overall_accesses::cpu.itb.walker 8121 # number of overall (read+write) accesses 1044system.cpu.l2cache.overall_accesses::cpu.inst 1050235 # number of overall (read+write) accesses 1045system.cpu.l2cache.overall_accesses::cpu.data 1659486 # number of overall (read+write) accesses 1046system.cpu.l2cache.overall_accesses::total 2819361 # number of overall (read+write) accesses 1047system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000522 # miss rate for ReadReq accesses 1048system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000862 # miss rate for ReadReq accesses 1049system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016044 # miss rate for ReadReq accesses 1050system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026776 # miss rate for ReadReq accesses 1051system.cpu.l2cache.ReadReq_miss_rate::total 0.021185 # miss rate for ReadReq accesses 1052system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.915404 # miss rate for UpgradeReq accesses 1053system.cpu.l2cache.UpgradeReq_miss_rate::total 0.915404 # miss rate for UpgradeReq accesses 1054system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459262 # miss rate for ReadExReq accesses 1055system.cpu.l2cache.ReadExReq_miss_rate::total 0.459262 # miss rate for ReadExReq accesses 1056system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000522 # miss rate for demand accesses 1057system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000862 # miss rate for demand accesses 1058system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016044 # miss rate for demand accesses 1059system.cpu.l2cache.demand_miss_rate::cpu.data 0.102140 # miss rate for demand accesses 1060system.cpu.l2cache.demand_miss_rate::total 0.066118 # miss rate for demand accesses 1061system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000522 # miss rate for overall accesses 1062system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000862 # miss rate for overall accesses 1063system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016044 # miss rate for overall accesses 1064system.cpu.l2cache.overall_miss_rate::cpu.data 0.102140 # miss rate for overall accesses 1065system.cpu.l2cache.overall_miss_rate::total 0.066118 # miss rate for overall accesses 1066system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88047.169811 # average ReadReq miss latency 1067system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65571.428571 # average ReadReq miss latency 1068system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69690.504451 # average ReadReq miss latency 1069system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68722.956556 # average ReadReq miss latency 1070system.cpu.l2cache.ReadReq_avg_miss_latency::total 69045.810694 # average ReadReq miss latency 1071system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4733.379310 # average UpgradeReq miss latency 1072system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4733.379310 # average UpgradeReq miss latency 1073system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51491.713664 # average ReadExReq miss latency 1074system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51491.713664 # average ReadExReq miss latency 1075system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88047.169811 # average overall miss latency 1076system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65571.428571 # average overall miss latency 1077system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69690.504451 # average overall miss latency 1078system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55221.693209 # average overall miss latency 1079system.cpu.l2cache.demand_avg_miss_latency::total 56539.281686 # average overall miss latency 1080system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88047.169811 # average overall miss latency 1081system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65571.428571 # average overall miss latency 1082system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69690.504451 # average overall miss latency 1083system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55221.693209 # average overall miss latency 1084system.cpu.l2cache.overall_avg_miss_latency::total 56539.281686 # average overall miss latency 1085system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1086system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1087system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1088system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1089system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1090system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1091system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1092system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1093system.cpu.l2cache.writebacks::writebacks 102512 # number of writebacks 1094system.cpu.l2cache.writebacks::total 102512 # number of writebacks 1095system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 1096system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1097system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1098system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 1099system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1100system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 1101system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 1102system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1103system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits 1104system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses 1105system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses 1106system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16848 # number of ReadReq MSHR misses 1107system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36690 # number of ReadReq MSHR misses 1108system.cpu.l2cache.ReadReq_mshr_misses::total 53598 # number of ReadReq MSHR misses 1109system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3625 # number of UpgradeReq MSHR misses 1110system.cpu.l2cache.UpgradeReq_mshr_misses::total 3625 # number of UpgradeReq MSHR misses 1111system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132809 # number of ReadExReq MSHR misses 1112system.cpu.l2cache.ReadExReq_mshr_misses::total 132809 # number of ReadExReq MSHR misses 1113system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 53 # number of demand (read+write) MSHR misses 1114system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses 1115system.cpu.l2cache.demand_mshr_misses::cpu.inst 16848 # number of demand (read+write) MSHR misses 1116system.cpu.l2cache.demand_mshr_misses::cpu.data 169499 # number of demand (read+write) MSHR misses 1117system.cpu.l2cache.demand_mshr_misses::total 186407 # number of demand (read+write) MSHR misses 1118system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 53 # number of overall MSHR misses 1119system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 1120system.cpu.l2cache.overall_mshr_misses::cpu.inst 16848 # number of overall MSHR misses 1121system.cpu.l2cache.overall_mshr_misses::cpu.data 169499 # number of overall MSHR misses 1122system.cpu.l2cache.overall_mshr_misses::total 186407 # number of overall MSHR misses 1123system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4003602 # number of ReadReq MSHR miss cycles 1124system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 370512 # number of ReadReq MSHR miss cycles 1125system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 964285581 # number of ReadReq MSHR miss cycles 1126system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2065462567 # number of ReadReq MSHR miss cycles 1127system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3034122262 # number of ReadReq MSHR miss cycles 1128system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37079107 # number of UpgradeReq MSHR miss cycles 1129system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37079107 # number of UpgradeReq MSHR miss cycles 1130system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5200762570 # number of ReadExReq MSHR miss cycles 1131system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5200762570 # number of ReadExReq MSHR miss cycles 1132system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4003602 # number of demand (read+write) MSHR miss cycles 1133system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 370512 # number of demand (read+write) MSHR miss cycles 1134system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 964285581 # number of demand (read+write) MSHR miss cycles 1135system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7266225137 # number of demand (read+write) MSHR miss cycles 1136system.cpu.l2cache.demand_mshr_miss_latency::total 8234884832 # number of demand (read+write) MSHR miss cycles 1137system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4003602 # number of overall MSHR miss cycles 1138system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 370512 # number of overall MSHR miss cycles 1139system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 964285581 # number of overall MSHR miss cycles 1140system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7266225137 # number of overall MSHR miss cycles 1141system.cpu.l2cache.overall_mshr_miss_latency::total 8234884832 # number of overall MSHR miss cycles 1142system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89188560000 # number of ReadReq MSHR uncacheable cycles 1143system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89188560000 # number of ReadReq MSHR uncacheable cycles 1144system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2310705000 # number of WriteReq MSHR uncacheable cycles 1145system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2310705000 # number of WriteReq MSHR uncacheable cycles 1146system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91499265000 # number of overall MSHR uncacheable cycles 1147system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91499265000 # number of overall MSHR uncacheable cycles 1148system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for ReadReq accesses 1149system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for ReadReq accesses 1150system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for ReadReq accesses 1151system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026775 # mshr miss rate for ReadReq accesses 1152system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021183 # mshr miss rate for ReadReq accesses 1153system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.915404 # mshr miss rate for UpgradeReq accesses 1154system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.915404 # mshr miss rate for UpgradeReq accesses 1155system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459262 # mshr miss rate for ReadExReq accesses 1156system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459262 # mshr miss rate for ReadExReq accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for demand accesses 1158system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for demand accesses 1159system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for demand accesses 1160system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102139 # mshr miss rate for demand accesses 1161system.cpu.l2cache.demand_mshr_miss_rate::total 0.066117 # mshr miss rate for demand accesses 1162system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for overall accesses 1163system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for overall accesses 1164system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for overall accesses 1165system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102139 # mshr miss rate for overall accesses 1166system.cpu.l2cache.overall_mshr_miss_rate::total 0.066117 # mshr miss rate for overall accesses 1167system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average ReadReq mshr miss latency 1168system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average ReadReq mshr miss latency 1169system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57234.424323 # average ReadReq mshr miss latency 1170system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56294.973208 # average ReadReq mshr miss latency 1171system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56608.870891 # average ReadReq mshr miss latency 1172system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10228.719172 # average UpgradeReq mshr miss latency 1173system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10228.719172 # average UpgradeReq mshr miss latency 1174system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39159.714854 # average ReadExReq mshr miss latency 1175system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39159.714854 # average ReadExReq mshr miss latency 1176system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average overall mshr miss latency 1177system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average overall mshr miss latency 1178system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57234.424323 # average overall mshr miss latency 1179system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42868.837793 # average overall mshr miss latency 1180system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44176.907691 # average overall mshr miss latency 1181system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average overall mshr miss latency 1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average overall mshr miss latency 1183system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57234.424323 # average overall mshr miss latency 1184system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42868.837793 # average overall mshr miss latency 1185system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44176.907691 # average overall mshr miss latency 1186system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1187system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1188system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1189system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1190system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1191system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1192system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1193system.cpu.kern.inst.arm 0 # number of arm instructions executed 1194system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1195 1196---------- End Simulation Statistics ---------- 1197