stats.txt revision 9312:e05e1b69ebf2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.128875 # Number of seconds simulated 4sim_ticks 5128875494000 # Number of ticks simulated 5final_tick 5128875494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 179743 # Simulator instruction rate (inst/s) 8host_op_rate 355302 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2259848354 # Simulator tick rate (ticks/s) 10host_mem_usage 404644 # Number of bytes of host memory used 11host_seconds 2269.57 # Real time elapsed on the host 12sim_insts 407937807 # Number of instructions simulated 13sim_ops 806381430 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2484160 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 1082048 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10897856 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14467456 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1082048 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1082048 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9613376 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9613376 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38815 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 16907 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 170279 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 226054 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 150209 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 150209 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 484348 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 574 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 210972 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2124804 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2820785 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 210972 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 210972 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1874363 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1874363 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1874363 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 484348 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 574 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 210972 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2124804 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4695148 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.readReqs 226054 # Total number of read requests seen 50system.physmem.writeReqs 150209 # Total number of write requests seen 51system.physmem.cpureqs 390083 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 14467456 # Total number of bytes read from memory 53system.physmem.bytesWritten 9613376 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 14467456 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 9613376 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 85 # Number of read reqs serviced by write Q 57system.physmem.neitherReadNorWrite 3870 # Reqs where no action is needed 58system.physmem.perBankRdReqs::0 13592 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::1 14674 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::2 12790 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::3 14969 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::4 13832 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::5 14849 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::6 12900 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::7 14193 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::8 13720 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::9 14770 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::10 14195 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::11 14927 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::12 13783 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::13 14903 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::14 12863 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::15 15009 # Track reads on a per bank basis 74system.physmem.perBankWrReqs::0 8622 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::1 10212 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::2 8230 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::3 10302 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::4 8995 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::5 10163 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::6 8186 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::7 9599 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::8 8962 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::9 10025 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::10 9289 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::11 10268 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::12 8898 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::13 10138 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::14 8164 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::15 10156 # Track writes on a per bank basis 90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 91system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 92system.physmem.totGap 5128875413000 # Total gap between requests 93system.physmem.readPktSize::0 0 # Categorize read packet sizes 94system.physmem.readPktSize::1 0 # Categorize read packet sizes 95system.physmem.readPktSize::2 0 # Categorize read packet sizes 96system.physmem.readPktSize::3 0 # Categorize read packet sizes 97system.physmem.readPktSize::4 0 # Categorize read packet sizes 98system.physmem.readPktSize::5 0 # Categorize read packet sizes 99system.physmem.readPktSize::6 226054 # Categorize read packet sizes 100system.physmem.readPktSize::7 0 # Categorize read packet sizes 101system.physmem.readPktSize::8 0 # Categorize read packet sizes 102system.physmem.writePktSize::0 0 # categorize write packet sizes 103system.physmem.writePktSize::1 0 # categorize write packet sizes 104system.physmem.writePktSize::2 0 # categorize write packet sizes 105system.physmem.writePktSize::3 0 # categorize write packet sizes 106system.physmem.writePktSize::4 0 # categorize write packet sizes 107system.physmem.writePktSize::5 0 # categorize write packet sizes 108system.physmem.writePktSize::6 150209 # categorize write packet sizes 109system.physmem.writePktSize::7 0 # categorize write packet sizes 110system.physmem.writePktSize::8 0 # categorize write packet sizes 111system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 112system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 113system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::6 3870 # categorize neither packet sizes 118system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 120system.physmem.rdQLenPdf::0 177383 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::1 21698 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::2 8154 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::3 2813 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::4 2817 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::5 2133 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::6 1311 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::7 1520 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::8 1375 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::9 1300 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::10 1219 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::11 1111 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::12 1091 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::13 864 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::14 470 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::15 266 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::16 194 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::17 116 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 153system.physmem.wrQLenPdf::0 5738 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::1 6395 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::2 6494 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::3 6512 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::4 6522 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::5 6525 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::6 6530 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::7 6530 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::8 6530 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::9 6531 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::10 6531 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::11 6531 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::12 6531 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::13 6531 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::14 6531 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::15 6531 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::16 6531 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::17 6531 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::18 6531 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::19 6530 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::20 6530 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::21 6530 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::22 6530 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::23 793 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::24 136 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::28 6 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 186system.physmem.totQLat 3329517724 # Total cycles spent in queuing delays 187system.physmem.totMemAccLat 7605839724 # Sum of mem lat for all requests 188system.physmem.totBusLat 903876000 # Total cycles spent in databus access 189system.physmem.totBankLat 3372446000 # Total cycles spent in bank access 190system.physmem.avgQLat 14734.40 # Average queueing delay per request 191system.physmem.avgBankLat 14924.37 # Average bank access latency per request 192system.physmem.avgBusLat 4000.00 # Average bus latency per request 193system.physmem.avgMemAccLat 33658.77 # Average memory access latency 194system.physmem.avgRdBW 2.82 # Average achieved read bandwidth in MB/s 195system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s 196system.physmem.avgConsumedRdBW 2.82 # Average consumed read bandwidth in MB/s 197system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s 198system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 199system.physmem.busUtil 0.03 # Data bus utilization in percentage 200system.physmem.avgRdQLen 0.00 # Average read queue length over time 201system.physmem.avgWrQLen 14.06 # Average write queue length over time 202system.physmem.readRowHits 199198 # Number of row buffer hits during reads 203system.physmem.writeRowHits 88428 # Number of row buffer hits during writes 204system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads 205system.physmem.writeRowHitRate 58.87 # Row buffer hit rate for writes 206system.physmem.avgGap 13631091.58 # Average gap between requests 207system.iocache.replacements 47576 # number of replacements 208system.iocache.tagsinuse 0.091613 # Cycle average of tags in use 209system.iocache.total_refs 0 # Total number of references to valid blocks. 210system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. 211system.iocache.avg_refs 0 # Average number of references to valid blocks. 212system.iocache.warmup_cycle 4991895066000 # Cycle when the warmup percentage was hit. 213system.iocache.occ_blocks::pc.south_bridge.ide 0.091613 # Average occupied blocks per requestor 214system.iocache.occ_percent::pc.south_bridge.ide 0.005726 # Average percentage of cache occupancy 215system.iocache.occ_percent::total 0.005726 # Average percentage of cache occupancy 216system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses 217system.iocache.ReadReq_misses::total 911 # number of ReadReq misses 218system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 219system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 220system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses 221system.iocache.demand_misses::total 47631 # number of demand (read+write) misses 222system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses 223system.iocache.overall_misses::total 47631 # number of overall misses 224system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143697932 # number of ReadReq miss cycles 225system.iocache.ReadReq_miss_latency::total 143697932 # number of ReadReq miss cycles 226system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8983849160 # number of WriteReq miss cycles 227system.iocache.WriteReq_miss_latency::total 8983849160 # number of WriteReq miss cycles 228system.iocache.demand_miss_latency::pc.south_bridge.ide 9127547092 # number of demand (read+write) miss cycles 229system.iocache.demand_miss_latency::total 9127547092 # number of demand (read+write) miss cycles 230system.iocache.overall_miss_latency::pc.south_bridge.ide 9127547092 # number of overall miss cycles 231system.iocache.overall_miss_latency::total 9127547092 # number of overall miss cycles 232system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) 233system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) 234system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 235system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 236system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses 237system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses 238system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses 239system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses 240system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 241system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 242system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 243system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 244system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 245system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 246system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 247system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 248system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157736.478595 # average ReadReq miss latency 249system.iocache.ReadReq_avg_miss_latency::total 157736.478595 # average ReadReq miss latency 250system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 192291.291952 # average WriteReq miss latency 251system.iocache.WriteReq_avg_miss_latency::total 192291.291952 # average WriteReq miss latency 252system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency 253system.iocache.demand_avg_miss_latency::total 191630.389704 # average overall miss latency 254system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 191630.389704 # average overall miss latency 255system.iocache.overall_avg_miss_latency::total 191630.389704 # average overall miss latency 256system.iocache.blocked_cycles::no_mshrs 56345 # number of cycles access was blocked 257system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 258system.iocache.blocked::no_mshrs 7566 # number of cycles access was blocked 259system.iocache.blocked::no_targets 0 # number of cycles access was blocked 260system.iocache.avg_blocked_cycles::no_mshrs 7.447132 # average number of cycles each access was blocked 261system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 262system.iocache.fast_writes 0 # number of fast writes performed 263system.iocache.cache_copies 0 # number of cache copies performed 264system.iocache.writebacks::writebacks 46667 # number of writebacks 265system.iocache.writebacks::total 46667 # number of writebacks 266system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses 267system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses 268system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 269system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 270system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses 271system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses 272system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses 273system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses 274system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96295990 # number of ReadReq MSHR miss cycles 275system.iocache.ReadReq_mshr_miss_latency::total 96295990 # number of ReadReq MSHR miss cycles 276system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6552154765 # number of WriteReq MSHR miss cycles 277system.iocache.WriteReq_mshr_miss_latency::total 6552154765 # number of WriteReq MSHR miss cycles 278system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of demand (read+write) MSHR miss cycles 279system.iocache.demand_mshr_miss_latency::total 6648450755 # number of demand (read+write) MSHR miss cycles 280system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6648450755 # number of overall MSHR miss cycles 281system.iocache.overall_mshr_miss_latency::total 6648450755 # number of overall MSHR miss cycles 282system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 283system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 284system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 285system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 286system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 287system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 288system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 289system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 290system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105703.611416 # average ReadReq mshr miss latency 291system.iocache.ReadReq_avg_mshr_miss_latency::total 105703.611416 # average ReadReq mshr miss latency 292system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 140243.038634 # average WriteReq mshr miss latency 293system.iocache.WriteReq_avg_mshr_miss_latency::total 140243.038634 # average WriteReq mshr miss latency 294system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency 295system.iocache.demand_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency 296system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 139582.430665 # average overall mshr miss latency 297system.iocache.overall_avg_mshr_miss_latency::total 139582.430665 # average overall mshr miss latency 298system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 299system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 300system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 301system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 302system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 303system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 304system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 305system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 306system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 307system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 308system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 309system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 310system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 311system.cpu.numCycles 448887765 # number of cpu cycles simulated 312system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 313system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 314system.cpu.BPredUnit.lookups 86493598 # Number of BP lookups 315system.cpu.BPredUnit.condPredicted 86493598 # Number of conditional branches predicted 316system.cpu.BPredUnit.condIncorrect 1184200 # Number of conditional branches incorrect 317system.cpu.BPredUnit.BTBLookups 81985656 # Number of BTB lookups 318system.cpu.BPredUnit.BTBHits 79438611 # Number of BTB hits 319system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 320system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 321system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 322system.cpu.fetch.icacheStallCycles 28044653 # Number of cycles fetch is stalled on an Icache miss 323system.cpu.fetch.Insts 427268280 # Number of instructions fetch has processed 324system.cpu.fetch.Branches 86493598 # Number of branches that fetch encountered 325system.cpu.fetch.predictedBranches 79438611 # Number of branches that fetch has predicted taken 326system.cpu.fetch.Cycles 164008180 # Number of cycles fetch has run and was not squashing or blocked 327system.cpu.fetch.SquashCycles 5056188 # Number of cycles fetch has spent squashing 328system.cpu.fetch.TlbCycles 124973 # Number of cycles fetch has spent waiting for tlb 329system.cpu.fetch.BlockedCycles 62751260 # Number of cycles fetch has spent blocked 330system.cpu.fetch.MiscStallCycles 36198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 331system.cpu.fetch.PendingTrapStallCycles 62335 # Number of stall cycles due to pending traps 332system.cpu.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR 333system.cpu.fetch.CacheLines 9257771 # Number of cache lines fetched 334system.cpu.fetch.IcacheSquashes 519239 # Number of outstanding Icache misses that were squashed 335system.cpu.fetch.ItlbSquashes 3803 # Number of outstanding ITLB misses that were squashed 336system.cpu.fetch.rateDist::samples 258861392 # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::mean 3.258152 # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::stdev 3.417945 # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::0 95283812 36.81% 36.81% # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::1 1591927 0.61% 37.42% # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::2 71954404 27.80% 65.22% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::3 971846 0.38% 65.60% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::4 1615863 0.62% 66.22% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::5 2450126 0.95% 67.17% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::6 1121647 0.43% 67.60% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::7 1424659 0.55% 68.15% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::8 82447108 31.85% 100.00% # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::total 258861392 # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.branchRate 0.192684 # Number of branch fetches per cycle 354system.cpu.fetch.rate 0.951838 # Number of inst fetches per cycle 355system.cpu.decode.IdleCycles 31762033 # Number of cycles decode is idle 356system.cpu.decode.BlockedCycles 60235448 # Number of cycles decode is blocked 357system.cpu.decode.RunCycles 159762632 # Number of cycles decode is running 358system.cpu.decode.UnblockCycles 3267698 # Number of cycles decode is unblocking 359system.cpu.decode.SquashCycles 3833581 # Number of cycles decode is squashing 360system.cpu.decode.DecodedInsts 840104917 # Number of instructions handled by decode 361system.cpu.decode.SquashedInsts 1244 # Number of squashed instructions handled by decode 362system.cpu.rename.SquashCycles 3833581 # Number of cycles rename is squashing 363system.cpu.rename.IdleCycles 34530134 # Number of cycles rename is idle 364system.cpu.rename.BlockCycles 37412206 # Number of cycles rename is blocking 365system.cpu.rename.serializeStallCycles 10702091 # count of cycles rename stalled for serializing inst 366system.cpu.rename.RunCycles 159938633 # Number of cycles rename is running 367system.cpu.rename.UnblockCycles 12444747 # Number of cycles rename is unblocking 368system.cpu.rename.RenamedInsts 836257763 # Number of instructions processed by rename 369system.cpu.rename.ROBFullEvents 19698 # Number of times rename has blocked due to ROB full 370system.cpu.rename.IQFullEvents 5896480 # Number of times rename has blocked due to IQ full 371system.cpu.rename.LSQFullEvents 4716940 # Number of times rename has blocked due to LSQ full 372system.cpu.rename.FullRegisterEvents 7816 # Number of times there has been no free registers 373system.cpu.rename.RenamedOperands 997992319 # Number of destination operands rename has renamed 374system.cpu.rename.RenameLookups 1816026440 # Number of register rename lookups that rename has made 375system.cpu.rename.int_rename_lookups 1816025416 # Number of integer rename lookups 376system.cpu.rename.fp_rename_lookups 1024 # Number of floating rename lookups 377system.cpu.rename.CommittedMaps 964353103 # Number of HB maps that are committed 378system.cpu.rename.UndoneMaps 33639209 # Number of HB maps that are undone due to squashing 379system.cpu.rename.serializingInsts 466352 # count of serializing insts renamed 380system.cpu.rename.tempSerializingInsts 473282 # count of temporary serializing insts renamed 381system.cpu.rename.skidInsts 28808345 # count of insts added to the skid buffer 382system.cpu.memDep0.insertedLoads 17312855 # Number of loads inserted to the mem dependence unit. 383system.cpu.memDep0.insertedStores 10260076 # Number of stores inserted to the mem dependence unit. 384system.cpu.memDep0.conflictingLoads 1206444 # Number of conflicting loads. 385system.cpu.memDep0.conflictingStores 946818 # Number of conflicting stores. 386system.cpu.iq.iqInstsAdded 829834961 # Number of instructions added to the IQ (excludes non-spec) 387system.cpu.iq.iqNonSpecInstsAdded 1255797 # Number of non-speculative instructions added to the IQ 388system.cpu.iq.iqInstsIssued 824342965 # Number of instructions issued 389system.cpu.iq.iqSquashedInstsIssued 165215 # Number of squashed instructions issued 390system.cpu.iq.iqSquashedInstsExamined 23689940 # Number of squashed instructions iterated over during squash; mainly for profiling 391system.cpu.iq.iqSquashedOperandsExamined 36113140 # Number of squashed operands that are examined and possibly removed from graph 392system.cpu.iq.iqSquashedNonSpecRemoved 203193 # Number of squashed non-spec instructions that were removed 393system.cpu.iq.issued_per_cycle::samples 258861392 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::mean 3.184496 # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::stdev 2.385380 # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::0 72001826 27.81% 27.81% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::1 15596239 6.02% 33.84% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::2 10365970 4.00% 37.84% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::3 7555139 2.92% 40.76% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::4 75952295 29.34% 70.10% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::5 3901347 1.51% 71.61% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::6 72539766 28.02% 99.63% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::7 795622 0.31% 99.94% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::8 153188 0.06% 100.00% # Number of insts issued each cycle 406system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 409system.cpu.iq.issued_per_cycle::total 258861392 # Number of insts issued each cycle 410system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 411system.cpu.iq.fu_full::IntAlu 354431 33.41% 33.41% # attempts to use FU when none available 412system.cpu.iq.fu_full::IntMult 0 0.00% 33.41% # attempts to use FU when none available 413system.cpu.iq.fu_full::IntDiv 0 0.00% 33.41% # attempts to use FU when none available 414system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.41% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.41% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.41% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatMult 0 0.00% 33.41% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.41% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.41% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.41% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.41% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.41% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.41% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.41% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.41% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdMult 0 0.00% 33.41% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.41% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdShift 0 0.00% 33.41% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.41% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.41% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.41% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.41% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.41% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.41% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.41% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.41% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.41% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.41% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.41% # attempts to use FU when none available 440system.cpu.iq.fu_full::MemRead 554175 52.24% 85.65% # attempts to use FU when none available 441system.cpu.iq.fu_full::MemWrite 152275 14.35% 100.00% # attempts to use FU when none available 442system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 443system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 444system.cpu.iq.FU_type_0::No_OpClass 306719 0.04% 0.04% # Type of FU issued 445system.cpu.iq.FU_type_0::IntAlu 796534260 96.63% 96.66% # Type of FU issued 446system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued 447system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.66% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued 474system.cpu.iq.FU_type_0::MemRead 18029662 2.19% 98.85% # Type of FU issued 475system.cpu.iq.FU_type_0::MemWrite 9472324 1.15% 100.00% # Type of FU issued 476system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 478system.cpu.iq.FU_type_0::total 824342965 # Type of FU issued 479system.cpu.iq.rate 1.836412 # Inst issue rate 480system.cpu.iq.fu_busy_cnt 1060881 # FU busy when requested 481system.cpu.iq.fu_busy_rate 0.001287 # FU busy rate (busy events/executed inst) 482system.cpu.iq.int_inst_queue_reads 1908906757 # Number of integer instruction queue reads 483system.cpu.iq.int_inst_queue_writes 854790380 # Number of integer instruction queue writes 484system.cpu.iq.int_inst_queue_wakeup_accesses 819662460 # Number of integer instruction queue wakeup accesses 485system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads 486system.cpu.iq.fp_inst_queue_writes 438 # Number of floating instruction queue writes 487system.cpu.iq.fp_inst_queue_wakeup_accesses 58 # Number of floating instruction queue wakeup accesses 488system.cpu.iq.int_alu_accesses 825097030 # Number of integer alu accesses 489system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses 490system.cpu.iew.lsq.thread0.forwLoads 1650086 # Number of loads that had data forwarded from stores 491system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 492system.cpu.iew.lsq.thread0.squashedLoads 3338406 # Number of loads squashed 493system.cpu.iew.lsq.thread0.ignoredResponses 26898 # Number of memory responses ignored because the instruction is squashed 494system.cpu.iew.lsq.thread0.memOrderViolation 11294 # Number of memory ordering violations 495system.cpu.iew.lsq.thread0.squashedStores 1845192 # Number of stores squashed 496system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 497system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 498system.cpu.iew.lsq.thread0.rescheduledLoads 1932288 # Number of loads that were rescheduled 499system.cpu.iew.lsq.thread0.cacheBlocked 11793 # Number of times an access to memory failed due to the cache being blocked 500system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 501system.cpu.iew.iewSquashCycles 3833581 # Number of cycles IEW is squashing 502system.cpu.iew.iewBlockCycles 26182715 # Number of cycles IEW is blocking 503system.cpu.iew.iewUnblockCycles 2118325 # Number of cycles IEW is unblocking 504system.cpu.iew.iewDispatchedInsts 831090758 # Number of instructions dispatched to IQ 505system.cpu.iew.iewDispSquashedInsts 325842 # Number of squashed instructions skipped by dispatch 506system.cpu.iew.iewDispLoadInsts 17312855 # Number of dispatched load instructions 507system.cpu.iew.iewDispStoreInsts 10260082 # Number of dispatched store instructions 508system.cpu.iew.iewDispNonSpecInsts 724912 # Number of dispatched non-speculative instructions 509system.cpu.iew.iewIQFullEvents 1616921 # Number of times the IQ has become full, causing a stall 510system.cpu.iew.iewLSQFullEvents 15962 # Number of times the LSQ has become full, causing a stall 511system.cpu.iew.memOrderViolationEvents 11294 # Number of memory order violations 512system.cpu.iew.predictedTakenIncorrect 708686 # Number of branches that were predicted taken incorrectly 513system.cpu.iew.predictedNotTakenIncorrect 624381 # Number of branches that were predicted not taken incorrectly 514system.cpu.iew.branchMispredicts 1333067 # Number of branch mispredicts detected at execute 515system.cpu.iew.iewExecutedInsts 822327193 # Number of executed instructions 516system.cpu.iew.iewExecLoadInsts 17600649 # Number of load instructions executed 517system.cpu.iew.iewExecSquashedInsts 2015771 # Number of squashed instructions skipped in execute 518system.cpu.iew.exec_swp 0 # number of swp insts executed 519system.cpu.iew.exec_nop 0 # number of nop insts executed 520system.cpu.iew.exec_refs 26823265 # number of memory reference insts executed 521system.cpu.iew.exec_branches 83275848 # Number of branches executed 522system.cpu.iew.exec_stores 9222616 # Number of stores executed 523system.cpu.iew.exec_rate 1.831922 # Inst execution rate 524system.cpu.iew.wb_sent 821819072 # cumulative count of insts sent to commit 525system.cpu.iew.wb_count 819662518 # cumulative count of insts written-back 526system.cpu.iew.wb_producers 640525310 # num instructions producing a value 527system.cpu.iew.wb_consumers 1046521436 # num instructions consuming a value 528system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 529system.cpu.iew.wb_rate 1.825985 # insts written-back per cycle 530system.cpu.iew.wb_fanout 0.612052 # average fanout of values written-back 531system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 532system.cpu.commit.commitSquashedInsts 24603279 # The number of squashed insts skipped by commit 533system.cpu.commit.commitNonSpecStalls 1052602 # The number of times commit has been forced to stall to communicate backwards 534system.cpu.commit.branchMispredicts 1189396 # The number of times a branch was mispredicted 535system.cpu.commit.committed_per_cycle::samples 255043204 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::mean 3.161744 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::stdev 2.853415 # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::0 83146159 32.60% 32.60% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::1 11856679 4.65% 37.25% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::2 3955758 1.55% 38.80% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::3 74970525 29.40% 68.20% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::4 2479858 0.97% 69.17% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::5 1486016 0.58% 69.75% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::6 951787 0.37% 70.12% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::7 70929950 27.81% 97.94% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::8 5266472 2.06% 100.00% # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::total 255043204 # Number of insts commited each cycle 552system.cpu.commit.committedInsts 407937807 # Number of instructions committed 553system.cpu.commit.committedOps 806381430 # Number of ops (including micro ops) committed 554system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 555system.cpu.commit.refs 22389336 # Number of memory references committed 556system.cpu.commit.loads 13974446 # Number of loads committed 557system.cpu.commit.membars 473457 # Number of memory barriers committed 558system.cpu.commit.branches 82191509 # Number of branches committed 559system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 560system.cpu.commit.int_insts 735317730 # Number of committed integer instructions. 561system.cpu.commit.function_calls 0 # Number of function calls committed. 562system.cpu.commit.bw_lim_events 5266472 # number cycles where commit BW limit reached 563system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 564system.cpu.rob.rob_reads 1080683249 # The number of ROB reads 565system.cpu.rob.rob_writes 1665823647 # The number of ROB writes 566system.cpu.timesIdled 1223181 # Number of times that the entire CPU went into an idle state and unscheduled itself 567system.cpu.idleCycles 190026373 # Total number of cycles that the CPU has spent unscheduled due to idling 568system.cpu.quiesceCycles 9808860643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 569system.cpu.committedInsts 407937807 # Number of Instructions Simulated 570system.cpu.committedOps 806381430 # Number of Ops (including micro ops) Simulated 571system.cpu.committedInsts_total 407937807 # Number of Instructions Simulated 572system.cpu.cpi 1.100383 # CPI: Cycles Per Instruction 573system.cpu.cpi_total 1.100383 # CPI: Total CPI of All Threads 574system.cpu.ipc 0.908775 # IPC: Instructions Per Cycle 575system.cpu.ipc_total 0.908775 # IPC: Total IPC of All Threads 576system.cpu.int_regfile_reads 1508172140 # number of integer regfile reads 577system.cpu.int_regfile_writes 977803744 # number of integer regfile writes 578system.cpu.fp_regfile_reads 58 # number of floating regfile reads 579system.cpu.misc_regfile_reads 265152690 # number of misc regfile reads 580system.cpu.misc_regfile_writes 402177 # number of misc regfile writes 581system.cpu.icache.replacements 1074366 # number of replacements 582system.cpu.icache.tagsinuse 510.322538 # Cycle average of tags in use 583system.cpu.icache.total_refs 8113553 # Total number of references to valid blocks. 584system.cpu.icache.sampled_refs 1074878 # Sample count of references to valid blocks. 585system.cpu.icache.avg_refs 7.548348 # Average number of references to valid blocks. 586system.cpu.icache.warmup_cycle 56079311000 # Cycle when the warmup percentage was hit. 587system.cpu.icache.occ_blocks::cpu.inst 510.322538 # Average occupied blocks per requestor 588system.cpu.icache.occ_percent::cpu.inst 0.996724 # Average percentage of cache occupancy 589system.cpu.icache.occ_percent::total 0.996724 # Average percentage of cache occupancy 590system.cpu.icache.ReadReq_hits::cpu.inst 8113553 # number of ReadReq hits 591system.cpu.icache.ReadReq_hits::total 8113553 # number of ReadReq hits 592system.cpu.icache.demand_hits::cpu.inst 8113553 # number of demand (read+write) hits 593system.cpu.icache.demand_hits::total 8113553 # number of demand (read+write) hits 594system.cpu.icache.overall_hits::cpu.inst 8113553 # number of overall hits 595system.cpu.icache.overall_hits::total 8113553 # number of overall hits 596system.cpu.icache.ReadReq_misses::cpu.inst 1144218 # number of ReadReq misses 597system.cpu.icache.ReadReq_misses::total 1144218 # number of ReadReq misses 598system.cpu.icache.demand_misses::cpu.inst 1144218 # number of demand (read+write) misses 599system.cpu.icache.demand_misses::total 1144218 # number of demand (read+write) misses 600system.cpu.icache.overall_misses::cpu.inst 1144218 # number of overall misses 601system.cpu.icache.overall_misses::total 1144218 # number of overall misses 602system.cpu.icache.ReadReq_miss_latency::cpu.inst 15461286493 # number of ReadReq miss cycles 603system.cpu.icache.ReadReq_miss_latency::total 15461286493 # number of ReadReq miss cycles 604system.cpu.icache.demand_miss_latency::cpu.inst 15461286493 # number of demand (read+write) miss cycles 605system.cpu.icache.demand_miss_latency::total 15461286493 # number of demand (read+write) miss cycles 606system.cpu.icache.overall_miss_latency::cpu.inst 15461286493 # number of overall miss cycles 607system.cpu.icache.overall_miss_latency::total 15461286493 # number of overall miss cycles 608system.cpu.icache.ReadReq_accesses::cpu.inst 9257771 # number of ReadReq accesses(hits+misses) 609system.cpu.icache.ReadReq_accesses::total 9257771 # number of ReadReq accesses(hits+misses) 610system.cpu.icache.demand_accesses::cpu.inst 9257771 # number of demand (read+write) accesses 611system.cpu.icache.demand_accesses::total 9257771 # number of demand (read+write) accesses 612system.cpu.icache.overall_accesses::cpu.inst 9257771 # number of overall (read+write) accesses 613system.cpu.icache.overall_accesses::total 9257771 # number of overall (read+write) accesses 614system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123595 # miss rate for ReadReq accesses 615system.cpu.icache.ReadReq_miss_rate::total 0.123595 # miss rate for ReadReq accesses 616system.cpu.icache.demand_miss_rate::cpu.inst 0.123595 # miss rate for demand accesses 617system.cpu.icache.demand_miss_rate::total 0.123595 # miss rate for demand accesses 618system.cpu.icache.overall_miss_rate::cpu.inst 0.123595 # miss rate for overall accesses 619system.cpu.icache.overall_miss_rate::total 0.123595 # miss rate for overall accesses 620system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13512.535630 # average ReadReq miss latency 621system.cpu.icache.ReadReq_avg_miss_latency::total 13512.535630 # average ReadReq miss latency 622system.cpu.icache.demand_avg_miss_latency::cpu.inst 13512.535630 # average overall miss latency 623system.cpu.icache.demand_avg_miss_latency::total 13512.535630 # average overall miss latency 624system.cpu.icache.overall_avg_miss_latency::cpu.inst 13512.535630 # average overall miss latency 625system.cpu.icache.overall_avg_miss_latency::total 13512.535630 # average overall miss latency 626system.cpu.icache.blocked_cycles::no_mshrs 7080 # number of cycles access was blocked 627system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 628system.cpu.icache.blocked::no_mshrs 251 # number of cycles access was blocked 629system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 630system.cpu.icache.avg_blocked_cycles::no_mshrs 28.207171 # average number of cycles each access was blocked 631system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 632system.cpu.icache.fast_writes 0 # number of fast writes performed 633system.cpu.icache.cache_copies 0 # number of cache copies performed 634system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67124 # number of ReadReq MSHR hits 635system.cpu.icache.ReadReq_mshr_hits::total 67124 # number of ReadReq MSHR hits 636system.cpu.icache.demand_mshr_hits::cpu.inst 67124 # number of demand (read+write) MSHR hits 637system.cpu.icache.demand_mshr_hits::total 67124 # number of demand (read+write) MSHR hits 638system.cpu.icache.overall_mshr_hits::cpu.inst 67124 # number of overall MSHR hits 639system.cpu.icache.overall_mshr_hits::total 67124 # number of overall MSHR hits 640system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077094 # number of ReadReq MSHR misses 641system.cpu.icache.ReadReq_mshr_misses::total 1077094 # number of ReadReq MSHR misses 642system.cpu.icache.demand_mshr_misses::cpu.inst 1077094 # number of demand (read+write) MSHR misses 643system.cpu.icache.demand_mshr_misses::total 1077094 # number of demand (read+write) MSHR misses 644system.cpu.icache.overall_mshr_misses::cpu.inst 1077094 # number of overall MSHR misses 645system.cpu.icache.overall_mshr_misses::total 1077094 # number of overall MSHR misses 646system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12721673493 # number of ReadReq MSHR miss cycles 647system.cpu.icache.ReadReq_mshr_miss_latency::total 12721673493 # number of ReadReq MSHR miss cycles 648system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12721673493 # number of demand (read+write) MSHR miss cycles 649system.cpu.icache.demand_mshr_miss_latency::total 12721673493 # number of demand (read+write) MSHR miss cycles 650system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12721673493 # number of overall MSHR miss cycles 651system.cpu.icache.overall_mshr_miss_latency::total 12721673493 # number of overall MSHR miss cycles 652system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for ReadReq accesses 653system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116345 # mshr miss rate for ReadReq accesses 654system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for demand accesses 655system.cpu.icache.demand_mshr_miss_rate::total 0.116345 # mshr miss rate for demand accesses 656system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116345 # mshr miss rate for overall accesses 657system.cpu.icache.overall_mshr_miss_rate::total 0.116345 # mshr miss rate for overall accesses 658system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11811.107938 # average ReadReq mshr miss latency 659system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11811.107938 # average ReadReq mshr miss latency 660system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11811.107938 # average overall mshr miss latency 661system.cpu.icache.demand_avg_mshr_miss_latency::total 11811.107938 # average overall mshr miss latency 662system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11811.107938 # average overall mshr miss latency 663system.cpu.icache.overall_avg_mshr_miss_latency::total 11811.107938 # average overall mshr miss latency 664system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 665system.cpu.itb_walker_cache.replacements 10271 # number of replacements 666system.cpu.itb_walker_cache.tagsinuse 6.965877 # Cycle average of tags in use 667system.cpu.itb_walker_cache.total_refs 29367 # Total number of references to valid blocks. 668system.cpu.itb_walker_cache.sampled_refs 10284 # Sample count of references to valid blocks. 669system.cpu.itb_walker_cache.avg_refs 2.855601 # Average number of references to valid blocks. 670system.cpu.itb_walker_cache.warmup_cycle 5103910768500 # Cycle when the warmup percentage was hit. 671system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.965877 # Average occupied blocks per requestor 672system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.435367 # Average percentage of cache occupancy 673system.cpu.itb_walker_cache.occ_percent::total 0.435367 # Average percentage of cache occupancy 674system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 29379 # number of ReadReq hits 675system.cpu.itb_walker_cache.ReadReq_hits::total 29379 # number of ReadReq hits 676system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits 677system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits 678system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 29382 # number of demand (read+write) hits 679system.cpu.itb_walker_cache.demand_hits::total 29382 # number of demand (read+write) hits 680system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 29382 # number of overall hits 681system.cpu.itb_walker_cache.overall_hits::total 29382 # number of overall hits 682system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11163 # number of ReadReq misses 683system.cpu.itb_walker_cache.ReadReq_misses::total 11163 # number of ReadReq misses 684system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11163 # number of demand (read+write) misses 685system.cpu.itb_walker_cache.demand_misses::total 11163 # number of demand (read+write) misses 686system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11163 # number of overall misses 687system.cpu.itb_walker_cache.overall_misses::total 11163 # number of overall misses 688system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 123160000 # number of ReadReq miss cycles 689system.cpu.itb_walker_cache.ReadReq_miss_latency::total 123160000 # number of ReadReq miss cycles 690system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 123160000 # number of demand (read+write) miss cycles 691system.cpu.itb_walker_cache.demand_miss_latency::total 123160000 # number of demand (read+write) miss cycles 692system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 123160000 # number of overall miss cycles 693system.cpu.itb_walker_cache.overall_miss_latency::total 123160000 # number of overall miss cycles 694system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 40542 # number of ReadReq accesses(hits+misses) 695system.cpu.itb_walker_cache.ReadReq_accesses::total 40542 # number of ReadReq accesses(hits+misses) 696system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) 697system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 698system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 40545 # number of demand (read+write) accesses 699system.cpu.itb_walker_cache.demand_accesses::total 40545 # number of demand (read+write) accesses 700system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 40545 # number of overall (read+write) accesses 701system.cpu.itb_walker_cache.overall_accesses::total 40545 # number of overall (read+write) accesses 702system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275344 # miss rate for ReadReq accesses 703system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275344 # miss rate for ReadReq accesses 704system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275324 # miss rate for demand accesses 705system.cpu.itb_walker_cache.demand_miss_rate::total 0.275324 # miss rate for demand accesses 706system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275324 # miss rate for overall accesses 707system.cpu.itb_walker_cache.overall_miss_rate::total 0.275324 # miss rate for overall accesses 708system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11032.876467 # average ReadReq miss latency 709system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11032.876467 # average ReadReq miss latency 710system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency 711system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11032.876467 # average overall miss latency 712system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11032.876467 # average overall miss latency 713system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11032.876467 # average overall miss latency 714system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 715system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 716system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 717system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 718system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 719system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 720system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 721system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 722system.cpu.itb_walker_cache.writebacks::writebacks 1731 # number of writebacks 723system.cpu.itb_walker_cache.writebacks::total 1731 # number of writebacks 724system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11163 # number of ReadReq MSHR misses 725system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11163 # number of ReadReq MSHR misses 726system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11163 # number of demand (read+write) MSHR misses 727system.cpu.itb_walker_cache.demand_mshr_misses::total 11163 # number of demand (read+write) MSHR misses 728system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11163 # number of overall MSHR misses 729system.cpu.itb_walker_cache.overall_mshr_misses::total 11163 # number of overall MSHR misses 730system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 100834000 # number of ReadReq MSHR miss cycles 731system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 100834000 # number of ReadReq MSHR miss cycles 732system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 100834000 # number of demand (read+write) MSHR miss cycles 733system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 100834000 # number of demand (read+write) MSHR miss cycles 734system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 100834000 # number of overall MSHR miss cycles 735system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 100834000 # number of overall MSHR miss cycles 736system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275344 # mshr miss rate for ReadReq accesses 737system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275344 # mshr miss rate for ReadReq accesses 738system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for demand accesses 739system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275324 # mshr miss rate for demand accesses 740system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275324 # mshr miss rate for overall accesses 741system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275324 # mshr miss rate for overall accesses 742system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average ReadReq mshr miss latency 743system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9032.876467 # average ReadReq mshr miss latency 744system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency 745system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency 746system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9032.876467 # average overall mshr miss latency 747system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9032.876467 # average overall mshr miss latency 748system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 749system.cpu.dtb_walker_cache.replacements 109401 # number of replacements 750system.cpu.dtb_walker_cache.tagsinuse 13.751867 # Cycle average of tags in use 751system.cpu.dtb_walker_cache.total_refs 137796 # Total number of references to valid blocks. 752system.cpu.dtb_walker_cache.sampled_refs 109417 # Sample count of references to valid blocks. 753system.cpu.dtb_walker_cache.avg_refs 1.259366 # Average number of references to valid blocks. 754system.cpu.dtb_walker_cache.warmup_cycle 5100515626500 # Cycle when the warmup percentage was hit. 755system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.751867 # Average occupied blocks per requestor 756system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.859492 # Average percentage of cache occupancy 757system.cpu.dtb_walker_cache.occ_percent::total 0.859492 # Average percentage of cache occupancy 758system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 137796 # number of ReadReq hits 759system.cpu.dtb_walker_cache.ReadReq_hits::total 137796 # number of ReadReq hits 760system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 137796 # number of demand (read+write) hits 761system.cpu.dtb_walker_cache.demand_hits::total 137796 # number of demand (read+write) hits 762system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 137796 # number of overall hits 763system.cpu.dtb_walker_cache.overall_hits::total 137796 # number of overall hits 764system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110443 # number of ReadReq misses 765system.cpu.dtb_walker_cache.ReadReq_misses::total 110443 # number of ReadReq misses 766system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110443 # number of demand (read+write) misses 767system.cpu.dtb_walker_cache.demand_misses::total 110443 # number of demand (read+write) misses 768system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110443 # number of overall misses 769system.cpu.dtb_walker_cache.overall_misses::total 110443 # number of overall misses 770system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1382584000 # number of ReadReq miss cycles 771system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1382584000 # number of ReadReq miss cycles 772system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1382584000 # number of demand (read+write) miss cycles 773system.cpu.dtb_walker_cache.demand_miss_latency::total 1382584000 # number of demand (read+write) miss cycles 774system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1382584000 # number of overall miss cycles 775system.cpu.dtb_walker_cache.overall_miss_latency::total 1382584000 # number of overall miss cycles 776system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 248239 # number of ReadReq accesses(hits+misses) 777system.cpu.dtb_walker_cache.ReadReq_accesses::total 248239 # number of ReadReq accesses(hits+misses) 778system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 248239 # number of demand (read+write) accesses 779system.cpu.dtb_walker_cache.demand_accesses::total 248239 # number of demand (read+write) accesses 780system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248239 # number of overall (read+write) accesses 781system.cpu.dtb_walker_cache.overall_accesses::total 248239 # number of overall (read+write) accesses 782system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.444906 # miss rate for ReadReq accesses 783system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.444906 # miss rate for ReadReq accesses 784system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.444906 # miss rate for demand accesses 785system.cpu.dtb_walker_cache.demand_miss_rate::total 0.444906 # miss rate for demand accesses 786system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.444906 # miss rate for overall accesses 787system.cpu.dtb_walker_cache.overall_miss_rate::total 0.444906 # miss rate for overall accesses 788system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12518.529920 # average ReadReq miss latency 789system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12518.529920 # average ReadReq miss latency 790system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency 791system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12518.529920 # average overall miss latency 792system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12518.529920 # average overall miss latency 793system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12518.529920 # average overall miss latency 794system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 795system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 796system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 797system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 798system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 799system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 800system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 801system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 802system.cpu.dtb_walker_cache.writebacks::writebacks 36585 # number of writebacks 803system.cpu.dtb_walker_cache.writebacks::total 36585 # number of writebacks 804system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110443 # number of ReadReq MSHR misses 805system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110443 # number of ReadReq MSHR misses 806system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110443 # number of demand (read+write) MSHR misses 807system.cpu.dtb_walker_cache.demand_mshr_misses::total 110443 # number of demand (read+write) MSHR misses 808system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110443 # number of overall MSHR misses 809system.cpu.dtb_walker_cache.overall_mshr_misses::total 110443 # number of overall MSHR misses 810system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of ReadReq MSHR miss cycles 811system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1161698000 # number of ReadReq MSHR miss cycles 812system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of demand (read+write) MSHR miss cycles 813system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1161698000 # number of demand (read+write) MSHR miss cycles 814system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1161698000 # number of overall MSHR miss cycles 815system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1161698000 # number of overall MSHR miss cycles 816system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for ReadReq accesses 817system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.444906 # mshr miss rate for ReadReq accesses 818system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for demand accesses 819system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.444906 # mshr miss rate for demand accesses 820system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.444906 # mshr miss rate for overall accesses 821system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.444906 # mshr miss rate for overall accesses 822system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average ReadReq mshr miss latency 823system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10518.529920 # average ReadReq mshr miss latency 824system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average overall mshr miss latency 825system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10518.529920 # average overall mshr miss latency 826system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10518.529920 # average overall mshr miss latency 827system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10518.529920 # average overall mshr miss latency 828system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 829system.cpu.dcache.replacements 1672817 # number of replacements 830system.cpu.dcache.tagsinuse 511.996932 # Cycle average of tags in use 831system.cpu.dcache.total_refs 19210877 # Total number of references to valid blocks. 832system.cpu.dcache.sampled_refs 1673329 # Sample count of references to valid blocks. 833system.cpu.dcache.avg_refs 11.480634 # Average number of references to valid blocks. 834system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit. 835system.cpu.dcache.occ_blocks::cpu.data 511.996932 # Average occupied blocks per requestor 836system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 837system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy 838system.cpu.dcache.ReadReq_hits::cpu.data 11119324 # number of ReadReq hits 839system.cpu.dcache.ReadReq_hits::total 11119324 # number of ReadReq hits 840system.cpu.dcache.WriteReq_hits::cpu.data 8086692 # number of WriteReq hits 841system.cpu.dcache.WriteReq_hits::total 8086692 # number of WriteReq hits 842system.cpu.dcache.demand_hits::cpu.data 19206016 # number of demand (read+write) hits 843system.cpu.dcache.demand_hits::total 19206016 # number of demand (read+write) hits 844system.cpu.dcache.overall_hits::cpu.data 19206016 # number of overall hits 845system.cpu.dcache.overall_hits::total 19206016 # number of overall hits 846system.cpu.dcache.ReadReq_misses::cpu.data 2269518 # number of ReadReq misses 847system.cpu.dcache.ReadReq_misses::total 2269518 # number of ReadReq misses 848system.cpu.dcache.WriteReq_misses::cpu.data 318969 # number of WriteReq misses 849system.cpu.dcache.WriteReq_misses::total 318969 # number of WriteReq misses 850system.cpu.dcache.demand_misses::cpu.data 2588487 # number of demand (read+write) misses 851system.cpu.dcache.demand_misses::total 2588487 # number of demand (read+write) misses 852system.cpu.dcache.overall_misses::cpu.data 2588487 # number of overall misses 853system.cpu.dcache.overall_misses::total 2588487 # number of overall misses 854system.cpu.dcache.ReadReq_miss_latency::cpu.data 32394569000 # number of ReadReq miss cycles 855system.cpu.dcache.ReadReq_miss_latency::total 32394569000 # number of ReadReq miss cycles 856system.cpu.dcache.WriteReq_miss_latency::cpu.data 9644667991 # number of WriteReq miss cycles 857system.cpu.dcache.WriteReq_miss_latency::total 9644667991 # number of WriteReq miss cycles 858system.cpu.dcache.demand_miss_latency::cpu.data 42039236991 # number of demand (read+write) miss cycles 859system.cpu.dcache.demand_miss_latency::total 42039236991 # number of demand (read+write) miss cycles 860system.cpu.dcache.overall_miss_latency::cpu.data 42039236991 # number of overall miss cycles 861system.cpu.dcache.overall_miss_latency::total 42039236991 # number of overall miss cycles 862system.cpu.dcache.ReadReq_accesses::cpu.data 13388842 # number of ReadReq accesses(hits+misses) 863system.cpu.dcache.ReadReq_accesses::total 13388842 # number of ReadReq accesses(hits+misses) 864system.cpu.dcache.WriteReq_accesses::cpu.data 8405661 # number of WriteReq accesses(hits+misses) 865system.cpu.dcache.WriteReq_accesses::total 8405661 # number of WriteReq accesses(hits+misses) 866system.cpu.dcache.demand_accesses::cpu.data 21794503 # number of demand (read+write) accesses 867system.cpu.dcache.demand_accesses::total 21794503 # number of demand (read+write) accesses 868system.cpu.dcache.overall_accesses::cpu.data 21794503 # number of overall (read+write) accesses 869system.cpu.dcache.overall_accesses::total 21794503 # number of overall (read+write) accesses 870system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169508 # miss rate for ReadReq accesses 871system.cpu.dcache.ReadReq_miss_rate::total 0.169508 # miss rate for ReadReq accesses 872system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037947 # miss rate for WriteReq accesses 873system.cpu.dcache.WriteReq_miss_rate::total 0.037947 # miss rate for WriteReq accesses 874system.cpu.dcache.demand_miss_rate::cpu.data 0.118768 # miss rate for demand accesses 875system.cpu.dcache.demand_miss_rate::total 0.118768 # miss rate for demand accesses 876system.cpu.dcache.overall_miss_rate::cpu.data 0.118768 # miss rate for overall accesses 877system.cpu.dcache.overall_miss_rate::total 0.118768 # miss rate for overall accesses 878system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14273.766060 # average ReadReq miss latency 879system.cpu.dcache.ReadReq_avg_miss_latency::total 14273.766060 # average ReadReq miss latency 880system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30237.007330 # average WriteReq miss latency 881system.cpu.dcache.WriteReq_avg_miss_latency::total 30237.007330 # average WriteReq miss latency 882system.cpu.dcache.demand_avg_miss_latency::cpu.data 16240.853051 # average overall miss latency 883system.cpu.dcache.demand_avg_miss_latency::total 16240.853051 # average overall miss latency 884system.cpu.dcache.overall_avg_miss_latency::cpu.data 16240.853051 # average overall miss latency 885system.cpu.dcache.overall_avg_miss_latency::total 16240.853051 # average overall miss latency 886system.cpu.dcache.blocked_cycles::no_mshrs 395046 # number of cycles access was blocked 887system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 888system.cpu.dcache.blocked::no_mshrs 42533 # number of cycles access was blocked 889system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 890system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.287988 # average number of cycles each access was blocked 891system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu.dcache.fast_writes 0 # number of fast writes performed 893system.cpu.dcache.cache_copies 0 # number of cache copies performed 894system.cpu.dcache.writebacks::writebacks 1572293 # number of writebacks 895system.cpu.dcache.writebacks::total 1572293 # number of writebacks 896system.cpu.dcache.ReadReq_mshr_hits::cpu.data 885972 # number of ReadReq MSHR hits 897system.cpu.dcache.ReadReq_mshr_hits::total 885972 # number of ReadReq MSHR hits 898system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24759 # number of WriteReq MSHR hits 899system.cpu.dcache.WriteReq_mshr_hits::total 24759 # number of WriteReq MSHR hits 900system.cpu.dcache.demand_mshr_hits::cpu.data 910731 # number of demand (read+write) MSHR hits 901system.cpu.dcache.demand_mshr_hits::total 910731 # number of demand (read+write) MSHR hits 902system.cpu.dcache.overall_mshr_hits::cpu.data 910731 # number of overall MSHR hits 903system.cpu.dcache.overall_mshr_hits::total 910731 # number of overall MSHR hits 904system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1383546 # number of ReadReq MSHR misses 905system.cpu.dcache.ReadReq_mshr_misses::total 1383546 # number of ReadReq MSHR misses 906system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294210 # number of WriteReq MSHR misses 907system.cpu.dcache.WriteReq_mshr_misses::total 294210 # number of WriteReq MSHR misses 908system.cpu.dcache.demand_mshr_misses::cpu.data 1677756 # number of demand (read+write) MSHR misses 909system.cpu.dcache.demand_mshr_misses::total 1677756 # number of demand (read+write) MSHR misses 910system.cpu.dcache.overall_mshr_misses::cpu.data 1677756 # number of overall MSHR misses 911system.cpu.dcache.overall_mshr_misses::total 1677756 # number of overall MSHR misses 912system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17475799000 # number of ReadReq MSHR miss cycles 913system.cpu.dcache.ReadReq_mshr_miss_latency::total 17475799000 # number of ReadReq MSHR miss cycles 914system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8804968491 # number of WriteReq MSHR miss cycles 915system.cpu.dcache.WriteReq_mshr_miss_latency::total 8804968491 # number of WriteReq MSHR miss cycles 916system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26280767491 # number of demand (read+write) MSHR miss cycles 917system.cpu.dcache.demand_mshr_miss_latency::total 26280767491 # number of demand (read+write) MSHR miss cycles 918system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26280767491 # number of overall MSHR miss cycles 919system.cpu.dcache.overall_mshr_miss_latency::total 26280767491 # number of overall MSHR miss cycles 920system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296545000 # number of ReadReq MSHR uncacheable cycles 921system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296545000 # number of ReadReq MSHR uncacheable cycles 922system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470181000 # number of WriteReq MSHR uncacheable cycles 923system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470181000 # number of WriteReq MSHR uncacheable cycles 924system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99766726000 # number of overall MSHR uncacheable cycles 925system.cpu.dcache.overall_mshr_uncacheable_latency::total 99766726000 # number of overall MSHR uncacheable cycles 926system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103336 # mshr miss rate for ReadReq accesses 927system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103336 # mshr miss rate for ReadReq accesses 928system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035001 # mshr miss rate for WriteReq accesses 929system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035001 # mshr miss rate for WriteReq accesses 930system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076981 # mshr miss rate for demand accesses 931system.cpu.dcache.demand_mshr_miss_rate::total 0.076981 # mshr miss rate for demand accesses 932system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076981 # mshr miss rate for overall accesses 933system.cpu.dcache.overall_mshr_miss_rate::total 0.076981 # mshr miss rate for overall accesses 934system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12631.165859 # average ReadReq mshr miss latency 935system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12631.165859 # average ReadReq mshr miss latency 936system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29927.495636 # average WriteReq mshr miss latency 937system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29927.495636 # average WriteReq mshr miss latency 938system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15664.236928 # average overall mshr miss latency 939system.cpu.dcache.demand_avg_mshr_miss_latency::total 15664.236928 # average overall mshr miss latency 940system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15664.236928 # average overall mshr miss latency 941system.cpu.dcache.overall_avg_mshr_miss_latency::total 15664.236928 # average overall mshr miss latency 942system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 943system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 944system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 945system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 946system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 947system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 948system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 949system.cpu.l2cache.replacements 114830 # number of replacements 950system.cpu.l2cache.tagsinuse 64834.632938 # Cycle average of tags in use 951system.cpu.l2cache.total_refs 3982137 # Total number of references to valid blocks. 952system.cpu.l2cache.sampled_refs 179006 # Sample count of references to valid blocks. 953system.cpu.l2cache.avg_refs 22.245830 # Average number of references to valid blocks. 954system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 955system.cpu.l2cache.occ_blocks::writebacks 50140.826343 # Average occupied blocks per requestor 956system.cpu.l2cache.occ_blocks::cpu.dtb.walker 11.977938 # Average occupied blocks per requestor 957system.cpu.l2cache.occ_blocks::cpu.itb.walker 1.120501 # Average occupied blocks per requestor 958system.cpu.l2cache.occ_blocks::cpu.inst 3151.862131 # Average occupied blocks per requestor 959system.cpu.l2cache.occ_blocks::cpu.data 11528.846024 # Average occupied blocks per requestor 960system.cpu.l2cache.occ_percent::writebacks 0.765088 # Average percentage of cache occupancy 961system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000183 # Average percentage of cache occupancy 962system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000017 # Average percentage of cache occupancy 963system.cpu.l2cache.occ_percent::cpu.inst 0.048094 # Average percentage of cache occupancy 964system.cpu.l2cache.occ_percent::cpu.data 0.175916 # Average percentage of cache occupancy 965system.cpu.l2cache.occ_percent::total 0.989298 # Average percentage of cache occupancy 966system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102782 # number of ReadReq hits 967system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8459 # number of ReadReq hits 968system.cpu.l2cache.ReadReq_hits::cpu.inst 1057919 # number of ReadReq hits 969system.cpu.l2cache.ReadReq_hits::cpu.data 1345123 # number of ReadReq hits 970system.cpu.l2cache.ReadReq_hits::total 2514283 # number of ReadReq hits 971system.cpu.l2cache.Writeback_hits::writebacks 1610609 # number of Writeback hits 972system.cpu.l2cache.Writeback_hits::total 1610609 # number of Writeback hits 973system.cpu.l2cache.UpgradeReq_hits::cpu.data 329 # number of UpgradeReq hits 974system.cpu.l2cache.UpgradeReq_hits::total 329 # number of UpgradeReq hits 975system.cpu.l2cache.ReadExReq_hits::cpu.data 156402 # number of ReadExReq hits 976system.cpu.l2cache.ReadExReq_hits::total 156402 # number of ReadExReq hits 977system.cpu.l2cache.demand_hits::cpu.dtb.walker 102782 # number of demand (read+write) hits 978system.cpu.l2cache.demand_hits::cpu.itb.walker 8459 # number of demand (read+write) hits 979system.cpu.l2cache.demand_hits::cpu.inst 1057919 # number of demand (read+write) hits 980system.cpu.l2cache.demand_hits::cpu.data 1501525 # number of demand (read+write) hits 981system.cpu.l2cache.demand_hits::total 2670685 # number of demand (read+write) hits 982system.cpu.l2cache.overall_hits::cpu.dtb.walker 102782 # number of overall hits 983system.cpu.l2cache.overall_hits::cpu.itb.walker 8459 # number of overall hits 984system.cpu.l2cache.overall_hits::cpu.inst 1057919 # number of overall hits 985system.cpu.l2cache.overall_hits::cpu.data 1501525 # number of overall hits 986system.cpu.l2cache.overall_hits::total 2670685 # number of overall hits 987system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses 988system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses 989system.cpu.l2cache.ReadReq_misses::cpu.inst 16908 # number of ReadReq misses 990system.cpu.l2cache.ReadReq_misses::cpu.data 37295 # number of ReadReq misses 991system.cpu.l2cache.ReadReq_misses::total 54256 # number of ReadReq misses 992system.cpu.l2cache.UpgradeReq_misses::cpu.data 3596 # number of UpgradeReq misses 993system.cpu.l2cache.UpgradeReq_misses::total 3596 # number of UpgradeReq misses 994system.cpu.l2cache.ReadExReq_misses::cpu.data 133929 # number of ReadExReq misses 995system.cpu.l2cache.ReadExReq_misses::total 133929 # number of ReadExReq misses 996system.cpu.l2cache.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses 997system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses 998system.cpu.l2cache.demand_misses::cpu.inst 16908 # number of demand (read+write) misses 999system.cpu.l2cache.demand_misses::cpu.data 171224 # number of demand (read+write) misses 1000system.cpu.l2cache.demand_misses::total 188185 # number of demand (read+write) misses 1001system.cpu.l2cache.overall_misses::cpu.dtb.walker 46 # number of overall misses 1002system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses 1003system.cpu.l2cache.overall_misses::cpu.inst 16908 # number of overall misses 1004system.cpu.l2cache.overall_misses::cpu.data 171224 # number of overall misses 1005system.cpu.l2cache.overall_misses::total 188185 # number of overall misses 1006system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3948500 # number of ReadReq miss cycles 1007system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 482500 # number of ReadReq miss cycles 1008system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1010290500 # number of ReadReq miss cycles 1009system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2408831998 # number of ReadReq miss cycles 1010system.cpu.l2cache.ReadReq_miss_latency::total 3423553498 # number of ReadReq miss cycles 1011system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17078500 # number of UpgradeReq miss cycles 1012system.cpu.l2cache.UpgradeReq_miss_latency::total 17078500 # number of UpgradeReq miss cycles 1013system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6857854500 # number of ReadExReq miss cycles 1014system.cpu.l2cache.ReadExReq_miss_latency::total 6857854500 # number of ReadExReq miss cycles 1015system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3948500 # number of demand (read+write) miss cycles 1016system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 482500 # number of demand (read+write) miss cycles 1017system.cpu.l2cache.demand_miss_latency::cpu.inst 1010290500 # number of demand (read+write) miss cycles 1018system.cpu.l2cache.demand_miss_latency::cpu.data 9266686498 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.demand_miss_latency::total 10281407998 # number of demand (read+write) miss cycles 1020system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3948500 # number of overall miss cycles 1021system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 482500 # number of overall miss cycles 1022system.cpu.l2cache.overall_miss_latency::cpu.inst 1010290500 # number of overall miss cycles 1023system.cpu.l2cache.overall_miss_latency::cpu.data 9266686498 # number of overall miss cycles 1024system.cpu.l2cache.overall_miss_latency::total 10281407998 # number of overall miss cycles 1025system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 102828 # number of ReadReq accesses(hits+misses) 1026system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8466 # number of ReadReq accesses(hits+misses) 1027system.cpu.l2cache.ReadReq_accesses::cpu.inst 1074827 # number of ReadReq accesses(hits+misses) 1028system.cpu.l2cache.ReadReq_accesses::cpu.data 1382418 # number of ReadReq accesses(hits+misses) 1029system.cpu.l2cache.ReadReq_accesses::total 2568539 # number of ReadReq accesses(hits+misses) 1030system.cpu.l2cache.Writeback_accesses::writebacks 1610609 # number of Writeback accesses(hits+misses) 1031system.cpu.l2cache.Writeback_accesses::total 1610609 # number of Writeback accesses(hits+misses) 1032system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3925 # number of UpgradeReq accesses(hits+misses) 1033system.cpu.l2cache.UpgradeReq_accesses::total 3925 # number of UpgradeReq accesses(hits+misses) 1034system.cpu.l2cache.ReadExReq_accesses::cpu.data 290331 # number of ReadExReq accesses(hits+misses) 1035system.cpu.l2cache.ReadExReq_accesses::total 290331 # number of ReadExReq accesses(hits+misses) 1036system.cpu.l2cache.demand_accesses::cpu.dtb.walker 102828 # number of demand (read+write) accesses 1037system.cpu.l2cache.demand_accesses::cpu.itb.walker 8466 # number of demand (read+write) accesses 1038system.cpu.l2cache.demand_accesses::cpu.inst 1074827 # number of demand (read+write) accesses 1039system.cpu.l2cache.demand_accesses::cpu.data 1672749 # number of demand (read+write) accesses 1040system.cpu.l2cache.demand_accesses::total 2858870 # number of demand (read+write) accesses 1041system.cpu.l2cache.overall_accesses::cpu.dtb.walker 102828 # number of overall (read+write) accesses 1042system.cpu.l2cache.overall_accesses::cpu.itb.walker 8466 # number of overall (read+write) accesses 1043system.cpu.l2cache.overall_accesses::cpu.inst 1074827 # number of overall (read+write) accesses 1044system.cpu.l2cache.overall_accesses::cpu.data 1672749 # number of overall (read+write) accesses 1045system.cpu.l2cache.overall_accesses::total 2858870 # number of overall (read+write) accesses 1046system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000447 # miss rate for ReadReq accesses 1047system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000827 # miss rate for ReadReq accesses 1048system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015731 # miss rate for ReadReq accesses 1049system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026978 # miss rate for ReadReq accesses 1050system.cpu.l2cache.ReadReq_miss_rate::total 0.021123 # miss rate for ReadReq accesses 1051system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.916178 # miss rate for UpgradeReq accesses 1052system.cpu.l2cache.UpgradeReq_miss_rate::total 0.916178 # miss rate for UpgradeReq accesses 1053system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461298 # miss rate for ReadExReq accesses 1054system.cpu.l2cache.ReadExReq_miss_rate::total 0.461298 # miss rate for ReadExReq accesses 1055system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000447 # miss rate for demand accesses 1056system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000827 # miss rate for demand accesses 1057system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015731 # miss rate for demand accesses 1058system.cpu.l2cache.demand_miss_rate::cpu.data 0.102361 # miss rate for demand accesses 1059system.cpu.l2cache.demand_miss_rate::total 0.065825 # miss rate for demand accesses 1060system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000447 # miss rate for overall accesses 1061system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000827 # miss rate for overall accesses 1062system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015731 # miss rate for overall accesses 1063system.cpu.l2cache.overall_miss_rate::cpu.data 0.102361 # miss rate for overall accesses 1064system.cpu.l2cache.overall_miss_rate::total 0.065825 # miss rate for overall accesses 1065system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85836.956522 # average ReadReq miss latency 1066system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 68928.571429 # average ReadReq miss latency 1067system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 59752.217885 # average ReadReq miss latency 1068system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64588.604317 # average ReadReq miss latency 1069system.cpu.l2cache.ReadReq_avg_miss_latency::total 63099.998120 # average ReadReq miss latency 1070system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4749.304783 # average UpgradeReq miss latency 1071system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4749.304783 # average UpgradeReq miss latency 1072system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51205.149744 # average ReadExReq miss latency 1073system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51205.149744 # average ReadExReq miss latency 1074system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85836.956522 # average overall miss latency 1075system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 68928.571429 # average overall miss latency 1076system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59752.217885 # average overall miss latency 1077system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54120.254742 # average overall miss latency 1078system.cpu.l2cache.demand_avg_miss_latency::total 54634.577666 # average overall miss latency 1079system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85836.956522 # average overall miss latency 1080system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 68928.571429 # average overall miss latency 1081system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59752.217885 # average overall miss latency 1082system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54120.254742 # average overall miss latency 1083system.cpu.l2cache.overall_avg_miss_latency::total 54634.577666 # average overall miss latency 1084system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1085system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1086system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1087system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1088system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1089system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1090system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1091system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1092system.cpu.l2cache.writebacks::writebacks 103542 # number of writebacks 1093system.cpu.l2cache.writebacks::total 103542 # number of writebacks 1094system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1095system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits 1096system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1097system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1098system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits 1099system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 1100system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1101system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits 1102system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits 1103system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 46 # number of ReadReq MSHR misses 1104system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses 1105system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16907 # number of ReadReq MSHR misses 1106system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 37293 # number of ReadReq MSHR misses 1107system.cpu.l2cache.ReadReq_mshr_misses::total 54253 # number of ReadReq MSHR misses 1108system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3596 # number of UpgradeReq MSHR misses 1109system.cpu.l2cache.UpgradeReq_mshr_misses::total 3596 # number of UpgradeReq MSHR misses 1110system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133929 # number of ReadExReq MSHR misses 1111system.cpu.l2cache.ReadExReq_mshr_misses::total 133929 # number of ReadExReq MSHR misses 1112system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 46 # number of demand (read+write) MSHR misses 1113system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses 1114system.cpu.l2cache.demand_mshr_misses::cpu.inst 16907 # number of demand (read+write) MSHR misses 1115system.cpu.l2cache.demand_mshr_misses::cpu.data 171222 # number of demand (read+write) MSHR misses 1116system.cpu.l2cache.demand_mshr_misses::total 188182 # number of demand (read+write) MSHR misses 1117system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 46 # number of overall MSHR misses 1118system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 1119system.cpu.l2cache.overall_mshr_misses::cpu.inst 16907 # number of overall MSHR misses 1120system.cpu.l2cache.overall_mshr_misses::cpu.data 171222 # number of overall MSHR misses 1121system.cpu.l2cache.overall_mshr_misses::total 188182 # number of overall MSHR misses 1122system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3366085 # number of ReadReq MSHR miss cycles 1123system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 392014 # number of ReadReq MSHR miss cycles 1124system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 796439838 # number of ReadReq MSHR miss cycles 1125system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1939128696 # number of ReadReq MSHR miss cycles 1126system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2739326633 # number of ReadReq MSHR miss cycles 1127system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 36904575 # number of UpgradeReq MSHR miss cycles 1128system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 36904575 # number of UpgradeReq MSHR miss cycles 1129system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5127896297 # number of ReadExReq MSHR miss cycles 1130system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5127896297 # number of ReadExReq MSHR miss cycles 1131system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3366085 # number of demand (read+write) MSHR miss cycles 1132system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 392014 # number of demand (read+write) MSHR miss cycles 1133system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 796439838 # number of demand (read+write) MSHR miss cycles 1134system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7067024993 # number of demand (read+write) MSHR miss cycles 1135system.cpu.l2cache.demand_mshr_miss_latency::total 7867222930 # number of demand (read+write) MSHR miss cycles 1136system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3366085 # number of overall MSHR miss cycles 1137system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 392014 # number of overall MSHR miss cycles 1138system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 796439838 # number of overall MSHR miss cycles 1139system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7067024993 # number of overall MSHR miss cycles 1140system.cpu.l2cache.overall_mshr_miss_latency::total 7867222930 # number of overall MSHR miss cycles 1141system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89185355500 # number of ReadReq MSHR uncacheable cycles 1142system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89185355500 # number of ReadReq MSHR uncacheable cycles 1143system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2304598500 # number of WriteReq MSHR uncacheable cycles 1144system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2304598500 # number of WriteReq MSHR uncacheable cycles 1145system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91489954000 # number of overall MSHR uncacheable cycles 1146system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91489954000 # number of overall MSHR uncacheable cycles 1147system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000447 # mshr miss rate for ReadReq accesses 1148system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000827 # mshr miss rate for ReadReq accesses 1149system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015730 # mshr miss rate for ReadReq accesses 1150system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026977 # mshr miss rate for ReadReq accesses 1151system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021122 # mshr miss rate for ReadReq accesses 1152system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916178 # mshr miss rate for UpgradeReq accesses 1153system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916178 # mshr miss rate for UpgradeReq accesses 1154system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461298 # mshr miss rate for ReadExReq accesses 1155system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461298 # mshr miss rate for ReadExReq accesses 1156system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000447 # mshr miss rate for demand accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000827 # mshr miss rate for demand accesses 1158system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015730 # mshr miss rate for demand accesses 1159system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102360 # mshr miss rate for demand accesses 1160system.cpu.l2cache.demand_mshr_miss_rate::total 0.065824 # mshr miss rate for demand accesses 1161system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000447 # mshr miss rate for overall accesses 1162system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000827 # mshr miss rate for overall accesses 1163system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015730 # mshr miss rate for overall accesses 1164system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102360 # mshr miss rate for overall accesses 1165system.cpu.l2cache.overall_mshr_miss_rate::total 0.065824 # mshr miss rate for overall accesses 1166system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73175.760870 # average ReadReq mshr miss latency 1167system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency 1168system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47107.105814 # average ReadReq mshr miss latency 1169system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51997.122677 # average ReadReq mshr miss latency 1170system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50491.707979 # average ReadReq mshr miss latency 1171system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10262.673804 # average UpgradeReq mshr miss latency 1172system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10262.673804 # average UpgradeReq mshr miss latency 1173system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38288.169829 # average ReadExReq mshr miss latency 1174system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38288.169829 # average ReadExReq mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73175.760870 # average overall mshr miss latency 1176system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency 1177system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47107.105814 # average overall mshr miss latency 1178system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41274.047687 # average overall mshr miss latency 1179system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41806.458269 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73175.760870 # average overall mshr miss latency 1181system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56002 # average overall mshr miss latency 1182system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47107.105814 # average overall mshr miss latency 1183system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41274.047687 # average overall mshr miss latency 1184system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41806.458269 # average overall mshr miss latency 1185system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1186system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1187system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1188system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1189system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1190system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1191system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1192system.cpu.kern.inst.arm 0 # number of arm instructions executed 1193system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1194 1195---------- End Simulation Statistics ---------- 1196