stats.txt revision 9125:65423863d963
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.172902 # Number of seconds simulated 4sim_ticks 5172902281500 # Number of ticks simulated 5final_tick 5172902281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 117061 # Simulator instruction rate (inst/s) 8host_op_rate 230687 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1419746087 # Simulator tick rate (ticks/s) 10host_mem_usage 420308 # Number of bytes of host memory used 11host_seconds 3643.54 # Real time elapsed on the host 12sim_insts 426515724 # Number of instructions simulated 13sim_ops 840516219 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2496512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 1067840 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10426304 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13994560 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1067840 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1067840 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9194240 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9194240 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 39008 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 16685 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 162911 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 218665 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 143660 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 143660 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 482613 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 680 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 206430 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2015562 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2705359 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 206430 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 206430 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1777385 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1777385 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1777385 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 482613 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 206430 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2015562 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4482745 # Total bandwidth to/from this memory (bytes/s) 49system.l2c.replacements 107419 # number of replacements 50system.l2c.tagsinuse 64844.084797 # Cycle average of tags in use 51system.l2c.total_refs 3992672 # Total number of references to valid blocks. 52system.l2c.sampled_refs 171622 # Sample count of references to valid blocks. 53system.l2c.avg_refs 23.264337 # Average number of references to valid blocks. 54system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 55system.l2c.occ_blocks::writebacks 50135.967843 # Average occupied blocks per requestor 56system.l2c.occ_blocks::cpu.dtb.walker 12.897301 # Average occupied blocks per requestor 57system.l2c.occ_blocks::cpu.itb.walker 0.156788 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu.inst 3372.666022 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu.data 11322.396844 # Average occupied blocks per requestor 60system.l2c.occ_percent::writebacks 0.765014 # Average percentage of cache occupancy 61system.l2c.occ_percent::cpu.dtb.walker 0.000197 # Average percentage of cache occupancy 62system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu.inst 0.051463 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu.data 0.172766 # Average percentage of cache occupancy 65system.l2c.occ_percent::total 0.989442 # Average percentage of cache occupancy 66system.l2c.ReadReq_hits::cpu.dtb.walker 110667 # number of ReadReq hits 67system.l2c.ReadReq_hits::cpu.itb.walker 8396 # number of ReadReq hits 68system.l2c.ReadReq_hits::cpu.inst 1054432 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu.data 1345104 # number of ReadReq hits 70system.l2c.ReadReq_hits::total 2518599 # number of ReadReq hits 71system.l2c.Writeback_hits::writebacks 1613189 # number of Writeback hits 72system.l2c.Writeback_hits::total 1613189 # number of Writeback hits 73system.l2c.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits 74system.l2c.UpgradeReq_hits::total 337 # number of UpgradeReq hits 75system.l2c.ReadExReq_hits::cpu.data 163997 # number of ReadExReq hits 76system.l2c.ReadExReq_hits::total 163997 # number of ReadExReq hits 77system.l2c.demand_hits::cpu.dtb.walker 110667 # number of demand (read+write) hits 78system.l2c.demand_hits::cpu.itb.walker 8396 # number of demand (read+write) hits 79system.l2c.demand_hits::cpu.inst 1054432 # number of demand (read+write) hits 80system.l2c.demand_hits::cpu.data 1509101 # number of demand (read+write) hits 81system.l2c.demand_hits::total 2682596 # number of demand (read+write) hits 82system.l2c.overall_hits::cpu.dtb.walker 110667 # number of overall hits 83system.l2c.overall_hits::cpu.itb.walker 8396 # number of overall hits 84system.l2c.overall_hits::cpu.inst 1054432 # number of overall hits 85system.l2c.overall_hits::cpu.data 1509101 # number of overall hits 86system.l2c.overall_hits::total 2682596 # number of overall hits 87system.l2c.ReadReq_misses::cpu.dtb.walker 55 # number of ReadReq misses 88system.l2c.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses 89system.l2c.ReadReq_misses::cpu.inst 16686 # number of ReadReq misses 90system.l2c.ReadReq_misses::cpu.data 35012 # number of ReadReq misses 91system.l2c.ReadReq_misses::total 51759 # number of ReadReq misses 92system.l2c.UpgradeReq_misses::cpu.data 1516 # number of UpgradeReq misses 93system.l2c.UpgradeReq_misses::total 1516 # number of UpgradeReq misses 94system.l2c.ReadExReq_misses::cpu.data 128839 # number of ReadExReq misses 95system.l2c.ReadExReq_misses::total 128839 # number of ReadExReq misses 96system.l2c.demand_misses::cpu.dtb.walker 55 # number of demand (read+write) misses 97system.l2c.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 98system.l2c.demand_misses::cpu.inst 16686 # number of demand (read+write) misses 99system.l2c.demand_misses::cpu.data 163851 # number of demand (read+write) misses 100system.l2c.demand_misses::total 180598 # number of demand (read+write) misses 101system.l2c.overall_misses::cpu.dtb.walker 55 # number of overall misses 102system.l2c.overall_misses::cpu.itb.walker 6 # number of overall misses 103system.l2c.overall_misses::cpu.inst 16686 # number of overall misses 104system.l2c.overall_misses::cpu.data 163851 # number of overall misses 105system.l2c.overall_misses::total 180598 # number of overall misses 106system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2907000 # number of ReadReq miss cycles 107system.l2c.ReadReq_miss_latency::cpu.itb.walker 312000 # number of ReadReq miss cycles 108system.l2c.ReadReq_miss_latency::cpu.inst 885914499 # number of ReadReq miss cycles 109system.l2c.ReadReq_miss_latency::cpu.data 1865182494 # number of ReadReq miss cycles 110system.l2c.ReadReq_miss_latency::total 2754315993 # number of ReadReq miss cycles 111system.l2c.UpgradeReq_miss_latency::cpu.data 39171500 # number of UpgradeReq miss cycles 112system.l2c.UpgradeReq_miss_latency::total 39171500 # number of UpgradeReq miss cycles 113system.l2c.ReadExReq_miss_latency::cpu.data 6715513999 # number of ReadExReq miss cycles 114system.l2c.ReadExReq_miss_latency::total 6715513999 # number of ReadExReq miss cycles 115system.l2c.demand_miss_latency::cpu.dtb.walker 2907000 # number of demand (read+write) miss cycles 116system.l2c.demand_miss_latency::cpu.itb.walker 312000 # number of demand (read+write) miss cycles 117system.l2c.demand_miss_latency::cpu.inst 885914499 # number of demand (read+write) miss cycles 118system.l2c.demand_miss_latency::cpu.data 8580696493 # number of demand (read+write) miss cycles 119system.l2c.demand_miss_latency::total 9469829992 # number of demand (read+write) miss cycles 120system.l2c.overall_miss_latency::cpu.dtb.walker 2907000 # number of overall miss cycles 121system.l2c.overall_miss_latency::cpu.itb.walker 312000 # number of overall miss cycles 122system.l2c.overall_miss_latency::cpu.inst 885914499 # number of overall miss cycles 123system.l2c.overall_miss_latency::cpu.data 8580696493 # number of overall miss cycles 124system.l2c.overall_miss_latency::total 9469829992 # number of overall miss cycles 125system.l2c.ReadReq_accesses::cpu.dtb.walker 110722 # number of ReadReq accesses(hits+misses) 126system.l2c.ReadReq_accesses::cpu.itb.walker 8402 # number of ReadReq accesses(hits+misses) 127system.l2c.ReadReq_accesses::cpu.inst 1071118 # number of ReadReq accesses(hits+misses) 128system.l2c.ReadReq_accesses::cpu.data 1380116 # number of ReadReq accesses(hits+misses) 129system.l2c.ReadReq_accesses::total 2570358 # number of ReadReq accesses(hits+misses) 130system.l2c.Writeback_accesses::writebacks 1613189 # number of Writeback accesses(hits+misses) 131system.l2c.Writeback_accesses::total 1613189 # number of Writeback accesses(hits+misses) 132system.l2c.UpgradeReq_accesses::cpu.data 1853 # number of UpgradeReq accesses(hits+misses) 133system.l2c.UpgradeReq_accesses::total 1853 # number of UpgradeReq accesses(hits+misses) 134system.l2c.ReadExReq_accesses::cpu.data 292836 # number of ReadExReq accesses(hits+misses) 135system.l2c.ReadExReq_accesses::total 292836 # number of ReadExReq accesses(hits+misses) 136system.l2c.demand_accesses::cpu.dtb.walker 110722 # number of demand (read+write) accesses 137system.l2c.demand_accesses::cpu.itb.walker 8402 # number of demand (read+write) accesses 138system.l2c.demand_accesses::cpu.inst 1071118 # number of demand (read+write) accesses 139system.l2c.demand_accesses::cpu.data 1672952 # number of demand (read+write) accesses 140system.l2c.demand_accesses::total 2863194 # number of demand (read+write) accesses 141system.l2c.overall_accesses::cpu.dtb.walker 110722 # number of overall (read+write) accesses 142system.l2c.overall_accesses::cpu.itb.walker 8402 # number of overall (read+write) accesses 143system.l2c.overall_accesses::cpu.inst 1071118 # number of overall (read+write) accesses 144system.l2c.overall_accesses::cpu.data 1672952 # number of overall (read+write) accesses 145system.l2c.overall_accesses::total 2863194 # number of overall (read+write) accesses 146system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000497 # miss rate for ReadReq accesses 147system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000714 # miss rate for ReadReq accesses 148system.l2c.ReadReq_miss_rate::cpu.inst 0.015578 # miss rate for ReadReq accesses 149system.l2c.ReadReq_miss_rate::cpu.data 0.025369 # miss rate for ReadReq accesses 150system.l2c.ReadReq_miss_rate::total 0.020137 # miss rate for ReadReq accesses 151system.l2c.UpgradeReq_miss_rate::cpu.data 0.818133 # miss rate for UpgradeReq accesses 152system.l2c.UpgradeReq_miss_rate::total 0.818133 # miss rate for UpgradeReq accesses 153system.l2c.ReadExReq_miss_rate::cpu.data 0.439970 # miss rate for ReadExReq accesses 154system.l2c.ReadExReq_miss_rate::total 0.439970 # miss rate for ReadExReq accesses 155system.l2c.demand_miss_rate::cpu.dtb.walker 0.000497 # miss rate for demand accesses 156system.l2c.demand_miss_rate::cpu.itb.walker 0.000714 # miss rate for demand accesses 157system.l2c.demand_miss_rate::cpu.inst 0.015578 # miss rate for demand accesses 158system.l2c.demand_miss_rate::cpu.data 0.097941 # miss rate for demand accesses 159system.l2c.demand_miss_rate::total 0.063076 # miss rate for demand accesses 160system.l2c.overall_miss_rate::cpu.dtb.walker 0.000497 # miss rate for overall accesses 161system.l2c.overall_miss_rate::cpu.itb.walker 0.000714 # miss rate for overall accesses 162system.l2c.overall_miss_rate::cpu.inst 0.015578 # miss rate for overall accesses 163system.l2c.overall_miss_rate::cpu.data 0.097941 # miss rate for overall accesses 164system.l2c.overall_miss_rate::total 0.063076 # miss rate for overall accesses 165system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52854.545455 # average ReadReq miss latency 166system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 167system.l2c.ReadReq_avg_miss_latency::cpu.inst 53093.281733 # average ReadReq miss latency 168system.l2c.ReadReq_avg_miss_latency::cpu.data 53272.663487 # average ReadReq miss latency 169system.l2c.ReadReq_avg_miss_latency::total 53214.242798 # average ReadReq miss latency 170system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25838.720317 # average UpgradeReq miss latency 171system.l2c.UpgradeReq_avg_miss_latency::total 25838.720317 # average UpgradeReq miss latency 172system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.301167 # average ReadExReq miss latency 173system.l2c.ReadExReq_avg_miss_latency::total 52123.301167 # average ReadExReq miss latency 174system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52854.545455 # average overall miss latency 175system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 176system.l2c.demand_avg_miss_latency::cpu.inst 53093.281733 # average overall miss latency 177system.l2c.demand_avg_miss_latency::cpu.data 52368.899140 # average overall miss latency 178system.l2c.demand_avg_miss_latency::total 52435.962702 # average overall miss latency 179system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52854.545455 # average overall miss latency 180system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 181system.l2c.overall_avg_miss_latency::cpu.inst 53093.281733 # average overall miss latency 182system.l2c.overall_avg_miss_latency::cpu.data 52368.899140 # average overall miss latency 183system.l2c.overall_avg_miss_latency::total 52435.962702 # average overall miss latency 184system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 185system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 186system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 187system.l2c.blocked::no_targets 0 # number of cycles access was blocked 188system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 189system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 190system.l2c.fast_writes 0 # number of fast writes performed 191system.l2c.cache_copies 0 # number of cache copies performed 192system.l2c.writebacks::writebacks 96993 # number of writebacks 193system.l2c.writebacks::total 96993 # number of writebacks 194system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 195system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 196system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 197system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 198system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 199system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 200system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 201system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 202system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits 203system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 55 # number of ReadReq MSHR misses 204system.l2c.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses 205system.l2c.ReadReq_mshr_misses::cpu.inst 16685 # number of ReadReq MSHR misses 206system.l2c.ReadReq_mshr_misses::cpu.data 35011 # number of ReadReq MSHR misses 207system.l2c.ReadReq_mshr_misses::total 51757 # number of ReadReq MSHR misses 208system.l2c.UpgradeReq_mshr_misses::cpu.data 1516 # number of UpgradeReq MSHR misses 209system.l2c.UpgradeReq_mshr_misses::total 1516 # number of UpgradeReq MSHR misses 210system.l2c.ReadExReq_mshr_misses::cpu.data 128839 # number of ReadExReq MSHR misses 211system.l2c.ReadExReq_mshr_misses::total 128839 # number of ReadExReq MSHR misses 212system.l2c.demand_mshr_misses::cpu.dtb.walker 55 # number of demand (read+write) MSHR misses 213system.l2c.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 214system.l2c.demand_mshr_misses::cpu.inst 16685 # number of demand (read+write) MSHR misses 215system.l2c.demand_mshr_misses::cpu.data 163850 # number of demand (read+write) MSHR misses 216system.l2c.demand_mshr_misses::total 180596 # number of demand (read+write) MSHR misses 217system.l2c.overall_mshr_misses::cpu.dtb.walker 55 # number of overall MSHR misses 218system.l2c.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 219system.l2c.overall_mshr_misses::cpu.inst 16685 # number of overall MSHR misses 220system.l2c.overall_mshr_misses::cpu.data 163850 # number of overall MSHR misses 221system.l2c.overall_mshr_misses::total 180596 # number of overall MSHR misses 222system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2241000 # number of ReadReq MSHR miss cycles 223system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles 224system.l2c.ReadReq_mshr_miss_latency::cpu.inst 682427500 # number of ReadReq MSHR miss cycles 225system.l2c.ReadReq_mshr_miss_latency::cpu.data 1437356500 # number of ReadReq MSHR miss cycles 226system.l2c.ReadReq_mshr_miss_latency::total 2122265000 # number of ReadReq MSHR miss cycles 227system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 61068000 # number of UpgradeReq MSHR miss cycles 228system.l2c.UpgradeReq_mshr_miss_latency::total 61068000 # number of UpgradeReq MSHR miss cycles 229system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5163609501 # number of ReadExReq MSHR miss cycles 230system.l2c.ReadExReq_mshr_miss_latency::total 5163609501 # number of ReadExReq MSHR miss cycles 231system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2241000 # number of demand (read+write) MSHR miss cycles 232system.l2c.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles 233system.l2c.demand_mshr_miss_latency::cpu.inst 682427500 # number of demand (read+write) MSHR miss cycles 234system.l2c.demand_mshr_miss_latency::cpu.data 6600966001 # number of demand (read+write) MSHR miss cycles 235system.l2c.demand_mshr_miss_latency::total 7285874501 # number of demand (read+write) MSHR miss cycles 236system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2241000 # number of overall MSHR miss cycles 237system.l2c.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles 238system.l2c.overall_mshr_miss_latency::cpu.inst 682427500 # number of overall MSHR miss cycles 239system.l2c.overall_mshr_miss_latency::cpu.data 6600966001 # number of overall MSHR miss cycles 240system.l2c.overall_mshr_miss_latency::total 7285874501 # number of overall MSHR miss cycles 241system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59192209064 # number of ReadReq MSHR uncacheable cycles 242system.l2c.ReadReq_mshr_uncacheable_latency::total 59192209064 # number of ReadReq MSHR uncacheable cycles 243system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1211526000 # number of WriteReq MSHR uncacheable cycles 244system.l2c.WriteReq_mshr_uncacheable_latency::total 1211526000 # number of WriteReq MSHR uncacheable cycles 245system.l2c.overall_mshr_uncacheable_latency::cpu.data 60403735064 # number of overall MSHR uncacheable cycles 246system.l2c.overall_mshr_uncacheable_latency::total 60403735064 # number of overall MSHR uncacheable cycles 247system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses 248system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for ReadReq accesses 249system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for ReadReq accesses 250system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses 251system.l2c.ReadReq_mshr_miss_rate::total 0.020136 # mshr miss rate for ReadReq accesses 252system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.818133 # mshr miss rate for UpgradeReq accesses 253system.l2c.UpgradeReq_mshr_miss_rate::total 0.818133 # mshr miss rate for UpgradeReq accesses 254system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.439970 # mshr miss rate for ReadExReq accesses 255system.l2c.ReadExReq_mshr_miss_rate::total 0.439970 # mshr miss rate for ReadExReq accesses 256system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses 257system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for demand accesses 258system.l2c.demand_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for demand accesses 259system.l2c.demand_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for demand accesses 260system.l2c.demand_mshr_miss_rate::total 0.063075 # mshr miss rate for demand accesses 261system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses 262system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for overall accesses 263system.l2c.overall_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for overall accesses 264system.l2c.overall_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for overall accesses 265system.l2c.overall_mshr_miss_rate::total 0.063075 # mshr miss rate for overall accesses 266system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average ReadReq mshr miss latency 267system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 268system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40900.659275 # average ReadReq mshr miss latency 269system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41054.425752 # average ReadReq mshr miss latency 270system.l2c.ReadReq_avg_mshr_miss_latency::total 41004.405201 # average ReadReq mshr miss latency 271system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40282.321900 # average UpgradeReq mshr miss latency 272system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40282.321900 # average UpgradeReq mshr miss latency 273system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.000458 # average ReadExReq mshr miss latency 274system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.000458 # average ReadExReq mshr miss latency 275system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency 276system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 277system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency 278system.l2c.demand_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency 279system.l2c.demand_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency 280system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency 281system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 282system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency 283system.l2c.overall_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency 284system.l2c.overall_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency 285system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 286system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 287system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 288system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 289system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 290system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 291system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 292system.iocache.replacements 47565 # number of replacements 293system.iocache.tagsinuse 0.200108 # Cycle average of tags in use 294system.iocache.total_refs 0 # Total number of references to valid blocks. 295system.iocache.sampled_refs 47581 # Sample count of references to valid blocks. 296system.iocache.avg_refs 0 # Average number of references to valid blocks. 297system.iocache.warmup_cycle 5000599162000 # Cycle when the warmup percentage was hit. 298system.iocache.occ_blocks::pc.south_bridge.ide 0.200108 # Average occupied blocks per requestor 299system.iocache.occ_percent::pc.south_bridge.ide 0.012507 # Average percentage of cache occupancy 300system.iocache.occ_percent::total 0.012507 # Average percentage of cache occupancy 301system.iocache.ReadReq_misses::pc.south_bridge.ide 900 # number of ReadReq misses 302system.iocache.ReadReq_misses::total 900 # number of ReadReq misses 303system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 304system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 305system.iocache.demand_misses::pc.south_bridge.ide 47620 # number of demand (read+write) misses 306system.iocache.demand_misses::total 47620 # number of demand (read+write) misses 307system.iocache.overall_misses::pc.south_bridge.ide 47620 # number of overall misses 308system.iocache.overall_misses::total 47620 # number of overall misses 309system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135466932 # number of ReadReq miss cycles 310system.iocache.ReadReq_miss_latency::total 135466932 # number of ReadReq miss cycles 311system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6926961160 # number of WriteReq miss cycles 312system.iocache.WriteReq_miss_latency::total 6926961160 # number of WriteReq miss cycles 313system.iocache.demand_miss_latency::pc.south_bridge.ide 7062428092 # number of demand (read+write) miss cycles 314system.iocache.demand_miss_latency::total 7062428092 # number of demand (read+write) miss cycles 315system.iocache.overall_miss_latency::pc.south_bridge.ide 7062428092 # number of overall miss cycles 316system.iocache.overall_miss_latency::total 7062428092 # number of overall miss cycles 317system.iocache.ReadReq_accesses::pc.south_bridge.ide 900 # number of ReadReq accesses(hits+misses) 318system.iocache.ReadReq_accesses::total 900 # number of ReadReq accesses(hits+misses) 319system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 320system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 321system.iocache.demand_accesses::pc.south_bridge.ide 47620 # number of demand (read+write) accesses 322system.iocache.demand_accesses::total 47620 # number of demand (read+write) accesses 323system.iocache.overall_accesses::pc.south_bridge.ide 47620 # number of overall (read+write) accesses 324system.iocache.overall_accesses::total 47620 # number of overall (read+write) accesses 325system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 326system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 327system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 328system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 329system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 330system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 331system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 332system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 333system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150518.813333 # average ReadReq miss latency 334system.iocache.ReadReq_avg_miss_latency::total 150518.813333 # average ReadReq miss latency 335system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148265.435788 # average WriteReq miss latency 336system.iocache.WriteReq_avg_miss_latency::total 148265.435788 # average WriteReq miss latency 337system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency 338system.iocache.demand_avg_miss_latency::total 148308.023772 # average overall miss latency 339system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency 340system.iocache.overall_avg_miss_latency::total 148308.023772 # average overall miss latency 341system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked 342system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 343system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked 344system.iocache.blocked::no_targets 0 # number of cycles access was blocked 345system.iocache.avg_blocked_cycles::no_mshrs 10760.160000 # average number of cycles each access was blocked 346system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 347system.iocache.fast_writes 0 # number of fast writes performed 348system.iocache.cache_copies 0 # number of cache copies performed 349system.iocache.writebacks::writebacks 46667 # number of writebacks 350system.iocache.writebacks::total 46667 # number of writebacks 351system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 900 # number of ReadReq MSHR misses 352system.iocache.ReadReq_mshr_misses::total 900 # number of ReadReq MSHR misses 353system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 354system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 355system.iocache.demand_mshr_misses::pc.south_bridge.ide 47620 # number of demand (read+write) MSHR misses 356system.iocache.demand_mshr_misses::total 47620 # number of demand (read+write) MSHR misses 357system.iocache.overall_mshr_misses::pc.south_bridge.ide 47620 # number of overall MSHR misses 358system.iocache.overall_mshr_misses::total 47620 # number of overall MSHR misses 359system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88635000 # number of ReadReq MSHR miss cycles 360system.iocache.ReadReq_mshr_miss_latency::total 88635000 # number of ReadReq MSHR miss cycles 361system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4497207944 # number of WriteReq MSHR miss cycles 362system.iocache.WriteReq_mshr_miss_latency::total 4497207944 # number of WriteReq MSHR miss cycles 363system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of demand (read+write) MSHR miss cycles 364system.iocache.demand_mshr_miss_latency::total 4585842944 # number of demand (read+write) MSHR miss cycles 365system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of overall MSHR miss cycles 366system.iocache.overall_mshr_miss_latency::total 4585842944 # number of overall MSHR miss cycles 367system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 368system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 369system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 370system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 371system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 372system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 373system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 374system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 375system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98483.333333 # average ReadReq mshr miss latency 376system.iocache.ReadReq_avg_mshr_miss_latency::total 98483.333333 # average ReadReq mshr miss latency 377system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96258.731678 # average WriteReq mshr miss latency 378system.iocache.WriteReq_avg_mshr_miss_latency::total 96258.731678 # average WriteReq mshr miss latency 379system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency 380system.iocache.demand_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency 381system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency 382system.iocache.overall_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency 383system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 384system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 385system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 386system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 387system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 388system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 389system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 390system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 391system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 392system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 393system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 394system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 395system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 396system.cpu.numCycles 472946175 # number of cpu cycles simulated 397system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 398system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 399system.cpu.BPredUnit.lookups 90027772 # Number of BP lookups 400system.cpu.BPredUnit.condPredicted 90027772 # Number of conditional branches predicted 401system.cpu.BPredUnit.condIncorrect 1176455 # Number of conditional branches incorrect 402system.cpu.BPredUnit.BTBLookups 84282590 # Number of BTB lookups 403system.cpu.BPredUnit.BTBHits 81704922 # Number of BTB hits 404system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 405system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 406system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 407system.cpu.fetch.icacheStallCycles 31264026 # Number of cycles fetch is stalled on an Icache miss 408system.cpu.fetch.Insts 446943348 # Number of instructions fetch has processed 409system.cpu.fetch.Branches 90027772 # Number of branches that fetch encountered 410system.cpu.fetch.predictedBranches 81704922 # Number of branches that fetch has predicted taken 411system.cpu.fetch.Cycles 169792009 # Number of cycles fetch has run and was not squashing or blocked 412system.cpu.fetch.SquashCycles 5327046 # Number of cycles fetch has spent squashing 413system.cpu.fetch.TlbCycles 167003 # Number of cycles fetch has spent waiting for tlb 414system.cpu.fetch.BlockedCycles 104616235 # Number of cycles fetch has spent blocked 415system.cpu.fetch.MiscStallCycles 37821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 416system.cpu.fetch.PendingTrapStallCycles 45804 # Number of stall cycles due to pending traps 417system.cpu.fetch.IcacheWaitRetryStallCycles 481 # Number of stall cycles due to full MSHR 418system.cpu.fetch.CacheLines 9365381 # Number of cache lines fetched 419system.cpu.fetch.IcacheSquashes 539972 # Number of outstanding Icache misses that were squashed 420system.cpu.fetch.ItlbSquashes 5058 # Number of outstanding ITLB misses that were squashed 421system.cpu.fetch.rateDist::samples 310035010 # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.rateDist::mean 2.836765 # Number of instructions fetched each cycle (Total) 423system.cpu.fetch.rateDist::stdev 3.376817 # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::0 140677603 45.37% 45.37% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::1 1773611 0.57% 45.95% # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::2 72784877 23.48% 69.42% # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::3 988899 0.32% 69.74% # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::4 1639325 0.53% 70.27% # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::5 3670845 1.18% 71.45% # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.rateDist::6 1138945 0.37% 71.82% # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.rateDist::7 1446155 0.47% 72.29% # Number of instructions fetched each cycle (Total) 433system.cpu.fetch.rateDist::8 85914750 27.71% 100.00% # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::total 310035010 # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.branchRate 0.190355 # Number of branch fetches per cycle 439system.cpu.fetch.rate 0.945019 # Number of inst fetches per cycle 440system.cpu.decode.IdleCycles 36438516 # Number of cycles decode is idle 441system.cpu.decode.BlockedCycles 100672732 # Number of cycles decode is blocked 442system.cpu.decode.RunCycles 164105371 # Number of cycles decode is running 443system.cpu.decode.UnblockCycles 4706760 # Number of cycles decode is unblocking 444system.cpu.decode.SquashCycles 4111631 # Number of cycles decode is squashing 445system.cpu.decode.DecodedInsts 876235114 # Number of instructions handled by decode 446system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode 447system.cpu.rename.SquashCycles 4111631 # Number of cycles rename is squashing 448system.cpu.rename.IdleCycles 40855551 # Number of cycles rename is idle 449system.cpu.rename.BlockCycles 44279722 # Number of cycles rename is blocking 450system.cpu.rename.serializeStallCycles 10981847 # count of cycles rename stalled for serializing inst 451system.cpu.rename.RunCycles 163785428 # Number of cycles rename is running 452system.cpu.rename.UnblockCycles 46020831 # Number of cycles rename is unblocking 453system.cpu.rename.RenamedInsts 872430616 # Number of instructions processed by rename 454system.cpu.rename.ROBFullEvents 10252 # Number of times rename has blocked due to ROB full 455system.cpu.rename.IQFullEvents 35253394 # Number of times rename has blocked due to IQ full 456system.cpu.rename.LSQFullEvents 3952381 # Number of times rename has blocked due to LSQ full 457system.cpu.rename.FullRegisterEvents 31994944 # Number of times there has been no free registers 458system.cpu.rename.RenamedOperands 1394146617 # Number of destination operands rename has renamed 459system.cpu.rename.RenameLookups 2488353855 # Number of register rename lookups that rename has made 460system.cpu.rename.int_rename_lookups 2488353319 # Number of integer rename lookups 461system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups 462system.cpu.rename.CommittedMaps 1347546781 # Number of HB maps that are committed 463system.cpu.rename.UndoneMaps 46599829 # Number of HB maps that are undone due to squashing 464system.cpu.rename.serializingInsts 470336 # count of serializing insts renamed 465system.cpu.rename.tempSerializingInsts 478135 # count of temporary serializing insts renamed 466system.cpu.rename.skidInsts 48126988 # count of insts added to the skid buffer 467system.cpu.memDep0.insertedLoads 18909339 # Number of loads inserted to the mem dependence unit. 468system.cpu.memDep0.insertedStores 10455877 # Number of stores inserted to the mem dependence unit. 469system.cpu.memDep0.conflictingLoads 1294020 # Number of conflicting loads. 470system.cpu.memDep0.conflictingStores 1017517 # Number of conflicting stores. 471system.cpu.iq.iqInstsAdded 865756561 # Number of instructions added to the IQ (excludes non-spec) 472system.cpu.iq.iqNonSpecInstsAdded 1721302 # Number of non-speculative instructions added to the IQ 473system.cpu.iq.iqInstsIssued 864328719 # Number of instructions issued 474system.cpu.iq.iqSquashedInstsIssued 124616 # Number of squashed instructions issued 475system.cpu.iq.iqSquashedInstsExamined 26046990 # Number of squashed instructions iterated over during squash; mainly for profiling 476system.cpu.iq.iqSquashedOperandsExamined 53600910 # Number of squashed operands that are examined and possibly removed from graph 477system.cpu.iq.iqSquashedNonSpecRemoved 205527 # Number of squashed non-spec instructions that were removed 478system.cpu.iq.issued_per_cycle::samples 310035010 # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::mean 2.787842 # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::stdev 2.396151 # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::0 102334281 33.01% 33.01% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::1 23751530 7.66% 40.67% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::2 19011662 6.13% 46.80% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::3 7830278 2.53% 49.33% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::4 80611792 26.00% 75.33% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::5 3104970 1.00% 76.33% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::6 72755101 23.47% 99.80% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::7 522761 0.17% 99.96% # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::8 112635 0.04% 100.00% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::total 310035010 # Number of insts issued each cycle 495system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 496system.cpu.iq.fu_full::IntAlu 164564 7.88% 7.88% # attempts to use FU when none available 497system.cpu.iq.fu_full::IntMult 0 0.00% 7.88% # attempts to use FU when none available 498system.cpu.iq.fu_full::IntDiv 0 0.00% 7.88% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.88% # attempts to use FU when none available 500system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.88% # attempts to use FU when none available 501system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.88% # attempts to use FU when none available 502system.cpu.iq.fu_full::FloatMult 0 0.00% 7.88% # attempts to use FU when none available 503system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.88% # attempts to use FU when none available 504system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.88% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.88% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.88% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.88% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.88% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.88% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.88% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdMult 0 0.00% 7.88% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.88% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdShift 0 0.00% 7.88% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.88% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.88% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.88% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.88% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.88% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.88% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.88% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.88% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.88% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.88% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.88% # attempts to use FU when none available 525system.cpu.iq.fu_full::MemRead 1763434 84.48% 92.37% # attempts to use FU when none available 526system.cpu.iq.fu_full::MemWrite 159280 7.63% 100.00% # attempts to use FU when none available 527system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 528system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 529system.cpu.iq.FU_type_0::No_OpClass 297202 0.03% 0.03% # Type of FU issued 530system.cpu.iq.FU_type_0::IntAlu 829439322 95.96% 96.00% # Type of FU issued 531system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued 532system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued 534system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued 535system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued 536system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued 537system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued 538system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued 559system.cpu.iq.FU_type_0::MemRead 25154463 2.91% 98.91% # Type of FU issued 560system.cpu.iq.FU_type_0::MemWrite 9437732 1.09% 100.00% # Type of FU issued 561system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 562system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 563system.cpu.iq.FU_type_0::total 864328719 # Type of FU issued 564system.cpu.iq.rate 1.827541 # Inst issue rate 565system.cpu.iq.fu_busy_cnt 2087278 # FU busy when requested 566system.cpu.iq.fu_busy_rate 0.002415 # FU busy rate (busy events/executed inst) 567system.cpu.iq.int_inst_queue_reads 2041042185 # Number of integer instruction queue reads 568system.cpu.iq.int_inst_queue_writes 893535851 # Number of integer instruction queue writes 569system.cpu.iq.int_inst_queue_wakeup_accesses 853927067 # Number of integer instruction queue wakeup accesses 570system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads 571system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes 572system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses 573system.cpu.iq.int_alu_accesses 866118699 # Number of integer alu accesses 574system.cpu.iq.fp_alu_accesses 96 # Number of floating point alu accesses 575system.cpu.iew.lsq.thread0.forwLoads 1579181 # Number of loads that had data forwarded from stores 576system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 577system.cpu.iew.lsq.thread0.squashedLoads 3618734 # Number of loads squashed 578system.cpu.iew.lsq.thread0.ignoredResponses 20083 # Number of memory responses ignored because the instruction is squashed 579system.cpu.iew.lsq.thread0.memOrderViolation 12084 # Number of memory ordering violations 580system.cpu.iew.lsq.thread0.squashedStores 2054359 # Number of stores squashed 581system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 582system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 583system.cpu.iew.lsq.thread0.rescheduledLoads 7821519 # Number of loads that were rescheduled 584system.cpu.iew.lsq.thread0.cacheBlocked 4487 # Number of times an access to memory failed due to the cache being blocked 585system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 586system.cpu.iew.iewSquashCycles 4111631 # Number of cycles IEW is squashing 587system.cpu.iew.iewBlockCycles 27910035 # Number of cycles IEW is blocking 588system.cpu.iew.iewUnblockCycles 1927143 # Number of cycles IEW is unblocking 589system.cpu.iew.iewDispatchedInsts 867477863 # Number of instructions dispatched to IQ 590system.cpu.iew.iewDispSquashedInsts 297836 # Number of squashed instructions skipped by dispatch 591system.cpu.iew.iewDispLoadInsts 18909339 # Number of dispatched load instructions 592system.cpu.iew.iewDispStoreInsts 10455877 # Number of dispatched store instructions 593system.cpu.iew.iewDispNonSpecInsts 883178 # Number of dispatched non-speculative instructions 594system.cpu.iew.iewIQFullEvents 975186 # Number of times the IQ has become full, causing a stall 595system.cpu.iew.iewLSQFullEvents 15536 # Number of times the LSQ has become full, causing a stall 596system.cpu.iew.memOrderViolationEvents 12084 # Number of memory order violations 597system.cpu.iew.predictedTakenIncorrect 697834 # Number of branches that were predicted taken incorrectly 598system.cpu.iew.predictedNotTakenIncorrect 626380 # Number of branches that were predicted not taken incorrectly 599system.cpu.iew.branchMispredicts 1324214 # Number of branch mispredicts detected at execute 600system.cpu.iew.iewExecutedInsts 862437508 # Number of executed instructions 601system.cpu.iew.iewExecLoadInsts 24726867 # Number of load instructions executed 602system.cpu.iew.iewExecSquashedInsts 1891210 # Number of squashed instructions skipped in execute 603system.cpu.iew.exec_swp 0 # number of swp insts executed 604system.cpu.iew.exec_nop 0 # number of nop insts executed 605system.cpu.iew.exec_refs 33920253 # number of memory reference insts executed 606system.cpu.iew.exec_branches 86495383 # Number of branches executed 607system.cpu.iew.exec_stores 9193386 # Number of stores executed 608system.cpu.iew.exec_rate 1.823543 # Inst execution rate 609system.cpu.iew.wb_sent 861952908 # cumulative count of insts sent to commit 610system.cpu.iew.wb_count 853927121 # cumulative count of insts written-back 611system.cpu.iew.wb_producers 669642895 # num instructions producing a value 612system.cpu.iew.wb_consumers 1918737755 # num instructions consuming a value 613system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 614system.cpu.iew.wb_rate 1.805548 # insts written-back per cycle 615system.cpu.iew.wb_fanout 0.349002 # average fanout of values written-back 616system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 617system.cpu.commit.commitCommittedInsts 426515724 # The number of committed instructions 618system.cpu.commit.commitCommittedOps 840516219 # The number of committed instructions 619system.cpu.commit.commitSquashedInsts 26857823 # The number of squashed insts skipped by commit 620system.cpu.commit.commitNonSpecStalls 1515773 # The number of times commit has been forced to stall to communicate backwards 621system.cpu.commit.branchMispredicts 1181578 # The number of times a branch was mispredicted 622system.cpu.commit.committed_per_cycle::samples 305938932 # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::mean 2.747333 # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::stdev 2.861326 # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::0 125006118 40.86% 40.86% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::1 14720749 4.81% 45.67% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::2 4254060 1.39% 47.06% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::3 76641454 25.05% 72.11% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::4 3896789 1.27% 73.39% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::5 1794252 0.59% 73.97% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::6 1101361 0.36% 74.33% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::7 71996786 23.53% 97.87% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::8 6527363 2.13% 100.00% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::total 305938932 # Number of insts commited each cycle 639system.cpu.commit.committedInsts 426515724 # Number of instructions committed 640system.cpu.commit.committedOps 840516219 # Number of ops (including micro ops) committed 641system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 642system.cpu.commit.refs 23692120 # Number of memory references committed 643system.cpu.commit.loads 15290602 # Number of loads committed 644system.cpu.commit.membars 781565 # Number of memory barriers committed 645system.cpu.commit.branches 85505775 # Number of branches committed 646system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 647system.cpu.commit.int_insts 768334838 # Number of committed integer instructions. 648system.cpu.commit.function_calls 0 # Number of function calls committed. 649system.cpu.commit.bw_lim_events 6527363 # number cycles where commit BW limit reached 650system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 651system.cpu.rob.rob_reads 1166706140 # The number of ROB reads 652system.cpu.rob.rob_writes 1738874776 # The number of ROB writes 653system.cpu.timesIdled 2996123 # Number of times that the entire CPU went into an idle state and unscheduled itself 654system.cpu.idleCycles 162911165 # Total number of cycles that the CPU has spent unscheduled due to idling 655system.cpu.quiesceCycles 9872855838 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 656system.cpu.committedInsts 426515724 # Number of Instructions Simulated 657system.cpu.committedOps 840516219 # Number of Ops (including micro ops) Simulated 658system.cpu.committedInsts_total 426515724 # Number of Instructions Simulated 659system.cpu.cpi 1.108860 # CPI: Cycles Per Instruction 660system.cpu.cpi_total 1.108860 # CPI: Total CPI of All Threads 661system.cpu.ipc 0.901827 # IPC: Instructions Per Cycle 662system.cpu.ipc_total 0.901827 # IPC: Total IPC of All Threads 663system.cpu.int_regfile_reads 2163141042 # number of integer regfile reads 664system.cpu.int_regfile_writes 1362663536 # number of integer regfile writes 665system.cpu.fp_regfile_reads 54 # number of floating regfile reads 666system.cpu.misc_regfile_reads 281062978 # number of misc regfile reads 667system.cpu.misc_regfile_writes 403820 # number of misc regfile writes 668system.cpu.icache.replacements 1070658 # number of replacements 669system.cpu.icache.tagsinuse 510.425099 # Cycle average of tags in use 670system.cpu.icache.total_refs 8224431 # Total number of references to valid blocks. 671system.cpu.icache.sampled_refs 1071170 # Sample count of references to valid blocks. 672system.cpu.icache.avg_refs 7.677989 # Average number of references to valid blocks. 673system.cpu.icache.warmup_cycle 56932899000 # Cycle when the warmup percentage was hit. 674system.cpu.icache.occ_blocks::cpu.inst 510.425099 # Average occupied blocks per requestor 675system.cpu.icache.occ_percent::cpu.inst 0.996924 # Average percentage of cache occupancy 676system.cpu.icache.occ_percent::total 0.996924 # Average percentage of cache occupancy 677system.cpu.icache.ReadReq_hits::cpu.inst 8224431 # number of ReadReq hits 678system.cpu.icache.ReadReq_hits::total 8224431 # number of ReadReq hits 679system.cpu.icache.demand_hits::cpu.inst 8224431 # number of demand (read+write) hits 680system.cpu.icache.demand_hits::total 8224431 # number of demand (read+write) hits 681system.cpu.icache.overall_hits::cpu.inst 8224431 # number of overall hits 682system.cpu.icache.overall_hits::total 8224431 # number of overall hits 683system.cpu.icache.ReadReq_misses::cpu.inst 1140947 # number of ReadReq misses 684system.cpu.icache.ReadReq_misses::total 1140947 # number of ReadReq misses 685system.cpu.icache.demand_misses::cpu.inst 1140947 # number of demand (read+write) misses 686system.cpu.icache.demand_misses::total 1140947 # number of demand (read+write) misses 687system.cpu.icache.overall_misses::cpu.inst 1140947 # number of overall misses 688system.cpu.icache.overall_misses::total 1140947 # number of overall misses 689system.cpu.icache.ReadReq_miss_latency::cpu.inst 18841256486 # number of ReadReq miss cycles 690system.cpu.icache.ReadReq_miss_latency::total 18841256486 # number of ReadReq miss cycles 691system.cpu.icache.demand_miss_latency::cpu.inst 18841256486 # number of demand (read+write) miss cycles 692system.cpu.icache.demand_miss_latency::total 18841256486 # number of demand (read+write) miss cycles 693system.cpu.icache.overall_miss_latency::cpu.inst 18841256486 # number of overall miss cycles 694system.cpu.icache.overall_miss_latency::total 18841256486 # number of overall miss cycles 695system.cpu.icache.ReadReq_accesses::cpu.inst 9365378 # number of ReadReq accesses(hits+misses) 696system.cpu.icache.ReadReq_accesses::total 9365378 # number of ReadReq accesses(hits+misses) 697system.cpu.icache.demand_accesses::cpu.inst 9365378 # number of demand (read+write) accesses 698system.cpu.icache.demand_accesses::total 9365378 # number of demand (read+write) accesses 699system.cpu.icache.overall_accesses::cpu.inst 9365378 # number of overall (read+write) accesses 700system.cpu.icache.overall_accesses::total 9365378 # number of overall (read+write) accesses 701system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121826 # miss rate for ReadReq accesses 702system.cpu.icache.ReadReq_miss_rate::total 0.121826 # miss rate for ReadReq accesses 703system.cpu.icache.demand_miss_rate::cpu.inst 0.121826 # miss rate for demand accesses 704system.cpu.icache.demand_miss_rate::total 0.121826 # miss rate for demand accesses 705system.cpu.icache.overall_miss_rate::cpu.inst 0.121826 # miss rate for overall accesses 706system.cpu.icache.overall_miss_rate::total 0.121826 # miss rate for overall accesses 707system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16513.700011 # average ReadReq miss latency 708system.cpu.icache.ReadReq_avg_miss_latency::total 16513.700011 # average ReadReq miss latency 709system.cpu.icache.demand_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency 710system.cpu.icache.demand_avg_miss_latency::total 16513.700011 # average overall miss latency 711system.cpu.icache.overall_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency 712system.cpu.icache.overall_avg_miss_latency::total 16513.700011 # average overall miss latency 713system.cpu.icache.blocked_cycles::no_mshrs 3271992 # number of cycles access was blocked 714system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 715system.cpu.icache.blocked::no_mshrs 399 # number of cycles access was blocked 716system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 717system.cpu.icache.avg_blocked_cycles::no_mshrs 8200.481203 # average number of cycles each access was blocked 718system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 719system.cpu.icache.fast_writes 0 # number of fast writes performed 720system.cpu.icache.cache_copies 0 # number of cache copies performed 721system.cpu.icache.writebacks::writebacks 1605 # number of writebacks 722system.cpu.icache.writebacks::total 1605 # number of writebacks 723system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69655 # number of ReadReq MSHR hits 724system.cpu.icache.ReadReq_mshr_hits::total 69655 # number of ReadReq MSHR hits 725system.cpu.icache.demand_mshr_hits::cpu.inst 69655 # number of demand (read+write) MSHR hits 726system.cpu.icache.demand_mshr_hits::total 69655 # number of demand (read+write) MSHR hits 727system.cpu.icache.overall_mshr_hits::cpu.inst 69655 # number of overall MSHR hits 728system.cpu.icache.overall_mshr_hits::total 69655 # number of overall MSHR hits 729system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071292 # number of ReadReq MSHR misses 730system.cpu.icache.ReadReq_mshr_misses::total 1071292 # number of ReadReq MSHR misses 731system.cpu.icache.demand_mshr_misses::cpu.inst 1071292 # number of demand (read+write) MSHR misses 732system.cpu.icache.demand_mshr_misses::total 1071292 # number of demand (read+write) MSHR misses 733system.cpu.icache.overall_mshr_misses::cpu.inst 1071292 # number of overall MSHR misses 734system.cpu.icache.overall_mshr_misses::total 1071292 # number of overall MSHR misses 735system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14719464992 # number of ReadReq MSHR miss cycles 736system.cpu.icache.ReadReq_mshr_miss_latency::total 14719464992 # number of ReadReq MSHR miss cycles 737system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14719464992 # number of demand (read+write) MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::total 14719464992 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14719464992 # number of overall MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::total 14719464992 # number of overall MSHR miss cycles 741system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for ReadReq accesses 742system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114389 # mshr miss rate for ReadReq accesses 743system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for demand accesses 744system.cpu.icache.demand_mshr_miss_rate::total 0.114389 # mshr miss rate for demand accesses 745system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for overall accesses 746system.cpu.icache.overall_mshr_miss_rate::total 0.114389 # mshr miss rate for overall accesses 747system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13739.918708 # average ReadReq mshr miss latency 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13739.918708 # average ReadReq mshr miss latency 749system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency 751system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency 753system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 754system.cpu.itb_walker_cache.replacements 10504 # number of replacements 755system.cpu.itb_walker_cache.tagsinuse 6.031363 # Cycle average of tags in use 756system.cpu.itb_walker_cache.total_refs 31807 # Total number of references to valid blocks. 757system.cpu.itb_walker_cache.sampled_refs 10516 # Sample count of references to valid blocks. 758system.cpu.itb_walker_cache.avg_refs 3.024629 # Average number of references to valid blocks. 759system.cpu.itb_walker_cache.warmup_cycle 5135227037000 # Cycle when the warmup percentage was hit. 760system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.031363 # Average occupied blocks per requestor 761system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376960 # Average percentage of cache occupancy 762system.cpu.itb_walker_cache.occ_percent::total 0.376960 # Average percentage of cache occupancy 763system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31848 # number of ReadReq hits 764system.cpu.itb_walker_cache.ReadReq_hits::total 31848 # number of ReadReq hits 765system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits 766system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits 767system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31851 # number of demand (read+write) hits 768system.cpu.itb_walker_cache.demand_hits::total 31851 # number of demand (read+write) hits 769system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31851 # number of overall hits 770system.cpu.itb_walker_cache.overall_hits::total 31851 # number of overall hits 771system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11386 # number of ReadReq misses 772system.cpu.itb_walker_cache.ReadReq_misses::total 11386 # number of ReadReq misses 773system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11386 # number of demand (read+write) misses 774system.cpu.itb_walker_cache.demand_misses::total 11386 # number of demand (read+write) misses 775system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11386 # number of overall misses 776system.cpu.itb_walker_cache.overall_misses::total 11386 # number of overall misses 777system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 182254500 # number of ReadReq miss cycles 778system.cpu.itb_walker_cache.ReadReq_miss_latency::total 182254500 # number of ReadReq miss cycles 779system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 182254500 # number of demand (read+write) miss cycles 780system.cpu.itb_walker_cache.demand_miss_latency::total 182254500 # number of demand (read+write) miss cycles 781system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 182254500 # number of overall miss cycles 782system.cpu.itb_walker_cache.overall_miss_latency::total 182254500 # number of overall miss cycles 783system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43234 # number of ReadReq accesses(hits+misses) 784system.cpu.itb_walker_cache.ReadReq_accesses::total 43234 # number of ReadReq accesses(hits+misses) 785system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) 786system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 787system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43237 # number of demand (read+write) accesses 788system.cpu.itb_walker_cache.demand_accesses::total 43237 # number of demand (read+write) accesses 789system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43237 # number of overall (read+write) accesses 790system.cpu.itb_walker_cache.overall_accesses::total 43237 # number of overall (read+write) accesses 791system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.263358 # miss rate for ReadReq accesses 792system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.263358 # miss rate for ReadReq accesses 793system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.263339 # miss rate for demand accesses 794system.cpu.itb_walker_cache.demand_miss_rate::total 0.263339 # miss rate for demand accesses 795system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.263339 # miss rate for overall accesses 796system.cpu.itb_walker_cache.overall_miss_rate::total 0.263339 # miss rate for overall accesses 797system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16006.894432 # average ReadReq miss latency 798system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16006.894432 # average ReadReq miss latency 799system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency 800system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16006.894432 # average overall miss latency 801system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency 802system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16006.894432 # average overall miss latency 803system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 804system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 805system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 806system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 807system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 808system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 809system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 810system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 811system.cpu.itb_walker_cache.writebacks::writebacks 1641 # number of writebacks 812system.cpu.itb_walker_cache.writebacks::total 1641 # number of writebacks 813system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11386 # number of ReadReq MSHR misses 814system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11386 # number of ReadReq MSHR misses 815system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11386 # number of demand (read+write) MSHR misses 816system.cpu.itb_walker_cache.demand_mshr_misses::total 11386 # number of demand (read+write) MSHR misses 817system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11386 # number of overall MSHR misses 818system.cpu.itb_walker_cache.overall_mshr_misses::total 11386 # number of overall MSHR misses 819system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147453030 # number of ReadReq MSHR miss cycles 820system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147453030 # number of ReadReq MSHR miss cycles 821system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147453030 # number of demand (read+write) MSHR miss cycles 822system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147453030 # number of demand (read+write) MSHR miss cycles 823system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147453030 # number of overall MSHR miss cycles 824system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147453030 # number of overall MSHR miss cycles 825system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.263358 # mshr miss rate for ReadReq accesses 826system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.263358 # mshr miss rate for ReadReq accesses 827system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for demand accesses 828system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.263339 # mshr miss rate for demand accesses 829system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for overall accesses 830system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.263339 # mshr miss rate for overall accesses 831system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average ReadReq mshr miss latency 832system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12950.380292 # average ReadReq mshr miss latency 833system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency 834system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency 835system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency 836system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency 837system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 838system.cpu.dtb_walker_cache.replacements 117278 # number of replacements 839system.cpu.dtb_walker_cache.tagsinuse 13.523999 # Cycle average of tags in use 840system.cpu.dtb_walker_cache.total_refs 136775 # Total number of references to valid blocks. 841system.cpu.dtb_walker_cache.sampled_refs 117293 # Sample count of references to valid blocks. 842system.cpu.dtb_walker_cache.avg_refs 1.166097 # Average number of references to valid blocks. 843system.cpu.dtb_walker_cache.warmup_cycle 5112876101000 # Cycle when the warmup percentage was hit. 844system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.523999 # Average occupied blocks per requestor 845system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.845250 # Average percentage of cache occupancy 846system.cpu.dtb_walker_cache.occ_percent::total 0.845250 # Average percentage of cache occupancy 847system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 136779 # number of ReadReq hits 848system.cpu.dtb_walker_cache.ReadReq_hits::total 136779 # number of ReadReq hits 849system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 136779 # number of demand (read+write) hits 850system.cpu.dtb_walker_cache.demand_hits::total 136779 # number of demand (read+write) hits 851system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 136779 # number of overall hits 852system.cpu.dtb_walker_cache.overall_hits::total 136779 # number of overall hits 853system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 118304 # number of ReadReq misses 854system.cpu.dtb_walker_cache.ReadReq_misses::total 118304 # number of ReadReq misses 855system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 118304 # number of demand (read+write) misses 856system.cpu.dtb_walker_cache.demand_misses::total 118304 # number of demand (read+write) misses 857system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 118304 # number of overall misses 858system.cpu.dtb_walker_cache.overall_misses::total 118304 # number of overall misses 859system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2123660000 # number of ReadReq miss cycles 860system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2123660000 # number of ReadReq miss cycles 861system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2123660000 # number of demand (read+write) miss cycles 862system.cpu.dtb_walker_cache.demand_miss_latency::total 2123660000 # number of demand (read+write) miss cycles 863system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2123660000 # number of overall miss cycles 864system.cpu.dtb_walker_cache.overall_miss_latency::total 2123660000 # number of overall miss cycles 865system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255083 # number of ReadReq accesses(hits+misses) 866system.cpu.dtb_walker_cache.ReadReq_accesses::total 255083 # number of ReadReq accesses(hits+misses) 867system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255083 # number of demand (read+write) accesses 868system.cpu.dtb_walker_cache.demand_accesses::total 255083 # number of demand (read+write) accesses 869system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255083 # number of overall (read+write) accesses 870system.cpu.dtb_walker_cache.overall_accesses::total 255083 # number of overall (read+write) accesses 871system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463786 # miss rate for ReadReq accesses 872system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463786 # miss rate for ReadReq accesses 873system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463786 # miss rate for demand accesses 874system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463786 # miss rate for demand accesses 875system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463786 # miss rate for overall accesses 876system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463786 # miss rate for overall accesses 877system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17950.872329 # average ReadReq miss latency 878system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17950.872329 # average ReadReq miss latency 879system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency 880system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17950.872329 # average overall miss latency 881system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency 882system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17950.872329 # average overall miss latency 883system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 884system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 885system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 886system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 887system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 888system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 889system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 890system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 891system.cpu.dtb_walker_cache.writebacks::writebacks 37674 # number of writebacks 892system.cpu.dtb_walker_cache.writebacks::total 37674 # number of writebacks 893system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 118304 # number of ReadReq MSHR misses 894system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 118304 # number of ReadReq MSHR misses 895system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 118304 # number of demand (read+write) MSHR misses 896system.cpu.dtb_walker_cache.demand_mshr_misses::total 118304 # number of demand (read+write) MSHR misses 897system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 118304 # number of overall MSHR misses 898system.cpu.dtb_walker_cache.overall_mshr_misses::total 118304 # number of overall MSHR misses 899system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of ReadReq MSHR miss cycles 900system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1766049009 # number of ReadReq MSHR miss cycles 901system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of demand (read+write) MSHR miss cycles 902system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1766049009 # number of demand (read+write) MSHR miss cycles 903system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of overall MSHR miss cycles 904system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1766049009 # number of overall MSHR miss cycles 905system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for ReadReq accesses 906system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463786 # mshr miss rate for ReadReq accesses 907system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for demand accesses 908system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463786 # mshr miss rate for demand accesses 909system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for overall accesses 910system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463786 # mshr miss rate for overall accesses 911system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average ReadReq mshr miss latency 912system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14928.058299 # average ReadReq mshr miss latency 913system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency 914system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency 915system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency 916system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency 917system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 918system.cpu.dcache.replacements 1673136 # number of replacements 919system.cpu.dcache.tagsinuse 511.997556 # Cycle average of tags in use 920system.cpu.dcache.total_refs 19006106 # Total number of references to valid blocks. 921system.cpu.dcache.sampled_refs 1673648 # Sample count of references to valid blocks. 922system.cpu.dcache.avg_refs 11.356095 # Average number of references to valid blocks. 923system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit. 924system.cpu.dcache.occ_blocks::cpu.data 511.997556 # Average occupied blocks per requestor 925system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy 926system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy 927system.cpu.dcache.ReadReq_hits::cpu.data 10928708 # number of ReadReq hits 928system.cpu.dcache.ReadReq_hits::total 10928708 # number of ReadReq hits 929system.cpu.dcache.WriteReq_hits::cpu.data 8074811 # number of WriteReq hits 930system.cpu.dcache.WriteReq_hits::total 8074811 # number of WriteReq hits 931system.cpu.dcache.demand_hits::cpu.data 19003519 # number of demand (read+write) hits 932system.cpu.dcache.demand_hits::total 19003519 # number of demand (read+write) hits 933system.cpu.dcache.overall_hits::cpu.data 19003519 # number of overall hits 934system.cpu.dcache.overall_hits::total 19003519 # number of overall hits 935system.cpu.dcache.ReadReq_misses::cpu.data 2430538 # number of ReadReq misses 936system.cpu.dcache.ReadReq_misses::total 2430538 # number of ReadReq misses 937system.cpu.dcache.WriteReq_misses::cpu.data 317333 # number of WriteReq misses 938system.cpu.dcache.WriteReq_misses::total 317333 # number of WriteReq misses 939system.cpu.dcache.demand_misses::cpu.data 2747871 # number of demand (read+write) misses 940system.cpu.dcache.demand_misses::total 2747871 # number of demand (read+write) misses 941system.cpu.dcache.overall_misses::cpu.data 2747871 # number of overall misses 942system.cpu.dcache.overall_misses::total 2747871 # number of overall misses 943system.cpu.dcache.ReadReq_miss_latency::cpu.data 45186101000 # number of ReadReq miss cycles 944system.cpu.dcache.ReadReq_miss_latency::total 45186101000 # number of ReadReq miss cycles 945system.cpu.dcache.WriteReq_miss_latency::cpu.data 10603069990 # number of WriteReq miss cycles 946system.cpu.dcache.WriteReq_miss_latency::total 10603069990 # number of WriteReq miss cycles 947system.cpu.dcache.demand_miss_latency::cpu.data 55789170990 # number of demand (read+write) miss cycles 948system.cpu.dcache.demand_miss_latency::total 55789170990 # number of demand (read+write) miss cycles 949system.cpu.dcache.overall_miss_latency::cpu.data 55789170990 # number of overall miss cycles 950system.cpu.dcache.overall_miss_latency::total 55789170990 # number of overall miss cycles 951system.cpu.dcache.ReadReq_accesses::cpu.data 13359246 # number of ReadReq accesses(hits+misses) 952system.cpu.dcache.ReadReq_accesses::total 13359246 # number of ReadReq accesses(hits+misses) 953system.cpu.dcache.WriteReq_accesses::cpu.data 8392144 # number of WriteReq accesses(hits+misses) 954system.cpu.dcache.WriteReq_accesses::total 8392144 # number of WriteReq accesses(hits+misses) 955system.cpu.dcache.demand_accesses::cpu.data 21751390 # number of demand (read+write) accesses 956system.cpu.dcache.demand_accesses::total 21751390 # number of demand (read+write) accesses 957system.cpu.dcache.overall_accesses::cpu.data 21751390 # number of overall (read+write) accesses 958system.cpu.dcache.overall_accesses::total 21751390 # number of overall (read+write) accesses 959system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181937 # miss rate for ReadReq accesses 960system.cpu.dcache.ReadReq_miss_rate::total 0.181937 # miss rate for ReadReq accesses 961system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses 962system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses 963system.cpu.dcache.demand_miss_rate::cpu.data 0.126331 # miss rate for demand accesses 964system.cpu.dcache.demand_miss_rate::total 0.126331 # miss rate for demand accesses 965system.cpu.dcache.overall_miss_rate::cpu.data 0.126331 # miss rate for overall accesses 966system.cpu.dcache.overall_miss_rate::total 0.126331 # miss rate for overall accesses 967system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18590.987263 # average ReadReq miss latency 968system.cpu.dcache.ReadReq_avg_miss_latency::total 18590.987263 # average ReadReq miss latency 969system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33413.070781 # average WriteReq miss latency 970system.cpu.dcache.WriteReq_avg_miss_latency::total 33413.070781 # average WriteReq miss latency 971system.cpu.dcache.demand_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency 972system.cpu.dcache.demand_avg_miss_latency::total 20302.689242 # average overall miss latency 973system.cpu.dcache.overall_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency 974system.cpu.dcache.overall_avg_miss_latency::total 20302.689242 # average overall miss latency 975system.cpu.dcache.blocked_cycles::no_mshrs 27875990 # number of cycles access was blocked 976system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 977system.cpu.dcache.blocked::no_mshrs 4957 # number of cycles access was blocked 978system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 979system.cpu.dcache.avg_blocked_cycles::no_mshrs 5623.560621 # average number of cycles each access was blocked 980system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 981system.cpu.dcache.fast_writes 0 # number of fast writes performed 982system.cpu.dcache.cache_copies 0 # number of cache copies performed 983system.cpu.dcache.writebacks::writebacks 1572269 # number of writebacks 984system.cpu.dcache.writebacks::total 1572269 # number of writebacks 985system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1049151 # number of ReadReq MSHR hits 986system.cpu.dcache.ReadReq_mshr_hits::total 1049151 # number of ReadReq MSHR hits 987system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22726 # number of WriteReq MSHR hits 988system.cpu.dcache.WriteReq_mshr_hits::total 22726 # number of WriteReq MSHR hits 989system.cpu.dcache.demand_mshr_hits::cpu.data 1071877 # number of demand (read+write) MSHR hits 990system.cpu.dcache.demand_mshr_hits::total 1071877 # number of demand (read+write) MSHR hits 991system.cpu.dcache.overall_mshr_hits::cpu.data 1071877 # number of overall MSHR hits 992system.cpu.dcache.overall_mshr_hits::total 1071877 # number of overall MSHR hits 993system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381387 # number of ReadReq MSHR misses 994system.cpu.dcache.ReadReq_mshr_misses::total 1381387 # number of ReadReq MSHR misses 995system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294607 # number of WriteReq MSHR misses 996system.cpu.dcache.WriteReq_mshr_misses::total 294607 # number of WriteReq MSHR misses 997system.cpu.dcache.demand_mshr_misses::cpu.data 1675994 # number of demand (read+write) MSHR misses 998system.cpu.dcache.demand_mshr_misses::total 1675994 # number of demand (read+write) MSHR misses 999system.cpu.dcache.overall_mshr_misses::cpu.data 1675994 # number of overall MSHR misses 1000system.cpu.dcache.overall_mshr_misses::total 1675994 # number of overall MSHR misses 1001system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23290713035 # number of ReadReq MSHR miss cycles 1002system.cpu.dcache.ReadReq_mshr_miss_latency::total 23290713035 # number of ReadReq MSHR miss cycles 1003system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9337845997 # number of WriteReq MSHR miss cycles 1004system.cpu.dcache.WriteReq_mshr_miss_latency::total 9337845997 # number of WriteReq MSHR miss cycles 1005system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32628559032 # number of demand (read+write) MSHR miss cycles 1006system.cpu.dcache.demand_mshr_miss_latency::total 32628559032 # number of demand (read+write) MSHR miss cycles 1007system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32628559032 # number of overall MSHR miss cycles 1008system.cpu.dcache.overall_mshr_miss_latency::total 32628559032 # number of overall MSHR miss cycles 1009system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207723000 # number of ReadReq MSHR uncacheable cycles 1010system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207723000 # number of ReadReq MSHR uncacheable cycles 1011system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386731000 # number of WriteReq MSHR uncacheable cycles 1012system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386731000 # number of WriteReq MSHR uncacheable cycles 1013system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86594454000 # number of overall MSHR uncacheable cycles 1014system.cpu.dcache.overall_mshr_uncacheable_latency::total 86594454000 # number of overall MSHR uncacheable cycles 1015system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103403 # mshr miss rate for ReadReq accesses 1016system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103403 # mshr miss rate for ReadReq accesses 1017system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035105 # mshr miss rate for WriteReq accesses 1018system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035105 # mshr miss rate for WriteReq accesses 1019system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for demand accesses 1020system.cpu.dcache.demand_mshr_miss_rate::total 0.077052 # mshr miss rate for demand accesses 1021system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for overall accesses 1022system.cpu.dcache.overall_mshr_miss_rate::total 0.077052 # mshr miss rate for overall accesses 1023system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16860.382380 # average ReadReq mshr miss latency 1024system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16860.382380 # average ReadReq mshr miss latency 1025system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31695.940684 # average WriteReq mshr miss latency 1026system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31695.940684 # average WriteReq mshr miss latency 1027system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency 1028system.cpu.dcache.demand_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency 1029system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency 1030system.cpu.dcache.overall_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency 1031system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1032system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1033system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1034system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1035system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1036system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1037system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1038system.cpu.kern.inst.arm 0 # number of arm instructions executed 1039system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1040 1041---------- End Simulation Statistics ---------- 1042