stats.txt revision 11245:1c5102c0a7a9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.144275 # Number of seconds simulated 4sim_ticks 5144274809000 # Number of ticks simulated 5final_tick 5144274809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 169693 # Simulator instruction rate (inst/s) 8host_op_rate 335427 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2145113000 # Simulator tick rate (ticks/s) 10host_mem_usage 770200 # Number of bytes of host memory used 11host_seconds 2398.14 # Real time elapsed on the host 12sim_insts 406947274 # Number of instructions simulated 13sim_ops 804399711 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1034048 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10709312 # Number of bytes read from this memory 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11775872 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1034048 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1034048 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9547776 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9547776 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 16157 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 167333 # Number of read requests responded to by this memory 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 183998 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 149184 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 149184 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 746 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.inst 201009 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 2081792 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2289122 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 201009 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 201009 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1856000 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1856000 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1856000 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 746 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.inst 201009 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 2081792 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4145122 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 183998 # Number of read requests accepted 52system.physmem.writeReqs 149184 # Number of write requests accepted 53system.physmem.readBursts 183998 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 149184 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 11761088 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 14784 # Total number of bytes read from write queue 57system.physmem.bytesWritten 9546240 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 11775872 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 9547776 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 231 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 58239 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 11315 # Per bank write bursts 64system.physmem.perBankRdBursts::1 10581 # Per bank write bursts 65system.physmem.perBankRdBursts::2 12129 # Per bank write bursts 66system.physmem.perBankRdBursts::3 11752 # Per bank write bursts 67system.physmem.perBankRdBursts::4 11319 # Per bank write bursts 68system.physmem.perBankRdBursts::5 10663 # Per bank write bursts 69system.physmem.perBankRdBursts::6 10930 # Per bank write bursts 70system.physmem.perBankRdBursts::7 11239 # Per bank write bursts 71system.physmem.perBankRdBursts::8 10920 # Per bank write bursts 72system.physmem.perBankRdBursts::9 11403 # Per bank write bursts 73system.physmem.perBankRdBursts::10 11471 # Per bank write bursts 74system.physmem.perBankRdBursts::11 11421 # Per bank write bursts 75system.physmem.perBankRdBursts::12 12415 # Per bank write bursts 76system.physmem.perBankRdBursts::13 12512 # Per bank write bursts 77system.physmem.perBankRdBursts::14 11823 # Per bank write bursts 78system.physmem.perBankRdBursts::15 11874 # Per bank write bursts 79system.physmem.perBankWrBursts::0 9756 # Per bank write bursts 80system.physmem.perBankWrBursts::1 9158 # Per bank write bursts 81system.physmem.perBankWrBursts::2 9767 # Per bank write bursts 82system.physmem.perBankWrBursts::3 9469 # Per bank write bursts 83system.physmem.perBankWrBursts::4 9300 # Per bank write bursts 84system.physmem.perBankWrBursts::5 9148 # Per bank write bursts 85system.physmem.perBankWrBursts::6 8815 # Per bank write bursts 86system.physmem.perBankWrBursts::7 8963 # Per bank write bursts 87system.physmem.perBankWrBursts::8 8876 # Per bank write bursts 88system.physmem.perBankWrBursts::9 9249 # Per bank write bursts 89system.physmem.perBankWrBursts::10 9141 # Per bank write bursts 90system.physmem.perBankWrBursts::11 9048 # Per bank write bursts 91system.physmem.perBankWrBursts::12 9841 # Per bank write bursts 92system.physmem.perBankWrBursts::13 9699 # Per bank write bursts 93system.physmem.perBankWrBursts::14 9635 # Per bank write bursts 94system.physmem.perBankWrBursts::15 9295 # Per bank write bursts 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 10 # Number of times write queue was full causing retry 97system.physmem.totGap 5144274759500 # Total gap between requests 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) 104system.physmem.readPktSize::6 183998 # Read request sizes (log2) 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) 111system.physmem.writePktSize::6 149184 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 169620 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 11412 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 1942 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 450 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 36 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 38 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 33 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 144system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 2916 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 7399 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 7449 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 8122 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 8310 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 9443 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 8747 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 9907 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 10037 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 9884 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 11487 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 9002 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 8428 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 8682 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 8054 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 7610 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 7540 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 380 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 268 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 294 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 173 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 146 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 158 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 126 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 170 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 142 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 93 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 70 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 63 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 50 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 41 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 36 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 72943 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 292.108413 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 174.353373 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 313.792232 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 28114 38.54% 38.54% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 17711 24.28% 62.82% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 7670 10.52% 73.34% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 4213 5.78% 79.11% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 2951 4.05% 83.16% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 2449 3.36% 86.52% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1349 1.85% 88.37% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 1138 1.56% 89.93% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 7348 10.07% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 72943 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 7277 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 25.251615 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 563.083563 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 7276 99.99% 99.99% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::total 7277 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 7277 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 20.497458 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 18.666266 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 13.148532 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 6223 85.52% 85.52% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 179 2.46% 87.98% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 37 0.51% 88.48% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 181 2.49% 90.97% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 17 0.23% 91.21% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 151 2.08% 93.28% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 102 1.40% 94.68% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 5 0.07% 94.75% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 29 0.40% 95.15% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 31 0.43% 95.58% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 5 0.07% 95.64% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 9 0.12% 95.77% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 222 3.05% 98.82% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 6 0.08% 98.90% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 6 0.08% 98.98% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 40 0.55% 99.53% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 1 0.01% 99.55% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::92-95 1 0.01% 99.56% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::100-103 5 0.07% 99.63% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::112-115 1 0.01% 99.64% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::120-123 1 0.01% 99.66% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::124-127 2 0.03% 99.68% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::128-131 17 0.23% 99.92% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::144-147 1 0.01% 99.95% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::164-167 1 0.01% 99.99% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::168-171 1 0.01% 100.00% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::total 7277 # Writes before turning the bus around for reads 261system.physmem.totQLat 2097648589 # Total ticks spent queuing 262system.physmem.totMemAccLat 5543279839 # Total ticks spent from burst creation until serviced by the DRAM 263system.physmem.totBusLat 918835000 # Total ticks spent in databus transfers 264system.physmem.avgQLat 11414.72 # Average queueing delay per DRAM burst 265system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 266system.physmem.avgMemAccLat 30164.72 # Average memory access latency per DRAM burst 267system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s 268system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s 269system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s 270system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s 271system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 272system.physmem.busUtil 0.03 # Data bus utilization in percentage 273system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 274system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 275system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 276system.physmem.avgWrQLen 21.26 # Average write queue length when enqueuing 277system.physmem.readRowHits 150147 # Number of row buffer hits during reads 278system.physmem.writeRowHits 109836 # Number of row buffer hits during writes 279system.physmem.readRowHitRate 81.71 # Row buffer hit rate for reads 280system.physmem.writeRowHitRate 73.62 # Row buffer hit rate for writes 281system.physmem.avgGap 15439833.96 # Average gap between requests 282system.physmem.pageHitRate 78.08 # Row buffer hit rate, read and write combined 283system.physmem_0.actEnergy 269030160 # Energy for activate commands per rank (pJ) 284system.physmem_0.preEnergy 146792250 # Energy for precharge commands per rank (pJ) 285system.physmem_0.readEnergy 701430600 # Energy for read commands per rank (pJ) 286system.physmem_0.writeEnergy 481956480 # Energy for write commands per rank (pJ) 287system.physmem_0.refreshEnergy 335998980720 # Energy for refresh commands per rank (pJ) 288system.physmem_0.actBackEnergy 132992885070 # Energy for active background per rank (pJ) 289system.physmem_0.preBackEnergy 2969904214500 # Energy for precharge background per rank (pJ) 290system.physmem_0.totalEnergy 3440495289780 # Total energy per rank (pJ) 291system.physmem_0.averagePower 668.800889 # Core power per rank (mW) 292system.physmem_0.memoryStateTime::IDLE 4940616567724 # Time in different power states 293system.physmem_0.memoryStateTime::REF 171778620000 # Time in different power states 294system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 295system.physmem_0.memoryStateTime::ACT 31879461276 # Time in different power states 296system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 297system.physmem_1.actEnergy 282418920 # Energy for activate commands per rank (pJ) 298system.physmem_1.preEnergy 154097625 # Energy for precharge commands per rank (pJ) 299system.physmem_1.readEnergy 731944200 # Energy for read commands per rank (pJ) 300system.physmem_1.writeEnergy 484600320 # Energy for write commands per rank (pJ) 301system.physmem_1.refreshEnergy 335998980720 # Energy for refresh commands per rank (pJ) 302system.physmem_1.actBackEnergy 133085381535 # Energy for active background per rank (pJ) 303system.physmem_1.preBackEnergy 2969823077250 # Energy for precharge background per rank (pJ) 304system.physmem_1.totalEnergy 3440560500570 # Total energy per rank (pJ) 305system.physmem_1.averagePower 668.813565 # Core power per rank (mW) 306system.physmem_1.memoryStateTime::IDLE 4940481114488 # Time in different power states 307system.physmem_1.memoryStateTime::REF 171778620000 # Time in different power states 308system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 309system.physmem_1.memoryStateTime::ACT 32014679262 # Time in different power states 310system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 311system.cpu.branchPred.lookups 86341843 # Number of BP lookups 312system.cpu.branchPred.condPredicted 86341843 # Number of conditional branches predicted 313system.cpu.branchPred.condIncorrect 843606 # Number of conditional branches incorrect 314system.cpu.branchPred.BTBLookups 79482226 # Number of BTB lookups 315system.cpu.branchPred.BTBHits 77803537 # Number of BTB hits 316system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 317system.cpu.branchPred.BTBHitPct 97.887969 # BTB Hit Percentage 318system.cpu.branchPred.usedRAS 1532975 # Number of times the RAS was used to get a target. 319system.cpu.branchPred.RASInCorrect 177711 # Number of incorrect RAS predictions. 320system.cpu_clk_domain.clock 500 # Clock period in ticks 321system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 322system.cpu.numCycles 465489033 # number of cpu cycles simulated 323system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 324system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 325system.cpu.fetch.icacheStallCycles 27349012 # Number of cycles fetch is stalled on an Icache miss 326system.cpu.fetch.Insts 426558725 # Number of instructions fetch has processed 327system.cpu.fetch.Branches 86341843 # Number of branches that fetch encountered 328system.cpu.fetch.predictedBranches 79336512 # Number of branches that fetch has predicted taken 329system.cpu.fetch.Cycles 433328456 # Number of cycles fetch has run and was not squashing or blocked 330system.cpu.fetch.SquashCycles 1773234 # Number of cycles fetch has spent squashing 331system.cpu.fetch.TlbCycles 140367 # Number of cycles fetch has spent waiting for tlb 332system.cpu.fetch.MiscStallCycles 61411 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 333system.cpu.fetch.PendingTrapStallCycles 195746 # Number of stall cycles due to pending traps 334system.cpu.fetch.PendingQuiesceStallCycles 62 # Number of stall cycles due to pending quiesce instructions 335system.cpu.fetch.IcacheWaitRetryStallCycles 949 # Number of stall cycles due to full MSHR 336system.cpu.fetch.CacheLines 8924695 # Number of cache lines fetched 337system.cpu.fetch.IcacheSquashes 425342 # Number of outstanding Icache misses that were squashed 338system.cpu.fetch.ItlbSquashes 4681 # Number of outstanding ITLB misses that were squashed 339system.cpu.fetch.rateDist::samples 461962620 # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::mean 1.822369 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::stdev 3.015343 # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::0 297385469 64.37% 64.37% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::1 2141918 0.46% 64.84% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::2 72009169 15.59% 80.43% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::3 1542851 0.33% 80.76% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::4 2093373 0.45% 81.21% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::5 2277762 0.49% 81.71% # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::6 1468275 0.32% 82.02% # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::7 1844826 0.40% 82.42% # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::8 81198977 17.58% 100.00% # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 355system.cpu.fetch.rateDist::total 461962620 # Number of instructions fetched each cycle (Total) 356system.cpu.fetch.branchRate 0.185486 # Number of branch fetches per cycle 357system.cpu.fetch.rate 0.916367 # Number of inst fetches per cycle 358system.cpu.decode.IdleCycles 23051751 # Number of cycles decode is idle 359system.cpu.decode.BlockedCycles 281963390 # Number of cycles decode is blocked 360system.cpu.decode.RunCycles 147749616 # Number of cycles decode is running 361system.cpu.decode.UnblockCycles 8311246 # Number of cycles decode is unblocking 362system.cpu.decode.SquashCycles 886617 # Number of cycles decode is squashing 363system.cpu.decode.DecodedInsts 834090099 # Number of instructions handled by decode 364system.cpu.rename.SquashCycles 886617 # Number of cycles rename is squashing 365system.cpu.rename.IdleCycles 26334343 # Number of cycles rename is idle 366system.cpu.rename.BlockCycles 229948938 # Number of cycles rename is blocking 367system.cpu.rename.serializeStallCycles 14545958 # count of cycles rename stalled for serializing inst 368system.cpu.rename.RunCycles 152100341 # Number of cycles rename is running 369system.cpu.rename.UnblockCycles 38146423 # Number of cycles rename is unblocking 370system.cpu.rename.RenamedInsts 830806639 # Number of instructions processed by rename 371system.cpu.rename.ROBFullEvents 454355 # Number of times rename has blocked due to ROB full 372system.cpu.rename.IQFullEvents 12555277 # Number of times rename has blocked due to IQ full 373system.cpu.rename.LQFullEvents 214921 # Number of times rename has blocked due to LQ full 374system.cpu.rename.SQFullEvents 22219847 # Number of times rename has blocked due to SQ full 375system.cpu.rename.RenamedOperands 992487524 # Number of destination operands rename has renamed 376system.cpu.rename.RenameLookups 1803840100 # Number of register rename lookups that rename has made 377system.cpu.rename.int_rename_lookups 1108929979 # Number of integer rename lookups 378system.cpu.rename.fp_rename_lookups 295 # Number of floating rename lookups 379system.cpu.rename.CommittedMaps 961885153 # Number of HB maps that are committed 380system.cpu.rename.UndoneMaps 30602369 # Number of HB maps that are undone due to squashing 381system.cpu.rename.serializingInsts 460175 # count of serializing insts renamed 382system.cpu.rename.tempSerializingInsts 463946 # count of temporary serializing insts renamed 383system.cpu.rename.skidInsts 42648824 # count of insts added to the skid buffer 384system.cpu.memDep0.insertedLoads 17020536 # Number of loads inserted to the mem dependence unit. 385system.cpu.memDep0.insertedStores 10013615 # Number of stores inserted to the mem dependence unit. 386system.cpu.memDep0.conflictingLoads 1265948 # Number of conflicting loads. 387system.cpu.memDep0.conflictingStores 1065839 # Number of conflicting stores. 388system.cpu.iq.iqInstsAdded 825617137 # Number of instructions added to the IQ (excludes non-spec) 389system.cpu.iq.iqNonSpecInstsAdded 1152647 # Number of non-speculative instructions added to the IQ 390system.cpu.iq.iqInstsIssued 820744592 # Number of instructions issued 391system.cpu.iq.iqSquashedInstsIssued 214843 # Number of squashed instructions issued 392system.cpu.iq.iqSquashedInstsExamined 22370068 # Number of squashed instructions iterated over during squash; mainly for profiling 393system.cpu.iq.iqSquashedOperandsExamined 33775079 # Number of squashed operands that are examined and possibly removed from graph 394system.cpu.iq.iqSquashedNonSpecRemoved 142908 # Number of squashed non-spec instructions that were removed 395system.cpu.iq.issued_per_cycle::samples 461962620 # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::mean 1.776647 # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::stdev 2.400230 # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::0 278779319 60.35% 60.35% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::1 13677385 2.96% 63.31% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::2 9694463 2.10% 65.41% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::3 7479161 1.62% 67.02% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::4 73155086 15.84% 82.86% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::5 4780135 1.03% 83.90% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::6 72637826 15.72% 99.62% # Number of insts issued each cycle 406system.cpu.iq.issued_per_cycle::7 1181137 0.26% 99.87% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::8 578108 0.13% 100.00% # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 409system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 410system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 411system.cpu.iq.issued_per_cycle::total 461962620 # Number of insts issued each cycle 412system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 413system.cpu.iq.fu_full::IntAlu 2412123 76.39% 76.39% # attempts to use FU when none available 414system.cpu.iq.fu_full::IntMult 0 0.00% 76.39% # attempts to use FU when none available 415system.cpu.iq.fu_full::IntDiv 0 0.00% 76.39% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.39% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.39% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.39% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatMult 0 0.00% 76.39% # attempts to use FU when none available 420system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.39% # attempts to use FU when none available 421system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.39% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.39% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.39% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.39% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.39% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.39% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.39% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdMult 0 0.00% 76.39% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.39% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdShift 0 0.00% 76.39% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.39% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.39% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.39% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.39% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.39% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.39% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.39% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.39% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.39% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.39% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.39% # attempts to use FU when none available 442system.cpu.iq.fu_full::MemRead 586072 18.56% 94.95% # attempts to use FU when none available 443system.cpu.iq.fu_full::MemWrite 159607 5.05% 100.00% # attempts to use FU when none available 444system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 445system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 446system.cpu.iq.FU_type_0::No_OpClass 284241 0.03% 0.03% # Type of FU issued 447system.cpu.iq.FU_type_0::IntAlu 792878234 96.60% 96.64% # Type of FU issued 448system.cpu.iq.FU_type_0::IntMult 149840 0.02% 96.66% # Type of FU issued 449system.cpu.iq.FU_type_0::IntDiv 126459 0.02% 96.67% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.67% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.67% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatCvt 91 0.00% 96.67% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.67% # Type of FU issued 454system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.67% # Type of FU issued 455system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.67% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.67% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.67% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.67% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.67% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.67% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.67% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.67% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.67% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.67% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.67% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.67% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.67% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.67% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.67% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.67% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.67% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.67% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.67% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.67% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.67% # Type of FU issued 476system.cpu.iq.FU_type_0::MemRead 18033989 2.20% 98.87% # Type of FU issued 477system.cpu.iq.FU_type_0::MemWrite 9271738 1.13% 100.00% # Type of FU issued 478system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 479system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 480system.cpu.iq.FU_type_0::total 820744592 # Type of FU issued 481system.cpu.iq.rate 1.763188 # Inst issue rate 482system.cpu.iq.fu_busy_cnt 3157802 # FU busy when requested 483system.cpu.iq.fu_busy_rate 0.003847 # FU busy rate (busy events/executed inst) 484system.cpu.iq.int_inst_queue_reads 2106824012 # Number of integer instruction queue reads 485system.cpu.iq.int_inst_queue_writes 849151947 # Number of integer instruction queue writes 486system.cpu.iq.int_inst_queue_wakeup_accesses 816471101 # Number of integer instruction queue wakeup accesses 487system.cpu.iq.fp_inst_queue_reads 436 # Number of floating instruction queue reads 488system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes 489system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses 490system.cpu.iq.int_alu_accesses 823617942 # Number of integer alu accesses 491system.cpu.iq.fp_alu_accesses 211 # Number of floating point alu accesses 492system.cpu.iew.lsq.thread0.forwLoads 1861954 # Number of loads that had data forwarded from stores 493system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 494system.cpu.iew.lsq.thread0.squashedLoads 3065804 # Number of loads squashed 495system.cpu.iew.lsq.thread0.ignoredResponses 14153 # Number of memory responses ignored because the instruction is squashed 496system.cpu.iew.lsq.thread0.memOrderViolation 14111 # Number of memory ordering violations 497system.cpu.iew.lsq.thread0.squashedStores 1593948 # Number of stores squashed 498system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 499system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 500system.cpu.iew.lsq.thread0.rescheduledLoads 2095806 # Number of loads that were rescheduled 501system.cpu.iew.lsq.thread0.cacheBlocked 68873 # Number of times an access to memory failed due to the cache being blocked 502system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 503system.cpu.iew.iewSquashCycles 886617 # Number of cycles IEW is squashing 504system.cpu.iew.iewBlockCycles 206103955 # Number of cycles IEW is blocking 505system.cpu.iew.iewUnblockCycles 15659492 # Number of cycles IEW is unblocking 506system.cpu.iew.iewDispatchedInsts 826769784 # Number of instructions dispatched to IQ 507system.cpu.iew.iewDispSquashedInsts 162986 # Number of squashed instructions skipped by dispatch 508system.cpu.iew.iewDispLoadInsts 17020536 # Number of dispatched load instructions 509system.cpu.iew.iewDispStoreInsts 10013615 # Number of dispatched store instructions 510system.cpu.iew.iewDispNonSpecInsts 683525 # Number of dispatched non-speculative instructions 511system.cpu.iew.iewIQFullEvents 383471 # Number of times the IQ has become full, causing a stall 512system.cpu.iew.iewLSQFullEvents 14451239 # Number of times the LSQ has become full, causing a stall 513system.cpu.iew.memOrderViolationEvents 14111 # Number of memory order violations 514system.cpu.iew.predictedTakenIncorrect 476576 # Number of branches that were predicted taken incorrectly 515system.cpu.iew.predictedNotTakenIncorrect 506351 # Number of branches that were predicted not taken incorrectly 516system.cpu.iew.branchMispredicts 982927 # Number of branch mispredicts detected at execute 517system.cpu.iew.iewExecutedInsts 819239221 # Number of executed instructions 518system.cpu.iew.iewExecLoadInsts 17663851 # Number of load instructions executed 519system.cpu.iew.iewExecSquashedInsts 1381012 # Number of squashed instructions skipped in execute 520system.cpu.iew.exec_swp 0 # number of swp insts executed 521system.cpu.iew.exec_nop 0 # number of nop insts executed 522system.cpu.iew.exec_refs 26724913 # number of memory reference insts executed 523system.cpu.iew.exec_branches 82983667 # Number of branches executed 524system.cpu.iew.exec_stores 9061062 # Number of stores executed 525system.cpu.iew.exec_rate 1.759954 # Inst execution rate 526system.cpu.iew.wb_sent 818769187 # cumulative count of insts sent to commit 527system.cpu.iew.wb_count 816471257 # cumulative count of insts written-back 528system.cpu.iew.wb_producers 638649867 # num instructions producing a value 529system.cpu.iew.wb_consumers 1046653125 # num instructions consuming a value 530system.cpu.iew.wb_rate 1.754008 # insts written-back per cycle 531system.cpu.iew.wb_fanout 0.610183 # average fanout of values written-back 532system.cpu.commit.commitSquashedInsts 22245724 # The number of squashed insts skipped by commit 533system.cpu.commit.commitNonSpecStalls 1009739 # The number of times commit has been forced to stall to communicate backwards 534system.cpu.commit.branchMispredicts 854697 # The number of times a branch was mispredicted 535system.cpu.commit.committed_per_cycle::samples 458607756 # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::mean 1.754004 # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::stdev 2.647518 # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::0 288145143 62.83% 62.83% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::1 11087272 2.42% 65.25% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::2 3640468 0.79% 66.04% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::3 74478879 16.24% 82.28% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::4 2430107 0.53% 82.81% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::5 1625402 0.35% 83.17% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::6 1001040 0.22% 83.38% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::7 70854372 15.45% 98.83% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::8 5345073 1.17% 100.00% # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::total 458607756 # Number of insts commited each cycle 552system.cpu.commit.committedInsts 406947274 # Number of instructions committed 553system.cpu.commit.committedOps 804399711 # Number of ops (including micro ops) committed 554system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 555system.cpu.commit.refs 22374398 # Number of memory references committed 556system.cpu.commit.loads 13954731 # Number of loads committed 557system.cpu.commit.membars 448033 # Number of memory barriers committed 558system.cpu.commit.branches 81999646 # Number of branches committed 559system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 560system.cpu.commit.int_insts 733379682 # Number of committed integer instructions. 561system.cpu.commit.function_calls 1155571 # Number of function calls committed. 562system.cpu.commit.op_class_0::No_OpClass 171831 0.02% 0.02% # Class of committed instruction 563system.cpu.commit.op_class_0::IntAlu 781589650 97.16% 97.19% # Class of committed instruction 564system.cpu.commit.op_class_0::IntMult 144528 0.02% 97.20% # Class of committed instruction 565system.cpu.commit.op_class_0::IntDiv 121874 0.02% 97.22% # Class of committed instruction 566system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 567system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 568system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction 569system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 570system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 571system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction 574system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction 576system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction 577system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction 578system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction 579system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction 580system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction 581system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction 582system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction 583system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction 584system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 585system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 586system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 587system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 588system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 589system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 590system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 591system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction 592system.cpu.commit.op_class_0::MemRead 13952145 1.73% 98.95% # Class of committed instruction 593system.cpu.commit.op_class_0::MemWrite 8419667 1.05% 100.00% # Class of committed instruction 594system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 595system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 596system.cpu.commit.op_class_0::total 804399711 # Class of committed instruction 597system.cpu.commit.bw_lim_events 5345073 # number cycles where commit BW limit reached 598system.cpu.rob.rob_reads 1279829790 # The number of ROB reads 599system.cpu.rob.rob_writes 1656663443 # The number of ROB writes 600system.cpu.timesIdled 287506 # Number of times that the entire CPU went into an idle state and unscheduled itself 601system.cpu.idleCycles 3526413 # Total number of cycles that the CPU has spent unscheduled due to idling 602system.cpu.quiesceCycles 9823058000 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 603system.cpu.committedInsts 406947274 # Number of Instructions Simulated 604system.cpu.committedOps 804399711 # Number of Ops (including micro ops) Simulated 605system.cpu.cpi 1.143856 # CPI: Cycles Per Instruction 606system.cpu.cpi_total 1.143856 # CPI: Total CPI of All Threads 607system.cpu.ipc 0.874236 # IPC: Instructions Per Cycle 608system.cpu.ipc_total 0.874236 # IPC: Total IPC of All Threads 609system.cpu.int_regfile_reads 1088022059 # number of integer regfile reads 610system.cpu.int_regfile_writes 653481018 # number of integer regfile writes 611system.cpu.fp_regfile_reads 156 # number of floating regfile reads 612system.cpu.cc_regfile_reads 414844045 # number of cc regfile reads 613system.cpu.cc_regfile_writes 320950754 # number of cc regfile writes 614system.cpu.misc_regfile_reads 264261421 # number of misc regfile reads 615system.cpu.misc_regfile_writes 400173 # number of misc regfile writes 616system.cpu.dcache.tags.replacements 1656014 # number of replacements 617system.cpu.dcache.tags.tagsinuse 511.995636 # Cycle average of tags in use 618system.cpu.dcache.tags.total_refs 18946459 # Total number of references to valid blocks. 619system.cpu.dcache.tags.sampled_refs 1656526 # Sample count of references to valid blocks. 620system.cpu.dcache.tags.avg_refs 11.437466 # Average number of references to valid blocks. 621system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit. 622system.cpu.dcache.tags.occ_blocks::cpu.data 511.995636 # Average occupied blocks per requestor 623system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy 624system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy 625system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 626system.cpu.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id 627system.cpu.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id 628system.cpu.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id 629system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 630system.cpu.dcache.tags.tag_accesses 87599396 # Number of tag accesses 631system.cpu.dcache.tags.data_accesses 87599396 # Number of data accesses 632system.cpu.dcache.ReadReq_hits::cpu.data 10805755 # number of ReadReq hits 633system.cpu.dcache.ReadReq_hits::total 10805755 # number of ReadReq hits 634system.cpu.dcache.WriteReq_hits::cpu.data 8075007 # number of WriteReq hits 635system.cpu.dcache.WriteReq_hits::total 8075007 # number of WriteReq hits 636system.cpu.dcache.SoftPFReq_hits::cpu.data 62855 # number of SoftPFReq hits 637system.cpu.dcache.SoftPFReq_hits::total 62855 # number of SoftPFReq hits 638system.cpu.dcache.demand_hits::cpu.data 18880762 # number of demand (read+write) hits 639system.cpu.dcache.demand_hits::total 18880762 # number of demand (read+write) hits 640system.cpu.dcache.overall_hits::cpu.data 18943617 # number of overall hits 641system.cpu.dcache.overall_hits::total 18943617 # number of overall hits 642system.cpu.dcache.ReadReq_misses::cpu.data 1800696 # number of ReadReq misses 643system.cpu.dcache.ReadReq_misses::total 1800696 # number of ReadReq misses 644system.cpu.dcache.WriteReq_misses::cpu.data 334991 # number of WriteReq misses 645system.cpu.dcache.WriteReq_misses::total 334991 # number of WriteReq misses 646system.cpu.dcache.SoftPFReq_misses::cpu.data 406405 # number of SoftPFReq misses 647system.cpu.dcache.SoftPFReq_misses::total 406405 # number of SoftPFReq misses 648system.cpu.dcache.demand_misses::cpu.data 2135687 # number of demand (read+write) misses 649system.cpu.dcache.demand_misses::total 2135687 # number of demand (read+write) misses 650system.cpu.dcache.overall_misses::cpu.data 2542092 # number of overall misses 651system.cpu.dcache.overall_misses::total 2542092 # number of overall misses 652system.cpu.dcache.ReadReq_miss_latency::cpu.data 30137867500 # number of ReadReq miss cycles 653system.cpu.dcache.ReadReq_miss_latency::total 30137867500 # number of ReadReq miss cycles 654system.cpu.dcache.WriteReq_miss_latency::cpu.data 21089945740 # number of WriteReq miss cycles 655system.cpu.dcache.WriteReq_miss_latency::total 21089945740 # number of WriteReq miss cycles 656system.cpu.dcache.demand_miss_latency::cpu.data 51227813240 # number of demand (read+write) miss cycles 657system.cpu.dcache.demand_miss_latency::total 51227813240 # number of demand (read+write) miss cycles 658system.cpu.dcache.overall_miss_latency::cpu.data 51227813240 # number of overall miss cycles 659system.cpu.dcache.overall_miss_latency::total 51227813240 # number of overall miss cycles 660system.cpu.dcache.ReadReq_accesses::cpu.data 12606451 # number of ReadReq accesses(hits+misses) 661system.cpu.dcache.ReadReq_accesses::total 12606451 # number of ReadReq accesses(hits+misses) 662system.cpu.dcache.WriteReq_accesses::cpu.data 8409998 # number of WriteReq accesses(hits+misses) 663system.cpu.dcache.WriteReq_accesses::total 8409998 # number of WriteReq accesses(hits+misses) 664system.cpu.dcache.SoftPFReq_accesses::cpu.data 469260 # number of SoftPFReq accesses(hits+misses) 665system.cpu.dcache.SoftPFReq_accesses::total 469260 # number of SoftPFReq accesses(hits+misses) 666system.cpu.dcache.demand_accesses::cpu.data 21016449 # number of demand (read+write) accesses 667system.cpu.dcache.demand_accesses::total 21016449 # number of demand (read+write) accesses 668system.cpu.dcache.overall_accesses::cpu.data 21485709 # number of overall (read+write) accesses 669system.cpu.dcache.overall_accesses::total 21485709 # number of overall (read+write) accesses 670system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142839 # miss rate for ReadReq accesses 671system.cpu.dcache.ReadReq_miss_rate::total 0.142839 # miss rate for ReadReq accesses 672system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039832 # miss rate for WriteReq accesses 673system.cpu.dcache.WriteReq_miss_rate::total 0.039832 # miss rate for WriteReq accesses 674system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.866055 # miss rate for SoftPFReq accesses 675system.cpu.dcache.SoftPFReq_miss_rate::total 0.866055 # miss rate for SoftPFReq accesses 676system.cpu.dcache.demand_miss_rate::cpu.data 0.101620 # miss rate for demand accesses 677system.cpu.dcache.demand_miss_rate::total 0.101620 # miss rate for demand accesses 678system.cpu.dcache.overall_miss_rate::cpu.data 0.118315 # miss rate for overall accesses 679system.cpu.dcache.overall_miss_rate::total 0.118315 # miss rate for overall accesses 680system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16736.788164 # average ReadReq miss latency 681system.cpu.dcache.ReadReq_avg_miss_latency::total 16736.788164 # average ReadReq miss latency 682system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62956.753286 # average WriteReq miss latency 683system.cpu.dcache.WriteReq_avg_miss_latency::total 62956.753286 # average WriteReq miss latency 684system.cpu.dcache.demand_avg_miss_latency::cpu.data 23986.573519 # average overall miss latency 685system.cpu.dcache.demand_avg_miss_latency::total 23986.573519 # average overall miss latency 686system.cpu.dcache.overall_avg_miss_latency::cpu.data 20151.832916 # average overall miss latency 687system.cpu.dcache.overall_avg_miss_latency::total 20151.832916 # average overall miss latency 688system.cpu.dcache.blocked_cycles::no_mshrs 556428 # number of cycles access was blocked 689system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 690system.cpu.dcache.blocked::no_mshrs 52454 # number of cycles access was blocked 691system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 692system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.607923 # average number of cycles each access was blocked 693system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 694system.cpu.dcache.fast_writes 0 # number of fast writes performed 695system.cpu.dcache.cache_copies 0 # number of cache copies performed 696system.cpu.dcache.writebacks::writebacks 1558074 # number of writebacks 697system.cpu.dcache.writebacks::total 1558074 # number of writebacks 698system.cpu.dcache.ReadReq_mshr_hits::cpu.data 834885 # number of ReadReq MSHR hits 699system.cpu.dcache.ReadReq_mshr_hits::total 834885 # number of ReadReq MSHR hits 700system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44903 # number of WriteReq MSHR hits 701system.cpu.dcache.WriteReq_mshr_hits::total 44903 # number of WriteReq MSHR hits 702system.cpu.dcache.demand_mshr_hits::cpu.data 879788 # number of demand (read+write) MSHR hits 703system.cpu.dcache.demand_mshr_hits::total 879788 # number of demand (read+write) MSHR hits 704system.cpu.dcache.overall_mshr_hits::cpu.data 879788 # number of overall MSHR hits 705system.cpu.dcache.overall_mshr_hits::total 879788 # number of overall MSHR hits 706system.cpu.dcache.ReadReq_mshr_misses::cpu.data 965811 # number of ReadReq MSHR misses 707system.cpu.dcache.ReadReq_mshr_misses::total 965811 # number of ReadReq MSHR misses 708system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290088 # number of WriteReq MSHR misses 709system.cpu.dcache.WriteReq_mshr_misses::total 290088 # number of WriteReq MSHR misses 710system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402915 # number of SoftPFReq MSHR misses 711system.cpu.dcache.SoftPFReq_mshr_misses::total 402915 # number of SoftPFReq MSHR misses 712system.cpu.dcache.demand_mshr_misses::cpu.data 1255899 # number of demand (read+write) MSHR misses 713system.cpu.dcache.demand_mshr_misses::total 1255899 # number of demand (read+write) MSHR misses 714system.cpu.dcache.overall_mshr_misses::cpu.data 1658814 # number of overall MSHR misses 715system.cpu.dcache.overall_mshr_misses::total 1658814 # number of overall MSHR misses 716system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable 717system.cpu.dcache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable 718system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13899 # number of WriteReq MSHR uncacheable 719system.cpu.dcache.WriteReq_mshr_uncacheable::total 13899 # number of WriteReq MSHR uncacheable 720system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587359 # number of overall MSHR uncacheable misses 721system.cpu.dcache.overall_mshr_uncacheable_misses::total 587359 # number of overall MSHR uncacheable misses 722system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14288232000 # number of ReadReq MSHR miss cycles 723system.cpu.dcache.ReadReq_mshr_miss_latency::total 14288232000 # number of ReadReq MSHR miss cycles 724system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19138141242 # number of WriteReq MSHR miss cycles 725system.cpu.dcache.WriteReq_mshr_miss_latency::total 19138141242 # number of WriteReq MSHR miss cycles 726system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6806565500 # number of SoftPFReq MSHR miss cycles 727system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6806565500 # number of SoftPFReq MSHR miss cycles 728system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33426373242 # number of demand (read+write) MSHR miss cycles 729system.cpu.dcache.demand_mshr_miss_latency::total 33426373242 # number of demand (read+write) MSHR miss cycles 730system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40232938742 # number of overall MSHR miss cycles 731system.cpu.dcache.overall_mshr_miss_latency::total 40232938742 # number of overall MSHR miss cycles 732system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98114325000 # number of ReadReq MSHR uncacheable cycles 733system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98114325000 # number of ReadReq MSHR uncacheable cycles 734system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2778681500 # number of WriteReq MSHR uncacheable cycles 735system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2778681500 # number of WriteReq MSHR uncacheable cycles 736system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100893006500 # number of overall MSHR uncacheable cycles 737system.cpu.dcache.overall_mshr_uncacheable_latency::total 100893006500 # number of overall MSHR uncacheable cycles 738system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076612 # mshr miss rate for ReadReq accesses 739system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076612 # mshr miss rate for ReadReq accesses 740system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034493 # mshr miss rate for WriteReq accesses 741system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034493 # mshr miss rate for WriteReq accesses 742system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858618 # mshr miss rate for SoftPFReq accesses 743system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858618 # mshr miss rate for SoftPFReq accesses 744system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059758 # mshr miss rate for demand accesses 745system.cpu.dcache.demand_mshr_miss_rate::total 0.059758 # mshr miss rate for demand accesses 746system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077205 # mshr miss rate for overall accesses 747system.cpu.dcache.overall_mshr_miss_rate::total 0.077205 # mshr miss rate for overall accesses 748system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14794.024918 # average ReadReq mshr miss latency 749system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14794.024918 # average ReadReq mshr miss latency 750system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65973.570923 # average WriteReq mshr miss latency 751system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65973.570923 # average WriteReq mshr miss latency 752system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16893.303799 # average SoftPFReq mshr miss latency 753system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16893.303799 # average SoftPFReq mshr miss latency 754system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26615.494751 # average overall mshr miss latency 755system.cpu.dcache.demand_avg_mshr_miss_latency::total 26615.494751 # average overall mshr miss latency 756system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24254.038573 # average overall mshr miss latency 757system.cpu.dcache.overall_avg_mshr_miss_latency::total 24254.038573 # average overall mshr miss latency 758system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171091.837269 # average ReadReq mshr uncacheable latency 759system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171091.837269 # average ReadReq mshr uncacheable latency 760system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199919.526585 # average WriteReq mshr uncacheable latency 761system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199919.526585 # average WriteReq mshr uncacheable latency 762system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171774.002782 # average overall mshr uncacheable latency 763system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171774.002782 # average overall mshr uncacheable latency 764system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 765system.cpu.dtb_walker_cache.tags.replacements 76780 # number of replacements 766system.cpu.dtb_walker_cache.tags.tagsinuse 15.821773 # Cycle average of tags in use 767system.cpu.dtb_walker_cache.tags.total_refs 101894 # Total number of references to valid blocks. 768system.cpu.dtb_walker_cache.tags.sampled_refs 76796 # Sample count of references to valid blocks. 769system.cpu.dtb_walker_cache.tags.avg_refs 1.326814 # Average number of references to valid blocks. 770system.cpu.dtb_walker_cache.tags.warmup_cycle 199830391500 # Cycle when the warmup percentage was hit. 771system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821773 # Average occupied blocks per requestor 772system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988861 # Average percentage of cache occupancy 773system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988861 # Average percentage of cache occupancy 774system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id 775system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 776system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id 777system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 778system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 779system.cpu.dtb_walker_cache.tags.tag_accesses 437119 # Number of tag accesses 780system.cpu.dtb_walker_cache.tags.data_accesses 437119 # Number of data accesses 781system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 101894 # number of ReadReq hits 782system.cpu.dtb_walker_cache.ReadReq_hits::total 101894 # number of ReadReq hits 783system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 101894 # number of demand (read+write) hits 784system.cpu.dtb_walker_cache.demand_hits::total 101894 # number of demand (read+write) hits 785system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 101894 # number of overall hits 786system.cpu.dtb_walker_cache.overall_hits::total 101894 # number of overall hits 787system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77777 # number of ReadReq misses 788system.cpu.dtb_walker_cache.ReadReq_misses::total 77777 # number of ReadReq misses 789system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77777 # number of demand (read+write) misses 790system.cpu.dtb_walker_cache.demand_misses::total 77777 # number of demand (read+write) misses 791system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77777 # number of overall misses 792system.cpu.dtb_walker_cache.overall_misses::total 77777 # number of overall misses 793system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 965958500 # number of ReadReq miss cycles 794system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 965958500 # number of ReadReq miss cycles 795system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 965958500 # number of demand (read+write) miss cycles 796system.cpu.dtb_walker_cache.demand_miss_latency::total 965958500 # number of demand (read+write) miss cycles 797system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 965958500 # number of overall miss cycles 798system.cpu.dtb_walker_cache.overall_miss_latency::total 965958500 # number of overall miss cycles 799system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 179671 # number of ReadReq accesses(hits+misses) 800system.cpu.dtb_walker_cache.ReadReq_accesses::total 179671 # number of ReadReq accesses(hits+misses) 801system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 179671 # number of demand (read+write) accesses 802system.cpu.dtb_walker_cache.demand_accesses::total 179671 # number of demand (read+write) accesses 803system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 179671 # number of overall (read+write) accesses 804system.cpu.dtb_walker_cache.overall_accesses::total 179671 # number of overall (read+write) accesses 805system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.432886 # miss rate for ReadReq accesses 806system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.432886 # miss rate for ReadReq accesses 807system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.432886 # miss rate for demand accesses 808system.cpu.dtb_walker_cache.demand_miss_rate::total 0.432886 # miss rate for demand accesses 809system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.432886 # miss rate for overall accesses 810system.cpu.dtb_walker_cache.overall_miss_rate::total 0.432886 # miss rate for overall accesses 811system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12419.590624 # average ReadReq miss latency 812system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12419.590624 # average ReadReq miss latency 813system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12419.590624 # average overall miss latency 814system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12419.590624 # average overall miss latency 815system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12419.590624 # average overall miss latency 816system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12419.590624 # average overall miss latency 817system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 818system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 819system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 820system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 821system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 822system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 823system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 824system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 825system.cpu.dtb_walker_cache.writebacks::writebacks 21553 # number of writebacks 826system.cpu.dtb_walker_cache.writebacks::total 21553 # number of writebacks 827system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77777 # number of ReadReq MSHR misses 828system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77777 # number of ReadReq MSHR misses 829system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77777 # number of demand (read+write) MSHR misses 830system.cpu.dtb_walker_cache.demand_mshr_misses::total 77777 # number of demand (read+write) MSHR misses 831system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77777 # number of overall MSHR misses 832system.cpu.dtb_walker_cache.overall_mshr_misses::total 77777 # number of overall MSHR misses 833system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 888181500 # number of ReadReq MSHR miss cycles 834system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 888181500 # number of ReadReq MSHR miss cycles 835system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 888181500 # number of demand (read+write) MSHR miss cycles 836system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 888181500 # number of demand (read+write) MSHR miss cycles 837system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 888181500 # number of overall MSHR miss cycles 838system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 888181500 # number of overall MSHR miss cycles 839system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for ReadReq accesses 840system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.432886 # mshr miss rate for ReadReq accesses 841system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for demand accesses 842system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.432886 # mshr miss rate for demand accesses 843system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for overall accesses 844system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.432886 # mshr miss rate for overall accesses 845system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average ReadReq mshr miss latency 846system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11419.590624 # average ReadReq mshr miss latency 847system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average overall mshr miss latency 848system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11419.590624 # average overall mshr miss latency 849system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average overall mshr miss latency 850system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11419.590624 # average overall mshr miss latency 851system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 852system.cpu.icache.tags.replacements 981325 # number of replacements 853system.cpu.icache.tags.tagsinuse 508.752321 # Cycle average of tags in use 854system.cpu.icache.tags.total_refs 7876209 # Total number of references to valid blocks. 855system.cpu.icache.tags.sampled_refs 981837 # Sample count of references to valid blocks. 856system.cpu.icache.tags.avg_refs 8.021911 # Average number of references to valid blocks. 857system.cpu.icache.tags.warmup_cycle 150355632500 # Cycle when the warmup percentage was hit. 858system.cpu.icache.tags.occ_blocks::cpu.inst 508.752321 # Average occupied blocks per requestor 859system.cpu.icache.tags.occ_percent::cpu.inst 0.993657 # Average percentage of cache occupancy 860system.cpu.icache.tags.occ_percent::total 0.993657 # Average percentage of cache occupancy 861system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 862system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id 863system.cpu.icache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id 864system.cpu.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id 865system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 866system.cpu.icache.tags.tag_accesses 9906588 # Number of tag accesses 867system.cpu.icache.tags.data_accesses 9906588 # Number of data accesses 868system.cpu.icache.ReadReq_hits::cpu.inst 7876209 # number of ReadReq hits 869system.cpu.icache.ReadReq_hits::total 7876209 # number of ReadReq hits 870system.cpu.icache.demand_hits::cpu.inst 7876209 # number of demand (read+write) hits 871system.cpu.icache.demand_hits::total 7876209 # number of demand (read+write) hits 872system.cpu.icache.overall_hits::cpu.inst 7876209 # number of overall hits 873system.cpu.icache.overall_hits::total 7876209 # number of overall hits 874system.cpu.icache.ReadReq_misses::cpu.inst 1048476 # number of ReadReq misses 875system.cpu.icache.ReadReq_misses::total 1048476 # number of ReadReq misses 876system.cpu.icache.demand_misses::cpu.inst 1048476 # number of demand (read+write) misses 877system.cpu.icache.demand_misses::total 1048476 # number of demand (read+write) misses 878system.cpu.icache.overall_misses::cpu.inst 1048476 # number of overall misses 879system.cpu.icache.overall_misses::total 1048476 # number of overall misses 880system.cpu.icache.ReadReq_miss_latency::cpu.inst 15750091989 # number of ReadReq miss cycles 881system.cpu.icache.ReadReq_miss_latency::total 15750091989 # number of ReadReq miss cycles 882system.cpu.icache.demand_miss_latency::cpu.inst 15750091989 # number of demand (read+write) miss cycles 883system.cpu.icache.demand_miss_latency::total 15750091989 # number of demand (read+write) miss cycles 884system.cpu.icache.overall_miss_latency::cpu.inst 15750091989 # number of overall miss cycles 885system.cpu.icache.overall_miss_latency::total 15750091989 # number of overall miss cycles 886system.cpu.icache.ReadReq_accesses::cpu.inst 8924685 # number of ReadReq accesses(hits+misses) 887system.cpu.icache.ReadReq_accesses::total 8924685 # number of ReadReq accesses(hits+misses) 888system.cpu.icache.demand_accesses::cpu.inst 8924685 # number of demand (read+write) accesses 889system.cpu.icache.demand_accesses::total 8924685 # number of demand (read+write) accesses 890system.cpu.icache.overall_accesses::cpu.inst 8924685 # number of overall (read+write) accesses 891system.cpu.icache.overall_accesses::total 8924685 # number of overall (read+write) accesses 892system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117480 # miss rate for ReadReq accesses 893system.cpu.icache.ReadReq_miss_rate::total 0.117480 # miss rate for ReadReq accesses 894system.cpu.icache.demand_miss_rate::cpu.inst 0.117480 # miss rate for demand accesses 895system.cpu.icache.demand_miss_rate::total 0.117480 # miss rate for demand accesses 896system.cpu.icache.overall_miss_rate::cpu.inst 0.117480 # miss rate for overall accesses 897system.cpu.icache.overall_miss_rate::total 0.117480 # miss rate for overall accesses 898system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15021.890810 # average ReadReq miss latency 899system.cpu.icache.ReadReq_avg_miss_latency::total 15021.890810 # average ReadReq miss latency 900system.cpu.icache.demand_avg_miss_latency::cpu.inst 15021.890810 # average overall miss latency 901system.cpu.icache.demand_avg_miss_latency::total 15021.890810 # average overall miss latency 902system.cpu.icache.overall_avg_miss_latency::cpu.inst 15021.890810 # average overall miss latency 903system.cpu.icache.overall_avg_miss_latency::total 15021.890810 # average overall miss latency 904system.cpu.icache.blocked_cycles::no_mshrs 14497 # number of cycles access was blocked 905system.cpu.icache.blocked_cycles::no_targets 291 # number of cycles access was blocked 906system.cpu.icache.blocked::no_mshrs 495 # number of cycles access was blocked 907system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked 908system.cpu.icache.avg_blocked_cycles::no_mshrs 29.286869 # average number of cycles each access was blocked 909system.cpu.icache.avg_blocked_cycles::no_targets 72.750000 # average number of cycles each access was blocked 910system.cpu.icache.fast_writes 0 # number of fast writes performed 911system.cpu.icache.cache_copies 0 # number of cache copies performed 912system.cpu.icache.writebacks::writebacks 981325 # number of writebacks 913system.cpu.icache.writebacks::total 981325 # number of writebacks 914system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66573 # number of ReadReq MSHR hits 915system.cpu.icache.ReadReq_mshr_hits::total 66573 # number of ReadReq MSHR hits 916system.cpu.icache.demand_mshr_hits::cpu.inst 66573 # number of demand (read+write) MSHR hits 917system.cpu.icache.demand_mshr_hits::total 66573 # number of demand (read+write) MSHR hits 918system.cpu.icache.overall_mshr_hits::cpu.inst 66573 # number of overall MSHR hits 919system.cpu.icache.overall_mshr_hits::total 66573 # number of overall MSHR hits 920system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981903 # number of ReadReq MSHR misses 921system.cpu.icache.ReadReq_mshr_misses::total 981903 # number of ReadReq MSHR misses 922system.cpu.icache.demand_mshr_misses::cpu.inst 981903 # number of demand (read+write) MSHR misses 923system.cpu.icache.demand_mshr_misses::total 981903 # number of demand (read+write) MSHR misses 924system.cpu.icache.overall_mshr_misses::cpu.inst 981903 # number of overall MSHR misses 925system.cpu.icache.overall_mshr_misses::total 981903 # number of overall MSHR misses 926system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13872010992 # number of ReadReq MSHR miss cycles 927system.cpu.icache.ReadReq_mshr_miss_latency::total 13872010992 # number of ReadReq MSHR miss cycles 928system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13872010992 # number of demand (read+write) MSHR miss cycles 929system.cpu.icache.demand_mshr_miss_latency::total 13872010992 # number of demand (read+write) MSHR miss cycles 930system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13872010992 # number of overall MSHR miss cycles 931system.cpu.icache.overall_mshr_miss_latency::total 13872010992 # number of overall MSHR miss cycles 932system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for ReadReq accesses 933system.cpu.icache.ReadReq_mshr_miss_rate::total 0.110021 # mshr miss rate for ReadReq accesses 934system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for demand accesses 935system.cpu.icache.demand_mshr_miss_rate::total 0.110021 # mshr miss rate for demand accesses 936system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for overall accesses 937system.cpu.icache.overall_mshr_miss_rate::total 0.110021 # mshr miss rate for overall accesses 938system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14127.679610 # average ReadReq mshr miss latency 939system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14127.679610 # average ReadReq mshr miss latency 940system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14127.679610 # average overall mshr miss latency 941system.cpu.icache.demand_avg_mshr_miss_latency::total 14127.679610 # average overall mshr miss latency 942system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14127.679610 # average overall mshr miss latency 943system.cpu.icache.overall_avg_mshr_miss_latency::total 14127.679610 # average overall mshr miss latency 944system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 945system.cpu.itb_walker_cache.tags.replacements 13612 # number of replacements 946system.cpu.itb_walker_cache.tags.tagsinuse 6.021123 # Cycle average of tags in use 947system.cpu.itb_walker_cache.tags.total_refs 25352 # Total number of references to valid blocks. 948system.cpu.itb_walker_cache.tags.sampled_refs 13625 # Sample count of references to valid blocks. 949system.cpu.itb_walker_cache.tags.avg_refs 1.860697 # Average number of references to valid blocks. 950system.cpu.itb_walker_cache.tags.warmup_cycle 5116302133500 # Cycle when the warmup percentage was hit. 951system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.021123 # Average occupied blocks per requestor 952system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376320 # Average percentage of cache occupancy 953system.cpu.itb_walker_cache.tags.occ_percent::total 0.376320 # Average percentage of cache occupancy 954system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id 955system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id 956system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 957system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 958system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 959system.cpu.itb_walker_cache.tags.tag_accesses 94236 # Number of tag accesses 960system.cpu.itb_walker_cache.tags.data_accesses 94236 # Number of data accesses 961system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25363 # number of ReadReq hits 962system.cpu.itb_walker_cache.ReadReq_hits::total 25363 # number of ReadReq hits 963system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 964system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 965system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25365 # number of demand (read+write) hits 966system.cpu.itb_walker_cache.demand_hits::total 25365 # number of demand (read+write) hits 967system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25365 # number of overall hits 968system.cpu.itb_walker_cache.overall_hits::total 25365 # number of overall hits 969system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14502 # number of ReadReq misses 970system.cpu.itb_walker_cache.ReadReq_misses::total 14502 # number of ReadReq misses 971system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14502 # number of demand (read+write) misses 972system.cpu.itb_walker_cache.demand_misses::total 14502 # number of demand (read+write) misses 973system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14502 # number of overall misses 974system.cpu.itb_walker_cache.overall_misses::total 14502 # number of overall misses 975system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176957500 # number of ReadReq miss cycles 976system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176957500 # number of ReadReq miss cycles 977system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176957500 # number of demand (read+write) miss cycles 978system.cpu.itb_walker_cache.demand_miss_latency::total 176957500 # number of demand (read+write) miss cycles 979system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176957500 # number of overall miss cycles 980system.cpu.itb_walker_cache.overall_miss_latency::total 176957500 # number of overall miss cycles 981system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 39865 # number of ReadReq accesses(hits+misses) 982system.cpu.itb_walker_cache.ReadReq_accesses::total 39865 # number of ReadReq accesses(hits+misses) 983system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 984system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 985system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 39867 # number of demand (read+write) accesses 986system.cpu.itb_walker_cache.demand_accesses::total 39867 # number of demand (read+write) accesses 987system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39867 # number of overall (read+write) accesses 988system.cpu.itb_walker_cache.overall_accesses::total 39867 # number of overall (read+write) accesses 989system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363778 # miss rate for ReadReq accesses 990system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363778 # miss rate for ReadReq accesses 991system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363760 # miss rate for demand accesses 992system.cpu.itb_walker_cache.demand_miss_rate::total 0.363760 # miss rate for demand accesses 993system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363760 # miss rate for overall accesses 994system.cpu.itb_walker_cache.overall_miss_rate::total 0.363760 # miss rate for overall accesses 995system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12202.282444 # average ReadReq miss latency 996system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12202.282444 # average ReadReq miss latency 997system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12202.282444 # average overall miss latency 998system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12202.282444 # average overall miss latency 999system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12202.282444 # average overall miss latency 1000system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12202.282444 # average overall miss latency 1001system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1002system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1003system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 1004system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 1005system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1006system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1007system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1008system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 1009system.cpu.itb_walker_cache.writebacks::writebacks 2767 # number of writebacks 1010system.cpu.itb_walker_cache.writebacks::total 2767 # number of writebacks 1011system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14502 # number of ReadReq MSHR misses 1012system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14502 # number of ReadReq MSHR misses 1013system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14502 # number of demand (read+write) MSHR misses 1014system.cpu.itb_walker_cache.demand_mshr_misses::total 14502 # number of demand (read+write) MSHR misses 1015system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14502 # number of overall MSHR misses 1016system.cpu.itb_walker_cache.overall_mshr_misses::total 14502 # number of overall MSHR misses 1017system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 162455500 # number of ReadReq MSHR miss cycles 1018system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 162455500 # number of ReadReq MSHR miss cycles 1019system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 162455500 # number of demand (read+write) MSHR miss cycles 1020system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 162455500 # number of demand (read+write) MSHR miss cycles 1021system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 162455500 # number of overall MSHR miss cycles 1022system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 162455500 # number of overall MSHR miss cycles 1023system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363778 # mshr miss rate for ReadReq accesses 1024system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363778 # mshr miss rate for ReadReq accesses 1025system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363760 # mshr miss rate for demand accesses 1026system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363760 # mshr miss rate for demand accesses 1027system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363760 # mshr miss rate for overall accesses 1028system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363760 # mshr miss rate for overall accesses 1029system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average ReadReq mshr miss latency 1030system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11202.282444 # average ReadReq mshr miss latency 1031system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average overall mshr miss latency 1032system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11202.282444 # average overall mshr miss latency 1033system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average overall mshr miss latency 1034system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11202.282444 # average overall mshr miss latency 1035system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 1036system.cpu.l2cache.tags.replacements 112087 # number of replacements 1037system.cpu.l2cache.tags.tagsinuse 64799.238973 # Cycle average of tags in use 1038system.cpu.l2cache.tags.total_refs 4898447 # Total number of references to valid blocks. 1039system.cpu.l2cache.tags.sampled_refs 176177 # Sample count of references to valid blocks. 1040system.cpu.l2cache.tags.avg_refs 27.804123 # Average number of references to valid blocks. 1041system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1042system.cpu.l2cache.tags.occ_blocks::writebacks 50590.672109 # Average occupied blocks per requestor 1043system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.620858 # Average occupied blocks per requestor 1044system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139554 # Average occupied blocks per requestor 1045system.cpu.l2cache.tags.occ_blocks::cpu.inst 3112.121923 # Average occupied blocks per requestor 1046system.cpu.l2cache.tags.occ_blocks::cpu.data 11083.684529 # Average occupied blocks per requestor 1047system.cpu.l2cache.tags.occ_percent::writebacks 0.771952 # Average percentage of cache occupancy 1048system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000193 # Average percentage of cache occupancy 1049system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 1050system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047487 # Average percentage of cache occupancy 1051system.cpu.l2cache.tags.occ_percent::cpu.data 0.169124 # Average percentage of cache occupancy 1052system.cpu.l2cache.tags.occ_percent::total 0.988758 # Average percentage of cache occupancy 1053system.cpu.l2cache.tags.occ_task_id_blocks::1024 64090 # Occupied blocks per task id 1054system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 1055system.cpu.l2cache.tags.age_task_id_blocks_1024::1 706 # Occupied blocks per task id 1056system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3231 # Occupied blocks per task id 1057system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6108 # Occupied blocks per task id 1058system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53982 # Occupied blocks per task id 1059system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977936 # Percentage of cache occupancy per task id 1060system.cpu.l2cache.tags.tag_accesses 43579518 # Number of tag accesses 1061system.cpu.l2cache.tags.data_accesses 43579518 # Number of data accesses 1062system.cpu.l2cache.WritebackDirty_hits::writebacks 1582394 # number of WritebackDirty hits 1063system.cpu.l2cache.WritebackDirty_hits::total 1582394 # number of WritebackDirty hits 1064system.cpu.l2cache.WritebackClean_hits::writebacks 980190 # number of WritebackClean hits 1065system.cpu.l2cache.WritebackClean_hits::total 980190 # number of WritebackClean hits 1066system.cpu.l2cache.UpgradeReq_hits::cpu.data 342 # number of UpgradeReq hits 1067system.cpu.l2cache.UpgradeReq_hits::total 342 # number of UpgradeReq hits 1068system.cpu.l2cache.ReadExReq_hits::cpu.data 155444 # number of ReadExReq hits 1069system.cpu.l2cache.ReadExReq_hits::total 155444 # number of ReadExReq hits 1070system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 965615 # number of ReadCleanReq hits 1071system.cpu.l2cache.ReadCleanReq_hits::total 965615 # number of ReadCleanReq hits 1072system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 66816 # number of ReadSharedReq hits 1073system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12095 # number of ReadSharedReq hits 1074system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332257 # number of ReadSharedReq hits 1075system.cpu.l2cache.ReadSharedReq_hits::total 1411168 # number of ReadSharedReq hits 1076system.cpu.l2cache.demand_hits::cpu.dtb.walker 66816 # number of demand (read+write) hits 1077system.cpu.l2cache.demand_hits::cpu.itb.walker 12095 # number of demand (read+write) hits 1078system.cpu.l2cache.demand_hits::cpu.inst 965615 # number of demand (read+write) hits 1079system.cpu.l2cache.demand_hits::cpu.data 1487701 # number of demand (read+write) hits 1080system.cpu.l2cache.demand_hits::total 2532227 # number of demand (read+write) hits 1081system.cpu.l2cache.overall_hits::cpu.dtb.walker 66816 # number of overall hits 1082system.cpu.l2cache.overall_hits::cpu.itb.walker 12095 # number of overall hits 1083system.cpu.l2cache.overall_hits::cpu.inst 965615 # number of overall hits 1084system.cpu.l2cache.overall_hits::cpu.data 1487701 # number of overall hits 1085system.cpu.l2cache.overall_hits::total 2532227 # number of overall hits 1086system.cpu.l2cache.UpgradeReq_misses::cpu.data 1438 # number of UpgradeReq misses 1087system.cpu.l2cache.UpgradeReq_misses::total 1438 # number of UpgradeReq misses 1088system.cpu.l2cache.ReadExReq_misses::cpu.data 132521 # number of ReadExReq misses 1089system.cpu.l2cache.ReadExReq_misses::total 132521 # number of ReadExReq misses 1090system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16160 # number of ReadCleanReq misses 1091system.cpu.l2cache.ReadCleanReq_misses::total 16160 # number of ReadCleanReq misses 1092system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 60 # number of ReadSharedReq misses 1093system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses 1094system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35761 # number of ReadSharedReq misses 1095system.cpu.l2cache.ReadSharedReq_misses::total 35826 # number of ReadSharedReq misses 1096system.cpu.l2cache.demand_misses::cpu.dtb.walker 60 # number of demand (read+write) misses 1097system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 1098system.cpu.l2cache.demand_misses::cpu.inst 16160 # number of demand (read+write) misses 1099system.cpu.l2cache.demand_misses::cpu.data 168282 # number of demand (read+write) misses 1100system.cpu.l2cache.demand_misses::total 184507 # number of demand (read+write) misses 1101system.cpu.l2cache.overall_misses::cpu.dtb.walker 60 # number of overall misses 1102system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 1103system.cpu.l2cache.overall_misses::cpu.inst 16160 # number of overall misses 1104system.cpu.l2cache.overall_misses::cpu.data 168282 # number of overall misses 1105system.cpu.l2cache.overall_misses::total 184507 # number of overall misses 1106system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 57872000 # number of UpgradeReq miss cycles 1107system.cpu.l2cache.UpgradeReq_miss_latency::total 57872000 # number of UpgradeReq miss cycles 1108system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16936777500 # number of ReadExReq miss cycles 1109system.cpu.l2cache.ReadExReq_miss_latency::total 16936777500 # number of ReadExReq miss cycles 1110system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2166148500 # number of ReadCleanReq miss cycles 1111system.cpu.l2cache.ReadCleanReq_miss_latency::total 2166148500 # number of ReadCleanReq miss cycles 1112system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 8579000 # number of ReadSharedReq miss cycles 1113system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 679000 # number of ReadSharedReq miss cycles 1114system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4824922500 # number of ReadSharedReq miss cycles 1115system.cpu.l2cache.ReadSharedReq_miss_latency::total 4834180500 # number of ReadSharedReq miss cycles 1116system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 8579000 # number of demand (read+write) miss cycles 1117system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 679000 # number of demand (read+write) miss cycles 1118system.cpu.l2cache.demand_miss_latency::cpu.inst 2166148500 # number of demand (read+write) miss cycles 1119system.cpu.l2cache.demand_miss_latency::cpu.data 21761700000 # number of demand (read+write) miss cycles 1120system.cpu.l2cache.demand_miss_latency::total 23937106500 # number of demand (read+write) miss cycles 1121system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 8579000 # number of overall miss cycles 1122system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 679000 # number of overall miss cycles 1123system.cpu.l2cache.overall_miss_latency::cpu.inst 2166148500 # number of overall miss cycles 1124system.cpu.l2cache.overall_miss_latency::cpu.data 21761700000 # number of overall miss cycles 1125system.cpu.l2cache.overall_miss_latency::total 23937106500 # number of overall miss cycles 1126system.cpu.l2cache.WritebackDirty_accesses::writebacks 1582394 # number of WritebackDirty accesses(hits+misses) 1127system.cpu.l2cache.WritebackDirty_accesses::total 1582394 # number of WritebackDirty accesses(hits+misses) 1128system.cpu.l2cache.WritebackClean_accesses::writebacks 980190 # number of WritebackClean accesses(hits+misses) 1129system.cpu.l2cache.WritebackClean_accesses::total 980190 # number of WritebackClean accesses(hits+misses) 1130system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1780 # number of UpgradeReq accesses(hits+misses) 1131system.cpu.l2cache.UpgradeReq_accesses::total 1780 # number of UpgradeReq accesses(hits+misses) 1132system.cpu.l2cache.ReadExReq_accesses::cpu.data 287965 # number of ReadExReq accesses(hits+misses) 1133system.cpu.l2cache.ReadExReq_accesses::total 287965 # number of ReadExReq accesses(hits+misses) 1134system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 981775 # number of ReadCleanReq accesses(hits+misses) 1135system.cpu.l2cache.ReadCleanReq_accesses::total 981775 # number of ReadCleanReq accesses(hits+misses) 1136system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 66876 # number of ReadSharedReq accesses(hits+misses) 1137system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 12100 # number of ReadSharedReq accesses(hits+misses) 1138system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368018 # number of ReadSharedReq accesses(hits+misses) 1139system.cpu.l2cache.ReadSharedReq_accesses::total 1446994 # number of ReadSharedReq accesses(hits+misses) 1140system.cpu.l2cache.demand_accesses::cpu.dtb.walker 66876 # number of demand (read+write) accesses 1141system.cpu.l2cache.demand_accesses::cpu.itb.walker 12100 # number of demand (read+write) accesses 1142system.cpu.l2cache.demand_accesses::cpu.inst 981775 # number of demand (read+write) accesses 1143system.cpu.l2cache.demand_accesses::cpu.data 1655983 # number of demand (read+write) accesses 1144system.cpu.l2cache.demand_accesses::total 2716734 # number of demand (read+write) accesses 1145system.cpu.l2cache.overall_accesses::cpu.dtb.walker 66876 # number of overall (read+write) accesses 1146system.cpu.l2cache.overall_accesses::cpu.itb.walker 12100 # number of overall (read+write) accesses 1147system.cpu.l2cache.overall_accesses::cpu.inst 981775 # number of overall (read+write) accesses 1148system.cpu.l2cache.overall_accesses::cpu.data 1655983 # number of overall (read+write) accesses 1149system.cpu.l2cache.overall_accesses::total 2716734 # number of overall (read+write) accesses 1150system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807865 # miss rate for UpgradeReq accesses 1151system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807865 # miss rate for UpgradeReq accesses 1152system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460198 # miss rate for ReadExReq accesses 1153system.cpu.l2cache.ReadExReq_miss_rate::total 0.460198 # miss rate for ReadExReq accesses 1154system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016460 # miss rate for ReadCleanReq accesses 1155system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016460 # miss rate for ReadCleanReq accesses 1156system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000897 # miss rate for ReadSharedReq accesses 1157system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000413 # miss rate for ReadSharedReq accesses 1158system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026141 # miss rate for ReadSharedReq accesses 1159system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024759 # miss rate for ReadSharedReq accesses 1160system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000897 # miss rate for demand accesses 1161system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000413 # miss rate for demand accesses 1162system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016460 # miss rate for demand accesses 1163system.cpu.l2cache.demand_miss_rate::cpu.data 0.101621 # miss rate for demand accesses 1164system.cpu.l2cache.demand_miss_rate::total 0.067915 # miss rate for demand accesses 1165system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000897 # miss rate for overall accesses 1166system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000413 # miss rate for overall accesses 1167system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016460 # miss rate for overall accesses 1168system.cpu.l2cache.overall_miss_rate::cpu.data 0.101621 # miss rate for overall accesses 1169system.cpu.l2cache.overall_miss_rate::total 0.067915 # miss rate for overall accesses 1170system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40244.784423 # average UpgradeReq miss latency 1171system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40244.784423 # average UpgradeReq miss latency 1172system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127804.480045 # average ReadExReq miss latency 1173system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127804.480045 # average ReadExReq miss latency 1174system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134043.842822 # average ReadCleanReq miss latency 1175system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134043.842822 # average ReadCleanReq miss latency 1176system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 142983.333333 # average ReadSharedReq miss latency 1177system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 135800 # average ReadSharedReq miss latency 1178system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134921.352870 # average ReadSharedReq miss latency 1179system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134934.977391 # average ReadSharedReq miss latency 1180system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 142983.333333 # average overall miss latency 1181system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 135800 # average overall miss latency 1182system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134043.842822 # average overall miss latency 1183system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129316.860983 # average overall miss latency 1184system.cpu.l2cache.demand_avg_miss_latency::total 129735.492420 # average overall miss latency 1185system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 142983.333333 # average overall miss latency 1186system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 135800 # average overall miss latency 1187system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134043.842822 # average overall miss latency 1188system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129316.860983 # average overall miss latency 1189system.cpu.l2cache.overall_avg_miss_latency::total 129735.492420 # average overall miss latency 1190system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1191system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1192system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1193system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1194system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1195system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1196system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1197system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1198system.cpu.l2cache.writebacks::writebacks 102517 # number of writebacks 1199system.cpu.l2cache.writebacks::total 102517 # number of writebacks 1200system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1201system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1202system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1 # number of ReadSharedReq MSHR hits 1203system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits 1204system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1205system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1206system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 1207system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1208system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1209system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits 1210system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses 1211system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses 1212system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1438 # number of UpgradeReq MSHR misses 1213system.cpu.l2cache.UpgradeReq_mshr_misses::total 1438 # number of UpgradeReq MSHR misses 1214system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132521 # number of ReadExReq MSHR misses 1215system.cpu.l2cache.ReadExReq_mshr_misses::total 132521 # number of ReadExReq MSHR misses 1216system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16157 # number of ReadCleanReq MSHR misses 1217system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16157 # number of ReadCleanReq MSHR misses 1218system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 60 # number of ReadSharedReq MSHR misses 1219system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses 1220system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35760 # number of ReadSharedReq MSHR misses 1221system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35825 # number of ReadSharedReq MSHR misses 1222system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 60 # number of demand (read+write) MSHR misses 1223system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 1224system.cpu.l2cache.demand_mshr_misses::cpu.inst 16157 # number of demand (read+write) MSHR misses 1225system.cpu.l2cache.demand_mshr_misses::cpu.data 168281 # number of demand (read+write) MSHR misses 1226system.cpu.l2cache.demand_mshr_misses::total 184503 # number of demand (read+write) MSHR misses 1227system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 60 # number of overall MSHR misses 1228system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 1229system.cpu.l2cache.overall_mshr_misses::cpu.inst 16157 # number of overall MSHR misses 1230system.cpu.l2cache.overall_mshr_misses::cpu.data 168281 # number of overall MSHR misses 1231system.cpu.l2cache.overall_mshr_misses::total 184503 # number of overall MSHR misses 1232system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable 1233system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable 1234system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13899 # number of WriteReq MSHR uncacheable 1235system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13899 # number of WriteReq MSHR uncacheable 1236system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587359 # number of overall MSHR uncacheable misses 1237system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587359 # number of overall MSHR uncacheable misses 1238system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102774999 # number of UpgradeReq MSHR miss cycles 1239system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102774999 # number of UpgradeReq MSHR miss cycles 1240system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15611567500 # number of ReadExReq MSHR miss cycles 1241system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15611567500 # number of ReadExReq MSHR miss cycles 1242system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2004346500 # number of ReadCleanReq MSHR miss cycles 1243system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2004346500 # number of ReadCleanReq MSHR miss cycles 1244system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 7979000 # number of ReadSharedReq MSHR miss cycles 1245system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 629000 # number of ReadSharedReq MSHR miss cycles 1246system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4468306500 # number of ReadSharedReq MSHR miss cycles 1247system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4476914500 # number of ReadSharedReq MSHR miss cycles 1248system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 7979000 # number of demand (read+write) MSHR miss cycles 1249system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 629000 # number of demand (read+write) MSHR miss cycles 1250system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2004346500 # number of demand (read+write) MSHR miss cycles 1251system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20079874000 # number of demand (read+write) MSHR miss cycles 1252system.cpu.l2cache.demand_mshr_miss_latency::total 22092828500 # number of demand (read+write) MSHR miss cycles 1253system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 7979000 # number of overall MSHR miss cycles 1254system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 629000 # number of overall MSHR miss cycles 1255system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2004346500 # number of overall MSHR miss cycles 1256system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20079874000 # number of overall MSHR miss cycles 1257system.cpu.l2cache.overall_mshr_miss_latency::total 22092828500 # number of overall MSHR miss cycles 1258system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90946019500 # number of ReadReq MSHR uncacheable cycles 1259system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90946019500 # number of ReadReq MSHR uncacheable cycles 1260system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2618766000 # number of WriteReq MSHR uncacheable cycles 1261system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2618766000 # number of WriteReq MSHR uncacheable cycles 1262system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93564785500 # number of overall MSHR uncacheable cycles 1263system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93564785500 # number of overall MSHR uncacheable cycles 1264system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1265system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1266system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807865 # mshr miss rate for UpgradeReq accesses 1267system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807865 # mshr miss rate for UpgradeReq accesses 1268system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460198 # mshr miss rate for ReadExReq accesses 1269system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460198 # mshr miss rate for ReadExReq accesses 1270system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for ReadCleanReq accesses 1271system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016457 # mshr miss rate for ReadCleanReq accesses 1272system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for ReadSharedReq accesses 1273system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for ReadSharedReq accesses 1274system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026140 # mshr miss rate for ReadSharedReq accesses 1275system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024758 # mshr miss rate for ReadSharedReq accesses 1276system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for demand accesses 1277system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for demand accesses 1278system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for demand accesses 1279system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101620 # mshr miss rate for demand accesses 1280system.cpu.l2cache.demand_mshr_miss_rate::total 0.067914 # mshr miss rate for demand accesses 1281system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for overall accesses 1282system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for overall accesses 1283system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for overall accesses 1284system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101620 # mshr miss rate for overall accesses 1285system.cpu.l2cache.overall_mshr_miss_rate::total 0.067914 # mshr miss rate for overall accesses 1286system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71470.792072 # average UpgradeReq mshr miss latency 1287system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71470.792072 # average UpgradeReq mshr miss latency 1288system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117804.480045 # average ReadExReq mshr miss latency 1289system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117804.480045 # average ReadExReq mshr miss latency 1290system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124054.372718 # average ReadCleanReq mshr miss latency 1291system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124054.372718 # average ReadCleanReq mshr miss latency 1292system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average ReadSharedReq mshr miss latency 1293system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125800 # average ReadSharedReq mshr miss latency 1294system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124952.642617 # average ReadSharedReq mshr miss latency 1295system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124966.210747 # average ReadSharedReq mshr miss latency 1296system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average overall mshr miss latency 1297system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125800 # average overall mshr miss latency 1298system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124054.372718 # average overall mshr miss latency 1299system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119323.476804 # average overall mshr miss latency 1300system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119742.380883 # average overall mshr miss latency 1301system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average overall mshr miss latency 1302system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125800 # average overall mshr miss latency 1303system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124054.372718 # average overall mshr miss latency 1304system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119323.476804 # average overall mshr miss latency 1305system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119742.380883 # average overall mshr miss latency 1306system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.740488 # average ReadReq mshr uncacheable latency 1307system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.740488 # average ReadReq mshr uncacheable latency 1308system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188413.986618 # average WriteReq mshr uncacheable latency 1309system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188413.986618 # average WriteReq mshr uncacheable latency 1310system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159297.440747 # average overall mshr uncacheable latency 1311system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159297.440747 # average overall mshr uncacheable latency 1312system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1313system.cpu.toL2Bus.snoop_filter.tot_requests 5460741 # Total number of requests made to the snoop filter. 1314system.cpu.toL2Bus.snoop_filter.hit_single_requests 2718937 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1315system.cpu.toL2Bus.snoop_filter.hit_multi_requests 72407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1316system.cpu.toL2Bus.snoop_filter.tot_snoops 1221 # Total number of snoops made to the snoop filter. 1317system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1221 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1318system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1319system.cpu.toL2Bus.trans_dist::ReadReq 573460 # Transaction distribution 1320system.cpu.toL2Bus.trans_dist::ReadResp 3016607 # Transaction distribution 1321system.cpu.toL2Bus.trans_dist::WriteReq 13899 # Transaction distribution 1322system.cpu.toL2Bus.trans_dist::WriteResp 13899 # Transaction distribution 1323system.cpu.toL2Bus.trans_dist::WritebackDirty 1731587 # Transaction distribution 1324system.cpu.toL2Bus.trans_dist::WritebackClean 980190 # Transaction distribution 1325system.cpu.toL2Bus.trans_dist::CleanEvict 117679 # Transaction distribution 1326system.cpu.toL2Bus.trans_dist::UpgradeReq 2259 # Transaction distribution 1327system.cpu.toL2Bus.trans_dist::UpgradeResp 2259 # Transaction distribution 1328system.cpu.toL2Bus.trans_dist::ReadExReq 287973 # Transaction distribution 1329system.cpu.toL2Bus.trans_dist::ReadExResp 287973 # Transaction distribution 1330system.cpu.toL2Bus.trans_dist::ReadCleanReq 981903 # Transaction distribution 1331system.cpu.toL2Bus.trans_dist::ReadSharedReq 1461779 # Transaction distribution 1332system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution 1333system.cpu.toL2Bus.trans_dist::BadAddressError 9 # Transaction distribution 1334system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution 1335system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2943868 # Packet count per connected master and slave (bytes) 1336system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6146532 # Packet count per connected master and slave (bytes) 1337system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31429 # Packet count per connected master and slave (bytes) 1338system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 174582 # Packet count per connected master and slave (bytes) 1339system.cpu.toL2Bus.pkt_count::total 9296411 # Packet count per connected master and slave (bytes) 1340system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 125565760 # Cumulative packet size per connected master and slave (bytes) 1341system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207412623 # Cumulative packet size per connected master and slave (bytes) 1342system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 951488 # Cumulative packet size per connected master and slave (bytes) 1343system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5659456 # Cumulative packet size per connected master and slave (bytes) 1344system.cpu.toL2Bus.pkt_size::total 339589327 # Cumulative packet size per connected master and slave (bytes) 1345system.cpu.toL2Bus.snoops 223808 # Total snoops (count) 1346system.cpu.toL2Bus.snoop_fanout::samples 3529303 # Request fanout histogram 1347system.cpu.toL2Bus.snoop_fanout::mean 0.021448 # Request fanout histogram 1348system.cpu.toL2Bus.snoop_fanout::stdev 0.165576 # Request fanout histogram 1349system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1350system.cpu.toL2Bus.snoop_fanout::0 3464951 98.18% 98.18% # Request fanout histogram 1351system.cpu.toL2Bus.snoop_fanout::1 53009 1.50% 99.68% # Request fanout histogram 1352system.cpu.toL2Bus.snoop_fanout::2 11343 0.32% 100.00% # Request fanout histogram 1353system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram 1354system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1355system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1356system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1357system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1358system.cpu.toL2Bus.snoop_fanout::total 3529303 # Request fanout histogram 1359system.cpu.toL2Bus.reqLayer0.occupancy 5594725985 # Layer occupancy (ticks) 1360system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1361system.cpu.toL2Bus.snoopLayer0.occupancy 671790 # Layer occupancy (ticks) 1362system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1363system.cpu.toL2Bus.respLayer0.occupancy 1474740212 # Layer occupancy (ticks) 1364system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1365system.cpu.toL2Bus.respLayer1.occupancy 3066745270 # Layer occupancy (ticks) 1366system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1367system.cpu.toL2Bus.respLayer2.occupancy 21763478 # Layer occupancy (ticks) 1368system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1369system.cpu.toL2Bus.respLayer3.occupancy 116728873 # Layer occupancy (ticks) 1370system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1371system.iobus.trans_dist::ReadReq 212016 # Transaction distribution 1372system.iobus.trans_dist::ReadResp 212016 # Transaction distribution 1373system.iobus.trans_dist::WriteReq 57726 # Transaction distribution 1374system.iobus.trans_dist::WriteResp 57726 # Transaction distribution 1375system.iobus.trans_dist::MessageReq 1645 # Transaction distribution 1376system.iobus.trans_dist::MessageResp 1645 # Transaction distribution 1377system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1378system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1379system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 1380system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1381system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 1382system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1383system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1384system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes) 1385system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1386system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1387system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1388system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) 1389system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1390system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1391system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1392system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1393system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) 1394system.iobus.pkt_count_system.bridge.master::total 444236 # Packet count per connected master and slave (bytes) 1395system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) 1396system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) 1397system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) 1398system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) 1399system.iobus.pkt_count::total 542774 # Packet count per connected master and slave (bytes) 1400system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1401system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1402system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 1403system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1404system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 1405system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1406system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1407system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes) 1408system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1409system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1410system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1411system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) 1412system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1413system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1414system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1415system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1416system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) 1417system.iobus.pkt_size_system.bridge.master::total 228398 # Cumulative packet size per connected master and slave (bytes) 1418system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) 1419system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) 1420system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) 1421system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) 1422system.iobus.pkt_size::total 3262754 # Cumulative packet size per connected master and slave (bytes) 1423system.iobus.reqLayer0.occupancy 3980596 # Layer occupancy (ticks) 1424system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1425system.iobus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) 1426system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1427system.iobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) 1428system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1429system.iobus.reqLayer3.occupancy 10514500 # Layer occupancy (ticks) 1430system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1431system.iobus.reqLayer4.occupancy 1031500 # Layer occupancy (ticks) 1432system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1433system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks) 1434system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1435system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks) 1436system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1437system.iobus.reqLayer7.occupancy 32500 # Layer occupancy (ticks) 1438system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1439system.iobus.reqLayer8.occupancy 300003000 # Layer occupancy (ticks) 1440system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1441system.iobus.reqLayer9.occupancy 1175500 # Layer occupancy (ticks) 1442system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1443system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks) 1444system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1445system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 1446system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 1447system.iobus.reqLayer13.occupancy 24561500 # Layer occupancy (ticks) 1448system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1449system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 1450system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1451system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) 1452system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1453system.iobus.reqLayer16.occupancy 10000 # Layer occupancy (ticks) 1454system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1455system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) 1456system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1457system.iobus.reqLayer18.occupancy 241121329 # Layer occupancy (ticks) 1458system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1459system.iobus.reqLayer19.occupancy 1231500 # Layer occupancy (ticks) 1460system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1461system.iobus.respLayer0.occupancy 433230000 # Layer occupancy (ticks) 1462system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1463system.iobus.respLayer1.occupancy 50160000 # Layer occupancy (ticks) 1464system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1465system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) 1466system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 1467system.iocache.tags.replacements 47569 # number of replacements 1468system.iocache.tags.tagsinuse 0.116025 # Cycle average of tags in use 1469system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1470system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 1471system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1472system.iocache.tags.warmup_cycle 4999365177000 # Cycle when the warmup percentage was hit. 1473system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116025 # Average occupied blocks per requestor 1474system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007252 # Average percentage of cache occupancy 1475system.iocache.tags.occ_percent::total 0.007252 # Average percentage of cache occupancy 1476system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1477system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1478system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1479system.iocache.tags.tag_accesses 428616 # Number of tag accesses 1480system.iocache.tags.data_accesses 428616 # Number of data accesses 1481system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 1482system.iocache.ReadReq_misses::total 904 # number of ReadReq misses 1483system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 1484system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses 1485system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses 1486system.iocache.demand_misses::total 904 # number of demand (read+write) misses 1487system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses 1488system.iocache.overall_misses::total 904 # number of overall misses 1489system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 145501183 # number of ReadReq miss cycles 1490system.iocache.ReadReq_miss_latency::total 145501183 # number of ReadReq miss cycles 1491system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6077027146 # number of WriteLineReq miss cycles 1492system.iocache.WriteLineReq_miss_latency::total 6077027146 # number of WriteLineReq miss cycles 1493system.iocache.demand_miss_latency::pc.south_bridge.ide 145501183 # number of demand (read+write) miss cycles 1494system.iocache.demand_miss_latency::total 145501183 # number of demand (read+write) miss cycles 1495system.iocache.overall_miss_latency::pc.south_bridge.ide 145501183 # number of overall miss cycles 1496system.iocache.overall_miss_latency::total 145501183 # number of overall miss cycles 1497system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 1498system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) 1499system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 1500system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) 1501system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses 1502system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses 1503system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses 1504system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses 1505system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1506system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1507system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 1508system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1509system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1510system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1511system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1512system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1513system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average ReadReq miss latency 1514system.iocache.ReadReq_avg_miss_latency::total 160952.636062 # average ReadReq miss latency 1515system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 130073.355009 # average WriteLineReq miss latency 1516system.iocache.WriteLineReq_avg_miss_latency::total 130073.355009 # average WriteLineReq miss latency 1517system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average overall miss latency 1518system.iocache.demand_avg_miss_latency::total 160952.636062 # average overall miss latency 1519system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average overall miss latency 1520system.iocache.overall_avg_miss_latency::total 160952.636062 # average overall miss latency 1521system.iocache.blocked_cycles::no_mshrs 1232 # number of cycles access was blocked 1522system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1523system.iocache.blocked::no_mshrs 114 # number of cycles access was blocked 1524system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1525system.iocache.avg_blocked_cycles::no_mshrs 10.807018 # average number of cycles each access was blocked 1526system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1527system.iocache.fast_writes 0 # number of fast writes performed 1528system.iocache.cache_copies 0 # number of cache copies performed 1529system.iocache.writebacks::writebacks 46667 # number of writebacks 1530system.iocache.writebacks::total 46667 # number of writebacks 1531system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 904 # number of ReadReq MSHR misses 1532system.iocache.ReadReq_mshr_misses::total 904 # number of ReadReq MSHR misses 1533system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses 1534system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses 1535system.iocache.demand_mshr_misses::pc.south_bridge.ide 904 # number of demand (read+write) MSHR misses 1536system.iocache.demand_mshr_misses::total 904 # number of demand (read+write) MSHR misses 1537system.iocache.overall_mshr_misses::pc.south_bridge.ide 904 # number of overall MSHR misses 1538system.iocache.overall_mshr_misses::total 904 # number of overall MSHR misses 1539system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of ReadReq MSHR miss cycles 1540system.iocache.ReadReq_mshr_miss_latency::total 100301183 # number of ReadReq MSHR miss cycles 1541system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3741027146 # number of WriteLineReq MSHR miss cycles 1542system.iocache.WriteLineReq_mshr_miss_latency::total 3741027146 # number of WriteLineReq MSHR miss cycles 1543system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of demand (read+write) MSHR miss cycles 1544system.iocache.demand_mshr_miss_latency::total 100301183 # number of demand (read+write) MSHR miss cycles 1545system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of overall MSHR miss cycles 1546system.iocache.overall_mshr_miss_latency::total 100301183 # number of overall MSHR miss cycles 1547system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1548system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1549system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses 1550system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1551system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1552system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1553system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1554system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1555system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average ReadReq mshr miss latency 1556system.iocache.ReadReq_avg_mshr_miss_latency::total 110952.636062 # average ReadReq mshr miss latency 1557system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 80073.355009 # average WriteLineReq mshr miss latency 1558system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80073.355009 # average WriteLineReq mshr miss latency 1559system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average overall mshr miss latency 1560system.iocache.demand_avg_mshr_miss_latency::total 110952.636062 # average overall mshr miss latency 1561system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average overall mshr miss latency 1562system.iocache.overall_avg_mshr_miss_latency::total 110952.636062 # average overall mshr miss latency 1563system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1564system.membus.trans_dist::ReadReq 573460 # Transaction distribution 1565system.membus.trans_dist::ReadResp 626337 # Transaction distribution 1566system.membus.trans_dist::WriteReq 13899 # Transaction distribution 1567system.membus.trans_dist::WriteResp 13899 # Transaction distribution 1568system.membus.trans_dist::WritebackDirty 149184 # Transaction distribution 1569system.membus.trans_dist::CleanEvict 9829 # Transaction distribution 1570system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution 1571system.membus.trans_dist::UpgradeResp 1709 # Transaction distribution 1572system.membus.trans_dist::ReadExReq 132252 # Transaction distribution 1573system.membus.trans_dist::ReadExResp 132250 # Transaction distribution 1574system.membus.trans_dist::ReadSharedReq 52886 # Transaction distribution 1575system.membus.trans_dist::MessageReq 1645 # Transaction distribution 1576system.membus.trans_dist::MessageResp 1645 # Transaction distribution 1577system.membus.trans_dist::BadAddressError 9 # Transaction distribution 1578system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution 1579system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution 1580system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) 1581system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) 1582system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444236 # Packet count per connected master and slave (bytes) 1583system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730482 # Packet count per connected master and slave (bytes) 1584system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 483648 # Packet count per connected master and slave (bytes) 1585system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 18 # Packet count per connected master and slave (bytes) 1586system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1658384 # Packet count per connected master and slave (bytes) 1587system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141810 # Packet count per connected master and slave (bytes) 1588system.membus.pkt_count_system.iocache.mem_side::total 141810 # Packet count per connected master and slave (bytes) 1589system.membus.pkt_count::total 1803484 # Packet count per connected master and slave (bytes) 1590system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) 1591system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) 1592system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228398 # Cumulative packet size per connected master and slave (bytes) 1593system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460961 # Cumulative packet size per connected master and slave (bytes) 1594system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18308608 # Cumulative packet size per connected master and slave (bytes) 1595system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19997967 # Cumulative packet size per connected master and slave (bytes) 1596system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) 1597system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) 1598system.membus.pkt_size::total 23019587 # Cumulative packet size per connected master and slave (bytes) 1599system.membus.snoops 1629 # Total snoops (count) 1600system.membus.snoop_fanout::samples 982619 # Request fanout histogram 1601system.membus.snoop_fanout::mean 1.001674 # Request fanout histogram 1602system.membus.snoop_fanout::stdev 0.040881 # Request fanout histogram 1603system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1604system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1605system.membus.snoop_fanout::1 980974 99.83% 99.83% # Request fanout histogram 1606system.membus.snoop_fanout::2 1645 0.17% 100.00% # Request fanout histogram 1607system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1608system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1609system.membus.snoop_fanout::max_value 2 # Request fanout histogram 1610system.membus.snoop_fanout::total 982619 # Request fanout histogram 1611system.membus.reqLayer0.occupancy 339006500 # Layer occupancy (ticks) 1612system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1613system.membus.reqLayer1.occupancy 369115500 # Layer occupancy (ticks) 1614system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1615system.membus.reqLayer2.occupancy 3980404 # Layer occupancy (ticks) 1616system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1617system.membus.reqLayer3.occupancy 1013900787 # Layer occupancy (ticks) 1618system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1619system.membus.reqLayer4.occupancy 12000 # Layer occupancy (ticks) 1620system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 1621system.membus.respLayer0.occupancy 2335404 # Layer occupancy (ticks) 1622system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 1623system.membus.respLayer2.occupancy 2139201818 # Layer occupancy (ticks) 1624system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1625system.membus.respLayer4.occupancy 85763851 # Layer occupancy (ticks) 1626system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1627system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1628system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1629system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). 1630system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1631system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1632system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1633system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1634system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1635system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1636system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1637system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1638system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1639system.cpu.kern.inst.arm 0 # number of arm instructions executed 1640system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1641 1642---------- End Simulation Statistics ---------- 1643