stats.txt revision 11570:4aac82f10951
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.759348 # Number of seconds simulated 4sim_ticks 51759347706500 # Number of ticks simulated 5final_tick 51759347706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 706961 # Simulator instruction rate (inst/s) 8host_op_rate 830795 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43773319280 # Simulator tick rate (ticks/s) 10host_mem_usage 670816 # Number of bytes of host memory used 11host_seconds 1182.44 # Real time elapsed on the host 12sim_insts 835939132 # Number of instructions simulated 13sim_ops 982366087 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 152192 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 158144 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 4715828 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 36073224 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 410496 # Number of bytes read from this memory 22system.physmem.bytes_read::total 41509884 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 4715828 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 4715828 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 62909632 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 27system.physmem.bytes_written::total 62930212 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 2378 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2471 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 114092 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 563657 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6414 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 689012 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 982963 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 985536 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 2940 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 3055 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 91111 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 696941 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 7931 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 801978 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 91111 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 91111 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 1215426 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 1215823 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 1215426 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 2940 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 3055 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 91111 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 697339 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 7931 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 2017802 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 689012 # Number of read requests accepted 56system.physmem.writeReqs 985536 # Number of write requests accepted 57system.physmem.readBursts 689012 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 985536 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 44056384 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 40384 # Total number of bytes read from write queue 61system.physmem.bytesWritten 62928960 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 41509884 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 62930212 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 631 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 41424 # Per bank write bursts 68system.physmem.perBankRdBursts::1 42196 # Per bank write bursts 69system.physmem.perBankRdBursts::2 39305 # Per bank write bursts 70system.physmem.perBankRdBursts::3 41228 # Per bank write bursts 71system.physmem.perBankRdBursts::4 37796 # Per bank write bursts 72system.physmem.perBankRdBursts::5 46284 # Per bank write bursts 73system.physmem.perBankRdBursts::6 37646 # Per bank write bursts 74system.physmem.perBankRdBursts::7 36984 # Per bank write bursts 75system.physmem.perBankRdBursts::8 37874 # Per bank write bursts 76system.physmem.perBankRdBursts::9 85067 # Per bank write bursts 77system.physmem.perBankRdBursts::10 43899 # Per bank write bursts 78system.physmem.perBankRdBursts::11 46232 # Per bank write bursts 79system.physmem.perBankRdBursts::12 39321 # Per bank write bursts 80system.physmem.perBankRdBursts::13 40035 # Per bank write bursts 81system.physmem.perBankRdBursts::14 35465 # Per bank write bursts 82system.physmem.perBankRdBursts::15 37625 # Per bank write bursts 83system.physmem.perBankWrBursts::0 61899 # Per bank write bursts 84system.physmem.perBankWrBursts::1 62487 # Per bank write bursts 85system.physmem.perBankWrBursts::2 61087 # Per bank write bursts 86system.physmem.perBankWrBursts::3 63695 # Per bank write bursts 87system.physmem.perBankWrBursts::4 58991 # Per bank write bursts 88system.physmem.perBankWrBursts::5 64628 # Per bank write bursts 89system.physmem.perBankWrBursts::6 58592 # Per bank write bursts 90system.physmem.perBankWrBursts::7 59025 # Per bank write bursts 91system.physmem.perBankWrBursts::8 60354 # Per bank write bursts 92system.physmem.perBankWrBursts::9 64900 # Per bank write bursts 93system.physmem.perBankWrBursts::10 63044 # Per bank write bursts 94system.physmem.perBankWrBursts::11 64791 # Per bank write bursts 95system.physmem.perBankWrBursts::12 60176 # Per bank write bursts 96system.physmem.perBankWrBursts::13 61598 # Per bank write bursts 97system.physmem.perBankWrBursts::14 57895 # Per bank write bursts 98system.physmem.perBankWrBursts::15 60103 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 19 # Number of times write queue was full causing retry 101system.physmem.totGap 51759344769500 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 43101 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 2 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 645896 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 982963 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 659454 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 23139 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 405 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 338 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 474 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 555 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 545 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1172 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 668 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 279 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 358 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 162 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 174 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 128 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 114 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 31865 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 37580 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 54935 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 54491 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 57672 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 55206 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 58598 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 55686 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 56443 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 55845 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 56872 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 59532 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 57169 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 57139 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 58902 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 55823 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 54603 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 54399 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 2302 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 800 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 676 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 442 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 459 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 467 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 447 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 304 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 304 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 282 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 243 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 254 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 241 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 233 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 257 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 220 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 155 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 191 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 236 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 204 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 126 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 164 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 128 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 438828 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 243.797169 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 147.013209 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 285.979705 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 194919 44.42% 44.42% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 116778 26.61% 71.03% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 38832 8.85% 79.88% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 20430 4.66% 84.53% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 13130 2.99% 87.53% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 8793 2.00% 89.53% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 7414 1.69% 91.22% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 5819 1.33% 92.55% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 32713 7.45% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 438828 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 52143 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 13.201312 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 141.003763 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-1023 52140 99.99% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::total 52143 # Reads before turning the bus around for writes 234system.physmem.wrPerTurnAround::samples 52143 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::mean 18.857085 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::gmean 18.140227 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::stdev 8.284435 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::16-19 48446 92.91% 92.91% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::20-23 1855 3.56% 96.47% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::24-27 116 0.22% 96.69% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::28-31 101 0.19% 96.88% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::32-35 48 0.09% 96.98% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::36-39 101 0.19% 97.17% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::40-43 252 0.48% 97.65% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::44-47 24 0.05% 97.70% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::48-51 307 0.59% 98.29% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::52-55 75 0.14% 98.43% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::56-59 29 0.06% 98.49% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::60-63 51 0.10% 98.58% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::64-67 313 0.60% 99.18% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::68-71 41 0.08% 99.26% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::72-75 37 0.07% 99.33% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::76-79 129 0.25% 99.58% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::80-83 166 0.32% 99.90% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::96-99 1 0.00% 99.91% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::108-111 3 0.01% 99.92% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::128-131 11 0.02% 99.95% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::144-147 15 0.03% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::total 52143 # Writes before turning the bus around for reads 274system.physmem.totQLat 9222624910 # Total ticks spent queuing 275system.physmem.totMemAccLat 22129768660 # Total ticks spent from burst creation until serviced by the DRAM 276system.physmem.totBusLat 3441905000 # Total ticks spent in databus transfers 277system.physmem.avgQLat 13397.56 # Average queueing delay per DRAM burst 278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 279system.physmem.avgMemAccLat 32147.56 # Average memory access latency per DRAM burst 280system.physmem.avgRdBW 0.85 # Average DRAM read bandwidth in MiByte/s 281system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s 282system.physmem.avgRdBWSys 0.80 # Average system read bandwidth in MiByte/s 283system.physmem.avgWrBWSys 1.22 # Average system write bandwidth in MiByte/s 284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 285system.physmem.busUtil 0.02 # Data bus utilization in percentage 286system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 287system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 288system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 289system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing 290system.physmem.readRowHits 507228 # Number of row buffer hits during reads 291system.physmem.writeRowHits 725589 # Number of row buffer hits during writes 292system.physmem.readRowHitRate 73.68 # Row buffer hit rate for reads 293system.physmem.writeRowHitRate 73.79 # Row buffer hit rate for writes 294system.physmem.avgGap 30909442.29 # Average gap between requests 295system.physmem.pageHitRate 73.75 # Row buffer hit rate, read and write combined 296system.physmem_0.actEnergy 1651557600 # Energy for activate commands per rank (pJ) 297system.physmem_0.preEnergy 901147500 # Energy for precharge commands per rank (pJ) 298system.physmem_0.readEnergy 2518331400 # Energy for read commands per rank (pJ) 299system.physmem_0.writeEnergy 3177817920 # Energy for write commands per rank (pJ) 300system.physmem_0.refreshEnergy 3380668873920 # Energy for refresh commands per rank (pJ) 301system.physmem_0.actBackEnergy 1280908967265 # Energy for active background per rank (pJ) 302system.physmem_0.preBackEnergy 29932003411500 # Energy for precharge background per rank (pJ) 303system.physmem_0.totalEnergy 34601830107105 # Total energy per rank (pJ) 304system.physmem_0.averagePower 668.513662 # Core power per rank (mW) 305system.physmem_0.memoryStateTime::IDLE 49794254360042 # Time in different power states 306system.physmem_0.memoryStateTime::REF 1728358320000 # Time in different power states 307system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 308system.physmem_0.memoryStateTime::ACT 236733614958 # Time in different power states 309system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 310system.physmem_1.actEnergy 1665982080 # Energy for activate commands per rank (pJ) 311system.physmem_1.preEnergy 909018000 # Energy for precharge commands per rank (pJ) 312system.physmem_1.readEnergy 2851001400 # Energy for read commands per rank (pJ) 313system.physmem_1.writeEnergy 3193739280 # Energy for write commands per rank (pJ) 314system.physmem_1.refreshEnergy 3380668873920 # Energy for refresh commands per rank (pJ) 315system.physmem_1.actBackEnergy 1282600048680 # Energy for active background per rank (pJ) 316system.physmem_1.preBackEnergy 29930520006750 # Energy for precharge background per rank (pJ) 317system.physmem_1.totalEnergy 34602408670110 # Total energy per rank (pJ) 318system.physmem_1.averagePower 668.524840 # Core power per rank (mW) 319system.physmem_1.memoryStateTime::IDLE 49791748874504 # Time in different power states 320system.physmem_1.memoryStateTime::REF 1728358320000 # Time in different power states 321system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 322system.physmem_1.memoryStateTime::ACT 239239854996 # Time in different power states 323system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 324system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 325system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 327system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 329system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 330system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 331system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 332system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 333system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 339system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 340system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) 341system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 342system.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 343system.bridge.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 344system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 345system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 346system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 347system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 348system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 349system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 350system.cpu_clk_domain.clock 500 # Clock period in ticks 351system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 352system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 361system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 362system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 363system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 364system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 365system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 366system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 367system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 368system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 369system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 370system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 371system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 372system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 373system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 374system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 375system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 376system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 377system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 378system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 379system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 380system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 381system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 382system.cpu.dtb.walker.walks 186389 # Table walker walks requested 383system.cpu.dtb.walker.walksLong 186389 # Table walker walks initiated with long descriptors 384system.cpu.dtb.walker.walksLongTerminationLevel::Level2 11673 # Level at which table walker walks with long descriptors terminate 385system.cpu.dtb.walker.walksLongTerminationLevel::Level3 145933 # Level at which table walker walks with long descriptors terminate 386system.cpu.dtb.walker.walksSquashedBefore 20 # Table walks squashed before starting 387system.cpu.dtb.walker.walkWaitTime::samples 186369 # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::mean 0.214628 # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkWaitTime::stdev 70.564506 # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkWaitTime::0-2047 186367 100.00% 100.00% # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::total 186369 # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkCompletionTime::samples 157626 # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::mean 24833.263548 # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::gmean 20845.971920 # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::stdev 18169.669952 # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::0-65535 156391 99.22% 99.22% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 99.22% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::131072-196607 1058 0.67% 99.89% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::196608-262143 24 0.02% 99.91% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::262144-327679 78 0.05% 99.96% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::327680-393215 18 0.01% 99.97% # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::393216-458751 45 0.03% 100.00% # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::total 157626 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walksPending::samples -5176298892 # Table walker pending requests distribution 410system.cpu.dtb.walker.walksPending::mean 1.304609 # Table walker pending requests distribution 411system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution 412system.cpu.dtb.walker.walksPending::0 1576748204 -30.46% -30.46% # Table walker pending requests distribution 413system.cpu.dtb.walker.walksPending::1 -6753047096 130.46% 100.00% # Table walker pending requests distribution 414system.cpu.dtb.walker.walksPending::total -5176298892 # Table walker pending requests distribution 415system.cpu.dtb.walker.walkPageSizes::4K 145934 92.59% 92.59% # Table walker page sizes translated 416system.cpu.dtb.walker.walkPageSizes::2M 11673 7.41% 100.00% # Table walker page sizes translated 417system.cpu.dtb.walker.walkPageSizes::total 157607 # Table walker page sizes translated 418system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 186389 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 420system.cpu.dtb.walker.walkRequestOrigin_Requested::total 186389 # Table walker requests started/completed, data/inst 421system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 157607 # Table walker requests started/completed, data/inst 422system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 423system.cpu.dtb.walker.walkRequestOrigin_Completed::total 157607 # Table walker requests started/completed, data/inst 424system.cpu.dtb.walker.walkRequestOrigin::total 343996 # Table walker requests started/completed, data/inst 425system.cpu.dtb.inst_hits 0 # ITB inst hits 426system.cpu.dtb.inst_misses 0 # ITB inst misses 427system.cpu.dtb.read_hits 157302470 # DTB read hits 428system.cpu.dtb.read_misses 138254 # DTB read misses 429system.cpu.dtb.write_hits 142797891 # DTB write hits 430system.cpu.dtb.write_misses 48135 # DTB write misses 431system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 432system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 433system.cpu.dtb.flush_tlb_mva_asid 38509 # Number of times TLB was flushed by MVA & ASID 434system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID 435system.cpu.dtb.flush_entries 71109 # Number of entries that have been flushed from TLB 436system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 437system.cpu.dtb.prefetch_faults 6989 # Number of TLB faults due to prefetch 438system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 439system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions 440system.cpu.dtb.read_accesses 157440724 # DTB read accesses 441system.cpu.dtb.write_accesses 142846026 # DTB write accesses 442system.cpu.dtb.inst_accesses 0 # ITB inst accesses 443system.cpu.dtb.hits 300100361 # DTB hits 444system.cpu.dtb.misses 186389 # DTB misses 445system.cpu.dtb.accesses 300286750 # DTB accesses 446system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 447system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 450system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 451system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 456system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 457system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 458system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 459system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 460system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 461system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 462system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 463system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 464system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 465system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 466system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 467system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 468system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 469system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 470system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 471system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 472system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 473system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 474system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 475system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 476system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 477system.cpu.itb.walker.walks 119383 # Table walker walks requested 478system.cpu.itb.walker.walksLong 119383 # Table walker walks initiated with long descriptors 479system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate 480system.cpu.itb.walker.walksLongTerminationLevel::Level3 107813 # Level at which table walker walks with long descriptors terminate 481system.cpu.itb.walker.walkWaitTime::samples 119383 # Table walker wait (enqueue to first request) latency 482system.cpu.itb.walker.walkWaitTime::0 119383 100.00% 100.00% # Table walker wait (enqueue to first request) latency 483system.cpu.itb.walker.walkWaitTime::total 119383 # Table walker wait (enqueue to first request) latency 484system.cpu.itb.walker.walkCompletionTime::samples 108935 # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::mean 28686.574563 # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::gmean 24766.127594 # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::stdev 21816.949759 # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::0-65535 107446 98.63% 98.63% # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 98.64% # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::131072-196607 1285 1.18% 99.82% # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::196608-262143 37 0.03% 99.85% # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walkCompletionTime::262144-327679 72 0.07% 99.92% # Table walker service (enqueue to completion) latency 493system.cpu.itb.walker.walkCompletionTime::327680-393215 42 0.04% 99.95% # Table walker service (enqueue to completion) latency 494system.cpu.itb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency 495system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency 496system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 497system.cpu.itb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 498system.cpu.itb.walker.walkCompletionTime::total 108935 # Table walker service (enqueue to completion) latency 499system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution 500system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution 501system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution 502system.cpu.itb.walker.walkPageSizes::4K 107813 98.97% 98.97% # Table walker page sizes translated 503system.cpu.itb.walker.walkPageSizes::2M 1122 1.03% 100.00% # Table walker page sizes translated 504system.cpu.itb.walker.walkPageSizes::total 108935 # Table walker page sizes translated 505system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 506system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119383 # Table walker requests started/completed, data/inst 507system.cpu.itb.walker.walkRequestOrigin_Requested::total 119383 # Table walker requests started/completed, data/inst 508system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 509system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108935 # Table walker requests started/completed, data/inst 510system.cpu.itb.walker.walkRequestOrigin_Completed::total 108935 # Table walker requests started/completed, data/inst 511system.cpu.itb.walker.walkRequestOrigin::total 228318 # Table walker requests started/completed, data/inst 512system.cpu.itb.inst_hits 836454912 # ITB inst hits 513system.cpu.itb.inst_misses 119383 # ITB inst misses 514system.cpu.itb.read_hits 0 # DTB read hits 515system.cpu.itb.read_misses 0 # DTB read misses 516system.cpu.itb.write_hits 0 # DTB write hits 517system.cpu.itb.write_misses 0 # DTB write misses 518system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 519system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 520system.cpu.itb.flush_tlb_mva_asid 38509 # Number of times TLB was flushed by MVA & ASID 521system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID 522system.cpu.itb.flush_entries 50925 # Number of entries that have been flushed from TLB 523system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 524system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 525system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 526system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 527system.cpu.itb.read_accesses 0 # DTB read accesses 528system.cpu.itb.write_accesses 0 # DTB write accesses 529system.cpu.itb.inst_accesses 836574295 # ITB inst accesses 530system.cpu.itb.hits 836454912 # DTB hits 531system.cpu.itb.misses 119383 # DTB misses 532system.cpu.itb.accesses 836574295 # DTB accesses 533system.cpu.numPwrStateTransitions 32056 # Number of power state transitions 534system.cpu.pwrStateClkGateDist::samples 16028 # Distribution of time spent in the clock gated state 535system.cpu.pwrStateClkGateDist::mean 3133878336.314075 # Distribution of time spent in the clock gated state 536system.cpu.pwrStateClkGateDist::stdev 60741761061.559830 # Distribution of time spent in the clock gated state 537system.cpu.pwrStateClkGateDist::underflows 6738 42.04% 42.04% # Distribution of time spent in the clock gated state 538system.cpu.pwrStateClkGateDist::1000-5e+10 9255 57.74% 99.78% # Distribution of time spent in the clock gated state 539system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state 540system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 541system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 542system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 543system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 544system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 545system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 546system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 547system.cpu.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 548system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 549system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 550system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state 551system.cpu.pwrStateClkGateDist::total 16028 # Distribution of time spent in the clock gated state 552system.cpu.pwrStateResidencyTicks::ON 1529545732058 # Cumulative time (in ticks) in various power states 553system.cpu.pwrStateResidencyTicks::CLK_GATED 50229801974442 # Cumulative time (in ticks) in various power states 554system.cpu.numCycles 103518695413 # number of cpu cycles simulated 555system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 556system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 557system.cpu.kern.inst.arm 0 # number of arm instructions executed 558system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed 559system.cpu.committedInsts 835939132 # Number of instructions committed 560system.cpu.committedOps 982366087 # Number of ops (including micro ops) committed 561system.cpu.num_int_alu_accesses 902933087 # Number of integer alu accesses 562system.cpu.num_fp_alu_accesses 900158 # Number of float alu accesses 563system.cpu.num_func_calls 50090187 # number of times a function call or return occured 564system.cpu.num_conditional_control_insts 126876498 # number of instructions that are conditional controls 565system.cpu.num_int_insts 902933087 # number of integer instructions 566system.cpu.num_fp_insts 900158 # number of float instructions 567system.cpu.num_int_register_reads 1308206945 # number of times the integer registers were read 568system.cpu.num_int_register_writes 715740470 # number of times the integer registers were written 569system.cpu.num_fp_register_reads 1453094 # number of times the floating registers were read 570system.cpu.num_fp_register_writes 759824 # number of times the floating registers were written 571system.cpu.num_cc_register_reads 216985275 # number of times the CC registers were read 572system.cpu.num_cc_register_writes 216380044 # number of times the CC registers were written 573system.cpu.num_mem_refs 300079118 # number of memory refs 574system.cpu.num_load_insts 157292666 # Number of load instructions 575system.cpu.num_store_insts 142786452 # Number of store instructions 576system.cpu.num_idle_cycles 100459603948.882050 # Number of idle cycles 577system.cpu.num_busy_cycles 3059091464.117941 # Number of busy cycles 578system.cpu.not_idle_fraction 0.029551 # Percentage of non-idle cycles 579system.cpu.idle_fraction 0.970449 # Percentage of idle cycles 580system.cpu.Branches 186526742 # Number of branches fetched 581system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 582system.cpu.op_class::IntAlu 680504734 69.23% 69.23% # Class of executed instruction 583system.cpu.op_class::IntMult 2132093 0.22% 69.45% # Class of executed instruction 584system.cpu.op_class::IntDiv 96706 0.01% 69.46% # Class of executed instruction 585system.cpu.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction 586system.cpu.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction 587system.cpu.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction 588system.cpu.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction 589system.cpu.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction 590system.cpu.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction 591system.cpu.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction 592system.cpu.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction 593system.cpu.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction 594system.cpu.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction 595system.cpu.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction 596system.cpu.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction 597system.cpu.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction 598system.cpu.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction 599system.cpu.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction 600system.cpu.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction 601system.cpu.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction 602system.cpu.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction 603system.cpu.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction 604system.cpu.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction 605system.cpu.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction 606system.cpu.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction 607system.cpu.op_class::SimdFloatMisc 112297 0.01% 69.47% # Class of executed instruction 608system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction 609system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction 610system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction 611system.cpu.op_class::MemRead 157292666 16.00% 85.47% # Class of executed instruction 612system.cpu.op_class::MemWrite 142786452 14.53% 100.00% # Class of executed instruction 613system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 614system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 615system.cpu.op_class::total 982924991 # Class of executed instruction 616system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 617system.cpu.dcache.tags.replacements 9370067 # number of replacements 618system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use 619system.cpu.dcache.tags.total_refs 290532688 # Total number of references to valid blocks. 620system.cpu.dcache.tags.sampled_refs 9370579 # Sample count of references to valid blocks. 621system.cpu.dcache.tags.avg_refs 31.004774 # Average number of references to valid blocks. 622system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. 623system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor 624system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy 625system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy 626system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 627system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 628system.cpu.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id 629system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 630system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 631system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 632system.cpu.dcache.tags.tag_accesses 1209437211 # Number of tag accesses 633system.cpu.dcache.tags.data_accesses 1209437211 # Number of data accesses 634system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 635system.cpu.dcache.ReadReq_hits::cpu.data 147248395 # number of ReadReq hits 636system.cpu.dcache.ReadReq_hits::total 147248395 # number of ReadReq hits 637system.cpu.dcache.WriteReq_hits::cpu.data 135579268 # number of WriteReq hits 638system.cpu.dcache.WriteReq_hits::total 135579268 # number of WriteReq hits 639system.cpu.dcache.SoftPFReq_hits::cpu.data 373548 # number of SoftPFReq hits 640system.cpu.dcache.SoftPFReq_hits::total 373548 # number of SoftPFReq hits 641system.cpu.dcache.WriteLineReq_hits::cpu.data 331872 # number of WriteLineReq hits 642system.cpu.dcache.WriteLineReq_hits::total 331872 # number of WriteLineReq hits 643system.cpu.dcache.LoadLockedReq_hits::cpu.data 3336329 # number of LoadLockedReq hits 644system.cpu.dcache.LoadLockedReq_hits::total 3336329 # number of LoadLockedReq hits 645system.cpu.dcache.StoreCondReq_hits::cpu.data 3621011 # number of StoreCondReq hits 646system.cpu.dcache.StoreCondReq_hits::total 3621011 # number of StoreCondReq hits 647system.cpu.dcache.demand_hits::cpu.data 283159535 # number of demand (read+write) hits 648system.cpu.dcache.demand_hits::total 283159535 # number of demand (read+write) hits 649system.cpu.dcache.overall_hits::cpu.data 283533083 # number of overall hits 650system.cpu.dcache.overall_hits::total 283533083 # number of overall hits 651system.cpu.dcache.ReadReq_misses::cpu.data 4886658 # number of ReadReq misses 652system.cpu.dcache.ReadReq_misses::total 4886658 # number of ReadReq misses 653system.cpu.dcache.WriteReq_misses::cpu.data 1993718 # number of WriteReq misses 654system.cpu.dcache.WriteReq_misses::total 1993718 # number of WriteReq misses 655system.cpu.dcache.SoftPFReq_misses::cpu.data 1137538 # number of SoftPFReq misses 656system.cpu.dcache.SoftPFReq_misses::total 1137538 # number of SoftPFReq misses 657system.cpu.dcache.WriteLineReq_misses::cpu.data 1221988 # number of WriteLineReq misses 658system.cpu.dcache.WriteLineReq_misses::total 1221988 # number of WriteLineReq misses 659system.cpu.dcache.LoadLockedReq_misses::cpu.data 286320 # number of LoadLockedReq misses 660system.cpu.dcache.LoadLockedReq_misses::total 286320 # number of LoadLockedReq misses 661system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 662system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 663system.cpu.dcache.demand_misses::cpu.data 8102364 # number of demand (read+write) misses 664system.cpu.dcache.demand_misses::total 8102364 # number of demand (read+write) misses 665system.cpu.dcache.overall_misses::cpu.data 9239902 # number of overall misses 666system.cpu.dcache.overall_misses::total 9239902 # number of overall misses 667system.cpu.dcache.ReadReq_miss_latency::cpu.data 84160893500 # number of ReadReq miss cycles 668system.cpu.dcache.ReadReq_miss_latency::total 84160893500 # number of ReadReq miss cycles 669system.cpu.dcache.WriteReq_miss_latency::cpu.data 69982072000 # number of WriteReq miss cycles 670system.cpu.dcache.WriteReq_miss_latency::total 69982072000 # number of WriteReq miss cycles 671system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48119896000 # number of WriteLineReq miss cycles 672system.cpu.dcache.WriteLineReq_miss_latency::total 48119896000 # number of WriteLineReq miss cycles 673system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4409003500 # number of LoadLockedReq miss cycles 674system.cpu.dcache.LoadLockedReq_miss_latency::total 4409003500 # number of LoadLockedReq miss cycles 675system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 162000 # number of StoreCondReq miss cycles 676system.cpu.dcache.StoreCondReq_miss_latency::total 162000 # number of StoreCondReq miss cycles 677system.cpu.dcache.demand_miss_latency::cpu.data 202262861500 # number of demand (read+write) miss cycles 678system.cpu.dcache.demand_miss_latency::total 202262861500 # number of demand (read+write) miss cycles 679system.cpu.dcache.overall_miss_latency::cpu.data 202262861500 # number of overall miss cycles 680system.cpu.dcache.overall_miss_latency::total 202262861500 # number of overall miss cycles 681system.cpu.dcache.ReadReq_accesses::cpu.data 152135053 # number of ReadReq accesses(hits+misses) 682system.cpu.dcache.ReadReq_accesses::total 152135053 # number of ReadReq accesses(hits+misses) 683system.cpu.dcache.WriteReq_accesses::cpu.data 137572986 # number of WriteReq accesses(hits+misses) 684system.cpu.dcache.WriteReq_accesses::total 137572986 # number of WriteReq accesses(hits+misses) 685system.cpu.dcache.SoftPFReq_accesses::cpu.data 1511086 # number of SoftPFReq accesses(hits+misses) 686system.cpu.dcache.SoftPFReq_accesses::total 1511086 # number of SoftPFReq accesses(hits+misses) 687system.cpu.dcache.WriteLineReq_accesses::cpu.data 1553860 # number of WriteLineReq accesses(hits+misses) 688system.cpu.dcache.WriteLineReq_accesses::total 1553860 # number of WriteLineReq accesses(hits+misses) 689system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3622649 # number of LoadLockedReq accesses(hits+misses) 690system.cpu.dcache.LoadLockedReq_accesses::total 3622649 # number of LoadLockedReq accesses(hits+misses) 691system.cpu.dcache.StoreCondReq_accesses::cpu.data 3621013 # number of StoreCondReq accesses(hits+misses) 692system.cpu.dcache.StoreCondReq_accesses::total 3621013 # number of StoreCondReq accesses(hits+misses) 693system.cpu.dcache.demand_accesses::cpu.data 291261899 # number of demand (read+write) accesses 694system.cpu.dcache.demand_accesses::total 291261899 # number of demand (read+write) accesses 695system.cpu.dcache.overall_accesses::cpu.data 292772985 # number of overall (read+write) accesses 696system.cpu.dcache.overall_accesses::total 292772985 # number of overall (read+write) accesses 697system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032121 # miss rate for ReadReq accesses 698system.cpu.dcache.ReadReq_miss_rate::total 0.032121 # miss rate for ReadReq accesses 699system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014492 # miss rate for WriteReq accesses 700system.cpu.dcache.WriteReq_miss_rate::total 0.014492 # miss rate for WriteReq accesses 701system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752795 # miss rate for SoftPFReq accesses 702system.cpu.dcache.SoftPFReq_miss_rate::total 0.752795 # miss rate for SoftPFReq accesses 703system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786421 # miss rate for WriteLineReq accesses 704system.cpu.dcache.WriteLineReq_miss_rate::total 0.786421 # miss rate for WriteLineReq accesses 705system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079036 # miss rate for LoadLockedReq accesses 706system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079036 # miss rate for LoadLockedReq accesses 707system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 708system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 709system.cpu.dcache.demand_miss_rate::cpu.data 0.027818 # miss rate for demand accesses 710system.cpu.dcache.demand_miss_rate::total 0.027818 # miss rate for demand accesses 711system.cpu.dcache.overall_miss_rate::cpu.data 0.031560 # miss rate for overall accesses 712system.cpu.dcache.overall_miss_rate::total 0.031560 # miss rate for overall accesses 713system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17222.587196 # average ReadReq miss latency 714system.cpu.dcache.ReadReq_avg_miss_latency::total 17222.587196 # average ReadReq miss latency 715system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35101.289149 # average WriteReq miss latency 716system.cpu.dcache.WriteReq_avg_miss_latency::total 35101.289149 # average WriteReq miss latency 717system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39378.370328 # average WriteLineReq miss latency 718system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39378.370328 # average WriteLineReq miss latency 719system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15398.866653 # average LoadLockedReq miss latency 720system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15398.866653 # average LoadLockedReq miss latency 721system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 81000 # average StoreCondReq miss latency 722system.cpu.dcache.StoreCondReq_avg_miss_latency::total 81000 # average StoreCondReq miss latency 723system.cpu.dcache.demand_avg_miss_latency::cpu.data 24963.438016 # average overall miss latency 724system.cpu.dcache.demand_avg_miss_latency::total 24963.438016 # average overall miss latency 725system.cpu.dcache.overall_avg_miss_latency::cpu.data 21890.152244 # average overall miss latency 726system.cpu.dcache.overall_avg_miss_latency::total 21890.152244 # average overall miss latency 727system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 728system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 729system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 730system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 731system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 732system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 733system.cpu.dcache.writebacks::writebacks 7310347 # number of writebacks 734system.cpu.dcache.writebacks::total 7310347 # number of writebacks 735system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21149 # number of ReadReq MSHR hits 736system.cpu.dcache.ReadReq_mshr_hits::total 21149 # number of ReadReq MSHR hits 737system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21212 # number of WriteReq MSHR hits 738system.cpu.dcache.WriteReq_mshr_hits::total 21212 # number of WriteReq MSHR hits 739system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69210 # number of LoadLockedReq MSHR hits 740system.cpu.dcache.LoadLockedReq_mshr_hits::total 69210 # number of LoadLockedReq MSHR hits 741system.cpu.dcache.demand_mshr_hits::cpu.data 42361 # number of demand (read+write) MSHR hits 742system.cpu.dcache.demand_mshr_hits::total 42361 # number of demand (read+write) MSHR hits 743system.cpu.dcache.overall_mshr_hits::cpu.data 42361 # number of overall MSHR hits 744system.cpu.dcache.overall_mshr_hits::total 42361 # number of overall MSHR hits 745system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4865509 # number of ReadReq MSHR misses 746system.cpu.dcache.ReadReq_mshr_misses::total 4865509 # number of ReadReq MSHR misses 747system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1972506 # number of WriteReq MSHR misses 748system.cpu.dcache.WriteReq_mshr_misses::total 1972506 # number of WriteReq MSHR misses 749system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1135773 # number of SoftPFReq MSHR misses 750system.cpu.dcache.SoftPFReq_mshr_misses::total 1135773 # number of SoftPFReq MSHR misses 751system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221988 # number of WriteLineReq MSHR misses 752system.cpu.dcache.WriteLineReq_mshr_misses::total 1221988 # number of WriteLineReq MSHR misses 753system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 217110 # number of LoadLockedReq MSHR misses 754system.cpu.dcache.LoadLockedReq_mshr_misses::total 217110 # number of LoadLockedReq MSHR misses 755system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 756system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 757system.cpu.dcache.demand_mshr_misses::cpu.data 8060003 # number of demand (read+write) MSHR misses 758system.cpu.dcache.demand_mshr_misses::total 8060003 # number of demand (read+write) MSHR misses 759system.cpu.dcache.overall_mshr_misses::cpu.data 9195776 # number of overall MSHR misses 760system.cpu.dcache.overall_mshr_misses::total 9195776 # number of overall MSHR misses 761system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 762system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable 763system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 764system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 765system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 766system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses 767system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78024875000 # number of ReadReq MSHR miss cycles 768system.cpu.dcache.ReadReq_mshr_miss_latency::total 78024875000 # number of ReadReq MSHR miss cycles 769system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67036106500 # number of WriteReq MSHR miss cycles 770system.cpu.dcache.WriteReq_mshr_miss_latency::total 67036106500 # number of WriteReq MSHR miss cycles 771system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21307541000 # number of SoftPFReq MSHR miss cycles 772system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21307541000 # number of SoftPFReq MSHR miss cycles 773system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 46897908000 # number of WriteLineReq MSHR miss cycles 774system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 46897908000 # number of WriteLineReq MSHR miss cycles 775system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2989370500 # number of LoadLockedReq MSHR miss cycles 776system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2989370500 # number of LoadLockedReq MSHR miss cycles 777system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 160000 # number of StoreCondReq MSHR miss cycles 778system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 160000 # number of StoreCondReq MSHR miss cycles 779system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191958889500 # number of demand (read+write) MSHR miss cycles 780system.cpu.dcache.demand_mshr_miss_latency::total 191958889500 # number of demand (read+write) MSHR miss cycles 781system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213266430500 # number of overall MSHR miss cycles 782system.cpu.dcache.overall_mshr_miss_latency::total 213266430500 # number of overall MSHR miss cycles 783system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199627500 # number of ReadReq MSHR uncacheable cycles 784system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199627500 # number of ReadReq MSHR uncacheable cycles 785system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199627500 # number of overall MSHR uncacheable cycles 786system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199627500 # number of overall MSHR uncacheable cycles 787system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031982 # mshr miss rate for ReadReq accesses 788system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031982 # mshr miss rate for ReadReq accesses 789system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014338 # mshr miss rate for WriteReq accesses 790system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014338 # mshr miss rate for WriteReq accesses 791system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751627 # mshr miss rate for SoftPFReq accesses 792system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751627 # mshr miss rate for SoftPFReq accesses 793system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786421 # mshr miss rate for WriteLineReq accesses 794system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786421 # mshr miss rate for WriteLineReq accesses 795system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059931 # mshr miss rate for LoadLockedReq accesses 796system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059931 # mshr miss rate for LoadLockedReq accesses 797system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 798system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 799system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027673 # mshr miss rate for demand accesses 800system.cpu.dcache.demand_mshr_miss_rate::total 0.027673 # mshr miss rate for demand accesses 801system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031409 # mshr miss rate for overall accesses 802system.cpu.dcache.overall_mshr_miss_rate::total 0.031409 # mshr miss rate for overall accesses 803system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16036.323229 # average ReadReq mshr miss latency 804system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16036.323229 # average ReadReq mshr miss latency 805system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33985.248461 # average WriteReq mshr miss latency 806system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33985.248461 # average WriteReq mshr miss latency 807system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18760.386979 # average SoftPFReq mshr miss latency 808system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18760.386979 # average SoftPFReq mshr miss latency 809system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38378.370328 # average WriteLineReq mshr miss latency 810system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38378.370328 # average WriteLineReq mshr miss latency 811system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13768.921284 # average LoadLockedReq mshr miss latency 812system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13768.921284 # average LoadLockedReq mshr miss latency 813system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80000 # average StoreCondReq mshr miss latency 814system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80000 # average StoreCondReq mshr miss latency 815system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23816.230527 # average overall mshr miss latency 816system.cpu.dcache.demand_avg_mshr_miss_latency::total 23816.230527 # average overall mshr miss latency 817system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23191.781803 # average overall mshr miss latency 818system.cpu.dcache.overall_avg_mshr_miss_latency::total 23191.781803 # average overall mshr miss latency 819system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183954.290547 # average ReadReq mshr uncacheable latency 820system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183954.290547 # average ReadReq mshr uncacheable latency 821system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91968.958611 # average overall mshr uncacheable latency 822system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91968.958611 # average overall mshr uncacheable latency 823system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 824system.cpu.icache.tags.replacements 13316326 # number of replacements 825system.cpu.icache.tags.tagsinuse 511.820794 # Cycle average of tags in use 826system.cpu.icache.tags.total_refs 823138069 # Total number of references to valid blocks. 827system.cpu.icache.tags.sampled_refs 13316838 # Sample count of references to valid blocks. 828system.cpu.icache.tags.avg_refs 61.811826 # Average number of references to valid blocks. 829system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit. 830system.cpu.icache.tags.occ_blocks::cpu.inst 511.820794 # Average occupied blocks per requestor 831system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy 832system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy 833system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 834system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 835system.cpu.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id 836system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 838system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 839system.cpu.icache.tags.tag_accesses 849771755 # Number of tag accesses 840system.cpu.icache.tags.data_accesses 849771755 # Number of data accesses 841system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 842system.cpu.icache.ReadReq_hits::cpu.inst 823138069 # number of ReadReq hits 843system.cpu.icache.ReadReq_hits::total 823138069 # number of ReadReq hits 844system.cpu.icache.demand_hits::cpu.inst 823138069 # number of demand (read+write) hits 845system.cpu.icache.demand_hits::total 823138069 # number of demand (read+write) hits 846system.cpu.icache.overall_hits::cpu.inst 823138069 # number of overall hits 847system.cpu.icache.overall_hits::total 823138069 # number of overall hits 848system.cpu.icache.ReadReq_misses::cpu.inst 13316843 # number of ReadReq misses 849system.cpu.icache.ReadReq_misses::total 13316843 # number of ReadReq misses 850system.cpu.icache.demand_misses::cpu.inst 13316843 # number of demand (read+write) misses 851system.cpu.icache.demand_misses::total 13316843 # number of demand (read+write) misses 852system.cpu.icache.overall_misses::cpu.inst 13316843 # number of overall misses 853system.cpu.icache.overall_misses::total 13316843 # number of overall misses 854system.cpu.icache.ReadReq_miss_latency::cpu.inst 182043679500 # number of ReadReq miss cycles 855system.cpu.icache.ReadReq_miss_latency::total 182043679500 # number of ReadReq miss cycles 856system.cpu.icache.demand_miss_latency::cpu.inst 182043679500 # number of demand (read+write) miss cycles 857system.cpu.icache.demand_miss_latency::total 182043679500 # number of demand (read+write) miss cycles 858system.cpu.icache.overall_miss_latency::cpu.inst 182043679500 # number of overall miss cycles 859system.cpu.icache.overall_miss_latency::total 182043679500 # number of overall miss cycles 860system.cpu.icache.ReadReq_accesses::cpu.inst 836454912 # number of ReadReq accesses(hits+misses) 861system.cpu.icache.ReadReq_accesses::total 836454912 # number of ReadReq accesses(hits+misses) 862system.cpu.icache.demand_accesses::cpu.inst 836454912 # number of demand (read+write) accesses 863system.cpu.icache.demand_accesses::total 836454912 # number of demand (read+write) accesses 864system.cpu.icache.overall_accesses::cpu.inst 836454912 # number of overall (read+write) accesses 865system.cpu.icache.overall_accesses::total 836454912 # number of overall (read+write) accesses 866system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015921 # miss rate for ReadReq accesses 867system.cpu.icache.ReadReq_miss_rate::total 0.015921 # miss rate for ReadReq accesses 868system.cpu.icache.demand_miss_rate::cpu.inst 0.015921 # miss rate for demand accesses 869system.cpu.icache.demand_miss_rate::total 0.015921 # miss rate for demand accesses 870system.cpu.icache.overall_miss_rate::cpu.inst 0.015921 # miss rate for overall accesses 871system.cpu.icache.overall_miss_rate::total 0.015921 # miss rate for overall accesses 872system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13670.182903 # average ReadReq miss latency 873system.cpu.icache.ReadReq_avg_miss_latency::total 13670.182903 # average ReadReq miss latency 874system.cpu.icache.demand_avg_miss_latency::cpu.inst 13670.182903 # average overall miss latency 875system.cpu.icache.demand_avg_miss_latency::total 13670.182903 # average overall miss latency 876system.cpu.icache.overall_avg_miss_latency::cpu.inst 13670.182903 # average overall miss latency 877system.cpu.icache.overall_avg_miss_latency::total 13670.182903 # average overall miss latency 878system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 879system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 880system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 881system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 882system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 883system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 884system.cpu.icache.writebacks::writebacks 13316326 # number of writebacks 885system.cpu.icache.writebacks::total 13316326 # number of writebacks 886system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13316843 # number of ReadReq MSHR misses 887system.cpu.icache.ReadReq_mshr_misses::total 13316843 # number of ReadReq MSHR misses 888system.cpu.icache.demand_mshr_misses::cpu.inst 13316843 # number of demand (read+write) MSHR misses 889system.cpu.icache.demand_mshr_misses::total 13316843 # number of demand (read+write) MSHR misses 890system.cpu.icache.overall_mshr_misses::cpu.inst 13316843 # number of overall MSHR misses 891system.cpu.icache.overall_mshr_misses::total 13316843 # number of overall MSHR misses 892system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 893system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 894system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 895system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 896system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168726836500 # number of ReadReq MSHR miss cycles 897system.cpu.icache.ReadReq_mshr_miss_latency::total 168726836500 # number of ReadReq MSHR miss cycles 898system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168726836500 # number of demand (read+write) MSHR miss cycles 899system.cpu.icache.demand_mshr_miss_latency::total 168726836500 # number of demand (read+write) MSHR miss cycles 900system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168726836500 # number of overall MSHR miss cycles 901system.cpu.icache.overall_mshr_miss_latency::total 168726836500 # number of overall MSHR miss cycles 902system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles 903system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles 904system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles 905system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles 906system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for ReadReq accesses 907system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015921 # mshr miss rate for ReadReq accesses 908system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for demand accesses 909system.cpu.icache.demand_mshr_miss_rate::total 0.015921 # mshr miss rate for demand accesses 910system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for overall accesses 911system.cpu.icache.overall_mshr_miss_rate::total 0.015921 # mshr miss rate for overall accesses 912system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12670.182903 # average ReadReq mshr miss latency 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12670.182903 # average ReadReq mshr miss latency 914system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12670.182903 # average overall mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::total 12670.182903 # average overall mshr miss latency 916system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12670.182903 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::total 12670.182903 # average overall mshr miss latency 918system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency 919system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency 920system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency 921system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency 922system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 923system.cpu.l2cache.tags.replacements 1029342 # number of replacements 924system.cpu.l2cache.tags.tagsinuse 65301.929117 # Cycle average of tags in use 925system.cpu.l2cache.tags.total_refs 41597878 # Total number of references to valid blocks. 926system.cpu.l2cache.tags.sampled_refs 1091508 # Sample count of references to valid blocks. 927system.cpu.l2cache.tags.avg_refs 38.110466 # Average number of references to valid blocks. 928system.cpu.l2cache.tags.warmup_cycle 12385503500 # Cycle when the warmup percentage was hit. 929system.cpu.l2cache.tags.occ_blocks::writebacks 38086.632918 # Average occupied blocks per requestor 930system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 236.862091 # Average occupied blocks per requestor 931system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 354.562935 # Average occupied blocks per requestor 932system.cpu.l2cache.tags.occ_blocks::cpu.inst 7802.558346 # Average occupied blocks per requestor 933system.cpu.l2cache.tags.occ_blocks::cpu.data 18821.312827 # Average occupied blocks per requestor 934system.cpu.l2cache.tags.occ_percent::writebacks 0.581156 # Average percentage of cache occupancy 935system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003614 # Average percentage of cache occupancy 936system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005410 # Average percentage of cache occupancy 937system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119058 # Average percentage of cache occupancy 938system.cpu.l2cache.tags.occ_percent::cpu.data 0.287190 # Average percentage of cache occupancy 939system.cpu.l2cache.tags.occ_percent::total 0.996428 # Average percentage of cache occupancy 940system.cpu.l2cache.tags.occ_task_id_blocks::1023 232 # Occupied blocks per task id 941system.cpu.l2cache.tags.occ_task_id_blocks::1024 61934 # Occupied blocks per task id 942system.cpu.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 943system.cpu.l2cache.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id 944system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 945system.cpu.l2cache.tags.age_task_id_blocks_1024::1 403 # Occupied blocks per task id 946system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2431 # Occupied blocks per task id 947system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5392 # Occupied blocks per task id 948system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53675 # Occupied blocks per task id 949system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id 950system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945038 # Percentage of cache occupancy per task id 951system.cpu.l2cache.tags.tag_accesses 371610075 # Number of tag accesses 952system.cpu.l2cache.tags.data_accesses 371610075 # Number of data accesses 953system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 954system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 312133 # number of ReadReq hits 955system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242520 # number of ReadReq hits 956system.cpu.l2cache.ReadReq_hits::total 554653 # number of ReadReq hits 957system.cpu.l2cache.WritebackDirty_hits::writebacks 7310347 # number of WritebackDirty hits 958system.cpu.l2cache.WritebackDirty_hits::total 7310347 # number of WritebackDirty hits 959system.cpu.l2cache.WritebackClean_hits::writebacks 13314767 # number of WritebackClean hits 960system.cpu.l2cache.WritebackClean_hits::total 13314767 # number of WritebackClean hits 961system.cpu.l2cache.UpgradeReq_hits::cpu.data 8998 # number of UpgradeReq hits 962system.cpu.l2cache.UpgradeReq_hits::total 8998 # number of UpgradeReq hits 963system.cpu.l2cache.ReadExReq_hits::cpu.data 1590193 # number of ReadExReq hits 964system.cpu.l2cache.ReadExReq_hits::total 1590193 # number of ReadExReq hits 965system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13245839 # number of ReadCleanReq hits 966system.cpu.l2cache.ReadCleanReq_hits::total 13245839 # number of ReadCleanReq hits 967system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5993599 # number of ReadSharedReq hits 968system.cpu.l2cache.ReadSharedReq_hits::total 5993599 # number of ReadSharedReq hits 969system.cpu.l2cache.InvalidateReq_hits::cpu.data 742035 # number of InvalidateReq hits 970system.cpu.l2cache.InvalidateReq_hits::total 742035 # number of InvalidateReq hits 971system.cpu.l2cache.demand_hits::cpu.dtb.walker 312133 # number of demand (read+write) hits 972system.cpu.l2cache.demand_hits::cpu.itb.walker 242520 # number of demand (read+write) hits 973system.cpu.l2cache.demand_hits::cpu.inst 13245839 # number of demand (read+write) hits 974system.cpu.l2cache.demand_hits::cpu.data 7583792 # number of demand (read+write) hits 975system.cpu.l2cache.demand_hits::total 21384284 # number of demand (read+write) hits 976system.cpu.l2cache.overall_hits::cpu.dtb.walker 312133 # number of overall hits 977system.cpu.l2cache.overall_hits::cpu.itb.walker 242520 # number of overall hits 978system.cpu.l2cache.overall_hits::cpu.inst 13245839 # number of overall hits 979system.cpu.l2cache.overall_hits::cpu.data 7583792 # number of overall hits 980system.cpu.l2cache.overall_hits::total 21384284 # number of overall hits 981system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2378 # number of ReadReq misses 982system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2471 # number of ReadReq misses 983system.cpu.l2cache.ReadReq_misses::total 4849 # number of ReadReq misses 984system.cpu.l2cache.UpgradeReq_misses::cpu.data 33265 # number of UpgradeReq misses 985system.cpu.l2cache.UpgradeReq_misses::total 33265 # number of UpgradeReq misses 986system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 987system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 988system.cpu.l2cache.ReadExReq_misses::cpu.data 340050 # number of ReadExReq misses 989system.cpu.l2cache.ReadExReq_misses::total 340050 # number of ReadExReq misses 990system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 71004 # number of ReadCleanReq misses 991system.cpu.l2cache.ReadCleanReq_misses::total 71004 # number of ReadCleanReq misses 992system.cpu.l2cache.ReadSharedReq_misses::cpu.data 224793 # number of ReadSharedReq misses 993system.cpu.l2cache.ReadSharedReq_misses::total 224793 # number of ReadSharedReq misses 994system.cpu.l2cache.InvalidateReq_misses::cpu.data 479953 # number of InvalidateReq misses 995system.cpu.l2cache.InvalidateReq_misses::total 479953 # number of InvalidateReq misses 996system.cpu.l2cache.demand_misses::cpu.dtb.walker 2378 # number of demand (read+write) misses 997system.cpu.l2cache.demand_misses::cpu.itb.walker 2471 # number of demand (read+write) misses 998system.cpu.l2cache.demand_misses::cpu.inst 71004 # number of demand (read+write) misses 999system.cpu.l2cache.demand_misses::cpu.data 564843 # number of demand (read+write) misses 1000system.cpu.l2cache.demand_misses::total 640696 # number of demand (read+write) misses 1001system.cpu.l2cache.overall_misses::cpu.dtb.walker 2378 # number of overall misses 1002system.cpu.l2cache.overall_misses::cpu.itb.walker 2471 # number of overall misses 1003system.cpu.l2cache.overall_misses::cpu.inst 71004 # number of overall misses 1004system.cpu.l2cache.overall_misses::cpu.data 564843 # number of overall misses 1005system.cpu.l2cache.overall_misses::total 640696 # number of overall misses 1006system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 324181000 # number of ReadReq miss cycles 1007system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 343851000 # number of ReadReq miss cycles 1008system.cpu.l2cache.ReadReq_miss_latency::total 668032000 # number of ReadReq miss cycles 1009system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1328369000 # number of UpgradeReq miss cycles 1010system.cpu.l2cache.UpgradeReq_miss_latency::total 1328369000 # number of UpgradeReq miss cycles 1011system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 157000 # number of SCUpgradeReq miss cycles 1012system.cpu.l2cache.SCUpgradeReq_miss_latency::total 157000 # number of SCUpgradeReq miss cycles 1013system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 44644302500 # number of ReadExReq miss cycles 1014system.cpu.l2cache.ReadExReq_miss_latency::total 44644302500 # number of ReadExReq miss cycles 1015system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9404933500 # number of ReadCleanReq miss cycles 1016system.cpu.l2cache.ReadCleanReq_miss_latency::total 9404933500 # number of ReadCleanReq miss cycles 1017system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29984552500 # number of ReadSharedReq miss cycles 1018system.cpu.l2cache.ReadSharedReq_miss_latency::total 29984552500 # number of ReadSharedReq miss cycles 1019system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 542500 # number of InvalidateReq miss cycles 1020system.cpu.l2cache.InvalidateReq_miss_latency::total 542500 # number of InvalidateReq miss cycles 1021system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 324181000 # number of demand (read+write) miss cycles 1022system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 343851000 # number of demand (read+write) miss cycles 1023system.cpu.l2cache.demand_miss_latency::cpu.inst 9404933500 # number of demand (read+write) miss cycles 1024system.cpu.l2cache.demand_miss_latency::cpu.data 74628855000 # number of demand (read+write) miss cycles 1025system.cpu.l2cache.demand_miss_latency::total 84701820500 # number of demand (read+write) miss cycles 1026system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 324181000 # number of overall miss cycles 1027system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 343851000 # number of overall miss cycles 1028system.cpu.l2cache.overall_miss_latency::cpu.inst 9404933500 # number of overall miss cycles 1029system.cpu.l2cache.overall_miss_latency::cpu.data 74628855000 # number of overall miss cycles 1030system.cpu.l2cache.overall_miss_latency::total 84701820500 # number of overall miss cycles 1031system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 314511 # number of ReadReq accesses(hits+misses) 1032system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244991 # number of ReadReq accesses(hits+misses) 1033system.cpu.l2cache.ReadReq_accesses::total 559502 # number of ReadReq accesses(hits+misses) 1034system.cpu.l2cache.WritebackDirty_accesses::writebacks 7310347 # number of WritebackDirty accesses(hits+misses) 1035system.cpu.l2cache.WritebackDirty_accesses::total 7310347 # number of WritebackDirty accesses(hits+misses) 1036system.cpu.l2cache.WritebackClean_accesses::writebacks 13314767 # number of WritebackClean accesses(hits+misses) 1037system.cpu.l2cache.WritebackClean_accesses::total 13314767 # number of WritebackClean accesses(hits+misses) 1038system.cpu.l2cache.UpgradeReq_accesses::cpu.data 42263 # number of UpgradeReq accesses(hits+misses) 1039system.cpu.l2cache.UpgradeReq_accesses::total 42263 # number of UpgradeReq accesses(hits+misses) 1040system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1041system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 1042system.cpu.l2cache.ReadExReq_accesses::cpu.data 1930243 # number of ReadExReq accesses(hits+misses) 1043system.cpu.l2cache.ReadExReq_accesses::total 1930243 # number of ReadExReq accesses(hits+misses) 1044system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13316843 # number of ReadCleanReq accesses(hits+misses) 1045system.cpu.l2cache.ReadCleanReq_accesses::total 13316843 # number of ReadCleanReq accesses(hits+misses) 1046system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6218392 # number of ReadSharedReq accesses(hits+misses) 1047system.cpu.l2cache.ReadSharedReq_accesses::total 6218392 # number of ReadSharedReq accesses(hits+misses) 1048system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1221988 # number of InvalidateReq accesses(hits+misses) 1049system.cpu.l2cache.InvalidateReq_accesses::total 1221988 # number of InvalidateReq accesses(hits+misses) 1050system.cpu.l2cache.demand_accesses::cpu.dtb.walker 314511 # number of demand (read+write) accesses 1051system.cpu.l2cache.demand_accesses::cpu.itb.walker 244991 # number of demand (read+write) accesses 1052system.cpu.l2cache.demand_accesses::cpu.inst 13316843 # number of demand (read+write) accesses 1053system.cpu.l2cache.demand_accesses::cpu.data 8148635 # number of demand (read+write) accesses 1054system.cpu.l2cache.demand_accesses::total 22024980 # number of demand (read+write) accesses 1055system.cpu.l2cache.overall_accesses::cpu.dtb.walker 314511 # number of overall (read+write) accesses 1056system.cpu.l2cache.overall_accesses::cpu.itb.walker 244991 # number of overall (read+write) accesses 1057system.cpu.l2cache.overall_accesses::cpu.inst 13316843 # number of overall (read+write) accesses 1058system.cpu.l2cache.overall_accesses::cpu.data 8148635 # number of overall (read+write) accesses 1059system.cpu.l2cache.overall_accesses::total 22024980 # number of overall (read+write) accesses 1060system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007561 # miss rate for ReadReq accesses 1061system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010086 # miss rate for ReadReq accesses 1062system.cpu.l2cache.ReadReq_miss_rate::total 0.008667 # miss rate for ReadReq accesses 1063system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.787095 # miss rate for UpgradeReq accesses 1064system.cpu.l2cache.UpgradeReq_miss_rate::total 0.787095 # miss rate for UpgradeReq accesses 1065system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1066system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1067system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.176170 # miss rate for ReadExReq accesses 1068system.cpu.l2cache.ReadExReq_miss_rate::total 0.176170 # miss rate for ReadExReq accesses 1069system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005332 # miss rate for ReadCleanReq accesses 1070system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005332 # miss rate for ReadCleanReq accesses 1071system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036150 # miss rate for ReadSharedReq accesses 1072system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036150 # miss rate for ReadSharedReq accesses 1073system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.392764 # miss rate for InvalidateReq accesses 1074system.cpu.l2cache.InvalidateReq_miss_rate::total 0.392764 # miss rate for InvalidateReq accesses 1075system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007561 # miss rate for demand accesses 1076system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010086 # miss rate for demand accesses 1077system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005332 # miss rate for demand accesses 1078system.cpu.l2cache.demand_miss_rate::cpu.data 0.069317 # miss rate for demand accesses 1079system.cpu.l2cache.demand_miss_rate::total 0.029090 # miss rate for demand accesses 1080system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007561 # miss rate for overall accesses 1081system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010086 # miss rate for overall accesses 1082system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005332 # miss rate for overall accesses 1083system.cpu.l2cache.overall_miss_rate::cpu.data 0.069317 # miss rate for overall accesses 1084system.cpu.l2cache.overall_miss_rate::total 0.029090 # miss rate for overall accesses 1085system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136325.063078 # average ReadReq miss latency 1086system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139154.593282 # average ReadReq miss latency 1087system.cpu.l2cache.ReadReq_avg_miss_latency::total 137766.962260 # average ReadReq miss latency 1088system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39932.932512 # average UpgradeReq miss latency 1089system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39932.932512 # average UpgradeReq miss latency 1090system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 78500 # average SCUpgradeReq miss latency 1091system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 78500 # average SCUpgradeReq miss latency 1092system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131287.465079 # average ReadExReq miss latency 1093system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131287.465079 # average ReadExReq miss latency 1094system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132456.389781 # average ReadCleanReq miss latency 1095system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132456.389781 # average ReadCleanReq miss latency 1096system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133387.394180 # average ReadSharedReq miss latency 1097system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133387.394180 # average ReadSharedReq miss latency 1098system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 1.130319 # average InvalidateReq miss latency 1099system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 1.130319 # average InvalidateReq miss latency 1100system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136325.063078 # average overall miss latency 1101system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 139154.593282 # average overall miss latency 1102system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132456.389781 # average overall miss latency 1103system.cpu.l2cache.demand_avg_miss_latency::cpu.data 132123.182902 # average overall miss latency 1104system.cpu.l2cache.demand_avg_miss_latency::total 132202.823960 # average overall miss latency 1105system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136325.063078 # average overall miss latency 1106system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139154.593282 # average overall miss latency 1107system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132456.389781 # average overall miss latency 1108system.cpu.l2cache.overall_avg_miss_latency::cpu.data 132123.182902 # average overall miss latency 1109system.cpu.l2cache.overall_avg_miss_latency::total 132202.823960 # average overall miss latency 1110system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1111system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1112system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1113system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1114system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1115system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1116system.cpu.l2cache.writebacks::writebacks 876332 # number of writebacks 1117system.cpu.l2cache.writebacks::total 876332 # number of writebacks 1118system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2378 # number of ReadReq MSHR misses 1119system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2471 # number of ReadReq MSHR misses 1120system.cpu.l2cache.ReadReq_mshr_misses::total 4849 # number of ReadReq MSHR misses 1121system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33265 # number of UpgradeReq MSHR misses 1122system.cpu.l2cache.UpgradeReq_mshr_misses::total 33265 # number of UpgradeReq MSHR misses 1123system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1124system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1125system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 340050 # number of ReadExReq MSHR misses 1126system.cpu.l2cache.ReadExReq_mshr_misses::total 340050 # number of ReadExReq MSHR misses 1127system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 71004 # number of ReadCleanReq MSHR misses 1128system.cpu.l2cache.ReadCleanReq_mshr_misses::total 71004 # number of ReadCleanReq MSHR misses 1129system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 224793 # number of ReadSharedReq MSHR misses 1130system.cpu.l2cache.ReadSharedReq_mshr_misses::total 224793 # number of ReadSharedReq MSHR misses 1131system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 479953 # number of InvalidateReq MSHR misses 1132system.cpu.l2cache.InvalidateReq_mshr_misses::total 479953 # number of InvalidateReq MSHR misses 1133system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2378 # number of demand (read+write) MSHR misses 1134system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2471 # number of demand (read+write) MSHR misses 1135system.cpu.l2cache.demand_mshr_misses::cpu.inst 71004 # number of demand (read+write) MSHR misses 1136system.cpu.l2cache.demand_mshr_misses::cpu.data 564843 # number of demand (read+write) MSHR misses 1137system.cpu.l2cache.demand_mshr_misses::total 640696 # number of demand (read+write) MSHR misses 1138system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2378 # number of overall MSHR misses 1139system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2471 # number of overall MSHR misses 1140system.cpu.l2cache.overall_mshr_misses::cpu.inst 71004 # number of overall MSHR misses 1141system.cpu.l2cache.overall_mshr_misses::cpu.data 564843 # number of overall MSHR misses 1142system.cpu.l2cache.overall_mshr_misses::total 640696 # number of overall MSHR misses 1143system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 1144system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 1145system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76827 # number of ReadReq MSHR uncacheable 1146system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 1147system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 1148system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 1149system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 1150system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses 1151system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 300401000 # number of ReadReq MSHR miss cycles 1152system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 319141000 # number of ReadReq MSHR miss cycles 1153system.cpu.l2cache.ReadReq_mshr_miss_latency::total 619542000 # number of ReadReq MSHR miss cycles 1154system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2260005000 # number of UpgradeReq MSHR miss cycles 1155system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2260005000 # number of UpgradeReq MSHR miss cycles 1156system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 137000 # number of SCUpgradeReq MSHR miss cycles 1157system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles 1158system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41243802500 # number of ReadExReq MSHR miss cycles 1159system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41243802500 # number of ReadExReq MSHR miss cycles 1160system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8694893500 # number of ReadCleanReq MSHR miss cycles 1161system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8694893500 # number of ReadCleanReq MSHR miss cycles 1162system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27736359527 # number of ReadSharedReq MSHR miss cycles 1163system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27736359527 # number of ReadSharedReq MSHR miss cycles 1164system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 32474021500 # number of InvalidateReq MSHR miss cycles 1165system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 32474021500 # number of InvalidateReq MSHR miss cycles 1166system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 300401000 # number of demand (read+write) MSHR miss cycles 1167system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 319141000 # number of demand (read+write) MSHR miss cycles 1168system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8694893500 # number of demand (read+write) MSHR miss cycles 1169system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68980162027 # number of demand (read+write) MSHR miss cycles 1170system.cpu.l2cache.demand_mshr_miss_latency::total 78294597527 # number of demand (read+write) MSHR miss cycles 1171system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 300401000 # number of overall MSHR miss cycles 1172system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 319141000 # number of overall MSHR miss cycles 1173system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8694893500 # number of overall MSHR miss cycles 1174system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68980162027 # number of overall MSHR miss cycles 1175system.cpu.l2cache.overall_mshr_miss_latency::total 78294597527 # number of overall MSHR miss cycles 1176system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles 1177system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777547500 # number of ReadReq MSHR uncacheable cycles 1178system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675272000 # number of ReadReq MSHR uncacheable cycles 1179system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles 1180system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777547500 # number of overall MSHR uncacheable cycles 1181system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675272000 # number of overall MSHR uncacheable cycles 1182system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for ReadReq accesses 1183system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for ReadReq accesses 1184system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008667 # mshr miss rate for ReadReq accesses 1185system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787095 # mshr miss rate for UpgradeReq accesses 1186system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787095 # mshr miss rate for UpgradeReq accesses 1187system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1188system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1189system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176170 # mshr miss rate for ReadExReq accesses 1190system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176170 # mshr miss rate for ReadExReq accesses 1191system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for ReadCleanReq accesses 1192system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005332 # mshr miss rate for ReadCleanReq accesses 1193system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036150 # mshr miss rate for ReadSharedReq accesses 1194system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036150 # mshr miss rate for ReadSharedReq accesses 1195system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.392764 # mshr miss rate for InvalidateReq accesses 1196system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.392764 # mshr miss rate for InvalidateReq accesses 1197system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for demand accesses 1198system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for demand accesses 1199system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for demand accesses 1200system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069317 # mshr miss rate for demand accesses 1201system.cpu.l2cache.demand_mshr_miss_rate::total 0.029090 # mshr miss rate for demand accesses 1202system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for overall accesses 1203system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for overall accesses 1204system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for overall accesses 1205system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069317 # mshr miss rate for overall accesses 1206system.cpu.l2cache.overall_mshr_miss_rate::total 0.029090 # mshr miss rate for overall accesses 1207system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average ReadReq mshr miss latency 1208system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average ReadReq mshr miss latency 1209system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127766.962260 # average ReadReq mshr miss latency 1210system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67939.425823 # average UpgradeReq mshr miss latency 1211system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67939.425823 # average UpgradeReq mshr miss latency 1212system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency 1213system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency 1214system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121287.465079 # average ReadExReq mshr miss latency 1215system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121287.465079 # average ReadExReq mshr miss latency 1216system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122456.389781 # average ReadCleanReq mshr miss latency 1217system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122456.389781 # average ReadCleanReq mshr miss latency 1218system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123386.224335 # average ReadSharedReq mshr miss latency 1219system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123386.224335 # average ReadSharedReq mshr miss latency 1220system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67660.836582 # average InvalidateReq mshr miss latency 1221system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67660.836582 # average InvalidateReq mshr miss latency 1222system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average overall mshr miss latency 1223system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average overall mshr miss latency 1224system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122456.389781 # average overall mshr miss latency 1225system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122122.717334 # average overall mshr miss latency 1226system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122202.413511 # average overall mshr miss latency 1227system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average overall mshr miss latency 1228system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average overall mshr miss latency 1229system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122456.389781 # average overall mshr miss latency 1230system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122122.717334 # average overall mshr miss latency 1231system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122202.413511 # average overall mshr miss latency 1232system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency 1233system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.404724 # average ReadReq mshr uncacheable latency 1234system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.087157 # average ReadReq mshr uncacheable latency 1235system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency 1236system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85707.573060 # average overall mshr uncacheable latency 1237system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.205998 # average overall mshr uncacheable latency 1238system.cpu.toL2Bus.snoop_filter.tot_requests 45899412 # Total number of requests made to the snoop filter. 1239system.cpu.toL2Bus.snoop_filter.hit_single_requests 23211953 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1240system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1753 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1241system.cpu.toL2Bus.snoop_filter.tot_snoops 2701 # Total number of snoops made to the snoop filter. 1242system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2701 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1243system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1244system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1245system.cpu.toL2Bus.trans_dist::ReadReq 979874 # Transaction distribution 1246system.cpu.toL2Bus.trans_dist::ReadResp 20515947 # Transaction distribution 1247system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution 1248system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution 1249system.cpu.toL2Bus.trans_dist::WritebackDirty 8293329 # Transaction distribution 1250system.cpu.toL2Bus.trans_dist::WritebackClean 13316326 # Transaction distribution 1251system.cpu.toL2Bus.trans_dist::CleanEvict 2221598 # Transaction distribution 1252system.cpu.toL2Bus.trans_dist::UpgradeReq 42266 # Transaction distribution 1253system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1254system.cpu.toL2Bus.trans_dist::UpgradeResp 42268 # Transaction distribution 1255system.cpu.toL2Bus.trans_dist::ReadExReq 1930243 # Transaction distribution 1256system.cpu.toL2Bus.trans_dist::ReadExResp 1930243 # Transaction distribution 1257system.cpu.toL2Bus.trans_dist::ReadCleanReq 13316843 # Transaction distribution 1258system.cpu.toL2Bus.trans_dist::ReadSharedReq 6227282 # Transaction distribution 1259system.cpu.toL2Bus.trans_dist::InvalidateReq 1328652 # Transaction distribution 1260system.cpu.toL2Bus.trans_dist::InvalidateResp 1221988 # Transaction distribution 1261system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40036262 # Packet count per connected master and slave (bytes) 1262system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28331504 # Packet count per connected master and slave (bytes) 1263system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601742 # Packet count per connected master and slave (bytes) 1264system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 860807 # Packet count per connected master and slave (bytes) 1265system.cpu.toL2Bus.pkt_count::total 69830315 # Packet count per connected master and slave (bytes) 1266system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1704695316 # Cumulative packet size per connected master and slave (bytes) 1267system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 989618926 # Cumulative packet size per connected master and slave (bytes) 1268system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959928 # Cumulative packet size per connected master and slave (bytes) 1269system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2516088 # Cumulative packet size per connected master and slave (bytes) 1270system.cpu.toL2Bus.pkt_size::total 2698790258 # Cumulative packet size per connected master and slave (bytes) 1271system.cpu.toL2Bus.snoops 1604803 # Total snoops (count) 1272system.cpu.toL2Bus.snoopTraffic 65712840 # Total snoop traffic (bytes) 1273system.cpu.toL2Bus.snoop_fanout::samples 25003730 # Request fanout histogram 1274system.cpu.toL2Bus.snoop_fanout::mean 0.019507 # Request fanout histogram 1275system.cpu.toL2Bus.snoop_fanout::stdev 0.138299 # Request fanout histogram 1276system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1277system.cpu.toL2Bus.snoop_fanout::0 24515981 98.05% 98.05% # Request fanout histogram 1278system.cpu.toL2Bus.snoop_fanout::1 487749 1.95% 100.00% # Request fanout histogram 1279system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1280system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1281system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1282system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1283system.cpu.toL2Bus.snoop_fanout::total 25003730 # Request fanout histogram 1284system.cpu.toL2Bus.reqLayer0.occupancy 43858380000 # Layer occupancy (ticks) 1285system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1286system.cpu.toL2Bus.snoopLayer0.occupancy 1560894 # Layer occupancy (ticks) 1287system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1288system.cpu.toL2Bus.respLayer0.occupancy 20018389500 # Layer occupancy (ticks) 1289system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1290system.cpu.toL2Bus.respLayer1.occupancy 12905646976 # Layer occupancy (ticks) 1291system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1292system.cpu.toL2Bus.respLayer2.occupancy 356751000 # Layer occupancy (ticks) 1293system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1294system.cpu.toL2Bus.respLayer3.occupancy 546296000 # Layer occupancy (ticks) 1295system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1296system.iobus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1297system.iobus.trans_dist::ReadReq 40338 # Transaction distribution 1298system.iobus.trans_dist::ReadResp 40338 # Transaction distribution 1299system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1300system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1301system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1302system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1303system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1304system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1305system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1306system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1307system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1308system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1309system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1310system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1311system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1312system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1313system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1314system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1315system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231034 # Packet count per connected master and slave (bytes) 1316system.iobus.pkt_count_system.realview.ide.dma::total 231034 # Packet count per connected master and slave (bytes) 1317system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1318system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1319system.iobus.pkt_count::total 353818 # Packet count per connected master and slave (bytes) 1320system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1321system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1322system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1323system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1324system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1325system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1326system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1327system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1328system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1329system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1330system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1331system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1332system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1333system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1334system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334568 # Cumulative packet size per connected master and slave (bytes) 1335system.iobus.pkt_size_system.realview.ide.dma::total 7334568 # Cumulative packet size per connected master and slave (bytes) 1336system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1337system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1338system.iobus.pkt_size::total 7492488 # Cumulative packet size per connected master and slave (bytes) 1339system.iobus.reqLayer0.occupancy 42150000 # Layer occupancy (ticks) 1340system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1341system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1342system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1343system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) 1344system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1345system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) 1346system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1347system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) 1348system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1349system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) 1350system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1351system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 1352system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1353system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 1354system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1355system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 1356system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1357system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) 1358system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1359system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 1360system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1361system.iobus.reqLayer23.occupancy 25729000 # Layer occupancy (ticks) 1362system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1363system.iobus.reqLayer24.occupancy 38601000 # Layer occupancy (ticks) 1364system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1365system.iobus.reqLayer25.occupancy 566926866 # Layer occupancy (ticks) 1366system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1367system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1368system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1369system.iobus.respLayer3.occupancy 147794000 # Layer occupancy (ticks) 1370system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1371system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1372system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1373system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1374system.iocache.tags.replacements 115499 # number of replacements 1375system.iocache.tags.tagsinuse 10.446740 # Cycle average of tags in use 1376system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1377system.iocache.tags.sampled_refs 115515 # Sample count of references to valid blocks. 1378system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1379system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit. 1380system.iocache.tags.occ_blocks::realview.ethernet 5.847996 # Average occupied blocks per requestor 1381system.iocache.tags.occ_blocks::realview.ide 4.598744 # Average occupied blocks per requestor 1382system.iocache.tags.occ_percent::realview.ethernet 0.365500 # Average percentage of cache occupancy 1383system.iocache.tags.occ_percent::realview.ide 0.287422 # Average percentage of cache occupancy 1384system.iocache.tags.occ_percent::total 0.652921 # Average percentage of cache occupancy 1385system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1386system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1387system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1388system.iocache.tags.tag_accesses 1040010 # Number of tag accesses 1389system.iocache.tags.data_accesses 1040010 # Number of data accesses 1390system.iocache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1391system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1392system.iocache.ReadReq_misses::realview.ide 8853 # number of ReadReq misses 1393system.iocache.ReadReq_misses::total 8890 # number of ReadReq misses 1394system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1395system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1396system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1397system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1398system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1399system.iocache.demand_misses::realview.ide 115517 # number of demand (read+write) misses 1400system.iocache.demand_misses::total 115557 # number of demand (read+write) misses 1401system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1402system.iocache.overall_misses::realview.ide 115517 # number of overall misses 1403system.iocache.overall_misses::total 115557 # number of overall misses 1404system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles 1405system.iocache.ReadReq_miss_latency::realview.ide 1655174117 # number of ReadReq miss cycles 1406system.iocache.ReadReq_miss_latency::total 1660244617 # number of ReadReq miss cycles 1407system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1408system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1409system.iocache.WriteLineReq_miss_latency::realview.ide 13409764249 # number of WriteLineReq miss cycles 1410system.iocache.WriteLineReq_miss_latency::total 13409764249 # number of WriteLineReq miss cycles 1411system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles 1412system.iocache.demand_miss_latency::realview.ide 15064938366 # number of demand (read+write) miss cycles 1413system.iocache.demand_miss_latency::total 15070359866 # number of demand (read+write) miss cycles 1414system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles 1415system.iocache.overall_miss_latency::realview.ide 15064938366 # number of overall miss cycles 1416system.iocache.overall_miss_latency::total 15070359866 # number of overall miss cycles 1417system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1418system.iocache.ReadReq_accesses::realview.ide 8853 # number of ReadReq accesses(hits+misses) 1419system.iocache.ReadReq_accesses::total 8890 # number of ReadReq accesses(hits+misses) 1420system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1421system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1422system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1423system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1424system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1425system.iocache.demand_accesses::realview.ide 115517 # number of demand (read+write) accesses 1426system.iocache.demand_accesses::total 115557 # number of demand (read+write) accesses 1427system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1428system.iocache.overall_accesses::realview.ide 115517 # number of overall (read+write) accesses 1429system.iocache.overall_accesses::total 115557 # number of overall (read+write) accesses 1430system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1431system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1432system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1433system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1434system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1435system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1436system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1437system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1438system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1439system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1440system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1441system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1442system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1443system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency 1444system.iocache.ReadReq_avg_miss_latency::realview.ide 186961.947024 # average ReadReq miss latency 1445system.iocache.ReadReq_avg_miss_latency::total 186754.175141 # average ReadReq miss latency 1446system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1447system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1448system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125719.682826 # average WriteLineReq miss latency 1449system.iocache.WriteLineReq_avg_miss_latency::total 125719.682826 # average WriteLineReq miss latency 1450system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency 1451system.iocache.demand_avg_miss_latency::realview.ide 130413.171793 # average overall miss latency 1452system.iocache.demand_avg_miss_latency::total 130414.945577 # average overall miss latency 1453system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency 1454system.iocache.overall_avg_miss_latency::realview.ide 130413.171793 # average overall miss latency 1455system.iocache.overall_avg_miss_latency::total 130414.945577 # average overall miss latency 1456system.iocache.blocked_cycles::no_mshrs 33045 # number of cycles access was blocked 1457system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1458system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked 1459system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1460system.iocache.avg_blocked_cycles::no_mshrs 9.788211 # average number of cycles each access was blocked 1461system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1462system.iocache.writebacks::writebacks 106631 # number of writebacks 1463system.iocache.writebacks::total 106631 # number of writebacks 1464system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1465system.iocache.ReadReq_mshr_misses::realview.ide 8853 # number of ReadReq MSHR misses 1466system.iocache.ReadReq_mshr_misses::total 8890 # number of ReadReq MSHR misses 1467system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1468system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1469system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1470system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1471system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1472system.iocache.demand_mshr_misses::realview.ide 115517 # number of demand (read+write) MSHR misses 1473system.iocache.demand_mshr_misses::total 115557 # number of demand (read+write) MSHR misses 1474system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1475system.iocache.overall_mshr_misses::realview.ide 115517 # number of overall MSHR misses 1476system.iocache.overall_mshr_misses::total 115557 # number of overall MSHR misses 1477system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles 1478system.iocache.ReadReq_mshr_miss_latency::realview.ide 1212524117 # number of ReadReq MSHR miss cycles 1479system.iocache.ReadReq_mshr_miss_latency::total 1215744617 # number of ReadReq MSHR miss cycles 1480system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1481system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1482system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071395398 # number of WriteLineReq MSHR miss cycles 1483system.iocache.WriteLineReq_mshr_miss_latency::total 8071395398 # number of WriteLineReq MSHR miss cycles 1484system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles 1485system.iocache.demand_mshr_miss_latency::realview.ide 9283919515 # number of demand (read+write) MSHR miss cycles 1486system.iocache.demand_mshr_miss_latency::total 9287341015 # number of demand (read+write) MSHR miss cycles 1487system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles 1488system.iocache.overall_mshr_miss_latency::realview.ide 9283919515 # number of overall MSHR miss cycles 1489system.iocache.overall_mshr_miss_latency::total 9287341015 # number of overall MSHR miss cycles 1490system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1491system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1492system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1493system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1494system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1495system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1496system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1497system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1498system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1499system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1500system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1501system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1502system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1503system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency 1504system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136961.947024 # average ReadReq mshr miss latency 1505system.iocache.ReadReq_avg_mshr_miss_latency::total 136754.175141 # average ReadReq mshr miss latency 1506system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1507system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1508system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75671.223637 # average WriteLineReq mshr miss latency 1509system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75671.223637 # average WriteLineReq mshr miss latency 1510system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency 1511system.iocache.demand_avg_mshr_miss_latency::realview.ide 80368.426422 # average overall mshr miss latency 1512system.iocache.demand_avg_mshr_miss_latency::total 80370.215694 # average overall mshr miss latency 1513system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency 1514system.iocache.overall_avg_mshr_miss_latency::realview.ide 80368.426422 # average overall mshr miss latency 1515system.iocache.overall_avg_mshr_miss_latency::total 80370.215694 # average overall mshr miss latency 1516system.membus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1517system.membus.trans_dist::ReadReq 76827 # Transaction distribution 1518system.membus.trans_dist::ReadResp 386363 # Transaction distribution 1519system.membus.trans_dist::WriteReq 33708 # Transaction distribution 1520system.membus.trans_dist::WriteResp 33708 # Transaction distribution 1521system.membus.trans_dist::WritebackDirty 982963 # Transaction distribution 1522system.membus.trans_dist::CleanEvict 160860 # Transaction distribution 1523system.membus.trans_dist::UpgradeReq 33836 # Transaction distribution 1524system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1525system.membus.trans_dist::UpgradeResp 7 # Transaction distribution 1526system.membus.trans_dist::ReadExReq 339489 # Transaction distribution 1527system.membus.trans_dist::ReadExResp 339489 # Transaction distribution 1528system.membus.trans_dist::ReadSharedReq 309536 # Transaction distribution 1529system.membus.trans_dist::InvalidateReq 586610 # Transaction distribution 1530system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1531system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1532system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) 1533system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2913100 # Packet count per connected master and slave (bytes) 1534system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3042792 # Packet count per connected master and slave (bytes) 1535system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237470 # Packet count per connected master and slave (bytes) 1536system.membus.pkt_count_system.iocache.mem_side::total 237470 # Packet count per connected master and slave (bytes) 1537system.membus.pkt_count::total 3280262 # Packet count per connected master and slave (bytes) 1538system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1539system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1540system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) 1541system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97205216 # Cumulative packet size per connected master and slave (bytes) 1542system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97375042 # Cumulative packet size per connected master and slave (bytes) 1543system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7234880 # Cumulative packet size per connected master and slave (bytes) 1544system.membus.pkt_size_system.iocache.mem_side::total 7234880 # Cumulative packet size per connected master and slave (bytes) 1545system.membus.pkt_size::total 104609922 # Cumulative packet size per connected master and slave (bytes) 1546system.membus.snoops 3136 # Total snoops (count) 1547system.membus.snoopTraffic 200256 # Total snoop traffic (bytes) 1548system.membus.snoop_fanout::samples 2523850 # Request fanout histogram 1549system.membus.snoop_fanout::mean 1 # Request fanout histogram 1550system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1551system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1552system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1553system.membus.snoop_fanout::1 2523850 100.00% 100.00% # Request fanout histogram 1554system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1555system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1556system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1557system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1558system.membus.snoop_fanout::total 2523850 # Request fanout histogram 1559system.membus.reqLayer0.occupancy 106906000 # Layer occupancy (ticks) 1560system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1561system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 1562system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1563system.membus.reqLayer2.occupancy 5727500 # Layer occupancy (ticks) 1564system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1565system.membus.reqLayer5.occupancy 6514212892 # Layer occupancy (ticks) 1566system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1567system.membus.respLayer2.occupancy 3604018785 # Layer occupancy (ticks) 1568system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1569system.membus.respLayer3.occupancy 44774812 # Layer occupancy (ticks) 1570system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1571system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1572system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1573system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1574system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1575system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1576system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1577system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1578system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1579system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1580system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1581system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1582system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1583system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1584system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1585system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1586system.realview.ethernet.txBytes 966 # Bytes Transmitted 1587system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1588system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1589system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1590system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1591system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1592system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1593system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1594system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1595system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 1596system.realview.ethernet.totPackets 3 # Total Packets 1597system.realview.ethernet.totBytes 966 # Total Bytes 1598system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1599system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 1600system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1601system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1602system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1603system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1604system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1605system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1606system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1607system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1608system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1609system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1610system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1611system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1612system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1613system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1614system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1615system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1616system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1617system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1618system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1619system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1620system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1621system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1622system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1623system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1624system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1625system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1626system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1627system.realview.ethernet.droppedPackets 0 # number of packets dropped 1628system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1629system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1630system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1631system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1632system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1633system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1634system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1635system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1636system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1637system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1638system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1639system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1640system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1641system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1642system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1643system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1644system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1645system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1646system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1647system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1648system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1649system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1650system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1651 1652---------- End Simulation Statistics ---------- 1653