stats.txt revision 11014:863d314f6356
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.832459 # Number of seconds simulated 4sim_ticks 51832458543500 # Number of ticks simulated 5final_tick 51832458543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 643815 # Simulator instruction rate (inst/s) 8host_op_rate 756535 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37796716864 # Simulator tick rate (ticks/s) 10host_mem_usage 668604 # Number of bytes of host memory used 11host_seconds 1371.35 # Real time elapsed on the host 12sim_insts 882895003 # Number of instructions simulated 13sim_ops 1037473525 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 255168 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 250176 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5270964 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 81048392 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 390144 # Number of bytes read from this memory 21system.physmem.bytes_read::total 87214844 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 5270964 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 5270964 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 75813760 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 75834340 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 3987 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 3909 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 122766 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1266394 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6096 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1403152 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1184590 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1187163 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 4923 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 4827 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 101692 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1563661 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7527 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1682630 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 101692 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 101692 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1462670 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1463067 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1462670 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 4923 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 4827 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 101692 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1564058 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7527 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3145697 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1403152 # Number of read requests accepted 55system.physmem.writeReqs 1187163 # Number of write requests accepted 56system.physmem.readBursts 1403152 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1187163 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 89743360 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 58368 # Total number of bytes read from write queue 60system.physmem.bytesWritten 75832768 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 87214844 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 75834340 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 912 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 142509 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 84707 # Per bank write bursts 67system.physmem.perBankRdBursts::1 87220 # Per bank write bursts 68system.physmem.perBankRdBursts::2 81347 # Per bank write bursts 69system.physmem.perBankRdBursts::3 82774 # Per bank write bursts 70system.physmem.perBankRdBursts::4 86841 # Per bank write bursts 71system.physmem.perBankRdBursts::5 98270 # Per bank write bursts 72system.physmem.perBankRdBursts::6 81495 # Per bank write bursts 73system.physmem.perBankRdBursts::7 83122 # Per bank write bursts 74system.physmem.perBankRdBursts::8 79285 # Per bank write bursts 75system.physmem.perBankRdBursts::9 129613 # Per bank write bursts 76system.physmem.perBankRdBursts::10 85444 # Per bank write bursts 77system.physmem.perBankRdBursts::11 88159 # Per bank write bursts 78system.physmem.perBankRdBursts::12 83519 # Per bank write bursts 79system.physmem.perBankRdBursts::13 84779 # Per bank write bursts 80system.physmem.perBankRdBursts::14 82284 # Per bank write bursts 81system.physmem.perBankRdBursts::15 83381 # Per bank write bursts 82system.physmem.perBankWrBursts::0 72521 # Per bank write bursts 83system.physmem.perBankWrBursts::1 74576 # Per bank write bursts 84system.physmem.perBankWrBursts::2 72526 # Per bank write bursts 85system.physmem.perBankWrBursts::3 74694 # Per bank write bursts 86system.physmem.perBankWrBursts::4 74615 # Per bank write bursts 87system.physmem.perBankWrBursts::5 83452 # Per bank write bursts 88system.physmem.perBankWrBursts::6 71356 # Per bank write bursts 89system.physmem.perBankWrBursts::7 73404 # Per bank write bursts 90system.physmem.perBankWrBursts::8 69434 # Per bank write bursts 91system.physmem.perBankWrBursts::9 76014 # Per bank write bursts 92system.physmem.perBankWrBursts::10 73389 # Per bank write bursts 93system.physmem.perBankWrBursts::11 75855 # Per bank write bursts 94system.physmem.perBankWrBursts::12 72723 # Per bank write bursts 95system.physmem.perBankWrBursts::13 74909 # Per bank write bursts 96system.physmem.perBankWrBursts::14 71861 # Per bank write bursts 97system.physmem.perBankWrBursts::15 73558 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 15 # Number of times write queue was full causing retry 100system.physmem.totGap 51832455911500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 43101 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 1360036 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 1184590 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1369724 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 26989 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 311 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 465 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 443 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 479 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 493 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 784 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 854 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 363 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 161 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 142 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 120 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 106 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 91 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 15525 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 18184 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 68862 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 70049 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 70008 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 69966 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 69777 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 72690 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 73075 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 75585 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 74412 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 74484 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 71661 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 71703 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 72226 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 69733 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 69498 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 68867 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 681 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 570 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 560 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 515 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 431 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 399 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 395 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 361 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 405 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 280 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 239 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 248 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 317 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 304 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 270 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 247 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 227 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 320 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 238 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 216 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 220 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 164 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 107 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 564142 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 293.500232 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 169.709934 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 326.462784 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 227896 40.40% 40.40% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 137874 24.44% 64.84% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 50148 8.89% 73.73% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 27962 4.96% 78.68% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 20021 3.55% 82.23% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 14110 2.50% 84.73% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 11549 2.05% 86.78% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 10920 1.94% 88.72% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 63662 11.28% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 564142 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 68197 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 20.561359 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 299.455370 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-4095 68195 100.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 68197 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 68197 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 17.374474 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 16.924162 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 6.358180 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 65696 96.33% 96.33% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 133 0.20% 96.53% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 441 0.65% 97.17% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 195 0.29% 97.46% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 359 0.53% 97.99% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 498 0.73% 98.72% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 123 0.18% 98.90% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 30 0.04% 98.94% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 34 0.05% 98.99% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 28 0.04% 99.03% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 38 0.06% 99.09% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 22 0.03% 99.12% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 434 0.64% 99.76% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 35 0.05% 99.81% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 41 0.06% 99.87% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 27 0.04% 99.91% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 2 0.00% 99.92% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 1 0.00% 99.92% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 1 0.00% 99.92% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 4 0.01% 99.93% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::100-103 4 0.01% 99.93% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::128-131 26 0.04% 99.98% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::148-151 5 0.01% 99.99% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::164-167 5 0.01% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::total 68197 # Writes before turning the bus around for reads 269system.physmem.totQLat 16916842552 # Total ticks spent queuing 270system.physmem.totMemAccLat 43208842552 # Total ticks spent from burst creation until serviced by the DRAM 271system.physmem.totBusLat 7011200000 # Total ticks spent in databus transfers 272system.physmem.avgQLat 12064.16 # Average queueing delay per DRAM burst 273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 274system.physmem.avgMemAccLat 30814.16 # Average memory access latency per DRAM burst 275system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s 276system.physmem.avgWrBW 1.46 # Average achieved write bandwidth in MiByte/s 277system.physmem.avgRdBWSys 1.68 # Average system read bandwidth in MiByte/s 278system.physmem.avgWrBWSys 1.46 # Average system write bandwidth in MiByte/s 279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 280system.physmem.busUtil 0.02 # Data bus utilization in percentage 281system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 282system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 283system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 284system.physmem.avgWrQLen 22.64 # Average write queue length when enqueuing 285system.physmem.readRowHits 1132918 # Number of row buffer hits during reads 286system.physmem.writeRowHits 890066 # Number of row buffer hits during writes 287system.physmem.readRowHitRate 80.79 # Row buffer hit rate for reads 288system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes 289system.physmem.avgGap 20010097.58 # Average gap between requests 290system.physmem.pageHitRate 78.19 # Row buffer hit rate, read and write combined 291system.physmem_0.actEnergy 2149066080 # Energy for activate commands per rank (pJ) 292system.physmem_0.preEnergy 1172605500 # Energy for precharge commands per rank (pJ) 293system.physmem_0.readEnergy 5349013800 # Energy for read commands per rank (pJ) 294system.physmem_0.writeEnergy 3869493120 # Energy for write commands per rank (pJ) 295system.physmem_0.refreshEnergy 3385443743760 # Energy for refresh commands per rank (pJ) 296system.physmem_0.actBackEnergy 1308122393760 # Energy for active background per rank (pJ) 297system.physmem_0.preBackEnergy 29951995045500 # Energy for precharge background per rank (pJ) 298system.physmem_0.totalEnergy 34658101361520 # Total energy per rank (pJ) 299system.physmem_0.averagePower 668.656420 # Core power per rank (mW) 300system.physmem_0.memoryStateTime::IDLE 49827055945457 # Time in different power states 301system.physmem_0.memoryStateTime::REF 1730799460000 # Time in different power states 302system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 303system.physmem_0.memoryStateTime::ACT 274602731543 # Time in different power states 304system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 305system.physmem_1.actEnergy 2115847440 # Energy for activate commands per rank (pJ) 306system.physmem_1.preEnergy 1154480250 # Energy for precharge commands per rank (pJ) 307system.physmem_1.readEnergy 5588419200 # Energy for read commands per rank (pJ) 308system.physmem_1.writeEnergy 3808574640 # Energy for write commands per rank (pJ) 309system.physmem_1.refreshEnergy 3385443743760 # Energy for refresh commands per rank (pJ) 310system.physmem_1.actBackEnergy 1306419956235 # Energy for active background per rank (pJ) 311system.physmem_1.preBackEnergy 29953488411750 # Energy for precharge background per rank (pJ) 312system.physmem_1.totalEnergy 34658019433275 # Total energy per rank (pJ) 313system.physmem_1.averagePower 668.654839 # Core power per rank (mW) 314system.physmem_1.memoryStateTime::IDLE 49829529145116 # Time in different power states 315system.physmem_1.memoryStateTime::REF 1730799460000 # Time in different power states 316system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 317system.physmem_1.memoryStateTime::ACT 272122791134 # Time in different power states 318system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 319system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 320system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 321system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 322system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 323system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 324system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 325system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 326system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 327system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 332system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 333system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 334system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) 335system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 336system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 337system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 338system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 339system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 340system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 341system.cpu_clk_domain.clock 500 # Clock period in ticks 342system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 343system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 346system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 351system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 352system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 353system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 354system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 355system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 356system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 357system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 358system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 359system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 360system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 361system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 362system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 363system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 364system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 365system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 366system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 367system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 368system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 369system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 370system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 371system.cpu.dtb.walker.walks 207675 # Table walker walks requested 372system.cpu.dtb.walker.walksLong 207675 # Table walker walks initiated with long descriptors 373system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15981 # Level at which table walker walks with long descriptors terminate 374system.cpu.dtb.walker.walksLongTerminationLevel::Level3 160171 # Level at which table walker walks with long descriptors terminate 375system.cpu.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting 376system.cpu.dtb.walker.walkWaitTime::samples 207653 # Table walker wait (enqueue to first request) latency 377system.cpu.dtb.walker.walkWaitTime::mean 0.182998 # Table walker wait (enqueue to first request) latency 378system.cpu.dtb.walker.walkWaitTime::stdev 62.840123 # Table walker wait (enqueue to first request) latency 379system.cpu.dtb.walker.walkWaitTime::0-2047 207651 100.00% 100.00% # Table walker wait (enqueue to first request) latency 380system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 381system.cpu.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 382system.cpu.dtb.walker.walkWaitTime::total 207653 # Table walker wait (enqueue to first request) latency 383system.cpu.dtb.walker.walkCompletionTime::samples 176174 # Table walker service (enqueue to completion) latency 384system.cpu.dtb.walker.walkCompletionTime::mean 24712.505818 # Table walker service (enqueue to completion) latency 385system.cpu.dtb.walker.walkCompletionTime::gmean 21157.403643 # Table walker service (enqueue to completion) latency 386system.cpu.dtb.walker.walkCompletionTime::stdev 15094.851220 # Table walker service (enqueue to completion) latency 387system.cpu.dtb.walker.walkCompletionTime::0-32767 111064 63.04% 63.04% # Table walker service (enqueue to completion) latency 388system.cpu.dtb.walker.walkCompletionTime::32768-65535 63199 35.87% 98.92% # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walkCompletionTime::65536-98303 999 0.57% 99.48% # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walkCompletionTime::98304-131071 662 0.38% 99.86% # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::131072-163839 15 0.01% 99.87% # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::163840-196607 88 0.05% 99.92% # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::196608-229375 11 0.01% 99.92% # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::229376-262143 50 0.03% 99.95% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::262144-294911 52 0.03% 99.98% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::294912-327679 13 0.01% 99.99% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::total 176174 # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walksPending::samples -781821628 # Table walker pending requests distribution 405system.cpu.dtb.walker.walksPending::mean 0.029012 # Table walker pending requests distribution 406system.cpu.dtb.walker.walksPending::stdev 0.167839 # Table walker pending requests distribution 407system.cpu.dtb.walker.walksPending::0 -759139796 97.10% 97.10% # Table walker pending requests distribution 408system.cpu.dtb.walker.walksPending::1 -22681832 2.90% 100.00% # Table walker pending requests distribution 409system.cpu.dtb.walker.walksPending::total -781821628 # Table walker pending requests distribution 410system.cpu.dtb.walker.walkPageSizes::4K 160172 90.93% 90.93% # Table walker page sizes translated 411system.cpu.dtb.walker.walkPageSizes::2M 15981 9.07% 100.00% # Table walker page sizes translated 412system.cpu.dtb.walker.walkPageSizes::total 176153 # Table walker page sizes translated 413system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 207675 # Table walker requests started/completed, data/inst 414system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu.dtb.walker.walkRequestOrigin_Requested::total 207675 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 176153 # Table walker requests started/completed, data/inst 417system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 418system.cpu.dtb.walker.walkRequestOrigin_Completed::total 176153 # Table walker requests started/completed, data/inst 419system.cpu.dtb.walker.walkRequestOrigin::total 383828 # Table walker requests started/completed, data/inst 420system.cpu.dtb.inst_hits 0 # ITB inst hits 421system.cpu.dtb.inst_misses 0 # ITB inst misses 422system.cpu.dtb.read_hits 165829611 # DTB read hits 423system.cpu.dtb.read_misses 153241 # DTB read misses 424system.cpu.dtb.write_hits 150793131 # DTB write hits 425system.cpu.dtb.write_misses 54434 # DTB write misses 426system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 427system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 428system.cpu.dtb.flush_tlb_mva_asid 42000 # Number of times TLB was flushed by MVA & ASID 429system.cpu.dtb.flush_tlb_asid 1055 # Number of times TLB was flushed by ASID 430system.cpu.dtb.flush_entries 75015 # Number of entries that have been flushed from TLB 431system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 432system.cpu.dtb.prefetch_faults 8164 # Number of TLB faults due to prefetch 433system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 434system.cpu.dtb.perms_faults 19719 # Number of TLB faults due to permissions restrictions 435system.cpu.dtb.read_accesses 165982852 # DTB read accesses 436system.cpu.dtb.write_accesses 150847565 # DTB write accesses 437system.cpu.dtb.inst_accesses 0 # ITB inst accesses 438system.cpu.dtb.hits 316622742 # DTB hits 439system.cpu.dtb.misses 207675 # DTB misses 440system.cpu.dtb.accesses 316830417 # DTB accesses 441system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 447system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 448system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 449system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 450system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 451system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 452system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 453system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 454system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 455system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 456system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 457system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 458system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 459system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 460system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 461system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 462system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 463system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 464system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 465system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 466system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 467system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 468system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 469system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 470system.cpu.itb.walker.walks 122431 # Table walker walks requested 471system.cpu.itb.walker.walksLong 122431 # Table walker walks initiated with long descriptors 472system.cpu.itb.walker.walksLongTerminationLevel::Level2 1128 # Level at which table walker walks with long descriptors terminate 473system.cpu.itb.walker.walksLongTerminationLevel::Level3 110257 # Level at which table walker walks with long descriptors terminate 474system.cpu.itb.walker.walkWaitTime::samples 122431 # Table walker wait (enqueue to first request) latency 475system.cpu.itb.walker.walkWaitTime::0 122431 100.00% 100.00% # Table walker wait (enqueue to first request) latency 476system.cpu.itb.walker.walkWaitTime::total 122431 # Table walker wait (enqueue to first request) latency 477system.cpu.itb.walker.walkCompletionTime::samples 111385 # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::mean 28118.386677 # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::gmean 24591.122191 # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::stdev 17995.361080 # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::0-65535 109197 98.04% 98.04% # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::65536-131071 1895 1.70% 99.74% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::131072-196607 129 0.12% 99.85% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::196608-262143 78 0.07% 99.92% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::262144-327679 51 0.05% 99.97% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 489system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 490system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 491system.cpu.itb.walker.walkCompletionTime::total 111385 # Table walker service (enqueue to completion) latency 492system.cpu.itb.walker.walksPending::samples -887504296 # Table walker pending requests distribution 493system.cpu.itb.walker.walksPending::0 -887504296 100.00% 100.00% # Table walker pending requests distribution 494system.cpu.itb.walker.walksPending::total -887504296 # Table walker pending requests distribution 495system.cpu.itb.walker.walkPageSizes::4K 110257 98.99% 98.99% # Table walker page sizes translated 496system.cpu.itb.walker.walkPageSizes::2M 1128 1.01% 100.00% # Table walker page sizes translated 497system.cpu.itb.walker.walkPageSizes::total 111385 # Table walker page sizes translated 498system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 499system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122431 # Table walker requests started/completed, data/inst 500system.cpu.itb.walker.walkRequestOrigin_Requested::total 122431 # Table walker requests started/completed, data/inst 501system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 502system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111385 # Table walker requests started/completed, data/inst 503system.cpu.itb.walker.walkRequestOrigin_Completed::total 111385 # Table walker requests started/completed, data/inst 504system.cpu.itb.walker.walkRequestOrigin::total 233816 # Table walker requests started/completed, data/inst 505system.cpu.itb.inst_hits 883439249 # ITB inst hits 506system.cpu.itb.inst_misses 122431 # ITB inst misses 507system.cpu.itb.read_hits 0 # DTB read hits 508system.cpu.itb.read_misses 0 # DTB read misses 509system.cpu.itb.write_hits 0 # DTB write hits 510system.cpu.itb.write_misses 0 # DTB write misses 511system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 512system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 513system.cpu.itb.flush_tlb_mva_asid 42000 # Number of times TLB was flushed by MVA & ASID 514system.cpu.itb.flush_tlb_asid 1055 # Number of times TLB was flushed by ASID 515system.cpu.itb.flush_entries 53485 # Number of entries that have been flushed from TLB 516system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 517system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 518system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 519system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 520system.cpu.itb.read_accesses 0 # DTB read accesses 521system.cpu.itb.write_accesses 0 # DTB write accesses 522system.cpu.itb.inst_accesses 883561680 # ITB inst accesses 523system.cpu.itb.hits 883439249 # DTB hits 524system.cpu.itb.misses 122431 # DTB misses 525system.cpu.itb.accesses 883561680 # DTB accesses 526system.cpu.numCycles 103664917087 # number of cpu cycles simulated 527system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 528system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 529system.cpu.committedInsts 882895003 # Number of instructions committed 530system.cpu.committedOps 1037473525 # Number of ops (including micro ops) committed 531system.cpu.num_int_alu_accesses 952709754 # Number of integer alu accesses 532system.cpu.num_fp_alu_accesses 896425 # Number of float alu accesses 533system.cpu.num_func_calls 52419949 # number of times a function call or return occured 534system.cpu.num_conditional_control_insts 134729686 # number of instructions that are conditional controls 535system.cpu.num_int_insts 952709754 # number of integer instructions 536system.cpu.num_fp_insts 896425 # number of float instructions 537system.cpu.num_int_register_reads 1388360502 # number of times the integer registers were read 538system.cpu.num_int_register_writes 755717952 # number of times the integer registers were written 539system.cpu.num_fp_register_reads 1444442 # number of times the floating registers were read 540system.cpu.num_fp_register_writes 761348 # number of times the floating registers were written 541system.cpu.num_cc_register_reads 231664947 # number of times the CC registers were read 542system.cpu.num_cc_register_writes 231068644 # number of times the CC registers were written 543system.cpu.num_mem_refs 316605789 # number of memory refs 544system.cpu.num_load_insts 165822487 # Number of load instructions 545system.cpu.num_store_insts 150783302 # Number of store instructions 546system.cpu.num_idle_cycles 100487560505.254059 # Number of idle cycles 547system.cpu.num_busy_cycles 3177356581.745939 # Number of busy cycles 548system.cpu.not_idle_fraction 0.030650 # Percentage of non-idle cycles 549system.cpu.idle_fraction 0.969350 # Percentage of idle cycles 550system.cpu.Branches 197184546 # Number of branches fetched 551system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 552system.cpu.op_class::IntAlu 719043510 69.27% 69.27% # Class of executed instruction 553system.cpu.op_class::IntMult 2202813 0.21% 69.48% # Class of executed instruction 554system.cpu.op_class::IntDiv 97927 0.01% 69.49% # Class of executed instruction 555system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction 556system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction 557system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction 558system.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction 559system.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction 560system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction 561system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction 562system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction 563system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction 564system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction 565system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction 566system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction 567system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction 568system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction 569system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction 570system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction 571system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction 572system.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction 573system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction 574system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction 575system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction 576system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction 577system.cpu.op_class::SimdFloatMisc 110813 0.01% 69.50% # Class of executed instruction 578system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction 579system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction 580system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction 581system.cpu.op_class::MemRead 165822487 15.97% 85.47% # Class of executed instruction 582system.cpu.op_class::MemWrite 150783302 14.53% 100.00% # Class of executed instruction 583system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 584system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 585system.cpu.op_class::total 1038060895 # Class of executed instruction 586system.cpu.kern.inst.arm 0 # number of arm instructions executed 587system.cpu.kern.inst.quiesce 16280 # number of quiesce instructions executed 588system.cpu.dcache.tags.replacements 10067650 # number of replacements 589system.cpu.dcache.tags.tagsinuse 511.966034 # Cycle average of tags in use 590system.cpu.dcache.tags.total_refs 306351638 # Total number of references to valid blocks. 591system.cpu.dcache.tags.sampled_refs 10068162 # Sample count of references to valid blocks. 592system.cpu.dcache.tags.avg_refs 30.427762 # Average number of references to valid blocks. 593system.cpu.dcache.tags.warmup_cycle 3466781500 # Cycle when the warmup percentage was hit. 594system.cpu.dcache.tags.occ_blocks::cpu.data 511.966034 # Average occupied blocks per requestor 595system.cpu.dcache.tags.occ_percent::cpu.data 0.999934 # Average percentage of cache occupancy 596system.cpu.dcache.tags.occ_percent::total 0.999934 # Average percentage of cache occupancy 597system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 598system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 599system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id 600system.cpu.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 601system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 602system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 603system.cpu.dcache.tags.tag_accesses 1276220350 # Number of tag accesses 604system.cpu.dcache.tags.data_accesses 1276220350 # Number of data accesses 605system.cpu.dcache.ReadReq_hits::cpu.data 154968992 # number of ReadReq hits 606system.cpu.dcache.ReadReq_hits::total 154968992 # number of ReadReq hits 607system.cpu.dcache.WriteReq_hits::cpu.data 143085243 # number of WriteReq hits 608system.cpu.dcache.WriteReq_hits::total 143085243 # number of WriteReq hits 609system.cpu.dcache.SoftPFReq_hits::cpu.data 390390 # number of SoftPFReq hits 610system.cpu.dcache.SoftPFReq_hits::total 390390 # number of SoftPFReq hits 611system.cpu.dcache.WriteLineReq_hits::cpu.data 335374 # number of WriteLineReq hits 612system.cpu.dcache.WriteLineReq_hits::total 335374 # number of WriteLineReq hits 613system.cpu.dcache.LoadLockedReq_hits::cpu.data 3613361 # number of LoadLockedReq hits 614system.cpu.dcache.LoadLockedReq_hits::total 3613361 # number of LoadLockedReq hits 615system.cpu.dcache.StoreCondReq_hits::cpu.data 3913213 # number of StoreCondReq hits 616system.cpu.dcache.StoreCondReq_hits::total 3913213 # number of StoreCondReq hits 617system.cpu.dcache.demand_hits::cpu.data 298054235 # number of demand (read+write) hits 618system.cpu.dcache.demand_hits::total 298054235 # number of demand (read+write) hits 619system.cpu.dcache.overall_hits::cpu.data 298444625 # number of overall hits 620system.cpu.dcache.overall_hits::total 298444625 # number of overall hits 621system.cpu.dcache.ReadReq_misses::cpu.data 5249224 # number of ReadReq misses 622system.cpu.dcache.ReadReq_misses::total 5249224 # number of ReadReq misses 623system.cpu.dcache.WriteReq_misses::cpu.data 2178798 # number of WriteReq misses 624system.cpu.dcache.WriteReq_misses::total 2178798 # number of WriteReq misses 625system.cpu.dcache.SoftPFReq_misses::cpu.data 1272425 # number of SoftPFReq misses 626system.cpu.dcache.SoftPFReq_misses::total 1272425 # number of SoftPFReq misses 627system.cpu.dcache.WriteLineReq_misses::cpu.data 1229487 # number of WriteLineReq misses 628system.cpu.dcache.WriteLineReq_misses::total 1229487 # number of WriteLineReq misses 629system.cpu.dcache.LoadLockedReq_misses::cpu.data 301533 # number of LoadLockedReq misses 630system.cpu.dcache.LoadLockedReq_misses::total 301533 # number of LoadLockedReq misses 631system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 632system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 633system.cpu.dcache.demand_misses::cpu.data 7428022 # number of demand (read+write) misses 634system.cpu.dcache.demand_misses::total 7428022 # number of demand (read+write) misses 635system.cpu.dcache.overall_misses::cpu.data 8700447 # number of overall misses 636system.cpu.dcache.overall_misses::total 8700447 # number of overall misses 637system.cpu.dcache.ReadReq_miss_latency::cpu.data 82824595500 # number of ReadReq miss cycles 638system.cpu.dcache.ReadReq_miss_latency::total 82824595500 # number of ReadReq miss cycles 639system.cpu.dcache.WriteReq_miss_latency::cpu.data 63552242000 # number of WriteReq miss cycles 640system.cpu.dcache.WriteReq_miss_latency::total 63552242000 # number of WriteReq miss cycles 641system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 50841662000 # number of WriteLineReq miss cycles 642system.cpu.dcache.WriteLineReq_miss_latency::total 50841662000 # number of WriteLineReq miss cycles 643system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4423231500 # number of LoadLockedReq miss cycles 644system.cpu.dcache.LoadLockedReq_miss_latency::total 4423231500 # number of LoadLockedReq miss cycles 645system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles 646system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles 647system.cpu.dcache.demand_miss_latency::cpu.data 146376837500 # number of demand (read+write) miss cycles 648system.cpu.dcache.demand_miss_latency::total 146376837500 # number of demand (read+write) miss cycles 649system.cpu.dcache.overall_miss_latency::cpu.data 146376837500 # number of overall miss cycles 650system.cpu.dcache.overall_miss_latency::total 146376837500 # number of overall miss cycles 651system.cpu.dcache.ReadReq_accesses::cpu.data 160218216 # number of ReadReq accesses(hits+misses) 652system.cpu.dcache.ReadReq_accesses::total 160218216 # number of ReadReq accesses(hits+misses) 653system.cpu.dcache.WriteReq_accesses::cpu.data 145264041 # number of WriteReq accesses(hits+misses) 654system.cpu.dcache.WriteReq_accesses::total 145264041 # number of WriteReq accesses(hits+misses) 655system.cpu.dcache.SoftPFReq_accesses::cpu.data 1662815 # number of SoftPFReq accesses(hits+misses) 656system.cpu.dcache.SoftPFReq_accesses::total 1662815 # number of SoftPFReq accesses(hits+misses) 657system.cpu.dcache.WriteLineReq_accesses::cpu.data 1564861 # number of WriteLineReq accesses(hits+misses) 658system.cpu.dcache.WriteLineReq_accesses::total 1564861 # number of WriteLineReq accesses(hits+misses) 659system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3914894 # number of LoadLockedReq accesses(hits+misses) 660system.cpu.dcache.LoadLockedReq_accesses::total 3914894 # number of LoadLockedReq accesses(hits+misses) 661system.cpu.dcache.StoreCondReq_accesses::cpu.data 3913214 # number of StoreCondReq accesses(hits+misses) 662system.cpu.dcache.StoreCondReq_accesses::total 3913214 # number of StoreCondReq accesses(hits+misses) 663system.cpu.dcache.demand_accesses::cpu.data 305482257 # number of demand (read+write) accesses 664system.cpu.dcache.demand_accesses::total 305482257 # number of demand (read+write) accesses 665system.cpu.dcache.overall_accesses::cpu.data 307145072 # number of overall (read+write) accesses 666system.cpu.dcache.overall_accesses::total 307145072 # number of overall (read+write) accesses 667system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032763 # miss rate for ReadReq accesses 668system.cpu.dcache.ReadReq_miss_rate::total 0.032763 # miss rate for ReadReq accesses 669system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014999 # miss rate for WriteReq accesses 670system.cpu.dcache.WriteReq_miss_rate::total 0.014999 # miss rate for WriteReq accesses 671system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.765223 # miss rate for SoftPFReq accesses 672system.cpu.dcache.SoftPFReq_miss_rate::total 0.765223 # miss rate for SoftPFReq accesses 673system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785684 # miss rate for WriteLineReq accesses 674system.cpu.dcache.WriteLineReq_miss_rate::total 0.785684 # miss rate for WriteLineReq accesses 675system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077022 # miss rate for LoadLockedReq accesses 676system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077022 # miss rate for LoadLockedReq accesses 677system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 678system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 679system.cpu.dcache.demand_miss_rate::cpu.data 0.024316 # miss rate for demand accesses 680system.cpu.dcache.demand_miss_rate::total 0.024316 # miss rate for demand accesses 681system.cpu.dcache.overall_miss_rate::cpu.data 0.028327 # miss rate for overall accesses 682system.cpu.dcache.overall_miss_rate::total 0.028327 # miss rate for overall accesses 683system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15778.445633 # average ReadReq miss latency 684system.cpu.dcache.ReadReq_avg_miss_latency::total 15778.445633 # average ReadReq miss latency 685system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29168.487395 # average WriteReq miss latency 686system.cpu.dcache.WriteReq_avg_miss_latency::total 29168.487395 # average WriteReq miss latency 687system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 41351.931334 # average WriteLineReq miss latency 688system.cpu.dcache.WriteLineReq_avg_miss_latency::total 41351.931334 # average WriteLineReq miss latency 689system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14669.145666 # average LoadLockedReq miss latency 690system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14669.145666 # average LoadLockedReq miss latency 691system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 692system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency 693system.cpu.dcache.demand_avg_miss_latency::cpu.data 19706.031767 # average overall miss latency 694system.cpu.dcache.demand_avg_miss_latency::total 19706.031767 # average overall miss latency 695system.cpu.dcache.overall_avg_miss_latency::cpu.data 16824.059442 # average overall miss latency 696system.cpu.dcache.overall_avg_miss_latency::total 16824.059442 # average overall miss latency 697system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 698system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 699system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 700system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 701system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 702system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 703system.cpu.dcache.fast_writes 0 # number of fast writes performed 704system.cpu.dcache.cache_copies 0 # number of cache copies performed 705system.cpu.dcache.writebacks::writebacks 7760504 # number of writebacks 706system.cpu.dcache.writebacks::total 7760504 # number of writebacks 707system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23609 # number of ReadReq MSHR hits 708system.cpu.dcache.ReadReq_mshr_hits::total 23609 # number of ReadReq MSHR hits 709system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21261 # number of WriteReq MSHR hits 710system.cpu.dcache.WriteReq_mshr_hits::total 21261 # number of WriteReq MSHR hits 711system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 71576 # number of LoadLockedReq MSHR hits 712system.cpu.dcache.LoadLockedReq_mshr_hits::total 71576 # number of LoadLockedReq MSHR hits 713system.cpu.dcache.demand_mshr_hits::cpu.data 44870 # number of demand (read+write) MSHR hits 714system.cpu.dcache.demand_mshr_hits::total 44870 # number of demand (read+write) MSHR hits 715system.cpu.dcache.overall_mshr_hits::cpu.data 44870 # number of overall MSHR hits 716system.cpu.dcache.overall_mshr_hits::total 44870 # number of overall MSHR hits 717system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5225615 # number of ReadReq MSHR misses 718system.cpu.dcache.ReadReq_mshr_misses::total 5225615 # number of ReadReq MSHR misses 719system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2157537 # number of WriteReq MSHR misses 720system.cpu.dcache.WriteReq_mshr_misses::total 2157537 # number of WriteReq MSHR misses 721system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1270654 # number of SoftPFReq MSHR misses 722system.cpu.dcache.SoftPFReq_mshr_misses::total 1270654 # number of SoftPFReq MSHR misses 723system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1229487 # number of WriteLineReq MSHR misses 724system.cpu.dcache.WriteLineReq_mshr_misses::total 1229487 # number of WriteLineReq MSHR misses 725system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 229957 # number of LoadLockedReq MSHR misses 726system.cpu.dcache.LoadLockedReq_mshr_misses::total 229957 # number of LoadLockedReq MSHR misses 727system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 728system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 729system.cpu.dcache.demand_mshr_misses::cpu.data 7383152 # number of demand (read+write) MSHR misses 730system.cpu.dcache.demand_mshr_misses::total 7383152 # number of demand (read+write) MSHR misses 731system.cpu.dcache.overall_mshr_misses::cpu.data 8653806 # number of overall MSHR misses 732system.cpu.dcache.overall_mshr_misses::total 8653806 # number of overall MSHR misses 733system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 734system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable 735system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 736system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 737system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 738system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses 739system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 77028808000 # number of ReadReq MSHR miss cycles 740system.cpu.dcache.ReadReq_mshr_miss_latency::total 77028808000 # number of ReadReq MSHR miss cycles 741system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60744856000 # number of WriteReq MSHR miss cycles 742system.cpu.dcache.WriteReq_mshr_miss_latency::total 60744856000 # number of WriteReq MSHR miss cycles 743system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20507265000 # number of SoftPFReq MSHR miss cycles 744system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20507265000 # number of SoftPFReq MSHR miss cycles 745system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 49612175000 # number of WriteLineReq MSHR miss cycles 746system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 49612175000 # number of WriteLineReq MSHR miss cycles 747system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3074046500 # number of LoadLockedReq MSHR miss cycles 748system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3074046500 # number of LoadLockedReq MSHR miss cycles 749system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles 750system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles 751system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137773664000 # number of demand (read+write) MSHR miss cycles 752system.cpu.dcache.demand_mshr_miss_latency::total 137773664000 # number of demand (read+write) MSHR miss cycles 753system.cpu.dcache.overall_mshr_miss_latency::cpu.data 158280929000 # number of overall MSHR miss cycles 754system.cpu.dcache.overall_mshr_miss_latency::total 158280929000 # number of overall MSHR miss cycles 755system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831352000 # number of ReadReq MSHR uncacheable cycles 756system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831352000 # number of ReadReq MSHR uncacheable cycles 757system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5695270000 # number of WriteReq MSHR uncacheable cycles 758system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5695270000 # number of WriteReq MSHR uncacheable cycles 759system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11526622000 # number of overall MSHR uncacheable cycles 760system.cpu.dcache.overall_mshr_uncacheable_latency::total 11526622000 # number of overall MSHR uncacheable cycles 761system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032616 # mshr miss rate for ReadReq accesses 762system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032616 # mshr miss rate for ReadReq accesses 763system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014853 # mshr miss rate for WriteReq accesses 764system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014853 # mshr miss rate for WriteReq accesses 765system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.764158 # mshr miss rate for SoftPFReq accesses 766system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.764158 # mshr miss rate for SoftPFReq accesses 767system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785684 # mshr miss rate for WriteLineReq accesses 768system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785684 # mshr miss rate for WriteLineReq accesses 769system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058739 # mshr miss rate for LoadLockedReq accesses 770system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058739 # mshr miss rate for LoadLockedReq accesses 771system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 772system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 773system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024169 # mshr miss rate for demand accesses 774system.cpu.dcache.demand_mshr_miss_rate::total 0.024169 # mshr miss rate for demand accesses 775system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028175 # mshr miss rate for overall accesses 776system.cpu.dcache.overall_mshr_miss_rate::total 0.028175 # mshr miss rate for overall accesses 777system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14740.620578 # average ReadReq mshr miss latency 778system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14740.620578 # average ReadReq mshr miss latency 779system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28154.722723 # average WriteReq mshr miss latency 780system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28154.722723 # average WriteReq mshr miss latency 781system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16139.141733 # average SoftPFReq mshr miss latency 782system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16139.141733 # average SoftPFReq mshr miss latency 783system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 40351.931334 # average WriteLineReq mshr miss latency 784system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 40351.931334 # average WriteLineReq mshr miss latency 785system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13367.918785 # average LoadLockedReq mshr miss latency 786system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13367.918785 # average LoadLockedReq mshr miss latency 787system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 788system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency 789system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18660.548232 # average overall mshr miss latency 790system.cpu.dcache.demand_avg_mshr_miss_latency::total 18660.548232 # average overall mshr miss latency 791system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18290.325552 # average overall mshr miss latency 792system.cpu.dcache.overall_avg_mshr_miss_latency::total 18290.325552 # average overall mshr miss latency 793system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173006.349018 # average ReadReq mshr uncacheable latency 794system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173006.349018 # average ReadReq mshr uncacheable latency 795system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 168948.976565 # average WriteReq mshr uncacheable latency 796system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168948.976565 # average WriteReq mshr uncacheable latency 797system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 170977.542423 # average overall mshr uncacheable latency 798system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 170977.542423 # average overall mshr uncacheable latency 799system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 800system.cpu.icache.tags.replacements 13898073 # number of replacements 801system.cpu.icache.tags.tagsinuse 511.854844 # Cycle average of tags in use 802system.cpu.icache.tags.total_refs 869540659 # Total number of references to valid blocks. 803system.cpu.icache.tags.sampled_refs 13898585 # Sample count of references to valid blocks. 804system.cpu.icache.tags.avg_refs 62.563251 # Average number of references to valid blocks. 805system.cpu.icache.tags.warmup_cycle 43284980500 # Cycle when the warmup percentage was hit. 806system.cpu.icache.tags.occ_blocks::cpu.inst 511.854844 # Average occupied blocks per requestor 807system.cpu.icache.tags.occ_percent::cpu.inst 0.999716 # Average percentage of cache occupancy 808system.cpu.icache.tags.occ_percent::total 0.999716 # Average percentage of cache occupancy 809system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 810system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 811system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id 812system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id 813system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id 814system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 815system.cpu.icache.tags.tag_accesses 897337839 # Number of tag accesses 816system.cpu.icache.tags.data_accesses 897337839 # Number of data accesses 817system.cpu.icache.ReadReq_hits::cpu.inst 869540659 # number of ReadReq hits 818system.cpu.icache.ReadReq_hits::total 869540659 # number of ReadReq hits 819system.cpu.icache.demand_hits::cpu.inst 869540659 # number of demand (read+write) hits 820system.cpu.icache.demand_hits::total 869540659 # number of demand (read+write) hits 821system.cpu.icache.overall_hits::cpu.inst 869540659 # number of overall hits 822system.cpu.icache.overall_hits::total 869540659 # number of overall hits 823system.cpu.icache.ReadReq_misses::cpu.inst 13898590 # number of ReadReq misses 824system.cpu.icache.ReadReq_misses::total 13898590 # number of ReadReq misses 825system.cpu.icache.demand_misses::cpu.inst 13898590 # number of demand (read+write) misses 826system.cpu.icache.demand_misses::total 13898590 # number of demand (read+write) misses 827system.cpu.icache.overall_misses::cpu.inst 13898590 # number of overall misses 828system.cpu.icache.overall_misses::total 13898590 # number of overall misses 829system.cpu.icache.ReadReq_miss_latency::cpu.inst 186400133500 # number of ReadReq miss cycles 830system.cpu.icache.ReadReq_miss_latency::total 186400133500 # number of ReadReq miss cycles 831system.cpu.icache.demand_miss_latency::cpu.inst 186400133500 # number of demand (read+write) miss cycles 832system.cpu.icache.demand_miss_latency::total 186400133500 # number of demand (read+write) miss cycles 833system.cpu.icache.overall_miss_latency::cpu.inst 186400133500 # number of overall miss cycles 834system.cpu.icache.overall_miss_latency::total 186400133500 # number of overall miss cycles 835system.cpu.icache.ReadReq_accesses::cpu.inst 883439249 # number of ReadReq accesses(hits+misses) 836system.cpu.icache.ReadReq_accesses::total 883439249 # number of ReadReq accesses(hits+misses) 837system.cpu.icache.demand_accesses::cpu.inst 883439249 # number of demand (read+write) accesses 838system.cpu.icache.demand_accesses::total 883439249 # number of demand (read+write) accesses 839system.cpu.icache.overall_accesses::cpu.inst 883439249 # number of overall (read+write) accesses 840system.cpu.icache.overall_accesses::total 883439249 # number of overall (read+write) accesses 841system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015732 # miss rate for ReadReq accesses 842system.cpu.icache.ReadReq_miss_rate::total 0.015732 # miss rate for ReadReq accesses 843system.cpu.icache.demand_miss_rate::cpu.inst 0.015732 # miss rate for demand accesses 844system.cpu.icache.demand_miss_rate::total 0.015732 # miss rate for demand accesses 845system.cpu.icache.overall_miss_rate::cpu.inst 0.015732 # miss rate for overall accesses 846system.cpu.icache.overall_miss_rate::total 0.015732 # miss rate for overall accesses 847system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13411.441988 # average ReadReq miss latency 848system.cpu.icache.ReadReq_avg_miss_latency::total 13411.441988 # average ReadReq miss latency 849system.cpu.icache.demand_avg_miss_latency::cpu.inst 13411.441988 # average overall miss latency 850system.cpu.icache.demand_avg_miss_latency::total 13411.441988 # average overall miss latency 851system.cpu.icache.overall_avg_miss_latency::cpu.inst 13411.441988 # average overall miss latency 852system.cpu.icache.overall_avg_miss_latency::total 13411.441988 # average overall miss latency 853system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 854system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 855system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 856system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 857system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 858system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 859system.cpu.icache.fast_writes 0 # number of fast writes performed 860system.cpu.icache.cache_copies 0 # number of cache copies performed 861system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13898590 # number of ReadReq MSHR misses 862system.cpu.icache.ReadReq_mshr_misses::total 13898590 # number of ReadReq MSHR misses 863system.cpu.icache.demand_mshr_misses::cpu.inst 13898590 # number of demand (read+write) MSHR misses 864system.cpu.icache.demand_mshr_misses::total 13898590 # number of demand (read+write) MSHR misses 865system.cpu.icache.overall_mshr_misses::cpu.inst 13898590 # number of overall MSHR misses 866system.cpu.icache.overall_mshr_misses::total 13898590 # number of overall MSHR misses 867system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 868system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 869system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 870system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 871system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 172501543500 # number of ReadReq MSHR miss cycles 872system.cpu.icache.ReadReq_mshr_miss_latency::total 172501543500 # number of ReadReq MSHR miss cycles 873system.cpu.icache.demand_mshr_miss_latency::cpu.inst 172501543500 # number of demand (read+write) MSHR miss cycles 874system.cpu.icache.demand_mshr_miss_latency::total 172501543500 # number of demand (read+write) MSHR miss cycles 875system.cpu.icache.overall_mshr_miss_latency::cpu.inst 172501543500 # number of overall MSHR miss cycles 876system.cpu.icache.overall_mshr_miss_latency::total 172501543500 # number of overall MSHR miss cycles 877system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3229158000 # number of ReadReq MSHR uncacheable cycles 878system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3229158000 # number of ReadReq MSHR uncacheable cycles 879system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3229158000 # number of overall MSHR uncacheable cycles 880system.cpu.icache.overall_mshr_uncacheable_latency::total 3229158000 # number of overall MSHR uncacheable cycles 881system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015732 # mshr miss rate for ReadReq accesses 882system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015732 # mshr miss rate for ReadReq accesses 883system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015732 # mshr miss rate for demand accesses 884system.cpu.icache.demand_mshr_miss_rate::total 0.015732 # mshr miss rate for demand accesses 885system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015732 # mshr miss rate for overall accesses 886system.cpu.icache.overall_mshr_miss_rate::total 0.015732 # mshr miss rate for overall accesses 887system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12411.441988 # average ReadReq mshr miss latency 888system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12411.441988 # average ReadReq mshr miss latency 889system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12411.441988 # average overall mshr miss latency 890system.cpu.icache.demand_avg_mshr_miss_latency::total 12411.441988 # average overall mshr miss latency 891system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12411.441988 # average overall mshr miss latency 892system.cpu.icache.overall_avg_mshr_miss_latency::total 12411.441988 # average overall mshr miss latency 893system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74879.026087 # average ReadReq mshr uncacheable latency 894system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74879.026087 # average ReadReq mshr uncacheable latency 895system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74879.026087 # average overall mshr uncacheable latency 896system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74879.026087 # average overall mshr uncacheable latency 897system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 898system.cpu.l2cache.tags.replacements 1262077 # number of replacements 899system.cpu.l2cache.tags.tagsinuse 65231.896667 # Cycle average of tags in use 900system.cpu.l2cache.tags.total_refs 43818011 # Total number of references to valid blocks. 901system.cpu.l2cache.tags.sampled_refs 1325564 # Sample count of references to valid blocks. 902system.cpu.l2cache.tags.avg_refs 33.056126 # Average number of references to valid blocks. 903system.cpu.l2cache.tags.warmup_cycle 38337641500 # Cycle when the warmup percentage was hit. 904system.cpu.l2cache.tags.occ_blocks::writebacks 38267.922304 # Average occupied blocks per requestor 905system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 322.380584 # Average occupied blocks per requestor 906system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 465.537699 # Average occupied blocks per requestor 907system.cpu.l2cache.tags.occ_blocks::cpu.inst 6521.520612 # Average occupied blocks per requestor 908system.cpu.l2cache.tags.occ_blocks::cpu.data 19654.535467 # Average occupied blocks per requestor 909system.cpu.l2cache.tags.occ_percent::writebacks 0.583922 # Average percentage of cache occupancy 910system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004919 # Average percentage of cache occupancy 911system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007104 # Average percentage of cache occupancy 912system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099511 # Average percentage of cache occupancy 913system.cpu.l2cache.tags.occ_percent::cpu.data 0.299904 # Average percentage of cache occupancy 914system.cpu.l2cache.tags.occ_percent::total 0.995360 # Average percentage of cache occupancy 915system.cpu.l2cache.tags.occ_task_id_blocks::1023 334 # Occupied blocks per task id 916system.cpu.l2cache.tags.occ_task_id_blocks::1024 63153 # Occupied blocks per task id 917system.cpu.l2cache.tags.age_task_id_blocks_1023::4 334 # Occupied blocks per task id 918system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 919system.cpu.l2cache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id 920system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2433 # Occupied blocks per task id 921system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5488 # Occupied blocks per task id 922system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54788 # Occupied blocks per task id 923system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005096 # Percentage of cache occupancy per task id 924system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963638 # Percentage of cache occupancy per task id 925system.cpu.l2cache.tags.tag_accesses 393503422 # Number of tag accesses 926system.cpu.l2cache.tags.data_accesses 393503422 # Number of data accesses 927system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 363149 # number of ReadReq hits 928system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250594 # number of ReadReq hits 929system.cpu.l2cache.ReadReq_hits::total 613743 # number of ReadReq hits 930system.cpu.l2cache.Writeback_hits::writebacks 7760504 # number of Writeback hits 931system.cpu.l2cache.Writeback_hits::total 7760504 # number of Writeback hits 932system.cpu.l2cache.UpgradeReq_hits::cpu.data 9779 # number of UpgradeReq hits 933system.cpu.l2cache.UpgradeReq_hits::total 9779 # number of UpgradeReq hits 934system.cpu.l2cache.ReadExReq_hits::cpu.data 1625617 # number of ReadExReq hits 935system.cpu.l2cache.ReadExReq_hits::total 1625617 # number of ReadExReq hits 936system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13818912 # number of ReadCleanReq hits 937system.cpu.l2cache.ReadCleanReq_hits::total 13818912 # number of ReadCleanReq hits 938system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6453062 # number of ReadSharedReq hits 939system.cpu.l2cache.ReadSharedReq_hits::total 6453062 # number of ReadSharedReq hits 940system.cpu.l2cache.InvalidateReq_hits::cpu.data 721925 # number of InvalidateReq hits 941system.cpu.l2cache.InvalidateReq_hits::total 721925 # number of InvalidateReq hits 942system.cpu.l2cache.demand_hits::cpu.dtb.walker 363149 # number of demand (read+write) hits 943system.cpu.l2cache.demand_hits::cpu.itb.walker 250594 # number of demand (read+write) hits 944system.cpu.l2cache.demand_hits::cpu.inst 13818912 # number of demand (read+write) hits 945system.cpu.l2cache.demand_hits::cpu.data 8078679 # number of demand (read+write) hits 946system.cpu.l2cache.demand_hits::total 22511334 # number of demand (read+write) hits 947system.cpu.l2cache.overall_hits::cpu.dtb.walker 363149 # number of overall hits 948system.cpu.l2cache.overall_hits::cpu.itb.walker 250594 # number of overall hits 949system.cpu.l2cache.overall_hits::cpu.inst 13818912 # number of overall hits 950system.cpu.l2cache.overall_hits::cpu.data 8078679 # number of overall hits 951system.cpu.l2cache.overall_hits::total 22511334 # number of overall hits 952system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3987 # number of ReadReq misses 953system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3909 # number of ReadReq misses 954system.cpu.l2cache.ReadReq_misses::total 7896 # number of ReadReq misses 955system.cpu.l2cache.UpgradeReq_misses::cpu.data 35285 # number of UpgradeReq misses 956system.cpu.l2cache.UpgradeReq_misses::total 35285 # number of UpgradeReq misses 957system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 958system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 959system.cpu.l2cache.ReadExReq_misses::cpu.data 486856 # number of ReadExReq misses 960system.cpu.l2cache.ReadExReq_misses::total 486856 # number of ReadExReq misses 961system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 79678 # number of ReadCleanReq misses 962system.cpu.l2cache.ReadCleanReq_misses::total 79678 # number of ReadCleanReq misses 963system.cpu.l2cache.ReadSharedReq_misses::cpu.data 273164 # number of ReadSharedReq misses 964system.cpu.l2cache.ReadSharedReq_misses::total 273164 # number of ReadSharedReq misses 965system.cpu.l2cache.InvalidateReq_misses::cpu.data 507562 # number of InvalidateReq misses 966system.cpu.l2cache.InvalidateReq_misses::total 507562 # number of InvalidateReq misses 967system.cpu.l2cache.demand_misses::cpu.dtb.walker 3987 # number of demand (read+write) misses 968system.cpu.l2cache.demand_misses::cpu.itb.walker 3909 # number of demand (read+write) misses 969system.cpu.l2cache.demand_misses::cpu.inst 79678 # number of demand (read+write) misses 970system.cpu.l2cache.demand_misses::cpu.data 760020 # number of demand (read+write) misses 971system.cpu.l2cache.demand_misses::total 847594 # number of demand (read+write) misses 972system.cpu.l2cache.overall_misses::cpu.dtb.walker 3987 # number of overall misses 973system.cpu.l2cache.overall_misses::cpu.itb.walker 3909 # number of overall misses 974system.cpu.l2cache.overall_misses::cpu.inst 79678 # number of overall misses 975system.cpu.l2cache.overall_misses::cpu.data 760020 # number of overall misses 976system.cpu.l2cache.overall_misses::total 847594 # number of overall misses 977system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 341850000 # number of ReadReq miss cycles 978system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 340742500 # number of ReadReq miss cycles 979system.cpu.l2cache.ReadReq_miss_latency::total 682592500 # number of ReadReq miss cycles 980system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 544841000 # number of UpgradeReq miss cycles 981system.cpu.l2cache.UpgradeReq_miss_latency::total 544841000 # number of UpgradeReq miss cycles 982system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles 983system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles 984system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 39254870000 # number of ReadExReq miss cycles 985system.cpu.l2cache.ReadExReq_miss_latency::total 39254870000 # number of ReadExReq miss cycles 986system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 6511661500 # number of ReadCleanReq miss cycles 987system.cpu.l2cache.ReadCleanReq_miss_latency::total 6511661500 # number of ReadCleanReq miss cycles 988system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22761554500 # number of ReadSharedReq miss cycles 989system.cpu.l2cache.ReadSharedReq_miss_latency::total 22761554500 # number of ReadSharedReq miss cycles 990system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 40187730500 # number of InvalidateReq miss cycles 991system.cpu.l2cache.InvalidateReq_miss_latency::total 40187730500 # number of InvalidateReq miss cycles 992system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 341850000 # number of demand (read+write) miss cycles 993system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 340742500 # number of demand (read+write) miss cycles 994system.cpu.l2cache.demand_miss_latency::cpu.inst 6511661500 # number of demand (read+write) miss cycles 995system.cpu.l2cache.demand_miss_latency::cpu.data 62016424500 # number of demand (read+write) miss cycles 996system.cpu.l2cache.demand_miss_latency::total 69210678500 # number of demand (read+write) miss cycles 997system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 341850000 # number of overall miss cycles 998system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 340742500 # number of overall miss cycles 999system.cpu.l2cache.overall_miss_latency::cpu.inst 6511661500 # number of overall miss cycles 1000system.cpu.l2cache.overall_miss_latency::cpu.data 62016424500 # number of overall miss cycles 1001system.cpu.l2cache.overall_miss_latency::total 69210678500 # number of overall miss cycles 1002system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 367136 # number of ReadReq accesses(hits+misses) 1003system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 254503 # number of ReadReq accesses(hits+misses) 1004system.cpu.l2cache.ReadReq_accesses::total 621639 # number of ReadReq accesses(hits+misses) 1005system.cpu.l2cache.Writeback_accesses::writebacks 7760504 # number of Writeback accesses(hits+misses) 1006system.cpu.l2cache.Writeback_accesses::total 7760504 # number of Writeback accesses(hits+misses) 1007system.cpu.l2cache.UpgradeReq_accesses::cpu.data 45064 # number of UpgradeReq accesses(hits+misses) 1008system.cpu.l2cache.UpgradeReq_accesses::total 45064 # number of UpgradeReq accesses(hits+misses) 1009system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 1010system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 1011system.cpu.l2cache.ReadExReq_accesses::cpu.data 2112473 # number of ReadExReq accesses(hits+misses) 1012system.cpu.l2cache.ReadExReq_accesses::total 2112473 # number of ReadExReq accesses(hits+misses) 1013system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13898590 # number of ReadCleanReq accesses(hits+misses) 1014system.cpu.l2cache.ReadCleanReq_accesses::total 13898590 # number of ReadCleanReq accesses(hits+misses) 1015system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6726226 # number of ReadSharedReq accesses(hits+misses) 1016system.cpu.l2cache.ReadSharedReq_accesses::total 6726226 # number of ReadSharedReq accesses(hits+misses) 1017system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1229487 # number of InvalidateReq accesses(hits+misses) 1018system.cpu.l2cache.InvalidateReq_accesses::total 1229487 # number of InvalidateReq accesses(hits+misses) 1019system.cpu.l2cache.demand_accesses::cpu.dtb.walker 367136 # number of demand (read+write) accesses 1020system.cpu.l2cache.demand_accesses::cpu.itb.walker 254503 # number of demand (read+write) accesses 1021system.cpu.l2cache.demand_accesses::cpu.inst 13898590 # number of demand (read+write) accesses 1022system.cpu.l2cache.demand_accesses::cpu.data 8838699 # number of demand (read+write) accesses 1023system.cpu.l2cache.demand_accesses::total 23358928 # number of demand (read+write) accesses 1024system.cpu.l2cache.overall_accesses::cpu.dtb.walker 367136 # number of overall (read+write) accesses 1025system.cpu.l2cache.overall_accesses::cpu.itb.walker 254503 # number of overall (read+write) accesses 1026system.cpu.l2cache.overall_accesses::cpu.inst 13898590 # number of overall (read+write) accesses 1027system.cpu.l2cache.overall_accesses::cpu.data 8838699 # number of overall (read+write) accesses 1028system.cpu.l2cache.overall_accesses::total 23358928 # number of overall (read+write) accesses 1029system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.010860 # miss rate for ReadReq accesses 1030system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.015359 # miss rate for ReadReq accesses 1031system.cpu.l2cache.ReadReq_miss_rate::total 0.012702 # miss rate for ReadReq accesses 1032system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782998 # miss rate for UpgradeReq accesses 1033system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782998 # miss rate for UpgradeReq accesses 1034system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1035system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1036system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.230467 # miss rate for ReadExReq accesses 1037system.cpu.l2cache.ReadExReq_miss_rate::total 0.230467 # miss rate for ReadExReq accesses 1038system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005733 # miss rate for ReadCleanReq accesses 1039system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005733 # miss rate for ReadCleanReq accesses 1040system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.040612 # miss rate for ReadSharedReq accesses 1041system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.040612 # miss rate for ReadSharedReq accesses 1042system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.412824 # miss rate for InvalidateReq accesses 1043system.cpu.l2cache.InvalidateReq_miss_rate::total 0.412824 # miss rate for InvalidateReq accesses 1044system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.010860 # miss rate for demand accesses 1045system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.015359 # miss rate for demand accesses 1046system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005733 # miss rate for demand accesses 1047system.cpu.l2cache.demand_miss_rate::cpu.data 0.085988 # miss rate for demand accesses 1048system.cpu.l2cache.demand_miss_rate::total 0.036286 # miss rate for demand accesses 1049system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.010860 # miss rate for overall accesses 1050system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.015359 # miss rate for overall accesses 1051system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005733 # miss rate for overall accesses 1052system.cpu.l2cache.overall_miss_rate::cpu.data 0.085988 # miss rate for overall accesses 1053system.cpu.l2cache.overall_miss_rate::total 0.036286 # miss rate for overall accesses 1054system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85741.158766 # average ReadReq miss latency 1055system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87168.713226 # average ReadReq miss latency 1056system.cpu.l2cache.ReadReq_avg_miss_latency::total 86447.885005 # average ReadReq miss latency 1057system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15441.150631 # average UpgradeReq miss latency 1058system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15441.150631 # average UpgradeReq miss latency 1059system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 1060system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 1061system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80629.323660 # average ReadExReq miss latency 1062system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80629.323660 # average ReadExReq miss latency 1063system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81724.710711 # average ReadCleanReq miss latency 1064system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81724.710711 # average ReadCleanReq miss latency 1065system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83325.601104 # average ReadSharedReq miss latency 1066system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83325.601104 # average ReadSharedReq miss latency 1067system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 79177.973331 # average InvalidateReq miss latency 1068system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 79177.973331 # average InvalidateReq miss latency 1069system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85741.158766 # average overall miss latency 1070system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87168.713226 # average overall miss latency 1071system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81724.710711 # average overall miss latency 1072system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81598.411226 # average overall miss latency 1073system.cpu.l2cache.demand_avg_miss_latency::total 81655.460633 # average overall miss latency 1074system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85741.158766 # average overall miss latency 1075system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87168.713226 # average overall miss latency 1076system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81724.710711 # average overall miss latency 1077system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81598.411226 # average overall miss latency 1078system.cpu.l2cache.overall_avg_miss_latency::total 81655.460633 # average overall miss latency 1079system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1080system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1081system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1082system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1083system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1084system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1085system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1086system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1087system.cpu.l2cache.writebacks::writebacks 1077959 # number of writebacks 1088system.cpu.l2cache.writebacks::total 1077959 # number of writebacks 1089system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3987 # number of ReadReq MSHR misses 1090system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3909 # number of ReadReq MSHR misses 1091system.cpu.l2cache.ReadReq_mshr_misses::total 7896 # number of ReadReq MSHR misses 1092system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1116 # number of CleanEvict MSHR misses 1093system.cpu.l2cache.CleanEvict_mshr_misses::total 1116 # number of CleanEvict MSHR misses 1094system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35285 # number of UpgradeReq MSHR misses 1095system.cpu.l2cache.UpgradeReq_mshr_misses::total 35285 # number of UpgradeReq MSHR misses 1096system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1097system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1098system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 486856 # number of ReadExReq MSHR misses 1099system.cpu.l2cache.ReadExReq_mshr_misses::total 486856 # number of ReadExReq MSHR misses 1100system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 79678 # number of ReadCleanReq MSHR misses 1101system.cpu.l2cache.ReadCleanReq_mshr_misses::total 79678 # number of ReadCleanReq MSHR misses 1102system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273164 # number of ReadSharedReq MSHR misses 1103system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273164 # number of ReadSharedReq MSHR misses 1104system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 507562 # number of InvalidateReq MSHR misses 1105system.cpu.l2cache.InvalidateReq_mshr_misses::total 507562 # number of InvalidateReq MSHR misses 1106system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3987 # number of demand (read+write) MSHR misses 1107system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3909 # number of demand (read+write) MSHR misses 1108system.cpu.l2cache.demand_mshr_misses::cpu.inst 79678 # number of demand (read+write) MSHR misses 1109system.cpu.l2cache.demand_mshr_misses::cpu.data 760020 # number of demand (read+write) MSHR misses 1110system.cpu.l2cache.demand_mshr_misses::total 847594 # number of demand (read+write) MSHR misses 1111system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3987 # number of overall MSHR misses 1112system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3909 # number of overall MSHR misses 1113system.cpu.l2cache.overall_mshr_misses::cpu.inst 79678 # number of overall MSHR misses 1114system.cpu.l2cache.overall_mshr_misses::cpu.data 760020 # number of overall MSHR misses 1115system.cpu.l2cache.overall_mshr_misses::total 847594 # number of overall MSHR misses 1116system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 1117system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 1118system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable 1119system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 1120system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 1121system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 1122system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 1123system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses 1124system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 301980000 # number of ReadReq MSHR miss cycles 1125system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 301652500 # number of ReadReq MSHR miss cycles 1126system.cpu.l2cache.ReadReq_mshr_miss_latency::total 603632500 # number of ReadReq MSHR miss cycles 1127system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 728816500 # number of UpgradeReq MSHR miss cycles 1128system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 728816500 # number of UpgradeReq MSHR miss cycles 1129system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles 1130system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles 1131system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34386310000 # number of ReadExReq MSHR miss cycles 1132system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34386310000 # number of ReadExReq MSHR miss cycles 1133system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 5714881500 # number of ReadCleanReq MSHR miss cycles 1134system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 5714881500 # number of ReadCleanReq MSHR miss cycles 1135system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20029914500 # number of ReadSharedReq MSHR miss cycles 1136system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20029914500 # number of ReadSharedReq MSHR miss cycles 1137system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 35112110500 # number of InvalidateReq MSHR miss cycles 1138system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 35112110500 # number of InvalidateReq MSHR miss cycles 1139system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 301980000 # number of demand (read+write) MSHR miss cycles 1140system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 301652500 # number of demand (read+write) MSHR miss cycles 1141system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5714881500 # number of demand (read+write) MSHR miss cycles 1142system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54416224500 # number of demand (read+write) MSHR miss cycles 1143system.cpu.l2cache.demand_mshr_miss_latency::total 60734738500 # number of demand (read+write) MSHR miss cycles 1144system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 301980000 # number of overall MSHR miss cycles 1145system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301652500 # number of overall MSHR miss cycles 1146system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5714881500 # number of overall MSHR miss cycles 1147system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54416224500 # number of overall MSHR miss cycles 1148system.cpu.l2cache.overall_mshr_miss_latency::total 60734738500 # number of overall MSHR miss cycles 1149system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2690095500 # number of ReadReq MSHR uncacheable cycles 1150system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5410027000 # number of ReadReq MSHR uncacheable cycles 1151system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8100122500 # number of ReadReq MSHR uncacheable cycles 1152system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5307605000 # number of WriteReq MSHR uncacheable cycles 1153system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5307605000 # number of WriteReq MSHR uncacheable cycles 1154system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2690095500 # number of overall MSHR uncacheable cycles 1155system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10717632000 # number of overall MSHR uncacheable cycles 1156system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13407727500 # number of overall MSHR uncacheable cycles 1157system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010860 # mshr miss rate for ReadReq accesses 1158system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015359 # mshr miss rate for ReadReq accesses 1159system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012702 # mshr miss rate for ReadReq accesses 1160system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1161system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1162system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782998 # mshr miss rate for UpgradeReq accesses 1163system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782998 # mshr miss rate for UpgradeReq accesses 1164system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1165system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1166system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.230467 # mshr miss rate for ReadExReq accesses 1167system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.230467 # mshr miss rate for ReadExReq accesses 1168system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005733 # mshr miss rate for ReadCleanReq accesses 1169system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005733 # mshr miss rate for ReadCleanReq accesses 1170system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.040612 # mshr miss rate for ReadSharedReq accesses 1171system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.040612 # mshr miss rate for ReadSharedReq accesses 1172system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.412824 # mshr miss rate for InvalidateReq accesses 1173system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.412824 # mshr miss rate for InvalidateReq accesses 1174system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010860 # mshr miss rate for demand accesses 1175system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015359 # mshr miss rate for demand accesses 1176system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005733 # mshr miss rate for demand accesses 1177system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.085988 # mshr miss rate for demand accesses 1178system.cpu.l2cache.demand_mshr_miss_rate::total 0.036286 # mshr miss rate for demand accesses 1179system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010860 # mshr miss rate for overall accesses 1180system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015359 # mshr miss rate for overall accesses 1181system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005733 # mshr miss rate for overall accesses 1182system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.085988 # mshr miss rate for overall accesses 1183system.cpu.l2cache.overall_mshr_miss_rate::total 0.036286 # mshr miss rate for overall accesses 1184system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766 # average ReadReq mshr miss latency 1185system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 77168.713226 # average ReadReq mshr miss latency 1186system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76447.885005 # average ReadReq mshr miss latency 1187system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20655.136744 # average UpgradeReq mshr miss latency 1188system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20655.136744 # average UpgradeReq mshr miss latency 1189system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1190system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency 1191system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70629.323660 # average ReadExReq mshr miss latency 1192system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70629.323660 # average ReadExReq mshr miss latency 1193system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71724.710711 # average ReadCleanReq mshr miss latency 1194system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71724.710711 # average ReadCleanReq mshr miss latency 1195system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73325.601104 # average ReadSharedReq mshr miss latency 1196system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73325.601104 # average ReadSharedReq mshr miss latency 1197system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69177.973331 # average InvalidateReq mshr miss latency 1198system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69177.973331 # average InvalidateReq mshr miss latency 1199system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766 # average overall mshr miss latency 1200system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 77168.713226 # average overall mshr miss latency 1201system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71724.710711 # average overall mshr miss latency 1202system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71598.411226 # average overall mshr miss latency 1203system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71655.460633 # average overall mshr miss latency 1204system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.158766 # average overall mshr miss latency 1205system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 77168.713226 # average overall mshr miss latency 1206system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71724.710711 # average overall mshr miss latency 1207system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71598.411226 # average overall mshr miss latency 1208system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71655.460633 # average overall mshr miss latency 1209system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62379.026087 # average ReadReq mshr uncacheable latency 1210system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160506.349018 # average ReadReq mshr uncacheable latency 1211system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105427.789564 # average ReadReq mshr uncacheable latency 1212system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 157448.976565 # average WriteReq mshr uncacheable latency 1213system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157448.976565 # average WriteReq mshr uncacheable latency 1214system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62379.026087 # average overall mshr uncacheable latency 1215system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 158977.572090 # average overall mshr uncacheable latency 1216system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 121291.896220 # average overall mshr uncacheable latency 1217system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1218system.cpu.toL2Bus.trans_dist::ReadReq 1048560 # Transaction distribution 1219system.cpu.toL2Bus.trans_dist::ReadResp 21674258 # Transaction distribution 1220system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution 1221system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution 1222system.cpu.toL2Bus.trans_dist::Writeback 8945109 # Transaction distribution 1223system.cpu.toL2Bus.trans_dist::CleanEvict 16396444 # Transaction distribution 1224system.cpu.toL2Bus.trans_dist::UpgradeReq 45067 # Transaction distribution 1225system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1226system.cpu.toL2Bus.trans_dist::UpgradeResp 45068 # Transaction distribution 1227system.cpu.toL2Bus.trans_dist::ReadExReq 2112473 # Transaction distribution 1228system.cpu.toL2Bus.trans_dist::ReadExResp 2112473 # Transaction distribution 1229system.cpu.toL2Bus.trans_dist::ReadCleanReq 13898590 # Transaction distribution 1230system.cpu.toL2Bus.trans_dist::ReadSharedReq 6735107 # Transaction distribution 1231system.cpu.toL2Bus.trans_dist::InvalidateReq 1336151 # Transaction distribution 1232system.cpu.toL2Bus.trans_dist::InvalidateResp 1229487 # Transaction distribution 1233system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41779933 # Packet count per connected master and slave (bytes) 1234system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30429687 # Packet count per connected master and slave (bytes) 1235system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 620392 # Packet count per connected master and slave (bytes) 1236system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 972976 # Packet count per connected master and slave (bytes) 1237system.cpu.toL2Bus.pkt_count::total 73802988 # Packet count per connected master and slave (bytes) 1238system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 889682260 # Cumulative packet size per connected master and slave (bytes) 1239system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1062595910 # Cumulative packet size per connected master and slave (bytes) 1240system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2036024 # Cumulative packet size per connected master and slave (bytes) 1241system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2937088 # Cumulative packet size per connected master and slave (bytes) 1242system.cpu.toL2Bus.pkt_size::total 1957251282 # Cumulative packet size per connected master and slave (bytes) 1243system.cpu.toL2Bus.snoops 1844105 # Total snoops (count) 1244system.cpu.toL2Bus.snoop_fanout::samples 50552964 # Request fanout histogram 1245system.cpu.toL2Bus.snoop_fanout::mean 1.048758 # Request fanout histogram 1246system.cpu.toL2Bus.snoop_fanout::stdev 0.215362 # Request fanout histogram 1247system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1248system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1249system.cpu.toL2Bus.snoop_fanout::1 48088105 95.12% 95.12% # Request fanout histogram 1250system.cpu.toL2Bus.snoop_fanout::2 2464859 4.88% 100.00% # Request fanout histogram 1251system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1252system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1253system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1254system.cpu.toL2Bus.snoop_fanout::total 50552964 # Request fanout histogram 1255system.cpu.toL2Bus.reqLayer0.occupancy 32307276000 # Layer occupancy (ticks) 1256system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1257system.cpu.toL2Bus.snoopLayer0.occupancy 1324500 # Layer occupancy (ticks) 1258system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1259system.cpu.toL2Bus.respLayer0.occupancy 20891010000 # Layer occupancy (ticks) 1260system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1261system.cpu.toL2Bus.respLayer1.occupancy 13945928913 # Layer occupancy (ticks) 1262system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1263system.cpu.toL2Bus.respLayer2.occupancy 365889000 # Layer occupancy (ticks) 1264system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1265system.cpu.toL2Bus.respLayer3.occupancy 605840000 # Layer occupancy (ticks) 1266system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1267system.iobus.trans_dist::ReadReq 40329 # Transaction distribution 1268system.iobus.trans_dist::ReadResp 40329 # Transaction distribution 1269system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1270system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1271system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1272system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1273system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1274system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1275system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1276system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1277system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1278system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1279system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1280system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1281system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1282system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1283system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1284system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1285system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1286system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1287system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231016 # Packet count per connected master and slave (bytes) 1288system.iobus.pkt_count_system.realview.ide.dma::total 231016 # Packet count per connected master and slave (bytes) 1289system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1290system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1291system.iobus.pkt_count::total 353800 # Packet count per connected master and slave (bytes) 1292system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1293system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1294system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1295system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1296system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1297system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1298system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1299system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1300system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1301system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1302system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1303system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 1304system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1305system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 1306system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1307system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1308system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334496 # Cumulative packet size per connected master and slave (bytes) 1309system.iobus.pkt_size_system.realview.ide.dma::total 7334496 # Cumulative packet size per connected master and slave (bytes) 1310system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1311system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1312system.iobus.pkt_size::total 7492416 # Cumulative packet size per connected master and slave (bytes) 1313system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) 1314system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1315system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1316system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1317system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 1318system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1319system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 1320system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1321system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1322system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1323system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1324system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1325system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1326system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1327system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1328system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1329system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 1330system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1331system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1332system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1333system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 1334system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1335system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 1336system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1337system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 1338system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1339system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 1340system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1341system.iobus.reqLayer27.occupancy 568778648 # Layer occupancy (ticks) 1342system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1343system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1344system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1345system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1346system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1347system.iobus.respLayer3.occupancy 147776000 # Layer occupancy (ticks) 1348system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1349system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1350system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1351system.iocache.tags.replacements 115490 # number of replacements 1352system.iocache.tags.tagsinuse 10.455215 # Cycle average of tags in use 1353system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1354system.iocache.tags.sampled_refs 115506 # Sample count of references to valid blocks. 1355system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1356system.iocache.tags.warmup_cycle 13165278431000 # Cycle when the warmup percentage was hit. 1357system.iocache.tags.occ_blocks::realview.ethernet 3.510021 # Average occupied blocks per requestor 1358system.iocache.tags.occ_blocks::realview.ide 6.945193 # Average occupied blocks per requestor 1359system.iocache.tags.occ_percent::realview.ethernet 0.219376 # Average percentage of cache occupancy 1360system.iocache.tags.occ_percent::realview.ide 0.434075 # Average percentage of cache occupancy 1361system.iocache.tags.occ_percent::total 0.653451 # Average percentage of cache occupancy 1362system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1363system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1364system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1365system.iocache.tags.tag_accesses 1039929 # Number of tag accesses 1366system.iocache.tags.data_accesses 1039929 # Number of data accesses 1367system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1368system.iocache.ReadReq_misses::realview.ide 8844 # number of ReadReq misses 1369system.iocache.ReadReq_misses::total 8881 # number of ReadReq misses 1370system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1371system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1372system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1373system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1374system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1375system.iocache.demand_misses::realview.ide 8844 # number of demand (read+write) misses 1376system.iocache.demand_misses::total 8884 # number of demand (read+write) misses 1377system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1378system.iocache.overall_misses::realview.ide 8844 # number of overall misses 1379system.iocache.overall_misses::total 8884 # number of overall misses 1380system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles 1381system.iocache.ReadReq_miss_latency::realview.ide 1566099238 # number of ReadReq miss cycles 1382system.iocache.ReadReq_miss_latency::total 1571168238 # number of ReadReq miss cycles 1383system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1384system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1385system.iocache.WriteLineReq_miss_latency::realview.ide 12612607410 # number of WriteLineReq miss cycles 1386system.iocache.WriteLineReq_miss_latency::total 12612607410 # number of WriteLineReq miss cycles 1387system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles 1388system.iocache.demand_miss_latency::realview.ide 1566099238 # number of demand (read+write) miss cycles 1389system.iocache.demand_miss_latency::total 1571519238 # number of demand (read+write) miss cycles 1390system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles 1391system.iocache.overall_miss_latency::realview.ide 1566099238 # number of overall miss cycles 1392system.iocache.overall_miss_latency::total 1571519238 # number of overall miss cycles 1393system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1394system.iocache.ReadReq_accesses::realview.ide 8844 # number of ReadReq accesses(hits+misses) 1395system.iocache.ReadReq_accesses::total 8881 # number of ReadReq accesses(hits+misses) 1396system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1397system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1398system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1399system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1400system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1401system.iocache.demand_accesses::realview.ide 8844 # number of demand (read+write) accesses 1402system.iocache.demand_accesses::total 8884 # number of demand (read+write) accesses 1403system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1404system.iocache.overall_accesses::realview.ide 8844 # number of overall (read+write) accesses 1405system.iocache.overall_accesses::total 8884 # number of overall (read+write) accesses 1406system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1407system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1408system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1409system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1410system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1411system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1412system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1413system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1414system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1415system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1416system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1417system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1418system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1419system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency 1420system.iocache.ReadReq_avg_miss_latency::realview.ide 177080.420398 # average ReadReq miss latency 1421system.iocache.ReadReq_avg_miss_latency::total 176913.437451 # average ReadReq miss latency 1422system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1423system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1424system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118246.150623 # average WriteLineReq miss latency 1425system.iocache.WriteLineReq_avg_miss_latency::total 118246.150623 # average WriteLineReq miss latency 1426system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency 1427system.iocache.demand_avg_miss_latency::realview.ide 177080.420398 # average overall miss latency 1428system.iocache.demand_avg_miss_latency::total 176893.205538 # average overall miss latency 1429system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency 1430system.iocache.overall_avg_miss_latency::realview.ide 177080.420398 # average overall miss latency 1431system.iocache.overall_avg_miss_latency::total 176893.205538 # average overall miss latency 1432system.iocache.blocked_cycles::no_mshrs 29516 # number of cycles access was blocked 1433system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1434system.iocache.blocked::no_mshrs 3281 # number of cycles access was blocked 1435system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1436system.iocache.avg_blocked_cycles::no_mshrs 8.996038 # average number of cycles each access was blocked 1437system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1438system.iocache.fast_writes 0 # number of fast writes performed 1439system.iocache.cache_copies 0 # number of cache copies performed 1440system.iocache.writebacks::writebacks 106631 # number of writebacks 1441system.iocache.writebacks::total 106631 # number of writebacks 1442system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1443system.iocache.ReadReq_mshr_misses::realview.ide 8844 # number of ReadReq MSHR misses 1444system.iocache.ReadReq_mshr_misses::total 8881 # number of ReadReq MSHR misses 1445system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1446system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1447system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1448system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1449system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1450system.iocache.demand_mshr_misses::realview.ide 8844 # number of demand (read+write) MSHR misses 1451system.iocache.demand_mshr_misses::total 8884 # number of demand (read+write) MSHR misses 1452system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1453system.iocache.overall_mshr_misses::realview.ide 8844 # number of overall MSHR misses 1454system.iocache.overall_mshr_misses::total 8884 # number of overall MSHR misses 1455system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles 1456system.iocache.ReadReq_mshr_miss_latency::realview.ide 1123899238 # number of ReadReq MSHR miss cycles 1457system.iocache.ReadReq_mshr_miss_latency::total 1127118238 # number of ReadReq MSHR miss cycles 1458system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1459system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1460system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7279407410 # number of WriteLineReq MSHR miss cycles 1461system.iocache.WriteLineReq_mshr_miss_latency::total 7279407410 # number of WriteLineReq MSHR miss cycles 1462system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles 1463system.iocache.demand_mshr_miss_latency::realview.ide 1123899238 # number of demand (read+write) MSHR miss cycles 1464system.iocache.demand_mshr_miss_latency::total 1127319238 # number of demand (read+write) MSHR miss cycles 1465system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles 1466system.iocache.overall_mshr_miss_latency::realview.ide 1123899238 # number of overall MSHR miss cycles 1467system.iocache.overall_mshr_miss_latency::total 1127319238 # number of overall MSHR miss cycles 1468system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1469system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1470system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1471system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1472system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1473system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1474system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1475system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1476system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1477system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1478system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1479system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1480system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1481system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency 1482system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127080.420398 # average ReadReq mshr miss latency 1483system.iocache.ReadReq_avg_mshr_miss_latency::total 126913.437451 # average ReadReq mshr miss latency 1484system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1485system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1486system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68246.150623 # average WriteLineReq mshr miss latency 1487system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68246.150623 # average WriteLineReq mshr miss latency 1488system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency 1489system.iocache.demand_avg_mshr_miss_latency::realview.ide 127080.420398 # average overall mshr miss latency 1490system.iocache.demand_avg_mshr_miss_latency::total 126893.205538 # average overall mshr miss latency 1491system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency 1492system.iocache.overall_avg_mshr_miss_latency::realview.ide 127080.420398 # average overall mshr miss latency 1493system.iocache.overall_avg_mshr_miss_latency::total 126893.205538 # average overall mshr miss latency 1494system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1495system.membus.trans_dist::ReadReq 76831 # Transaction distribution 1496system.membus.trans_dist::ReadResp 446450 # Transaction distribution 1497system.membus.trans_dist::WriteReq 33710 # Transaction distribution 1498system.membus.trans_dist::WriteResp 33710 # Transaction distribution 1499system.membus.trans_dist::Writeback 1184590 # Transaction distribution 1500system.membus.trans_dist::CleanEvict 190005 # Transaction distribution 1501system.membus.trans_dist::UpgradeReq 35851 # Transaction distribution 1502system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1503system.membus.trans_dist::UpgradeResp 35852 # Transaction distribution 1504system.membus.trans_dist::ReadExReq 993855 # Transaction distribution 1505system.membus.trans_dist::ReadExResp 993855 # Transaction distribution 1506system.membus.trans_dist::ReadSharedReq 369619 # Transaction distribution 1507system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution 1508system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution 1509system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1510system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1511system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) 1512system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4133679 # Packet count per connected master and slave (bytes) 1513system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4263383 # Packet count per connected master and slave (bytes) 1514system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340829 # Packet count per connected master and slave (bytes) 1515system.membus.pkt_count_system.iocache.mem_side::total 340829 # Packet count per connected master and slave (bytes) 1516system.membus.pkt_count::total 4604212 # Packet count per connected master and slave (bytes) 1517system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1518system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1519system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) 1520system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 155834656 # Cumulative packet size per connected master and slave (bytes) 1521system.membus.pkt_size_system.cpu.l2cache.mem_side::total 156004506 # Cumulative packet size per connected master and slave (bytes) 1522system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7214528 # Cumulative packet size per connected master and slave (bytes) 1523system.membus.pkt_size_system.iocache.mem_side::total 7214528 # Cumulative packet size per connected master and slave (bytes) 1524system.membus.pkt_size::total 163219034 # Cumulative packet size per connected master and slave (bytes) 1525system.membus.snoops 3445 # Total snoops (count) 1526system.membus.snoop_fanout::samples 2994110 # Request fanout histogram 1527system.membus.snoop_fanout::mean 1 # Request fanout histogram 1528system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1529system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1530system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1531system.membus.snoop_fanout::1 2994110 100.00% 100.00% # Request fanout histogram 1532system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1533system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1534system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1535system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1536system.membus.snoop_fanout::total 2994110 # Request fanout histogram 1537system.membus.reqLayer0.occupancy 107330000 # Layer occupancy (ticks) 1538system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1539system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 1540system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1541system.membus.reqLayer2.occupancy 5385500 # Layer occupancy (ticks) 1542system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1543system.membus.reqLayer5.occupancy 7724756059 # Layer occupancy (ticks) 1544system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1545system.membus.respLayer2.occupancy 7445249237 # Layer occupancy (ticks) 1546system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1547system.membus.respLayer3.occupancy 228975298 # Layer occupancy (ticks) 1548system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1549system.realview.ethernet.txBytes 966 # Bytes Transmitted 1550system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1551system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1552system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1553system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1554system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1555system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1556system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1557system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1558system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 1559system.realview.ethernet.totPackets 3 # Total Packets 1560system.realview.ethernet.totBytes 966 # Total Bytes 1561system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1562system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 1563system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1564system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1565system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1566system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1567system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1568system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1569system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1570system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1571system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1572system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1573system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1574system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1575system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1576system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1577system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1578system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1579system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1580system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1581system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1582system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1583system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1584system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1585system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1586system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1587system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1588system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1589system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1590system.realview.ethernet.droppedPackets 0 # number of packets dropped 1591system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 1592system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 1593system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 1594system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 1595system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 1596system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 1597system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 1598system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 1599system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 1600system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 1601 1602---------- End Simulation Statistics ---------- 1603