stats.txt revision 11570
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311570SCurtis.Dunham@arm.comsim_seconds 51.759348 # Number of seconds simulated 411570SCurtis.Dunham@arm.comsim_ticks 51759347706500 # Number of ticks simulated 511570SCurtis.Dunham@arm.comfinal_tick 51759347706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711570SCurtis.Dunham@arm.comhost_inst_rate 706961 # Simulator instruction rate (inst/s) 811570SCurtis.Dunham@arm.comhost_op_rate 830795 # Simulator op (including micro ops) rate (op/s) 911570SCurtis.Dunham@arm.comhost_tick_rate 43773319280 # Simulator tick rate (ticks/s) 1011570SCurtis.Dunham@arm.comhost_mem_usage 670816 # Number of bytes of host memory used 1111570SCurtis.Dunham@arm.comhost_seconds 1182.44 # Real time elapsed on the host 1211570SCurtis.Dunham@arm.comsim_insts 835939132 # Number of instructions simulated 1311570SCurtis.Dunham@arm.comsim_ops 982366087 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611570SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 1711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 152192 # Number of bytes read from this memory 1811570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.itb.walker 158144 # Number of bytes read from this memory 1911570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 4715828 # Number of bytes read from this memory 2011570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 36073224 # Number of bytes read from this memory 2111570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::realview.ide 410496 # Number of bytes read from this memory 2211570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 41509884 # Number of bytes read from this memory 2311570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 4715828 # Number of instructions bytes read from this memory 2411570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 4715828 # Number of instructions bytes read from this memory 2511570SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 62909632 # Number of bytes written to this memory 2610585SN/Asystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2711570SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 62930212 # Number of bytes written to this memory 2811570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.dtb.walker 2378 # Number of read requests responded to by this memory 2911570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.itb.walker 2471 # Number of read requests responded to by this memory 3011570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 114092 # Number of read requests responded to by this memory 3111570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 563657 # Number of read requests responded to by this memory 3211570SCurtis.Dunham@arm.comsystem.physmem.num_reads::realview.ide 6414 # Number of read requests responded to by this memory 3311570SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 689012 # Number of read requests responded to by this memory 3411570SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 982963 # Number of write requests responded to by this memory 3510585SN/Asystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3611570SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 985536 # Number of write requests responded to by this memory 3711570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.dtb.walker 2940 # Total read bandwidth from this memory (bytes/s) 3811570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.itb.walker 3055 # Total read bandwidth from this memory (bytes/s) 3911570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 91111 # Total read bandwidth from this memory (bytes/s) 4011570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 696941 # Total read bandwidth from this memory (bytes/s) 4111570SCurtis.Dunham@arm.comsystem.physmem.bw_read::realview.ide 7931 # Total read bandwidth from this memory (bytes/s) 4211570SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 801978 # Total read bandwidth from this memory (bytes/s) 4311570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 91111 # Instruction read bandwidth from this memory (bytes/s) 4411570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 91111 # Instruction read bandwidth from this memory (bytes/s) 4511570SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 1215426 # Write bandwidth from this memory (bytes/s) 4611353Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 4711570SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 1215823 # Write bandwidth from this memory (bytes/s) 4811570SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 1215426 # Total bandwidth to/from this memory (bytes/s) 4911570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.dtb.walker 2940 # Total bandwidth to/from this memory (bytes/s) 5011570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.itb.walker 3055 # Total bandwidth to/from this memory (bytes/s) 5111570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 91111 # Total bandwidth to/from this memory (bytes/s) 5211570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 697339 # Total bandwidth to/from this memory (bytes/s) 5311570SCurtis.Dunham@arm.comsystem.physmem.bw_total::realview.ide 7931 # Total bandwidth to/from this memory (bytes/s) 5411570SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 2017802 # Total bandwidth to/from this memory (bytes/s) 5511570SCurtis.Dunham@arm.comsystem.physmem.readReqs 689012 # Number of read requests accepted 5611570SCurtis.Dunham@arm.comsystem.physmem.writeReqs 985536 # Number of write requests accepted 5711570SCurtis.Dunham@arm.comsystem.physmem.readBursts 689012 # Number of DRAM read bursts, including those serviced by the write queue 5811570SCurtis.Dunham@arm.comsystem.physmem.writeBursts 985536 # Number of DRAM write bursts, including those merged in the write queue 5911570SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 44056384 # Total number of bytes read from DRAM 6011570SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 40384 # Total number of bytes read from write queue 6111570SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 62928960 # Total number of bytes written to DRAM 6211570SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 41509884 # Total read bytes from the system interface side 6311570SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 62930212 # Total written bytes from the system interface side 6411570SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 631 # Number of DRAM read bursts serviced by the write queue 6511570SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 6611336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6711570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 41424 # Per bank write bursts 6811570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 42196 # Per bank write bursts 6911570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 39305 # Per bank write bursts 7011570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 41228 # Per bank write bursts 7111570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 37796 # Per bank write bursts 7211570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 46284 # Per bank write bursts 7311570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 37646 # Per bank write bursts 7411570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 36984 # Per bank write bursts 7511570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 37874 # Per bank write bursts 7611570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 85067 # Per bank write bursts 7711570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 43899 # Per bank write bursts 7811570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 46232 # Per bank write bursts 7911570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 39321 # Per bank write bursts 8011570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 40035 # Per bank write bursts 8111570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 35465 # Per bank write bursts 8211570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 37625 # Per bank write bursts 8311570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 61899 # Per bank write bursts 8411570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 62487 # Per bank write bursts 8511570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 61087 # Per bank write bursts 8611570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 63695 # Per bank write bursts 8711570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 58991 # Per bank write bursts 8811570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 64628 # Per bank write bursts 8911570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 58592 # Per bank write bursts 9011570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 59025 # Per bank write bursts 9111570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 60354 # Per bank write bursts 9211570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 64900 # Per bank write bursts 9311570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 63044 # Per bank write bursts 9411570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 64791 # Per bank write bursts 9511570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 60176 # Per bank write bursts 9611570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 61598 # Per bank write bursts 9711570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 57895 # Per bank write bursts 9811570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 60103 # Per bank write bursts 9910515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 10011570SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 19 # Number of times write queue was full causing retry 10111570SCurtis.Dunham@arm.comsystem.physmem.totGap 51759344769500 # Total gap between requests 10210515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10310515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10410515SN/Asystem.physmem.readPktSize::2 43101 # Read request sizes (log2) 10510515SN/Asystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10610515SN/Asystem.physmem.readPktSize::4 2 # Read request sizes (log2) 10710515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10811570SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 645896 # Read request sizes (log2) 10910515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 11010515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11110515SN/Asystem.physmem.writePktSize::2 1 # Write request sizes (log2) 11210515SN/Asystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 11310515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 11410515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11511570SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 982963 # Write request sizes (log2) 11611570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 659454 # What read queue length does an incoming req see 11711570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 23139 # What read queue length does an incoming req see 11811570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 405 # What read queue length does an incoming req see 11911570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 338 # What read queue length does an incoming req see 12011570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 474 # What read queue length does an incoming req see 12111570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 555 # What read queue length does an incoming req see 12211570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 545 # What read queue length does an incoming req see 12311570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 1172 # What read queue length does an incoming req see 12411570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 668 # What read queue length does an incoming req see 12511570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 279 # What read queue length does an incoming req see 12611570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 358 # What read queue length does an incoming req see 12711570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 162 # What read queue length does an incoming req see 12811570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 174 # What read queue length does an incoming req see 12911570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 128 # What read queue length does an incoming req see 13011570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 114 # What read queue length does an incoming req see 13111570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see 13211570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see 13311570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see 13411570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see 13511570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see 13611570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see 13710515SN/Asystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 13810515SN/Asystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13910515SN/Asystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 14010515SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14110515SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14210515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 14310515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 14410515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14510515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14610515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14710515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14810515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14910515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 15010515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15110515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15210515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15310515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15410515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15510515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15610515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15710515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15810515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15910515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 16010515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16110515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16210515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 31865 # What write queue length does an incoming req see 16411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 37580 # What write queue length does an incoming req see 16511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 54935 # What write queue length does an incoming req see 16611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 54491 # What write queue length does an incoming req see 16711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 57672 # What write queue length does an incoming req see 16811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 55206 # What write queue length does an incoming req see 16911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 58598 # What write queue length does an incoming req see 17011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 55686 # What write queue length does an incoming req see 17111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 56443 # What write queue length does an incoming req see 17211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 55845 # What write queue length does an incoming req see 17311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 56872 # What write queue length does an incoming req see 17411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 59532 # What write queue length does an incoming req see 17511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 57169 # What write queue length does an incoming req see 17611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 57139 # What write queue length does an incoming req see 17711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 58902 # What write queue length does an incoming req see 17811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 55823 # What write queue length does an incoming req see 17911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 54603 # What write queue length does an incoming req see 18011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 54399 # What write queue length does an incoming req see 18111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 2302 # What write queue length does an incoming req see 18211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 800 # What write queue length does an incoming req see 18311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 676 # What write queue length does an incoming req see 18411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 442 # What write queue length does an incoming req see 18511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 459 # What write queue length does an incoming req see 18611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 467 # What write queue length does an incoming req see 18711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 447 # What write queue length does an incoming req see 18811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 304 # What write queue length does an incoming req see 18911353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see 19011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 304 # What write queue length does an incoming req see 19111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 282 # What write queue length does an incoming req see 19211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 243 # What write queue length does an incoming req see 19311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see 19411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 254 # What write queue length does an incoming req see 19511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 241 # What write queue length does an incoming req see 19611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 233 # What write queue length does an incoming req see 19711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see 19811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 257 # What write queue length does an incoming req see 19911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 220 # What write queue length does an incoming req see 20011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see 20111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 155 # What write queue length does an incoming req see 20211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see 20311353Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 191 # What write queue length does an incoming req see 20411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 236 # What write queue length does an incoming req see 20511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 204 # What write queue length does an incoming req see 20611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 126 # What write queue length does an incoming req see 20711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 164 # What write queue length does an incoming req see 20811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 128 # What write queue length does an incoming req see 20911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see 21011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see 21111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see 21211570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 438828 # Bytes accessed per row activation 21311570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 243.797169 # Bytes accessed per row activation 21411570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 147.013209 # Bytes accessed per row activation 21511570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 285.979705 # Bytes accessed per row activation 21611570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 194919 44.42% 44.42% # Bytes accessed per row activation 21711570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 116778 26.61% 71.03% # Bytes accessed per row activation 21811570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 38832 8.85% 79.88% # Bytes accessed per row activation 21911570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 20430 4.66% 84.53% # Bytes accessed per row activation 22011570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 13130 2.99% 87.53% # Bytes accessed per row activation 22111570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 8793 2.00% 89.53% # Bytes accessed per row activation 22211570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 7414 1.69% 91.22% # Bytes accessed per row activation 22311570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 5819 1.33% 92.55% # Bytes accessed per row activation 22411570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 32713 7.45% 100.00% # Bytes accessed per row activation 22511570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 438828 # Bytes accessed per row activation 22611570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 52143 # Reads before turning the bus around for writes 22711570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 13.201312 # Reads before turning the bus around for writes 22811570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 141.003763 # Reads before turning the bus around for writes 22911570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 52140 99.99% 99.99% # Reads before turning the bus around for writes 23011570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 23111353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 23211353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 23311570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 52143 # Reads before turning the bus around for writes 23411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 52143 # Writes before turning the bus around for reads 23511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 18.857085 # Writes before turning the bus around for reads 23611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 18.140227 # Writes before turning the bus around for reads 23711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 8.284435 # Writes before turning the bus around for reads 23811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16-19 48446 92.91% 92.91% # Writes before turning the bus around for reads 23911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20-23 1855 3.56% 96.47% # Writes before turning the bus around for reads 24011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24-27 116 0.22% 96.69% # Writes before turning the bus around for reads 24111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::28-31 101 0.19% 96.88% # Writes before turning the bus around for reads 24211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32-35 48 0.09% 96.98% # Writes before turning the bus around for reads 24311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::36-39 101 0.19% 97.17% # Writes before turning the bus around for reads 24411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::40-43 252 0.48% 97.65% # Writes before turning the bus around for reads 24511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::44-47 24 0.05% 97.70% # Writes before turning the bus around for reads 24611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::48-51 307 0.59% 98.29% # Writes before turning the bus around for reads 24711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::52-55 75 0.14% 98.43% # Writes before turning the bus around for reads 24811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::56-59 29 0.06% 98.49% # Writes before turning the bus around for reads 24911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::60-63 51 0.10% 98.58% # Writes before turning the bus around for reads 25011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::64-67 313 0.60% 99.18% # Writes before turning the bus around for reads 25111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::68-71 41 0.08% 99.26% # Writes before turning the bus around for reads 25211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::72-75 37 0.07% 99.33% # Writes before turning the bus around for reads 25311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::76-79 129 0.25% 99.58% # Writes before turning the bus around for reads 25411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::80-83 166 0.32% 99.90% # Writes before turning the bus around for reads 25511353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads 25611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads 25711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::96-99 1 0.00% 99.91% # Writes before turning the bus around for reads 25811336Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads 25911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads 26011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::108-111 3 0.01% 99.92% # Writes before turning the bus around for reads 26111353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads 26211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads 26311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads 26411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::128-131 11 0.02% 99.95% # Writes before turning the bus around for reads 26511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads 26611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::144-147 15 0.03% 99.98% # Writes before turning the bus around for reads 26711353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads 26811353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads 26911353Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 27011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads 27111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads 27211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads 27311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 52143 # Writes before turning the bus around for reads 27411570SCurtis.Dunham@arm.comsystem.physmem.totQLat 9222624910 # Total ticks spent queuing 27511570SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 22129768660 # Total ticks spent from burst creation until serviced by the DRAM 27611570SCurtis.Dunham@arm.comsystem.physmem.totBusLat 3441905000 # Total ticks spent in databus transfers 27711570SCurtis.Dunham@arm.comsystem.physmem.avgQLat 13397.56 # Average queueing delay per DRAM burst 27810515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27911570SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 32147.56 # Average memory access latency per DRAM burst 28011570SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 0.85 # Average DRAM read bandwidth in MiByte/s 28111353Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s 28211570SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 0.80 # Average system read bandwidth in MiByte/s 28311353Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.22 # Average system write bandwidth in MiByte/s 28410515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 28510892Sandreas.hansson@arm.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 28610515SN/Asystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 28710892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 28810515SN/Asystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 28911570SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing 29011570SCurtis.Dunham@arm.comsystem.physmem.readRowHits 507228 # Number of row buffer hits during reads 29111570SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 725589 # Number of row buffer hits during writes 29211570SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 73.68 # Row buffer hit rate for reads 29311570SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 73.79 # Row buffer hit rate for writes 29411570SCurtis.Dunham@arm.comsystem.physmem.avgGap 30909442.29 # Average gap between requests 29511570SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 73.75 # Row buffer hit rate, read and write combined 29611570SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 1651557600 # Energy for activate commands per rank (pJ) 29711570SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 901147500 # Energy for precharge commands per rank (pJ) 29811570SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 2518331400 # Energy for read commands per rank (pJ) 29911570SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 3177817920 # Energy for write commands per rank (pJ) 30011570SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 3380668873920 # Energy for refresh commands per rank (pJ) 30111570SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 1280908967265 # Energy for active background per rank (pJ) 30211570SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 29932003411500 # Energy for precharge background per rank (pJ) 30311570SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 34601830107105 # Total energy per rank (pJ) 30411570SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 668.513662 # Core power per rank (mW) 30511570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 49794254360042 # Time in different power states 30611570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 1728358320000 # Time in different power states 30710628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 30811570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 236733614958 # Time in different power states 30910628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 31011570SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 1665982080 # Energy for activate commands per rank (pJ) 31111570SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 909018000 # Energy for precharge commands per rank (pJ) 31211570SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 2851001400 # Energy for read commands per rank (pJ) 31311570SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 3193739280 # Energy for write commands per rank (pJ) 31411570SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 3380668873920 # Energy for refresh commands per rank (pJ) 31511570SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 1282600048680 # Energy for active background per rank (pJ) 31611570SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 29930520006750 # Energy for precharge background per rank (pJ) 31711570SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 34602408670110 # Total energy per rank (pJ) 31811570SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 668.524840 # Core power per rank (mW) 31911570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 49791748874504 # Time in different power states 32011570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 1728358320000 # Time in different power states 32110628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 32211570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 239239854996 # Time in different power states 32310628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 32411570SCurtis.Dunham@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 32510515SN/Asystem.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 32610515SN/Asystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 32710515SN/Asystem.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 32810515SN/Asystem.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 32910515SN/Asystem.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 33010515SN/Asystem.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 33110515SN/Asystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 33210515SN/Asystem.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 33310515SN/Asystem.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 33410515SN/Asystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 33510515SN/Asystem.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 33610515SN/Asystem.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 33710515SN/Asystem.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 33810515SN/Asystem.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 33910515SN/Asystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 34010515SN/Asystem.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) 34111570SCurtis.Dunham@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 34211570SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 34311570SCurtis.Dunham@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 34410585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 34510585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 34610585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 34710585SN/Asystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 34810585SN/Asystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 34910585SN/Asystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 35010585SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 35111570SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 35210628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 35310628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35410628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35510628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35610628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35710628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 35810628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35910628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36010585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 36110585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 36210585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 36310585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 36410585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 36510585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 36610585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 36710585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 36810585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 36910585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37010585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 37110585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 37210585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 37310585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 37410585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37510585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 37610585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 37710585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 37810585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 37910585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 38010585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 38111570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 38211570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 186389 # Table walker walks requested 38311570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksLong 186389 # Table walker walks initiated with long descriptors 38411570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 11673 # Level at which table walker walks with long descriptors terminate 38511570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 145933 # Level at which table walker walks with long descriptors terminate 38611570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksSquashedBefore 20 # Table walks squashed before starting 38711570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 186369 # Table walker wait (enqueue to first request) latency 38811570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkWaitTime::mean 0.214628 # Table walker wait (enqueue to first request) latency 38911570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkWaitTime::stdev 70.564506 # Table walker wait (enqueue to first request) latency 39011570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkWaitTime::0-2047 186367 100.00% 100.00% # Table walker wait (enqueue to first request) latency 39110628SN/Asystem.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 39211138Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 39311570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 186369 # Table walker wait (enqueue to first request) latency 39411570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::samples 157626 # Table walker service (enqueue to completion) latency 39511570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::mean 24833.263548 # Table walker service (enqueue to completion) latency 39611570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::gmean 20845.971920 # Table walker service (enqueue to completion) latency 39711570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::stdev 18169.669952 # Table walker service (enqueue to completion) latency 39811570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::0-65535 156391 99.22% 99.22% # Table walker service (enqueue to completion) latency 39911570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 99.22% # Table walker service (enqueue to completion) latency 40011570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::131072-196607 1058 0.67% 99.89% # Table walker service (enqueue to completion) latency 40111570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::196608-262143 24 0.02% 99.91% # Table walker service (enqueue to completion) latency 40211570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::262144-327679 78 0.05% 99.96% # Table walker service (enqueue to completion) latency 40311570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::327680-393215 18 0.01% 99.97% # Table walker service (enqueue to completion) latency 40411570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::393216-458751 45 0.03% 100.00% # Table walker service (enqueue to completion) latency 40511570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 40611570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 40711570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 40811570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkCompletionTime::total 157626 # Table walker service (enqueue to completion) latency 40911570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksPending::samples -5176298892 # Table walker pending requests distribution 41011570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksPending::mean 1.304609 # Table walker pending requests distribution 41111336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution 41211570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksPending::0 1576748204 -30.46% -30.46% # Table walker pending requests distribution 41311570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksPending::1 -6753047096 130.46% 100.00% # Table walker pending requests distribution 41411570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walksPending::total -5176298892 # Table walker pending requests distribution 41511570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 145934 92.59% 92.59% # Table walker page sizes translated 41611570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkPageSizes::2M 11673 7.41% 100.00% # Table walker page sizes translated 41711570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 157607 # Table walker page sizes translated 41811570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 186389 # Table walker requests started/completed, data/inst 41910628SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42011570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 186389 # Table walker requests started/completed, data/inst 42111570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 157607 # Table walker requests started/completed, data/inst 42210628SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42311570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 157607 # Table walker requests started/completed, data/inst 42411570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 343996 # Table walker requests started/completed, data/inst 42510585SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 42610585SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 42711570SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 157302470 # DTB read hits 42811570SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 138254 # DTB read misses 42911570SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 142797891 # DTB write hits 43011570SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 48135 # DTB write misses 43110585SN/Asystem.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 43210585SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 43311570SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 38509 # Number of times TLB was flushed by MVA & ASID 43411353Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID 43511570SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 71109 # Number of entries that have been flushed from TLB 43610585SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 43711570SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 6989 # Number of TLB faults due to prefetch 43810585SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 43911353Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions 44011570SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 157440724 # DTB read accesses 44111570SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 142846026 # DTB write accesses 44210585SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 44311570SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 300100361 # DTB hits 44411570SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 186389 # DTB misses 44511570SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 300286750 # DTB accesses 44611570SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 44710628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 44810628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44910628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45010628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 45110628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45210628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45310628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 45410628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 45510585SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 45610585SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 45710585SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 45810585SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45910585SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 46010585SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 46110585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 46210585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46310585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 46410585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 46510585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 46610585SN/Asystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 46710585SN/Asystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 46810585SN/Asystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 46910585SN/Asystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 47010585SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 47110585SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 47210585SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 47310585SN/Asystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 47410585SN/Asystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 47510585SN/Asystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 47611570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 47711570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 119383 # Table walker walks requested 47811570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walksLong 119383 # Table walker walks initiated with long descriptors 47911353Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate 48011570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walksLongTerminationLevel::Level3 107813 # Level at which table walker walks with long descriptors terminate 48111570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 119383 # Table walker wait (enqueue to first request) latency 48211570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkWaitTime::0 119383 100.00% 100.00% # Table walker wait (enqueue to first request) latency 48311570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkWaitTime::total 119383 # Table walker wait (enqueue to first request) latency 48411570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::samples 108935 # Table walker service (enqueue to completion) latency 48511570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::mean 28686.574563 # Table walker service (enqueue to completion) latency 48611570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::gmean 24766.127594 # Table walker service (enqueue to completion) latency 48711570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::stdev 21816.949759 # Table walker service (enqueue to completion) latency 48811570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::0-65535 107446 98.63% 98.63% # Table walker service (enqueue to completion) latency 48911570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 98.64% # Table walker service (enqueue to completion) latency 49011570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::131072-196607 1285 1.18% 99.82% # Table walker service (enqueue to completion) latency 49111570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::196608-262143 37 0.03% 99.85% # Table walker service (enqueue to completion) latency 49211570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::262144-327679 72 0.07% 99.92% # Table walker service (enqueue to completion) latency 49311570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::327680-393215 42 0.04% 99.95% # Table walker service (enqueue to completion) latency 49411570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency 49511570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency 49611570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 49711570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 49811570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkCompletionTime::total 108935 # Table walker service (enqueue to completion) latency 49911201Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution 50011201Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution 50111201Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution 50211570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 107813 98.97% 98.97% # Table walker page sizes translated 50311353Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::2M 1122 1.03% 100.00% # Table walker page sizes translated 50411570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkPageSizes::total 108935 # Table walker page sizes translated 50510628SN/Asystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 50611570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119383 # Table walker requests started/completed, data/inst 50711570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 119383 # Table walker requests started/completed, data/inst 50810628SN/Asystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 50911570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108935 # Table walker requests started/completed, data/inst 51011570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 108935 # Table walker requests started/completed, data/inst 51111570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 228318 # Table walker requests started/completed, data/inst 51211570SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 836454912 # ITB inst hits 51311570SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 119383 # ITB inst misses 51410585SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 51510585SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 51610585SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 51710585SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 51810585SN/Asystem.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 51910585SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52011570SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 38509 # Number of times TLB was flushed by MVA & ASID 52111353Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID 52211570SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 50925 # Number of entries that have been flushed from TLB 52310585SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 52410585SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 52510585SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 52610585SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52710585SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 52810585SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 52911570SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 836574295 # ITB inst accesses 53011570SCurtis.Dunham@arm.comsystem.cpu.itb.hits 836454912 # DTB hits 53111570SCurtis.Dunham@arm.comsystem.cpu.itb.misses 119383 # DTB misses 53211570SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 836574295 # DTB accesses 53311530Sandreas.sandberg@arm.comsystem.cpu.numPwrStateTransitions 32056 # Number of power state transitions 53411530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::samples 16028 # Distribution of time spent in the clock gated state 53511570SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::mean 3133878336.314075 # Distribution of time spent in the clock gated state 53611570SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::stdev 60741761061.559830 # Distribution of time spent in the clock gated state 53711530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::underflows 6738 42.04% 42.04% # Distribution of time spent in the clock gated state 53811530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10 9255 57.74% 99.78% # Distribution of time spent in the clock gated state 53911530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state 54011530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 54111530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 54211530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 54311530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 54411530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 54511530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 54611530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 54711530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 54811530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 54911570SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 55011530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state 55111530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::total 16028 # Distribution of time spent in the clock gated state 55211570SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON 1529545732058 # Cumulative time (in ticks) in various power states 55311570SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 50229801974442 # Cumulative time (in ticks) in various power states 55411570SCurtis.Dunham@arm.comsystem.cpu.numCycles 103518695413 # number of cpu cycles simulated 55510585SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 55610585SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 55711167Sjthestness@gmail.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 55811353Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed 55911570SCurtis.Dunham@arm.comsystem.cpu.committedInsts 835939132 # Number of instructions committed 56011570SCurtis.Dunham@arm.comsystem.cpu.committedOps 982366087 # Number of ops (including micro ops) committed 56111570SCurtis.Dunham@arm.comsystem.cpu.num_int_alu_accesses 902933087 # Number of integer alu accesses 56211570SCurtis.Dunham@arm.comsystem.cpu.num_fp_alu_accesses 900158 # Number of float alu accesses 56311570SCurtis.Dunham@arm.comsystem.cpu.num_func_calls 50090187 # number of times a function call or return occured 56411570SCurtis.Dunham@arm.comsystem.cpu.num_conditional_control_insts 126876498 # number of instructions that are conditional controls 56511570SCurtis.Dunham@arm.comsystem.cpu.num_int_insts 902933087 # number of integer instructions 56611570SCurtis.Dunham@arm.comsystem.cpu.num_fp_insts 900158 # number of float instructions 56711570SCurtis.Dunham@arm.comsystem.cpu.num_int_register_reads 1308206945 # number of times the integer registers were read 56811570SCurtis.Dunham@arm.comsystem.cpu.num_int_register_writes 715740470 # number of times the integer registers were written 56911570SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_reads 1453094 # number of times the floating registers were read 57011570SCurtis.Dunham@arm.comsystem.cpu.num_fp_register_writes 759824 # number of times the floating registers were written 57111570SCurtis.Dunham@arm.comsystem.cpu.num_cc_register_reads 216985275 # number of times the CC registers were read 57211570SCurtis.Dunham@arm.comsystem.cpu.num_cc_register_writes 216380044 # number of times the CC registers were written 57311570SCurtis.Dunham@arm.comsystem.cpu.num_mem_refs 300079118 # number of memory refs 57411570SCurtis.Dunham@arm.comsystem.cpu.num_load_insts 157292666 # Number of load instructions 57511570SCurtis.Dunham@arm.comsystem.cpu.num_store_insts 142786452 # Number of store instructions 57611570SCurtis.Dunham@arm.comsystem.cpu.num_idle_cycles 100459603948.882050 # Number of idle cycles 57711570SCurtis.Dunham@arm.comsystem.cpu.num_busy_cycles 3059091464.117941 # Number of busy cycles 57811570SCurtis.Dunham@arm.comsystem.cpu.not_idle_fraction 0.029551 # Percentage of non-idle cycles 57911570SCurtis.Dunham@arm.comsystem.cpu.idle_fraction 0.970449 # Percentage of idle cycles 58011570SCurtis.Dunham@arm.comsystem.cpu.Branches 186526742 # Number of branches fetched 58110585SN/Asystem.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 58211570SCurtis.Dunham@arm.comsystem.cpu.op_class::IntAlu 680504734 69.23% 69.23% # Class of executed instruction 58311570SCurtis.Dunham@arm.comsystem.cpu.op_class::IntMult 2132093 0.22% 69.45% # Class of executed instruction 58411570SCurtis.Dunham@arm.comsystem.cpu.op_class::IntDiv 96706 0.01% 69.46% # Class of executed instruction 58511353Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction 58611353Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction 58711353Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction 58811353Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction 58911353Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction 59011353Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction 59111353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction 59211353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction 59311353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction 59411353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction 59511353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction 59611353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction 59711353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction 59811353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction 59911353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction 60011353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction 60111353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction 60211353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction 60311353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction 60411353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction 60511353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction 60611353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction 60711353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 112297 0.01% 69.47% # Class of executed instruction 60811353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction 60911353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction 61011353Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction 61111570SCurtis.Dunham@arm.comsystem.cpu.op_class::MemRead 157292666 16.00% 85.47% # Class of executed instruction 61211570SCurtis.Dunham@arm.comsystem.cpu.op_class::MemWrite 142786452 14.53% 100.00% # Class of executed instruction 61310585SN/Asystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 61410585SN/Asystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 61511570SCurtis.Dunham@arm.comsystem.cpu.op_class::total 982924991 # Class of executed instruction 61611570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 61711570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 9370067 # number of replacements 61811353Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use 61911570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 290532688 # Total number of references to valid blocks. 62011570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 9370579 # Sample count of references to valid blocks. 62111570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 31.004774 # Average number of references to valid blocks. 62211201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. 62311353Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor 62411138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy 62511138Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy 62610585SN/Asystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 62711570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 62811570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id 62911570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 63011570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 63110585SN/Asystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 63211570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 1209437211 # Number of tag accesses 63311570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 1209437211 # Number of data accesses 63411570SCurtis.Dunham@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 63511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 147248395 # number of ReadReq hits 63611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 147248395 # number of ReadReq hits 63711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 135579268 # number of WriteReq hits 63811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 135579268 # number of WriteReq hits 63911570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 373548 # number of SoftPFReq hits 64011570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 373548 # number of SoftPFReq hits 64111570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_hits::cpu.data 331872 # number of WriteLineReq hits 64211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_hits::total 331872 # number of WriteLineReq hits 64311570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 3336329 # number of LoadLockedReq hits 64411570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 3336329 # number of LoadLockedReq hits 64511570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 3621011 # number of StoreCondReq hits 64611570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 3621011 # number of StoreCondReq hits 64711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 283159535 # number of demand (read+write) hits 64811570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 283159535 # number of demand (read+write) hits 64911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 283533083 # number of overall hits 65011570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 283533083 # number of overall hits 65111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 4886658 # number of ReadReq misses 65211570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 4886658 # number of ReadReq misses 65311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1993718 # number of WriteReq misses 65411570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 1993718 # number of WriteReq misses 65511570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 1137538 # number of SoftPFReq misses 65611570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 1137538 # number of SoftPFReq misses 65711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_misses::cpu.data 1221988 # number of WriteLineReq misses 65811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_misses::total 1221988 # number of WriteLineReq misses 65911570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 286320 # number of LoadLockedReq misses 66011570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 286320 # number of LoadLockedReq misses 66111570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 66211570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 66311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 8102364 # number of demand (read+write) misses 66411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 8102364 # number of demand (read+write) misses 66511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 9239902 # number of overall misses 66611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 9239902 # number of overall misses 66711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 84160893500 # number of ReadReq miss cycles 66811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 84160893500 # number of ReadReq miss cycles 66911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 69982072000 # number of WriteReq miss cycles 67011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 69982072000 # number of WriteReq miss cycles 67111570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48119896000 # number of WriteLineReq miss cycles 67211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_miss_latency::total 48119896000 # number of WriteLineReq miss cycles 67311570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4409003500 # number of LoadLockedReq miss cycles 67411570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 4409003500 # number of LoadLockedReq miss cycles 67511570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 162000 # number of StoreCondReq miss cycles 67611570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 162000 # number of StoreCondReq miss cycles 67711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 202262861500 # number of demand (read+write) miss cycles 67811570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 202262861500 # number of demand (read+write) miss cycles 67911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 202262861500 # number of overall miss cycles 68011570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 202262861500 # number of overall miss cycles 68111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 152135053 # number of ReadReq accesses(hits+misses) 68211570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 152135053 # number of ReadReq accesses(hits+misses) 68311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 137572986 # number of WriteReq accesses(hits+misses) 68411570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 137572986 # number of WriteReq accesses(hits+misses) 68511570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 1511086 # number of SoftPFReq accesses(hits+misses) 68611570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 1511086 # number of SoftPFReq accesses(hits+misses) 68711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_accesses::cpu.data 1553860 # number of WriteLineReq accesses(hits+misses) 68811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_accesses::total 1553860 # number of WriteLineReq accesses(hits+misses) 68911570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 3622649 # number of LoadLockedReq accesses(hits+misses) 69011570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 3622649 # number of LoadLockedReq accesses(hits+misses) 69111570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 3621013 # number of StoreCondReq accesses(hits+misses) 69211570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 3621013 # number of StoreCondReq accesses(hits+misses) 69311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 291261899 # number of demand (read+write) accesses 69411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 291261899 # number of demand (read+write) accesses 69511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 292772985 # number of overall (read+write) accesses 69611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 292772985 # number of overall (read+write) accesses 69711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032121 # miss rate for ReadReq accesses 69811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.032121 # miss rate for ReadReq accesses 69911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014492 # miss rate for WriteReq accesses 70011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.014492 # miss rate for WriteReq accesses 70111570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752795 # miss rate for SoftPFReq accesses 70211570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.752795 # miss rate for SoftPFReq accesses 70311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786421 # miss rate for WriteLineReq accesses 70411570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_miss_rate::total 0.786421 # miss rate for WriteLineReq accesses 70511570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079036 # miss rate for LoadLockedReq accesses 70611570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.079036 # miss rate for LoadLockedReq accesses 70711570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 70811570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 70911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.027818 # miss rate for demand accesses 71011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.027818 # miss rate for demand accesses 71111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.031560 # miss rate for overall accesses 71211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.031560 # miss rate for overall accesses 71311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17222.587196 # average ReadReq miss latency 71411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 17222.587196 # average ReadReq miss latency 71511570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35101.289149 # average WriteReq miss latency 71611570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 35101.289149 # average WriteReq miss latency 71711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39378.370328 # average WriteLineReq miss latency 71811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_avg_miss_latency::total 39378.370328 # average WriteLineReq miss latency 71911570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15398.866653 # average LoadLockedReq miss latency 72011570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15398.866653 # average LoadLockedReq miss latency 72111570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 81000 # average StoreCondReq miss latency 72211570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 81000 # average StoreCondReq miss latency 72311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 24963.438016 # average overall miss latency 72411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 24963.438016 # average overall miss latency 72511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 21890.152244 # average overall miss latency 72611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 21890.152244 # average overall miss latency 72710585SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 72810585SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 72910585SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 73010585SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 73110585SN/Asystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 73210585SN/Asystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 73311570SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 7310347 # number of writebacks 73411570SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 7310347 # number of writebacks 73511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 21149 # number of ReadReq MSHR hits 73611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 21149 # number of ReadReq MSHR hits 73711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 21212 # number of WriteReq MSHR hits 73811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 21212 # number of WriteReq MSHR hits 73911570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69210 # number of LoadLockedReq MSHR hits 74011570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 69210 # number of LoadLockedReq MSHR hits 74111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 42361 # number of demand (read+write) MSHR hits 74211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 42361 # number of demand (read+write) MSHR hits 74311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 42361 # number of overall MSHR hits 74411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 42361 # number of overall MSHR hits 74511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 4865509 # number of ReadReq MSHR misses 74611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 4865509 # number of ReadReq MSHR misses 74711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 1972506 # number of WriteReq MSHR misses 74811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 1972506 # number of WriteReq MSHR misses 74911570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1135773 # number of SoftPFReq MSHR misses 75011570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1135773 # number of SoftPFReq MSHR misses 75111570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221988 # number of WriteLineReq MSHR misses 75211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_misses::total 1221988 # number of WriteLineReq MSHR misses 75311570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 217110 # number of LoadLockedReq MSHR misses 75411570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 217110 # number of LoadLockedReq MSHR misses 75511570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 75611570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 75711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 8060003 # number of demand (read+write) MSHR misses 75811570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 8060003 # number of demand (read+write) MSHR misses 75911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 9195776 # number of overall MSHR misses 76011570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 9195776 # number of overall MSHR misses 76111138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 76211138Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable 76311138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 76411138Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 76511138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 76611138Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses 76711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78024875000 # number of ReadReq MSHR miss cycles 76811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 78024875000 # number of ReadReq MSHR miss cycles 76911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67036106500 # number of WriteReq MSHR miss cycles 77011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 67036106500 # number of WriteReq MSHR miss cycles 77111570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21307541000 # number of SoftPFReq MSHR miss cycles 77211570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21307541000 # number of SoftPFReq MSHR miss cycles 77311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 46897908000 # number of WriteLineReq MSHR miss cycles 77411570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_latency::total 46897908000 # number of WriteLineReq MSHR miss cycles 77511570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2989370500 # number of LoadLockedReq MSHR miss cycles 77611570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2989370500 # number of LoadLockedReq MSHR miss cycles 77711570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 160000 # number of StoreCondReq MSHR miss cycles 77811570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 160000 # number of StoreCondReq MSHR miss cycles 77911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 191958889500 # number of demand (read+write) MSHR miss cycles 78011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 191958889500 # number of demand (read+write) MSHR miss cycles 78111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 213266430500 # number of overall MSHR miss cycles 78211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 213266430500 # number of overall MSHR miss cycles 78311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199627500 # number of ReadReq MSHR uncacheable cycles 78411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199627500 # number of ReadReq MSHR uncacheable cycles 78511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199627500 # number of overall MSHR uncacheable cycles 78611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 6199627500 # number of overall MSHR uncacheable cycles 78711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031982 # mshr miss rate for ReadReq accesses 78811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031982 # mshr miss rate for ReadReq accesses 78911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014338 # mshr miss rate for WriteReq accesses 79011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014338 # mshr miss rate for WriteReq accesses 79111570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751627 # mshr miss rate for SoftPFReq accesses 79211570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751627 # mshr miss rate for SoftPFReq accesses 79311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786421 # mshr miss rate for WriteLineReq accesses 79411570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786421 # mshr miss rate for WriteLineReq accesses 79511570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059931 # mshr miss rate for LoadLockedReq accesses 79611570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059931 # mshr miss rate for LoadLockedReq accesses 79711570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 79811570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 79911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027673 # mshr miss rate for demand accesses 80011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.027673 # mshr miss rate for demand accesses 80111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031409 # mshr miss rate for overall accesses 80211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.031409 # mshr miss rate for overall accesses 80311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16036.323229 # average ReadReq mshr miss latency 80411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16036.323229 # average ReadReq mshr miss latency 80511570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33985.248461 # average WriteReq mshr miss latency 80611570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33985.248461 # average WriteReq mshr miss latency 80711570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18760.386979 # average SoftPFReq mshr miss latency 80811570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18760.386979 # average SoftPFReq mshr miss latency 80911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38378.370328 # average WriteLineReq mshr miss latency 81011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38378.370328 # average WriteLineReq mshr miss latency 81111570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13768.921284 # average LoadLockedReq mshr miss latency 81211570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13768.921284 # average LoadLockedReq mshr miss latency 81311570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80000 # average StoreCondReq mshr miss latency 81411570SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80000 # average StoreCondReq mshr miss latency 81511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23816.230527 # average overall mshr miss latency 81611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 23816.230527 # average overall mshr miss latency 81711570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23191.781803 # average overall mshr miss latency 81811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 23191.781803 # average overall mshr miss latency 81911570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183954.290547 # average ReadReq mshr uncacheable latency 82011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183954.290547 # average ReadReq mshr uncacheable latency 82111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91968.958611 # average overall mshr uncacheable latency 82211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91968.958611 # average overall mshr uncacheable latency 82311570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 82411570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 13316326 # number of replacements 82511570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 511.820794 # Cycle average of tags in use 82611570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 823138069 # Total number of references to valid blocks. 82711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 13316838 # Sample count of references to valid blocks. 82811570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 61.811826 # Average number of references to valid blocks. 82911353Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit. 83011570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.820794 # Average occupied blocks per requestor 83111353Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy 83211353Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy 83310585SN/Asystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 83411570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 83511570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id 83611570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id 83711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 83810585SN/Asystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 83911570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 849771755 # Number of tag accesses 84011570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 849771755 # Number of data accesses 84111570SCurtis.Dunham@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 84211570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 823138069 # number of ReadReq hits 84311570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 823138069 # number of ReadReq hits 84411570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 823138069 # number of demand (read+write) hits 84511570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 823138069 # number of demand (read+write) hits 84611570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 823138069 # number of overall hits 84711570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 823138069 # number of overall hits 84811570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 13316843 # number of ReadReq misses 84911570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 13316843 # number of ReadReq misses 85011570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 13316843 # number of demand (read+write) misses 85111570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 13316843 # number of demand (read+write) misses 85211570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 13316843 # number of overall misses 85311570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 13316843 # number of overall misses 85411570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 182043679500 # number of ReadReq miss cycles 85511570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 182043679500 # number of ReadReq miss cycles 85611570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 182043679500 # number of demand (read+write) miss cycles 85711570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 182043679500 # number of demand (read+write) miss cycles 85811570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 182043679500 # number of overall miss cycles 85911570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 182043679500 # number of overall miss cycles 86011570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 836454912 # number of ReadReq accesses(hits+misses) 86111570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 836454912 # number of ReadReq accesses(hits+misses) 86211570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 836454912 # number of demand (read+write) accesses 86311570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 836454912 # number of demand (read+write) accesses 86411570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 836454912 # number of overall (read+write) accesses 86511570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 836454912 # number of overall (read+write) accesses 86611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015921 # miss rate for ReadReq accesses 86711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.015921 # miss rate for ReadReq accesses 86811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.015921 # miss rate for demand accesses 86911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.015921 # miss rate for demand accesses 87011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.015921 # miss rate for overall accesses 87111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.015921 # miss rate for overall accesses 87211570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13670.182903 # average ReadReq miss latency 87311570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 13670.182903 # average ReadReq miss latency 87411570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13670.182903 # average overall miss latency 87511570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 13670.182903 # average overall miss latency 87611570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13670.182903 # average overall miss latency 87711570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 13670.182903 # average overall miss latency 87810585SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87910585SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88010585SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 88110585SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 88210585SN/Asystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 88310585SN/Asystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 88411570SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 13316326 # number of writebacks 88511570SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 13316326 # number of writebacks 88611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 13316843 # number of ReadReq MSHR misses 88711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 13316843 # number of ReadReq MSHR misses 88811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 13316843 # number of demand (read+write) MSHR misses 88911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 13316843 # number of demand (read+write) MSHR misses 89011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 13316843 # number of overall MSHR misses 89111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 13316843 # number of overall MSHR misses 89210827Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 89310827Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 89410827Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 89510827Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 89611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168726836500 # number of ReadReq MSHR miss cycles 89711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 168726836500 # number of ReadReq MSHR miss cycles 89811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 168726836500 # number of demand (read+write) MSHR miss cycles 89911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 168726836500 # number of demand (read+write) MSHR miss cycles 90011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 168726836500 # number of overall MSHR miss cycles 90111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 168726836500 # number of overall MSHR miss cycles 90211201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles 90311201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles 90411201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles 90511201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles 90611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for ReadReq accesses 90711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.015921 # mshr miss rate for ReadReq accesses 90811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for demand accesses 90911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.015921 # mshr miss rate for demand accesses 91011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for overall accesses 91111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.015921 # mshr miss rate for overall accesses 91211570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12670.182903 # average ReadReq mshr miss latency 91311570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12670.182903 # average ReadReq mshr miss latency 91411570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12670.182903 # average overall mshr miss latency 91511570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 12670.182903 # average overall mshr miss latency 91611570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12670.182903 # average overall mshr miss latency 91711570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 12670.182903 # average overall mshr miss latency 91811201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency 91911201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency 92011201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency 92111201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency 92211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 92311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 1029342 # number of replacements 92411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 65301.929117 # Cycle average of tags in use 92511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 41597878 # Total number of references to valid blocks. 92611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 1091508 # Sample count of references to valid blocks. 92711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 38.110466 # Average number of references to valid blocks. 92811353Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 12385503500 # Cycle when the warmup percentage was hit. 92911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 38086.632918 # Average occupied blocks per requestor 93011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 236.862091 # Average occupied blocks per requestor 93111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 354.562935 # Average occupied blocks per requestor 93211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 7802.558346 # Average occupied blocks per requestor 93311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 18821.312827 # Average occupied blocks per requestor 93411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.581156 # Average percentage of cache occupancy 93511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003614 # Average percentage of cache occupancy 93611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005410 # Average percentage of cache occupancy 93711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.119058 # Average percentage of cache occupancy 93811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.287190 # Average percentage of cache occupancy 93911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.996428 # Average percentage of cache occupancy 94011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 232 # Occupied blocks per task id 94111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 61934 # Occupied blocks per task id 94211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 94311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id 94411353Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 94511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 403 # Occupied blocks per task id 94611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2431 # Occupied blocks per task id 94711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5392 # Occupied blocks per task id 94811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 53675 # Occupied blocks per task id 94911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id 95011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.945038 # Percentage of cache occupancy per task id 95111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 371610075 # Number of tag accesses 95211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 371610075 # Number of data accesses 95311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 95411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 312133 # number of ReadReq hits 95511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242520 # number of ReadReq hits 95611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_hits::total 554653 # number of ReadReq hits 95711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 7310347 # number of WritebackDirty hits 95811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 7310347 # number of WritebackDirty hits 95911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 13314767 # number of WritebackClean hits 96011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 13314767 # number of WritebackClean hits 96111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 8998 # number of UpgradeReq hits 96211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 8998 # number of UpgradeReq hits 96311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1590193 # number of ReadExReq hits 96411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1590193 # number of ReadExReq hits 96511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13245839 # number of ReadCleanReq hits 96611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 13245839 # number of ReadCleanReq hits 96711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 5993599 # number of ReadSharedReq hits 96811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 5993599 # number of ReadSharedReq hits 96911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_hits::cpu.data 742035 # number of InvalidateReq hits 97011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_hits::total 742035 # number of InvalidateReq hits 97111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 312133 # number of demand (read+write) hits 97211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 242520 # number of demand (read+write) hits 97311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 13245839 # number of demand (read+write) hits 97411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 7583792 # number of demand (read+write) hits 97511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 21384284 # number of demand (read+write) hits 97611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 312133 # number of overall hits 97711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 242520 # number of overall hits 97811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 13245839 # number of overall hits 97911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 7583792 # number of overall hits 98011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 21384284 # number of overall hits 98111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2378 # number of ReadReq misses 98211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2471 # number of ReadReq misses 98311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_misses::total 4849 # number of ReadReq misses 98411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 33265 # number of UpgradeReq misses 98511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 33265 # number of UpgradeReq misses 98611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 98711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 98811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 340050 # number of ReadExReq misses 98911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 340050 # number of ReadExReq misses 99011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 71004 # number of ReadCleanReq misses 99111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 71004 # number of ReadCleanReq misses 99211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 224793 # number of ReadSharedReq misses 99311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 224793 # number of ReadSharedReq misses 99411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_misses::cpu.data 479953 # number of InvalidateReq misses 99511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_misses::total 479953 # number of InvalidateReq misses 99611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 2378 # number of demand (read+write) misses 99711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 2471 # number of demand (read+write) misses 99811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 71004 # number of demand (read+write) misses 99911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 564843 # number of demand (read+write) misses 100011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 640696 # number of demand (read+write) misses 100111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 2378 # number of overall misses 100211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 2471 # number of overall misses 100311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 71004 # number of overall misses 100411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 564843 # number of overall misses 100511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 640696 # number of overall misses 100611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 324181000 # number of ReadReq miss cycles 100711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 343851000 # number of ReadReq miss cycles 100811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 668032000 # number of ReadReq miss cycles 100911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1328369000 # number of UpgradeReq miss cycles 101011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 1328369000 # number of UpgradeReq miss cycles 101111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 157000 # number of SCUpgradeReq miss cycles 101211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 157000 # number of SCUpgradeReq miss cycles 101311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 44644302500 # number of ReadExReq miss cycles 101411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 44644302500 # number of ReadExReq miss cycles 101511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9404933500 # number of ReadCleanReq miss cycles 101611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 9404933500 # number of ReadCleanReq miss cycles 101711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29984552500 # number of ReadSharedReq miss cycles 101811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 29984552500 # number of ReadSharedReq miss cycles 101911353Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 542500 # number of InvalidateReq miss cycles 102011353Sandreas.hansson@arm.comsystem.cpu.l2cache.InvalidateReq_miss_latency::total 542500 # number of InvalidateReq miss cycles 102111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 324181000 # number of demand (read+write) miss cycles 102211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 343851000 # number of demand (read+write) miss cycles 102311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 9404933500 # number of demand (read+write) miss cycles 102411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 74628855000 # number of demand (read+write) miss cycles 102511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 84701820500 # number of demand (read+write) miss cycles 102611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 324181000 # number of overall miss cycles 102711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 343851000 # number of overall miss cycles 102811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 9404933500 # number of overall miss cycles 102911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 74628855000 # number of overall miss cycles 103011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 84701820500 # number of overall miss cycles 103111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 314511 # number of ReadReq accesses(hits+misses) 103211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244991 # number of ReadReq accesses(hits+misses) 103311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 559502 # number of ReadReq accesses(hits+misses) 103411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 7310347 # number of WritebackDirty accesses(hits+misses) 103511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 7310347 # number of WritebackDirty accesses(hits+misses) 103611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 13314767 # number of WritebackClean accesses(hits+misses) 103711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 13314767 # number of WritebackClean accesses(hits+misses) 103811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 42263 # number of UpgradeReq accesses(hits+misses) 103911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 42263 # number of UpgradeReq accesses(hits+misses) 104011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 104111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 104211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 1930243 # number of ReadExReq accesses(hits+misses) 104311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 1930243 # number of ReadExReq accesses(hits+misses) 104411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13316843 # number of ReadCleanReq accesses(hits+misses) 104511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 13316843 # number of ReadCleanReq accesses(hits+misses) 104611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6218392 # number of ReadSharedReq accesses(hits+misses) 104711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 6218392 # number of ReadSharedReq accesses(hits+misses) 104811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::cpu.data 1221988 # number of InvalidateReq accesses(hits+misses) 104911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_accesses::total 1221988 # number of InvalidateReq accesses(hits+misses) 105011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 314511 # number of demand (read+write) accesses 105111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 244991 # number of demand (read+write) accesses 105211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 13316843 # number of demand (read+write) accesses 105311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 8148635 # number of demand (read+write) accesses 105411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 22024980 # number of demand (read+write) accesses 105511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 314511 # number of overall (read+write) accesses 105611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 244991 # number of overall (read+write) accesses 105711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 13316843 # number of overall (read+write) accesses 105811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 8148635 # number of overall (read+write) accesses 105911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 22024980 # number of overall (read+write) accesses 106011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007561 # miss rate for ReadReq accesses 106111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010086 # miss rate for ReadReq accesses 106211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.008667 # miss rate for ReadReq accesses 106311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.787095 # miss rate for UpgradeReq accesses 106411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.787095 # miss rate for UpgradeReq accesses 106510585SN/Asystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 106610585SN/Asystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 106711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.176170 # miss rate for ReadExReq accesses 106811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.176170 # miss rate for ReadExReq accesses 106911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005332 # miss rate for ReadCleanReq accesses 107011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005332 # miss rate for ReadCleanReq accesses 107111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036150 # miss rate for ReadSharedReq accesses 107211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036150 # miss rate for ReadSharedReq accesses 107311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.392764 # miss rate for InvalidateReq accesses 107411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_miss_rate::total 0.392764 # miss rate for InvalidateReq accesses 107511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007561 # miss rate for demand accesses 107611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010086 # miss rate for demand accesses 107711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.005332 # miss rate for demand accesses 107811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.069317 # miss rate for demand accesses 107911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.029090 # miss rate for demand accesses 108011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007561 # miss rate for overall accesses 108111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010086 # miss rate for overall accesses 108211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.005332 # miss rate for overall accesses 108311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.069317 # miss rate for overall accesses 108411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.029090 # miss rate for overall accesses 108511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136325.063078 # average ReadReq miss latency 108611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139154.593282 # average ReadReq miss latency 108711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 137766.962260 # average ReadReq miss latency 108811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39932.932512 # average UpgradeReq miss latency 108911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39932.932512 # average UpgradeReq miss latency 109011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 78500 # average SCUpgradeReq miss latency 109111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 78500 # average SCUpgradeReq miss latency 109211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131287.465079 # average ReadExReq miss latency 109311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 131287.465079 # average ReadExReq miss latency 109411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132456.389781 # average ReadCleanReq miss latency 109511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132456.389781 # average ReadCleanReq miss latency 109611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133387.394180 # average ReadSharedReq miss latency 109711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133387.394180 # average ReadSharedReq miss latency 109811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 1.130319 # average InvalidateReq miss latency 109911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_avg_miss_latency::total 1.130319 # average InvalidateReq miss latency 110011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136325.063078 # average overall miss latency 110111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 139154.593282 # average overall miss latency 110211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132456.389781 # average overall miss latency 110311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 132123.182902 # average overall miss latency 110411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 132202.823960 # average overall miss latency 110511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136325.063078 # average overall miss latency 110611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139154.593282 # average overall miss latency 110711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132456.389781 # average overall miss latency 110811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 132123.182902 # average overall miss latency 110911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 132202.823960 # average overall miss latency 111010585SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 111110585SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 111210585SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 111310585SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 111410585SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 111510585SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 876332 # number of writebacks 111711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 876332 # number of writebacks 111811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2378 # number of ReadReq MSHR misses 111911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2471 # number of ReadReq MSHR misses 112011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 4849 # number of ReadReq MSHR misses 112111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33265 # number of UpgradeReq MSHR misses 112211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 33265 # number of UpgradeReq MSHR misses 112311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 112411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 112511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 340050 # number of ReadExReq MSHR misses 112611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 340050 # number of ReadExReq MSHR misses 112711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 71004 # number of ReadCleanReq MSHR misses 112811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 71004 # number of ReadCleanReq MSHR misses 112911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 224793 # number of ReadSharedReq MSHR misses 113011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 224793 # number of ReadSharedReq MSHR misses 113111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 479953 # number of InvalidateReq MSHR misses 113211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_misses::total 479953 # number of InvalidateReq MSHR misses 113311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2378 # number of demand (read+write) MSHR misses 113411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2471 # number of demand (read+write) MSHR misses 113511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 71004 # number of demand (read+write) MSHR misses 113611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 564843 # number of demand (read+write) MSHR misses 113711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 640696 # number of demand (read+write) MSHR misses 113811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2378 # number of overall MSHR misses 113911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2471 # number of overall MSHR misses 114011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 71004 # number of overall MSHR misses 114111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 564843 # number of overall MSHR misses 114211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 640696 # number of overall MSHR misses 114310827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 114411138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable 114511138Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 76827 # number of ReadReq MSHR uncacheable 114611138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable 114711138Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable 114810827Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 114911138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses 115011138Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses 115111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 300401000 # number of ReadReq MSHR miss cycles 115211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 319141000 # number of ReadReq MSHR miss cycles 115311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 619542000 # number of ReadReq MSHR miss cycles 115411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2260005000 # number of UpgradeReq MSHR miss cycles 115511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2260005000 # number of UpgradeReq MSHR miss cycles 115611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 137000 # number of SCUpgradeReq MSHR miss cycles 115711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles 115811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41243802500 # number of ReadExReq MSHR miss cycles 115911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41243802500 # number of ReadExReq MSHR miss cycles 116011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8694893500 # number of ReadCleanReq MSHR miss cycles 116111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8694893500 # number of ReadCleanReq MSHR miss cycles 116211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27736359527 # number of ReadSharedReq MSHR miss cycles 116311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27736359527 # number of ReadSharedReq MSHR miss cycles 116411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 32474021500 # number of InvalidateReq MSHR miss cycles 116511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 32474021500 # number of InvalidateReq MSHR miss cycles 116611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 300401000 # number of demand (read+write) MSHR miss cycles 116711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 319141000 # number of demand (read+write) MSHR miss cycles 116811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8694893500 # number of demand (read+write) MSHR miss cycles 116911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68980162027 # number of demand (read+write) MSHR miss cycles 117011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 78294597527 # number of demand (read+write) MSHR miss cycles 117111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 300401000 # number of overall MSHR miss cycles 117211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 319141000 # number of overall MSHR miss cycles 117311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8694893500 # number of overall MSHR miss cycles 117411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68980162027 # number of overall MSHR miss cycles 117511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 78294597527 # number of overall MSHR miss cycles 117611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles 117711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777547500 # number of ReadReq MSHR uncacheable cycles 117811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675272000 # number of ReadReq MSHR uncacheable cycles 117911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles 118011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777547500 # number of overall MSHR uncacheable cycles 118111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675272000 # number of overall MSHR uncacheable cycles 118211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for ReadReq accesses 118311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for ReadReq accesses 118411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008667 # mshr miss rate for ReadReq accesses 118511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787095 # mshr miss rate for UpgradeReq accesses 118611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787095 # mshr miss rate for UpgradeReq accesses 118710585SN/Asystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 118810585SN/Asystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 118911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176170 # mshr miss rate for ReadExReq accesses 119011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176170 # mshr miss rate for ReadExReq accesses 119111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for ReadCleanReq accesses 119211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005332 # mshr miss rate for ReadCleanReq accesses 119311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036150 # mshr miss rate for ReadSharedReq accesses 119411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036150 # mshr miss rate for ReadSharedReq accesses 119511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.392764 # mshr miss rate for InvalidateReq accesses 119611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.392764 # mshr miss rate for InvalidateReq accesses 119711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for demand accesses 119811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for demand accesses 119911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for demand accesses 120011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069317 # mshr miss rate for demand accesses 120111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.029090 # mshr miss rate for demand accesses 120211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for overall accesses 120311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for overall accesses 120411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for overall accesses 120511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069317 # mshr miss rate for overall accesses 120611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.029090 # mshr miss rate for overall accesses 120711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average ReadReq mshr miss latency 120811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average ReadReq mshr miss latency 120911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127766.962260 # average ReadReq mshr miss latency 121011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67939.425823 # average UpgradeReq mshr miss latency 121111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67939.425823 # average UpgradeReq mshr miss latency 121211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency 121311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency 121411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121287.465079 # average ReadExReq mshr miss latency 121511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121287.465079 # average ReadExReq mshr miss latency 121611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122456.389781 # average ReadCleanReq mshr miss latency 121711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122456.389781 # average ReadCleanReq mshr miss latency 121811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123386.224335 # average ReadSharedReq mshr miss latency 121911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123386.224335 # average ReadSharedReq mshr miss latency 122011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67660.836582 # average InvalidateReq mshr miss latency 122111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67660.836582 # average InvalidateReq mshr miss latency 122211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average overall mshr miss latency 122311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average overall mshr miss latency 122411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122456.389781 # average overall mshr miss latency 122511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122122.717334 # average overall mshr miss latency 122611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 122202.413511 # average overall mshr miss latency 122711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average overall mshr miss latency 122811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average overall mshr miss latency 122911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122456.389781 # average overall mshr miss latency 123011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122122.717334 # average overall mshr miss latency 123111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 122202.413511 # average overall mshr miss latency 123211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency 123311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.404724 # average ReadReq mshr uncacheable latency 123411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.087157 # average ReadReq mshr uncacheable latency 123511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency 123611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85707.573060 # average overall mshr uncacheable latency 123711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.205998 # average overall mshr uncacheable latency 123811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 45899412 # Total number of requests made to the snoop filter. 123911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 23211953 # Number of requests hitting in the snoop filter with a single holder of the requested data. 124011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 1753 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 124111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2701 # Total number of snoops made to the snoop filter. 124211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2701 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 124311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 124411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 124511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 979874 # Transaction distribution 124611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 20515947 # Transaction distribution 124711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution 124811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution 124911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 8293329 # Transaction distribution 125011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 13316326 # Transaction distribution 125111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 2221598 # Transaction distribution 125211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 42266 # Transaction distribution 125311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 125411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 42268 # Transaction distribution 125511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 1930243 # Transaction distribution 125611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 1930243 # Transaction distribution 125711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 13316843 # Transaction distribution 125811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 6227282 # Transaction distribution 125911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateReq 1328652 # Transaction distribution 126011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::InvalidateResp 1221988 # Transaction distribution 126111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40036262 # Packet count per connected master and slave (bytes) 126211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28331504 # Packet count per connected master and slave (bytes) 126311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601742 # Packet count per connected master and slave (bytes) 126411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 860807 # Packet count per connected master and slave (bytes) 126511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 69830315 # Packet count per connected master and slave (bytes) 126611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1704695316 # Cumulative packet size per connected master and slave (bytes) 126711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 989618926 # Cumulative packet size per connected master and slave (bytes) 126811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959928 # Cumulative packet size per connected master and slave (bytes) 126911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2516088 # Cumulative packet size per connected master and slave (bytes) 127011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 2698790258 # Cumulative packet size per connected master and slave (bytes) 127111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 1604803 # Total snoops (count) 127211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 65712840 # Total snoop traffic (bytes) 127311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 25003730 # Request fanout histogram 127411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.019507 # Request fanout histogram 127511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.138299 # Request fanout histogram 127610585SN/Asystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 127711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 24515981 98.05% 98.05% # Request fanout histogram 127811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 487749 1.95% 100.00% # Request fanout histogram 127911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 128010585SN/Asystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 128111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 128211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 128311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 25003730 # Request fanout histogram 128411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 43858380000 # Layer occupancy (ticks) 128510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 128611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1560894 # Layer occupancy (ticks) 128710585SN/Asystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 128811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 20018389500 # Layer occupancy (ticks) 128910585SN/Asystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 129011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 12905646976 # Layer occupancy (ticks) 129110585SN/Asystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 129211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer2.occupancy 356751000 # Layer occupancy (ticks) 129310585SN/Asystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 129411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer3.occupancy 546296000 # Layer occupancy (ticks) 129510585SN/Asystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 129611570SCurtis.Dunham@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 129711570SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadReq 40338 # Transaction distribution 129811570SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadResp 40338 # Transaction distribution 129910726SN/Asystem.iobus.trans_dist::WriteReq 136571 # Transaction distribution 130010892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136571 # Transaction distribution 130110726SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 130210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 130311245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 130410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 130510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 130610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 130710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 130810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 130910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 131010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 131110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 131210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 131310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 131410726SN/Asystem.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 131511570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231034 # Packet count per connected master and slave (bytes) 131611570SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231034 # Packet count per connected master and slave (bytes) 131710585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 131810585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 131911570SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 353818 # Packet count per connected master and slave (bytes) 132010726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 132110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 132211245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 132310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 132410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 132510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 132610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 132710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 132810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 132910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 133010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 133110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 133210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 133310726SN/Asystem.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 133411570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334568 # Cumulative packet size per connected master and slave (bytes) 133511570SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7334568 # Cumulative packet size per connected master and slave (bytes) 133610585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 133710585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 133811570SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 7492488 # Cumulative packet size per connected master and slave (bytes) 133911570SCurtis.Dunham@arm.comsystem.iobus.reqLayer0.occupancy 42150000 # Layer occupancy (ticks) 134010585SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 134111570SCurtis.Dunham@arm.comsystem.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 134210585SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 134311570SCurtis.Dunham@arm.comsystem.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) 134410585SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 134511245Sandreas.sandberg@arm.comsystem.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) 134610585SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 134711353Sandreas.hansson@arm.comsystem.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) 134811245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 134911201Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) 135010585SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 135111201Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 135210585SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 135311201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 135410585SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 135511201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 135610585SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 135711353Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) 135810585SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 135911201Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 136010585SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 136111570SCurtis.Dunham@arm.comsystem.iobus.reqLayer23.occupancy 25729000 # Layer occupancy (ticks) 136210585SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 136311570SCurtis.Dunham@arm.comsystem.iobus.reqLayer24.occupancy 38601000 # Layer occupancy (ticks) 136410585SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 136511570SCurtis.Dunham@arm.comsystem.iobus.reqLayer25.occupancy 566926866 # Layer occupancy (ticks) 136610585SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 136710726SN/Asystem.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 136810585SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 136911570SCurtis.Dunham@arm.comsystem.iobus.respLayer3.occupancy 147794000 # Layer occupancy (ticks) 137010585SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 137110892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 137210585SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 137311570SCurtis.Dunham@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 137411570SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 115499 # number of replacements 137511570SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 10.446740 # Cycle average of tags in use 137610585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 137711570SCurtis.Dunham@arm.comsystem.iocache.tags.sampled_refs 115515 # Sample count of references to valid blocks. 137810585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 137911353Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit. 138011570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 5.847996 # Average occupied blocks per requestor 138111570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 4.598744 # Average occupied blocks per requestor 138211570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.365500 # Average percentage of cache occupancy 138311570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.287422 # Average percentage of cache occupancy 138411570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.652921 # Average percentage of cache occupancy 138510585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 138610585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 138710585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 138811570SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 1040010 # Number of tag accesses 138911570SCurtis.Dunham@arm.comsystem.iocache.tags.data_accesses 1040010 # Number of data accesses 139011570SCurtis.Dunham@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 139110585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 139211570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::realview.ide 8853 # number of ReadReq misses 139311570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::total 8890 # number of ReadReq misses 139410585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 139510585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 139610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 139710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 139810585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 139911570SCurtis.Dunham@arm.comsystem.iocache.demand_misses::realview.ide 115517 # number of demand (read+write) misses 140011570SCurtis.Dunham@arm.comsystem.iocache.demand_misses::total 115557 # number of demand (read+write) misses 140110585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 140211570SCurtis.Dunham@arm.comsystem.iocache.overall_misses::realview.ide 115517 # number of overall misses 140311570SCurtis.Dunham@arm.comsystem.iocache.overall_misses::total 115557 # number of overall misses 140411570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles 140511570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1655174117 # number of ReadReq miss cycles 140611570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::total 1660244617 # number of ReadReq miss cycles 140710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 140810892Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 140911570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13409764249 # number of WriteLineReq miss cycles 141011570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13409764249 # number of WriteLineReq miss cycles 141111570SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles 141211570SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ide 15064938366 # number of demand (read+write) miss cycles 141311570SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::total 15070359866 # number of demand (read+write) miss cycles 141411570SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles 141511570SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ide 15064938366 # number of overall miss cycles 141611570SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::total 15070359866 # number of overall miss cycles 141710585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 141811570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8853 # number of ReadReq accesses(hits+misses) 141911570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::total 8890 # number of ReadReq accesses(hits+misses) 142010585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 142110585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 142210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 142310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 142410585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 142511570SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::realview.ide 115517 # number of demand (read+write) accesses 142611570SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::total 115557 # number of demand (read+write) accesses 142710585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 142811570SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::realview.ide 115517 # number of overall (read+write) accesses 142911570SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 115557 # number of overall (read+write) accesses 143010585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 143110585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 143210585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 143310585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 143410585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 143510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 143610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 143710585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 143810585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 143910585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 144010585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 144110585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 144210585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 144311570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency 144411570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 186961.947024 # average ReadReq miss latency 144511570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 186754.175141 # average ReadReq miss latency 144610892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 144710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 144811570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 125719.682826 # average WriteLineReq miss latency 144911570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 125719.682826 # average WriteLineReq miss latency 145011570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency 145111570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 130413.171793 # average overall miss latency 145211570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::total 130414.945577 # average overall miss latency 145311570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency 145411570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 130413.171793 # average overall miss latency 145511570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::total 130414.945577 # average overall miss latency 145611570SCurtis.Dunham@arm.comsystem.iocache.blocked_cycles::no_mshrs 33045 # number of cycles access was blocked 145710585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 145811570SCurtis.Dunham@arm.comsystem.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked 145910585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 146011570SCurtis.Dunham@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.788211 # average number of cycles each access was blocked 146110585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 146211353Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106631 # number of writebacks 146311353Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106631 # number of writebacks 146410585SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 146511570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8853 # number of ReadReq MSHR misses 146611570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::total 8890 # number of ReadReq MSHR misses 146710585SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 146810585SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 146910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 147010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 147110585SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 147211570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115517 # number of demand (read+write) MSHR misses 147311570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::total 115557 # number of demand (read+write) MSHR misses 147410585SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 147511570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115517 # number of overall MSHR misses 147611570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::total 115557 # number of overall MSHR misses 147711570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles 147811570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1212524117 # number of ReadReq MSHR miss cycles 147911570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1215744617 # number of ReadReq MSHR miss cycles 148010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 148110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 148211570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071395398 # number of WriteLineReq MSHR miss cycles 148311570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8071395398 # number of WriteLineReq MSHR miss cycles 148411570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles 148511570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 9283919515 # number of demand (read+write) MSHR miss cycles 148611570SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::total 9287341015 # number of demand (read+write) MSHR miss cycles 148711570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles 148811570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 9283919515 # number of overall MSHR miss cycles 148911570SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::total 9287341015 # number of overall MSHR miss cycles 149010585SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 149110585SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 149210585SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 149310585SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 149410585SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 149510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 149610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 149710585SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 149810585SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 149910585SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 150010585SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 150110585SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 150210585SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 150311570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency 150411570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136961.947024 # average ReadReq mshr miss latency 150511570SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 136754.175141 # average ReadReq mshr miss latency 150610892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 150710892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 150811570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75671.223637 # average WriteLineReq mshr miss latency 150911570SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 75671.223637 # average WriteLineReq mshr miss latency 151011570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency 151111570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 80368.426422 # average overall mshr miss latency 151211570SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 80370.215694 # average overall mshr miss latency 151311570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency 151411570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 80368.426422 # average overall mshr miss latency 151511570SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 80370.215694 # average overall mshr miss latency 151611570SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 151711138Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 76827 # Transaction distribution 151811570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 386363 # Transaction distribution 151911138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 33708 # Transaction distribution 152011138Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 33708 # Transaction distribution 152111570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 982963 # Transaction distribution 152211570SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 160860 # Transaction distribution 152311570SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 33836 # Transaction distribution 152411570SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 152511353Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 7 # Transaction distribution 152611570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 339489 # Transaction distribution 152711570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 339489 # Transaction distribution 152811570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 309536 # Transaction distribution 152911570SCurtis.Dunham@arm.comsystem.membus.trans_dist::InvalidateReq 586610 # Transaction distribution 153010726SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 153110515SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 153211138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) 153311570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2913100 # Packet count per connected master and slave (bytes) 153411570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 3042792 # Packet count per connected master and slave (bytes) 153511570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237470 # Packet count per connected master and slave (bytes) 153611570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 237470 # Packet count per connected master and slave (bytes) 153711570SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 3280262 # Packet count per connected master and slave (bytes) 153810726SN/Asystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 153910515SN/Asystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 154011138Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) 154111570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97205216 # Cumulative packet size per connected master and slave (bytes) 154211570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 97375042 # Cumulative packet size per connected master and slave (bytes) 154311570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7234880 # Cumulative packet size per connected master and slave (bytes) 154411570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7234880 # Cumulative packet size per connected master and slave (bytes) 154511570SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 104609922 # Cumulative packet size per connected master and slave (bytes) 154611570SCurtis.Dunham@arm.comsystem.membus.snoops 3136 # Total snoops (count) 154711570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 200256 # Total snoop traffic (bytes) 154811570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 2523850 # Request fanout histogram 154910515SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 155010515SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 155110515SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 155210515SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 155311570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 2523850 100.00% 100.00% # Request fanout histogram 155410515SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 155510515SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 155610515SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 155710515SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 155811570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 2523850 # Request fanout histogram 155911570SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 106906000 # Layer occupancy (ticks) 156010515SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 156110726SN/Asystem.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 156210515SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 156311570SCurtis.Dunham@arm.comsystem.membus.reqLayer2.occupancy 5727500 # Layer occupancy (ticks) 156410515SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 156511570SCurtis.Dunham@arm.comsystem.membus.reqLayer5.occupancy 6514212892 # Layer occupancy (ticks) 156610515SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 156711570SCurtis.Dunham@arm.comsystem.membus.respLayer2.occupancy 3604018785 # Layer occupancy (ticks) 156810515SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 156911570SCurtis.Dunham@arm.comsystem.membus.respLayer3.occupancy 44774812 # Layer occupancy (ticks) 157010515SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 157111570SCurtis.Dunham@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 157211570SCurtis.Dunham@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 157311570SCurtis.Dunham@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 157411570SCurtis.Dunham@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 157511570SCurtis.Dunham@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 157611570SCurtis.Dunham@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 157711570SCurtis.Dunham@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 157811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 157911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 158011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 158111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 158211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 158311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 158411570SCurtis.Dunham@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 158511570SCurtis.Dunham@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 158610515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 158710515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 158810515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 158910515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 159010515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 159110515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 159210515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 159310515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 159410515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 159510515SN/Asystem.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 159610515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 159710515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 159810515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 159910515SN/Asystem.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 160010515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 160110515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 160210515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 160310515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 160410515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 160510515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 160610515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 160710515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 160810515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 160910515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 161010515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 161110515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 161210515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 161310515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 161410515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 161510515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 161610515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 161710515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 161810515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 161910515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 162010515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 162110515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 162210515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 162310515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 162410515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 162510515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 162610515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 162710515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 162811570SCurtis.Dunham@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 162911570SCurtis.Dunham@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 163011570SCurtis.Dunham@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 163111570SCurtis.Dunham@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 163211570SCurtis.Dunham@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 163311570SCurtis.Dunham@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 163411570SCurtis.Dunham@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 163511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 163611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 163711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 163811239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 163911570SCurtis.Dunham@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 164011570SCurtis.Dunham@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 164111570SCurtis.Dunham@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 164211570SCurtis.Dunham@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 164311570SCurtis.Dunham@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 164411570SCurtis.Dunham@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 164511570SCurtis.Dunham@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 164611570SCurtis.Dunham@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 164711570SCurtis.Dunham@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 164811570SCurtis.Dunham@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 164911570SCurtis.Dunham@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 165011570SCurtis.Dunham@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states 165110515SN/A 165210515SN/A---------- End Simulation Statistics ---------- 1653