stats.txt revision 10827
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 310726SN/Asim_seconds 51.824462 # Number of seconds simulated 410726SN/Asim_ticks 51824462100500 # Number of ticks simulated 510726SN/Afinal_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710827Sandreas.hansson@arm.comhost_inst_rate 684695 # Simulator instruction rate (inst/s) 810827Sandreas.hansson@arm.comhost_op_rate 804548 # Simulator op (including micro ops) rate (op/s) 910827Sandreas.hansson@arm.comhost_tick_rate 39714246392 # Simulator tick rate (ticks/s) 1010827Sandreas.hansson@arm.comhost_mem_usage 713112 # Number of bytes of host memory used 1110827Sandreas.hansson@arm.comhost_seconds 1304.93 # Real time elapsed on the host 1210726SN/Asim_insts 893481288 # Number of instructions simulated 1310726SN/Asim_ops 1049881338 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1610726SN/Asystem.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory 1710726SN/Asystem.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory 1810726SN/Asystem.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory 1910726SN/Asystem.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory 2010726SN/Asystem.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory 2110726SN/Asystem.physmem.bytes_read::total 56537020 # Number of bytes read from this memory 2210726SN/Asystem.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory 2310726SN/Asystem.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory 2410726SN/Asystem.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory 2510585SN/Asystem.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 2610726SN/Asystem.physmem.bytes_written::total 77726372 # Number of bytes written to this memory 2710726SN/Asystem.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory 2810726SN/Asystem.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory 2910726SN/Asystem.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory 3010726SN/Asystem.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory 3110726SN/Asystem.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory 3210726SN/Asystem.physmem.num_reads::total 923811 # Number of read requests responded to by this memory 3310726SN/Asystem.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory 3410585SN/Asystem.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 3510726SN/Asystem.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory 3610726SN/Asystem.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s) 3710726SN/Asystem.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s) 3810726SN/Asystem.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s) 3910726SN/Asystem.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s) 4010726SN/Asystem.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s) 4110726SN/Asystem.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s) 4210726SN/Asystem.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s) 4310726SN/Asystem.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s) 4410726SN/Asystem.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s) 4510585SN/Asystem.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) 4610726SN/Asystem.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s) 4710726SN/Asystem.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s) 4810726SN/Asystem.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s) 4910726SN/Asystem.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s) 5010726SN/Asystem.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s) 5110726SN/Asystem.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s) 5210726SN/Asystem.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s) 5310726SN/Asystem.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s) 5410726SN/Asystem.physmem.readReqs 923811 # Number of read requests accepted 5510726SN/Asystem.physmem.writeReqs 1833124 # Number of write requests accepted 5610726SN/Asystem.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue 5710726SN/Asystem.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue 5810726SN/Asystem.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM 5910726SN/Asystem.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue 6010726SN/Asystem.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM 6110726SN/Asystem.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side 6210726SN/Asystem.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side 6310726SN/Asystem.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue 6410726SN/Asystem.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one 6510726SN/Asystem.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write 6610726SN/Asystem.physmem.perBankRdBursts::0 57129 # Per bank write bursts 6710726SN/Asystem.physmem.perBankRdBursts::1 60965 # Per bank write bursts 6810726SN/Asystem.physmem.perBankRdBursts::2 52485 # Per bank write bursts 6910726SN/Asystem.physmem.perBankRdBursts::3 50413 # Per bank write bursts 7010726SN/Asystem.physmem.perBankRdBursts::4 54002 # Per bank write bursts 7110726SN/Asystem.physmem.perBankRdBursts::5 59718 # Per bank write bursts 7210726SN/Asystem.physmem.perBankRdBursts::6 51713 # Per bank write bursts 7310726SN/Asystem.physmem.perBankRdBursts::7 51669 # Per bank write bursts 7410726SN/Asystem.physmem.perBankRdBursts::8 50247 # Per bank write bursts 7510726SN/Asystem.physmem.perBankRdBursts::9 101235 # Per bank write bursts 7610726SN/Asystem.physmem.perBankRdBursts::10 59848 # Per bank write bursts 7710726SN/Asystem.physmem.perBankRdBursts::11 58323 # Per bank write bursts 7810726SN/Asystem.physmem.perBankRdBursts::12 55369 # Per bank write bursts 7910726SN/Asystem.physmem.perBankRdBursts::13 55988 # Per bank write bursts 8010726SN/Asystem.physmem.perBankRdBursts::14 51743 # Per bank write bursts 8110726SN/Asystem.physmem.perBankRdBursts::15 52477 # Per bank write bursts 8210726SN/Asystem.physmem.perBankWrBursts::0 110630 # Per bank write bursts 8310726SN/Asystem.physmem.perBankWrBursts::1 112240 # Per bank write bursts 8410726SN/Asystem.physmem.perBankWrBursts::2 108805 # Per bank write bursts 8510726SN/Asystem.physmem.perBankWrBursts::3 108103 # Per bank write bursts 8610726SN/Asystem.physmem.perBankWrBursts::4 111102 # Per bank write bursts 8710726SN/Asystem.physmem.perBankWrBursts::5 113339 # Per bank write bursts 8810726SN/Asystem.physmem.perBankWrBursts::6 105567 # Per bank write bursts 8910726SN/Asystem.physmem.perBankWrBursts::7 107723 # Per bank write bursts 9010726SN/Asystem.physmem.perBankWrBursts::8 108849 # Per bank write bursts 9110726SN/Asystem.physmem.perBankWrBursts::9 115780 # Per bank write bursts 9210726SN/Asystem.physmem.perBankWrBursts::10 115663 # Per bank write bursts 9310726SN/Asystem.physmem.perBankWrBursts::11 113049 # Per bank write bursts 9410726SN/Asystem.physmem.perBankWrBursts::12 112494 # Per bank write bursts 9510726SN/Asystem.physmem.perBankWrBursts::13 116984 # Per bank write bursts 9610726SN/Asystem.physmem.perBankWrBursts::14 111502 # Per bank write bursts 9710726SN/Asystem.physmem.perBankWrBursts::15 110389 # Per bank write bursts 9810515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9910726SN/Asystem.physmem.numWrRetry 145 # Number of times write queue was full causing retry 10010726SN/Asystem.physmem.totGap 51824459475500 # Total gap between requests 10110515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 10210515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 10310515SN/Asystem.physmem.readPktSize::2 43101 # Read request sizes (log2) 10410515SN/Asystem.physmem.readPktSize::3 13 # Read request sizes (log2) 10510515SN/Asystem.physmem.readPktSize::4 2 # Read request sizes (log2) 10610515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10710726SN/Asystem.physmem.readPktSize::6 880695 # Read request sizes (log2) 10810515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 10910515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 11010515SN/Asystem.physmem.writePktSize::2 1 # Write request sizes (log2) 11110515SN/Asystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 11210515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 11310515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11410726SN/Asystem.physmem.writePktSize::6 1830551 # Write request sizes (log2) 11510726SN/Asystem.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see 11610726SN/Asystem.physmem.rdQLenPdf::1 28186 # What read queue length does an incoming req see 11710726SN/Asystem.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see 11810726SN/Asystem.physmem.rdQLenPdf::3 284 # What read queue length does an incoming req see 11910726SN/Asystem.physmem.rdQLenPdf::4 462 # What read queue length does an incoming req see 12010726SN/Asystem.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see 12110726SN/Asystem.physmem.rdQLenPdf::6 455 # What read queue length does an incoming req see 12210726SN/Asystem.physmem.rdQLenPdf::7 746 # What read queue length does an incoming req see 12310726SN/Asystem.physmem.rdQLenPdf::8 480 # What read queue length does an incoming req see 12410726SN/Asystem.physmem.rdQLenPdf::9 1765 # What read queue length does an incoming req see 12510726SN/Asystem.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see 12610726SN/Asystem.physmem.rdQLenPdf::11 111 # What read queue length does an incoming req see 12710726SN/Asystem.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see 12810726SN/Asystem.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see 12910726SN/Asystem.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see 13010726SN/Asystem.physmem.rdQLenPdf::15 102 # What read queue length does an incoming req see 13110726SN/Asystem.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see 13210726SN/Asystem.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see 13310726SN/Asystem.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see 13410726SN/Asystem.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see 13510726SN/Asystem.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see 13610515SN/Asystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 13710515SN/Asystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 13810515SN/Asystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 13910515SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 14010515SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 14110515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 14210515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 14310515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 14410515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 14510515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 14610515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14710515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14810515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14910515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15010515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15110515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15210515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15310515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15410515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15510515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15610515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15710515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15810515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15910515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16010515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16110515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16210726SN/Asystem.physmem.wrQLenPdf::15 57524 # What write queue length does an incoming req see 16310726SN/Asystem.physmem.wrQLenPdf::16 60978 # What write queue length does an incoming req see 16410726SN/Asystem.physmem.wrQLenPdf::17 91825 # What write queue length does an incoming req see 16510726SN/Asystem.physmem.wrQLenPdf::18 117209 # What write queue length does an incoming req see 16610726SN/Asystem.physmem.wrQLenPdf::19 106855 # What write queue length does an incoming req see 16710726SN/Asystem.physmem.wrQLenPdf::20 97040 # What write queue length does an incoming req see 16810726SN/Asystem.physmem.wrQLenPdf::21 98714 # What write queue length does an incoming req see 16910726SN/Asystem.physmem.wrQLenPdf::22 93369 # What write queue length does an incoming req see 17010726SN/Asystem.physmem.wrQLenPdf::23 94185 # What write queue length does an incoming req see 17110726SN/Asystem.physmem.wrQLenPdf::24 92986 # What write queue length does an incoming req see 17210726SN/Asystem.physmem.wrQLenPdf::25 93402 # What write queue length does an incoming req see 17310726SN/Asystem.physmem.wrQLenPdf::26 98737 # What write queue length does an incoming req see 17410726SN/Asystem.physmem.wrQLenPdf::27 96397 # What write queue length does an incoming req see 17510726SN/Asystem.physmem.wrQLenPdf::28 94916 # What write queue length does an incoming req see 17610726SN/Asystem.physmem.wrQLenPdf::29 105152 # What write queue length does an incoming req see 17710726SN/Asystem.physmem.wrQLenPdf::30 97025 # What write queue length does an incoming req see 17810726SN/Asystem.physmem.wrQLenPdf::31 94048 # What write queue length does an incoming req see 17910726SN/Asystem.physmem.wrQLenPdf::32 92817 # What write queue length does an incoming req see 18010726SN/Asystem.physmem.wrQLenPdf::33 5441 # What write queue length does an incoming req see 18110726SN/Asystem.physmem.wrQLenPdf::34 5084 # What write queue length does an incoming req see 18210726SN/Asystem.physmem.wrQLenPdf::35 5738 # What write queue length does an incoming req see 18310726SN/Asystem.physmem.wrQLenPdf::36 7709 # What write queue length does an incoming req see 18410726SN/Asystem.physmem.wrQLenPdf::37 7730 # What write queue length does an incoming req see 18510726SN/Asystem.physmem.wrQLenPdf::38 6924 # What write queue length does an incoming req see 18610726SN/Asystem.physmem.wrQLenPdf::39 6738 # What write queue length does an incoming req see 18710726SN/Asystem.physmem.wrQLenPdf::40 7452 # What write queue length does an incoming req see 18810726SN/Asystem.physmem.wrQLenPdf::41 5737 # What write queue length does an incoming req see 18910726SN/Asystem.physmem.wrQLenPdf::42 5138 # What write queue length does an incoming req see 19010726SN/Asystem.physmem.wrQLenPdf::43 4676 # What write queue length does an incoming req see 19110726SN/Asystem.physmem.wrQLenPdf::44 5004 # What write queue length does an incoming req see 19210726SN/Asystem.physmem.wrQLenPdf::45 4547 # What write queue length does an incoming req see 19310726SN/Asystem.physmem.wrQLenPdf::46 3838 # What write queue length does an incoming req see 19410726SN/Asystem.physmem.wrQLenPdf::47 3903 # What write queue length does an incoming req see 19510726SN/Asystem.physmem.wrQLenPdf::48 3022 # What write queue length does an incoming req see 19610726SN/Asystem.physmem.wrQLenPdf::49 2209 # What write queue length does an incoming req see 19710726SN/Asystem.physmem.wrQLenPdf::50 1452 # What write queue length does an incoming req see 19810726SN/Asystem.physmem.wrQLenPdf::51 1128 # What write queue length does an incoming req see 19910726SN/Asystem.physmem.wrQLenPdf::52 847 # What write queue length does an incoming req see 20010726SN/Asystem.physmem.wrQLenPdf::53 643 # What write queue length does an incoming req see 20110726SN/Asystem.physmem.wrQLenPdf::54 513 # What write queue length does an incoming req see 20210726SN/Asystem.physmem.wrQLenPdf::55 524 # What write queue length does an incoming req see 20310726SN/Asystem.physmem.wrQLenPdf::56 509 # What write queue length does an incoming req see 20410726SN/Asystem.physmem.wrQLenPdf::57 510 # What write queue length does an incoming req see 20510726SN/Asystem.physmem.wrQLenPdf::58 478 # What write queue length does an incoming req see 20610726SN/Asystem.physmem.wrQLenPdf::59 419 # What write queue length does an incoming req see 20710726SN/Asystem.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see 20810726SN/Asystem.physmem.wrQLenPdf::61 286 # What write queue length does an incoming req see 20910726SN/Asystem.physmem.wrQLenPdf::62 162 # What write queue length does an incoming req see 21010726SN/Asystem.physmem.wrQLenPdf::63 329 # What write queue length does an incoming req see 21110726SN/Asystem.physmem.bytesPerActivate::samples 603787 # Bytes accessed per row activation 21210726SN/Asystem.physmem.bytesPerActivate::mean 286.780656 # Bytes accessed per row activation 21310726SN/Asystem.physmem.bytesPerActivate::gmean 164.845955 # Bytes accessed per row activation 21410726SN/Asystem.physmem.bytesPerActivate::stdev 326.273004 # Bytes accessed per row activation 21510726SN/Asystem.physmem.bytesPerActivate::0-127 251324 41.62% 41.62% # Bytes accessed per row activation 21610726SN/Asystem.physmem.bytesPerActivate::128-255 149673 24.79% 66.41% # Bytes accessed per row activation 21710726SN/Asystem.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation 21810726SN/Asystem.physmem.bytesPerActivate::384-511 28017 4.64% 79.63% # Bytes accessed per row activation 21910726SN/Asystem.physmem.bytesPerActivate::512-639 19714 3.27% 82.89% # Bytes accessed per row activation 22010726SN/Asystem.physmem.bytesPerActivate::640-767 13055 2.16% 85.06% # Bytes accessed per row activation 22110726SN/Asystem.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation 22210726SN/Asystem.physmem.bytesPerActivate::896-1023 8959 1.48% 88.18% # Bytes accessed per row activation 22310726SN/Asystem.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation 22410726SN/Asystem.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation 22510726SN/Asystem.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes 22610726SN/Asystem.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes 22710726SN/Asystem.physmem.rdPerTurnAround::stdev 107.922360 # Reads before turning the bus around for writes 22810726SN/Asystem.physmem.rdPerTurnAround::0-1023 89134 100.00% 100.00% # Reads before turning the bus around for writes 22910585SN/Asystem.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 23010585SN/Asystem.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 23110726SN/Asystem.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes 23210726SN/Asystem.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads 23310726SN/Asystem.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads 23410726SN/Asystem.physmem.wrPerTurnAround::gmean 18.728374 # Writes before turning the bus around for reads 23510726SN/Asystem.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads 23610726SN/Asystem.physmem.wrPerTurnAround::16-31 87330 97.97% 97.97% # Writes before turning the bus around for reads 23710726SN/Asystem.physmem.wrPerTurnAround::32-47 694 0.78% 98.75% # Writes before turning the bus around for reads 23810726SN/Asystem.physmem.wrPerTurnAround::48-63 23 0.03% 98.78% # Writes before turning the bus around for reads 23910726SN/Asystem.physmem.wrPerTurnAround::64-79 47 0.05% 98.83% # Writes before turning the bus around for reads 24010726SN/Asystem.physmem.wrPerTurnAround::80-95 149 0.17% 99.00% # Writes before turning the bus around for reads 24110726SN/Asystem.physmem.wrPerTurnAround::96-111 187 0.21% 99.21% # Writes before turning the bus around for reads 24210726SN/Asystem.physmem.wrPerTurnAround::112-127 322 0.36% 99.57% # Writes before turning the bus around for reads 24310726SN/Asystem.physmem.wrPerTurnAround::128-143 118 0.13% 99.70% # Writes before turning the bus around for reads 24410726SN/Asystem.physmem.wrPerTurnAround::144-159 42 0.05% 99.75% # Writes before turning the bus around for reads 24510726SN/Asystem.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads 24610726SN/Asystem.physmem.wrPerTurnAround::176-191 62 0.07% 99.83% # Writes before turning the bus around for reads 24710726SN/Asystem.physmem.wrPerTurnAround::192-207 32 0.04% 99.87% # Writes before turning the bus around for reads 24810726SN/Asystem.physmem.wrPerTurnAround::208-223 11 0.01% 99.88% # Writes before turning the bus around for reads 24910726SN/Asystem.physmem.wrPerTurnAround::224-239 9 0.01% 99.89% # Writes before turning the bus around for reads 25010726SN/Asystem.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads 25110726SN/Asystem.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads 25210726SN/Asystem.physmem.wrPerTurnAround::272-287 2 0.00% 99.90% # Writes before turning the bus around for reads 25310726SN/Asystem.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads 25410726SN/Asystem.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads 25510726SN/Asystem.physmem.wrPerTurnAround::320-335 10 0.01% 99.93% # Writes before turning the bus around for reads 25610726SN/Asystem.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads 25710726SN/Asystem.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads 25810726SN/Asystem.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads 25910726SN/Asystem.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads 26010726SN/Asystem.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads 26110726SN/Asystem.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads 26210726SN/Asystem.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads 26310726SN/Asystem.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads 26410726SN/Asystem.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads 26510726SN/Asystem.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads 26610726SN/Asystem.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads 26710726SN/Asystem.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads 26810726SN/Asystem.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads 26910726SN/Asystem.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads 27010726SN/Asystem.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads 27110726SN/Asystem.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads 27210726SN/Asystem.physmem.totQLat 12043609520 # Total ticks spent queuing 27310726SN/Asystem.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM 27410726SN/Asystem.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers 27510726SN/Asystem.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst 27610515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27710726SN/Asystem.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst 27810726SN/Asystem.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s 27910726SN/Asystem.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s 28010726SN/Asystem.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s 28110726SN/Asystem.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s 28210515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 28310515SN/Asystem.physmem.busUtil 0.03 # Data bus utilization in percentage 28410515SN/Asystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 28510515SN/Asystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 28610515SN/Asystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 28710726SN/Asystem.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing 28810726SN/Asystem.physmem.readRowHits 694872 # Number of row buffer hits during reads 28910726SN/Asystem.physmem.writeRowHits 1406883 # Number of row buffer hits during writes 29010726SN/Asystem.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads 29110726SN/Asystem.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes 29210726SN/Asystem.physmem.avgGap 18797853.22 # Average gap between requests 29310726SN/Asystem.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined 29410726SN/Asystem.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ) 29510726SN/Asystem.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ) 29610726SN/Asystem.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ) 29710726SN/Asystem.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ) 29810726SN/Asystem.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) 29910726SN/Asystem.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ) 30010726SN/Asystem.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ) 30110726SN/Asystem.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ) 30210726SN/Asystem.physmem_0.averagePower 668.655841 # Core power per rank (mW) 30310726SN/Asystem.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states 30410726SN/Asystem.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states 30510628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 30610726SN/Asystem.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states 30710628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 30810726SN/Asystem.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ) 30910726SN/Asystem.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ) 31010726SN/Asystem.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ) 31110726SN/Asystem.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ) 31210726SN/Asystem.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) 31310726SN/Asystem.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ) 31410726SN/Asystem.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ) 31510726SN/Asystem.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ) 31610726SN/Asystem.physmem_1.averagePower 668.672178 # Core power per rank (mW) 31710726SN/Asystem.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states 31810726SN/Asystem.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states 31910628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 32010726SN/Asystem.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states 32110628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 32210515SN/Asystem.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 32310515SN/Asystem.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 32410515SN/Asystem.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 32510515SN/Asystem.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 32610515SN/Asystem.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 32710515SN/Asystem.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 32810515SN/Asystem.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 32910515SN/Asystem.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 33010515SN/Asystem.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 33110515SN/Asystem.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 33210515SN/Asystem.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 33310515SN/Asystem.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 33410515SN/Asystem.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 33510515SN/Asystem.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 33610515SN/Asystem.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 33710515SN/Asystem.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) 33810585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 33910585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 34010585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 34110585SN/Asystem.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 34210585SN/Asystem.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 34310585SN/Asystem.cf0.dma_write_txs 1669 # Number of DMA write transactions. 34410585SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 34510628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34610628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 34710628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 34810628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34910628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35010628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 35110628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35210628SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 35310585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 35410585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 35510585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 35610585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 35710585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 35810585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 35910585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 36010585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 36110585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 36210585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 36310585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 36410585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 36510585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 36610585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 36710585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36810585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 36910585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 37010585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 37110585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 37210585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 37310585SN/Asystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 37410726SN/Asystem.cpu.dtb.walker.walks 211321 # Table walker walks requested 37510726SN/Asystem.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors 37610726SN/Asystem.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate 37710726SN/Asystem.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate 37810628SN/Asystem.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting 37910726SN/Asystem.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency 38010726SN/Asystem.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency 38110726SN/Asystem.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency 38210726SN/Asystem.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency 38310628SN/Asystem.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 38410628SN/Asystem.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 38510726SN/Asystem.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency 38610726SN/Asystem.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency 38710726SN/Asystem.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency 38810726SN/Asystem.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency 38910726SN/Asystem.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency 39010726SN/Asystem.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency 39110726SN/Asystem.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency 39210726SN/Asystem.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency 39310726SN/Asystem.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency 39410726SN/Asystem.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency 39510726SN/Asystem.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency 39610726SN/Asystem.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 39710726SN/Asystem.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 39810726SN/Asystem.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 39910726SN/Asystem.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency 40010726SN/Asystem.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution 40110726SN/Asystem.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution 40210726SN/Asystem.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution 40310726SN/Asystem.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution 40410726SN/Asystem.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution 40510726SN/Asystem.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated 40610726SN/Asystem.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated 40710726SN/Asystem.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated 40810726SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst 40910628SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 41010726SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst 41110726SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst 41210628SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 41310726SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst 41410726SN/Asystem.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst 41510585SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 41610585SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 41710726SN/Asystem.cpu.dtb.read_hits 167775531 # DTB read hits 41810726SN/Asystem.cpu.dtb.read_misses 155743 # DTB read misses 41910726SN/Asystem.cpu.dtb.write_hits 152648275 # DTB write hits 42010726SN/Asystem.cpu.dtb.write_misses 55578 # DTB write misses 42110585SN/Asystem.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 42210585SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 42310726SN/Asystem.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID 42410726SN/Asystem.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID 42510726SN/Asystem.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB 42610585SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 42710726SN/Asystem.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch 42810585SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 42910726SN/Asystem.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions 43010726SN/Asystem.cpu.dtb.read_accesses 167931274 # DTB read accesses 43110726SN/Asystem.cpu.dtb.write_accesses 152703853 # DTB write accesses 43210585SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 43310726SN/Asystem.cpu.dtb.hits 320423806 # DTB hits 43410726SN/Asystem.cpu.dtb.misses 211321 # DTB misses 43510726SN/Asystem.cpu.dtb.accesses 320635127 # DTB accesses 43610628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43710628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 43810628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43910628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44010628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44110628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 44210628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 44310628SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 44410585SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 44510585SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 44610585SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44710585SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 44810585SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 44910585SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 45010585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 45110585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45210585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 45310585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 45410585SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 45510585SN/Asystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 45610585SN/Asystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 45710585SN/Asystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 45810585SN/Asystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 45910585SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 46010585SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 46110585SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 46210585SN/Asystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 46310585SN/Asystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 46410585SN/Asystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 46510726SN/Asystem.cpu.itb.walker.walks 122916 # Table walker walks requested 46610726SN/Asystem.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors 46710726SN/Asystem.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate 46810726SN/Asystem.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate 46910726SN/Asystem.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency 47010726SN/Asystem.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency 47110726SN/Asystem.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency 47210726SN/Asystem.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency 47310726SN/Asystem.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency 47410726SN/Asystem.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency 47510726SN/Asystem.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency 47610726SN/Asystem.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency 47710726SN/Asystem.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency 47810726SN/Asystem.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency 47910726SN/Asystem.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency 48010726SN/Asystem.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency 48110726SN/Asystem.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency 48210726SN/Asystem.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency 48310726SN/Asystem.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency 48410726SN/Asystem.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency 48510726SN/Asystem.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency 48610726SN/Asystem.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency 48710726SN/Asystem.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency 48810726SN/Asystem.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 48910726SN/Asystem.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 49010726SN/Asystem.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 49110726SN/Asystem.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 49210726SN/Asystem.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency 49310726SN/Asystem.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution 49410726SN/Asystem.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution 49510726SN/Asystem.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution 49610726SN/Asystem.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated 49710726SN/Asystem.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated 49810726SN/Asystem.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated 49910628SN/Asystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 50010726SN/Asystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst 50110726SN/Asystem.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst 50210628SN/Asystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 50310726SN/Asystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst 50410726SN/Asystem.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst 50510726SN/Asystem.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst 50610726SN/Asystem.cpu.itb.inst_hits 894030670 # ITB inst hits 50710726SN/Asystem.cpu.itb.inst_misses 122916 # ITB inst misses 50810585SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 50910585SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 51010585SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 51110585SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 51210585SN/Asystem.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 51310585SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 51410726SN/Asystem.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID 51510726SN/Asystem.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID 51610726SN/Asystem.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB 51710585SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 51810585SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 51910585SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 52010585SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52110585SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 52210585SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 52310726SN/Asystem.cpu.itb.inst_accesses 894153586 # ITB inst accesses 52410726SN/Asystem.cpu.itb.hits 894030670 # DTB hits 52510726SN/Asystem.cpu.itb.misses 122916 # DTB misses 52610726SN/Asystem.cpu.itb.accesses 894153586 # DTB accesses 52710726SN/Asystem.cpu.numCycles 103648924201 # number of cpu cycles simulated 52810585SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 52910585SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 53010726SN/Asystem.cpu.committedInsts 893481288 # Number of instructions committed 53110726SN/Asystem.cpu.committedOps 1049881338 # Number of ops (including micro ops) committed 53210726SN/Asystem.cpu.num_int_alu_accesses 963989017 # Number of integer alu accesses 53310726SN/Asystem.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses 53410726SN/Asystem.cpu.num_func_calls 52999943 # number of times a function call or return occured 53510726SN/Asystem.cpu.num_conditional_control_insts 136446519 # number of instructions that are conditional controls 53610726SN/Asystem.cpu.num_int_insts 963989017 # number of integer instructions 53710726SN/Asystem.cpu.num_fp_insts 895873 # number of float instructions 53810726SN/Asystem.cpu.num_int_register_reads 1405913792 # number of times the integer registers were read 53910726SN/Asystem.cpu.num_int_register_writes 764688301 # number of times the integer registers were written 54010726SN/Asystem.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read 54110726SN/Asystem.cpu.num_fp_register_writes 760516 # number of times the floating registers were written 54210726SN/Asystem.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read 54310726SN/Asystem.cpu.num_cc_register_writes 234155899 # number of times the CC registers were written 54410726SN/Asystem.cpu.num_mem_refs 320407593 # number of memory refs 54510726SN/Asystem.cpu.num_load_insts 167768846 # Number of load instructions 54610726SN/Asystem.cpu.num_store_insts 152638747 # Number of store instructions 54710726SN/Asystem.cpu.num_idle_cycles 100474792122.552063 # Number of idle cycles 54810726SN/Asystem.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles 54910726SN/Asystem.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles 55010726SN/Asystem.cpu.idle_fraction 0.969376 # Percentage of idle cycles 55110726SN/Asystem.cpu.Branches 199584978 # Number of branches fetched 55210585SN/Asystem.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 55310726SN/Asystem.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction 55410726SN/Asystem.cpu.op_class::IntMult 2217476 0.21% 69.48% # Class of executed instruction 55510726SN/Asystem.cpu.op_class::IntDiv 99175 0.01% 69.49% # Class of executed instruction 55610585SN/Asystem.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction 55710585SN/Asystem.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction 55810585SN/Asystem.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction 55910585SN/Asystem.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction 56010585SN/Asystem.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction 56110585SN/Asystem.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction 56210585SN/Asystem.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction 56310585SN/Asystem.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction 56410585SN/Asystem.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction 56510585SN/Asystem.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction 56610585SN/Asystem.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction 56710585SN/Asystem.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction 56810585SN/Asystem.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction 56910585SN/Asystem.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction 57010585SN/Asystem.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction 57110585SN/Asystem.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction 57210585SN/Asystem.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction 57310585SN/Asystem.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction 57410585SN/Asystem.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction 57510585SN/Asystem.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction 57610585SN/Asystem.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction 57710585SN/Asystem.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction 57810726SN/Asystem.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction 57910585SN/Asystem.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction 58010585SN/Asystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction 58110585SN/Asystem.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction 58210726SN/Asystem.cpu.op_class::MemRead 167768846 15.97% 85.47% # Class of executed instruction 58310726SN/Asystem.cpu.op_class::MemWrite 152638747 14.53% 100.00% # Class of executed instruction 58410585SN/Asystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 58510585SN/Asystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 58610726SN/Asystem.cpu.op_class::total 1050473844 # Class of executed instruction 58710585SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 58810726SN/Asystem.cpu.kern.inst.quiesce 16327 # number of quiesce instructions executed 58910726SN/Asystem.cpu.dcache.tags.replacements 10213653 # number of replacements 59010726SN/Asystem.cpu.dcache.tags.tagsinuse 511.965664 # Cycle average of tags in use 59110726SN/Asystem.cpu.dcache.tags.total_refs 310015199 # Total number of references to valid blocks. 59210726SN/Asystem.cpu.dcache.tags.sampled_refs 10214165 # Sample count of references to valid blocks. 59310726SN/Asystem.cpu.dcache.tags.avg_refs 30.351497 # Average number of references to valid blocks. 59410726SN/Asystem.cpu.dcache.tags.warmup_cycle 3500615250 # Cycle when the warmup percentage was hit. 59510726SN/Asystem.cpu.dcache.tags.occ_blocks::cpu.data 511.965664 # Average occupied blocks per requestor 59610726SN/Asystem.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy 59710726SN/Asystem.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy 59810585SN/Asystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 59910726SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id 60010628SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id 60110726SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 60210726SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 60310585SN/Asystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 60410726SN/Asystem.cpu.dcache.tags.tag_accesses 1291569953 # Number of tag accesses 60510726SN/Asystem.cpu.dcache.tags.data_accesses 1291569953 # Number of data accesses 60610726SN/Asystem.cpu.dcache.ReadReq_hits::cpu.data 156758765 # number of ReadReq hits 60710726SN/Asystem.cpu.dcache.ReadReq_hits::total 156758765 # number of ReadReq hits 60810726SN/Asystem.cpu.dcache.WriteReq_hits::cpu.data 144836105 # number of WriteReq hits 60910726SN/Asystem.cpu.dcache.WriteReq_hits::total 144836105 # number of WriteReq hits 61010726SN/Asystem.cpu.dcache.SoftPFReq_hits::cpu.data 393576 # number of SoftPFReq hits 61110726SN/Asystem.cpu.dcache.SoftPFReq_hits::total 393576 # number of SoftPFReq hits 61210726SN/Asystem.cpu.dcache.WriteInvalidateReq_hits::cpu.data 334400 # number of WriteInvalidateReq hits 61310726SN/Asystem.cpu.dcache.WriteInvalidateReq_hits::total 334400 # number of WriteInvalidateReq hits 61410726SN/Asystem.cpu.dcache.LoadLockedReq_hits::cpu.data 3672090 # number of LoadLockedReq hits 61510726SN/Asystem.cpu.dcache.LoadLockedReq_hits::total 3672090 # number of LoadLockedReq hits 61610726SN/Asystem.cpu.dcache.StoreCondReq_hits::cpu.data 3974747 # number of StoreCondReq hits 61710726SN/Asystem.cpu.dcache.StoreCondReq_hits::total 3974747 # number of StoreCondReq hits 61810726SN/Asystem.cpu.dcache.demand_hits::cpu.data 301594870 # number of demand (read+write) hits 61910726SN/Asystem.cpu.dcache.demand_hits::total 301594870 # number of demand (read+write) hits 62010726SN/Asystem.cpu.dcache.overall_hits::cpu.data 301988446 # number of overall hits 62110726SN/Asystem.cpu.dcache.overall_hits::total 301988446 # number of overall hits 62210726SN/Asystem.cpu.dcache.ReadReq_misses::cpu.data 5315823 # number of ReadReq misses 62310726SN/Asystem.cpu.dcache.ReadReq_misses::total 5315823 # number of ReadReq misses 62410726SN/Asystem.cpu.dcache.WriteReq_misses::cpu.data 2219045 # number of WriteReq misses 62510726SN/Asystem.cpu.dcache.WriteReq_misses::total 2219045 # number of WriteReq misses 62610726SN/Asystem.cpu.dcache.SoftPFReq_misses::cpu.data 1297249 # number of SoftPFReq misses 62710726SN/Asystem.cpu.dcache.SoftPFReq_misses::total 1297249 # number of SoftPFReq misses 62810726SN/Asystem.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232796 # number of WriteInvalidateReq misses 62910726SN/Asystem.cpu.dcache.WriteInvalidateReq_misses::total 1232796 # number of WriteInvalidateReq misses 63010726SN/Asystem.cpu.dcache.LoadLockedReq_misses::cpu.data 304342 # number of LoadLockedReq misses 63110726SN/Asystem.cpu.dcache.LoadLockedReq_misses::total 304342 # number of LoadLockedReq misses 63210628SN/Asystem.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 63310628SN/Asystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 63410726SN/Asystem.cpu.dcache.demand_misses::cpu.data 7534868 # number of demand (read+write) misses 63510726SN/Asystem.cpu.dcache.demand_misses::total 7534868 # number of demand (read+write) misses 63610726SN/Asystem.cpu.dcache.overall_misses::cpu.data 8832117 # number of overall misses 63710726SN/Asystem.cpu.dcache.overall_misses::total 8832117 # number of overall misses 63810726SN/Asystem.cpu.dcache.ReadReq_miss_latency::cpu.data 84066704475 # number of ReadReq miss cycles 63910726SN/Asystem.cpu.dcache.ReadReq_miss_latency::total 84066704475 # number of ReadReq miss cycles 64010726SN/Asystem.cpu.dcache.WriteReq_miss_latency::cpu.data 66382286210 # number of WriteReq miss cycles 64110726SN/Asystem.cpu.dcache.WriteReq_miss_latency::total 66382286210 # number of WriteReq miss cycles 64210726SN/Asystem.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 32849513005 # number of WriteInvalidateReq miss cycles 64310726SN/Asystem.cpu.dcache.WriteInvalidateReq_miss_latency::total 32849513005 # number of WriteInvalidateReq miss cycles 64410726SN/Asystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4463810234 # number of LoadLockedReq miss cycles 64510726SN/Asystem.cpu.dcache.LoadLockedReq_miss_latency::total 4463810234 # number of LoadLockedReq miss cycles 64610726SN/Asystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles 64710726SN/Asystem.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles 64810726SN/Asystem.cpu.dcache.demand_miss_latency::cpu.data 150448990685 # number of demand (read+write) miss cycles 64910726SN/Asystem.cpu.dcache.demand_miss_latency::total 150448990685 # number of demand (read+write) miss cycles 65010726SN/Asystem.cpu.dcache.overall_miss_latency::cpu.data 150448990685 # number of overall miss cycles 65110726SN/Asystem.cpu.dcache.overall_miss_latency::total 150448990685 # number of overall miss cycles 65210726SN/Asystem.cpu.dcache.ReadReq_accesses::cpu.data 162074588 # number of ReadReq accesses(hits+misses) 65310726SN/Asystem.cpu.dcache.ReadReq_accesses::total 162074588 # number of ReadReq accesses(hits+misses) 65410726SN/Asystem.cpu.dcache.WriteReq_accesses::cpu.data 147055150 # number of WriteReq accesses(hits+misses) 65510726SN/Asystem.cpu.dcache.WriteReq_accesses::total 147055150 # number of WriteReq accesses(hits+misses) 65610726SN/Asystem.cpu.dcache.SoftPFReq_accesses::cpu.data 1690825 # number of SoftPFReq accesses(hits+misses) 65710726SN/Asystem.cpu.dcache.SoftPFReq_accesses::total 1690825 # number of SoftPFReq accesses(hits+misses) 65810726SN/Asystem.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1567196 # number of WriteInvalidateReq accesses(hits+misses) 65910726SN/Asystem.cpu.dcache.WriteInvalidateReq_accesses::total 1567196 # number of WriteInvalidateReq accesses(hits+misses) 66010726SN/Asystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 3976432 # number of LoadLockedReq accesses(hits+misses) 66110726SN/Asystem.cpu.dcache.LoadLockedReq_accesses::total 3976432 # number of LoadLockedReq accesses(hits+misses) 66210726SN/Asystem.cpu.dcache.StoreCondReq_accesses::cpu.data 3974749 # number of StoreCondReq accesses(hits+misses) 66310726SN/Asystem.cpu.dcache.StoreCondReq_accesses::total 3974749 # number of StoreCondReq accesses(hits+misses) 66410726SN/Asystem.cpu.dcache.demand_accesses::cpu.data 309129738 # number of demand (read+write) accesses 66510726SN/Asystem.cpu.dcache.demand_accesses::total 309129738 # number of demand (read+write) accesses 66610726SN/Asystem.cpu.dcache.overall_accesses::cpu.data 310820563 # number of overall (read+write) accesses 66710726SN/Asystem.cpu.dcache.overall_accesses::total 310820563 # number of overall (read+write) accesses 66810726SN/Asystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032799 # miss rate for ReadReq accesses 66910726SN/Asystem.cpu.dcache.ReadReq_miss_rate::total 0.032799 # miss rate for ReadReq accesses 67010726SN/Asystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015090 # miss rate for WriteReq accesses 67110726SN/Asystem.cpu.dcache.WriteReq_miss_rate::total 0.015090 # miss rate for WriteReq accesses 67210726SN/Asystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767228 # miss rate for SoftPFReq accesses 67310726SN/Asystem.cpu.dcache.SoftPFReq_miss_rate::total 0.767228 # miss rate for SoftPFReq accesses 67410726SN/Asystem.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786625 # miss rate for WriteInvalidateReq accesses 67510726SN/Asystem.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786625 # miss rate for WriteInvalidateReq accesses 67610726SN/Asystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076536 # miss rate for LoadLockedReq accesses 67710726SN/Asystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.076536 # miss rate for LoadLockedReq accesses 67810726SN/Asystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 67910726SN/Asystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 68010726SN/Asystem.cpu.dcache.demand_miss_rate::cpu.data 0.024374 # miss rate for demand accesses 68110726SN/Asystem.cpu.dcache.demand_miss_rate::total 0.024374 # miss rate for demand accesses 68210726SN/Asystem.cpu.dcache.overall_miss_rate::cpu.data 0.028415 # miss rate for overall accesses 68310726SN/Asystem.cpu.dcache.overall_miss_rate::total 0.028415 # miss rate for overall accesses 68410726SN/Asystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15814.428824 # average ReadReq miss latency 68510726SN/Asystem.cpu.dcache.ReadReq_avg_miss_latency::total 15814.428824 # average ReadReq miss latency 68610726SN/Asystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29914.799479 # average WriteReq miss latency 68710726SN/Asystem.cpu.dcache.WriteReq_avg_miss_latency::total 29914.799479 # average WriteReq miss latency 68810726SN/Asystem.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 26646.349441 # average WriteInvalidateReq miss latency 68910726SN/Asystem.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 26646.349441 # average WriteInvalidateReq miss latency 69010726SN/Asystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14667.085825 # average LoadLockedReq miss latency 69110726SN/Asystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14667.085825 # average LoadLockedReq miss latency 69210726SN/Asystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 69310726SN/Asystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency 69410726SN/Asystem.cpu.dcache.demand_avg_miss_latency::cpu.data 19967.037337 # average overall miss latency 69510726SN/Asystem.cpu.dcache.demand_avg_miss_latency::total 19967.037337 # average overall miss latency 69610726SN/Asystem.cpu.dcache.overall_avg_miss_latency::cpu.data 17034.306802 # average overall miss latency 69710726SN/Asystem.cpu.dcache.overall_avg_miss_latency::total 17034.306802 # average overall miss latency 69810585SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 69910585SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 70010585SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 70110585SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 70210585SN/Asystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 70310585SN/Asystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 70410585SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 70510585SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 70610726SN/Asystem.cpu.dcache.writebacks::writebacks 7878976 # number of writebacks 70710726SN/Asystem.cpu.dcache.writebacks::total 7878976 # number of writebacks 70810726SN/Asystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 16016 # number of ReadReq MSHR hits 70910726SN/Asystem.cpu.dcache.ReadReq_mshr_hits::total 16016 # number of ReadReq MSHR hits 71010726SN/Asystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 21118 # number of WriteReq MSHR hits 71110726SN/Asystem.cpu.dcache.WriteReq_mshr_hits::total 21118 # number of WriteReq MSHR hits 71210726SN/Asystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70685 # number of LoadLockedReq MSHR hits 71310726SN/Asystem.cpu.dcache.LoadLockedReq_mshr_hits::total 70685 # number of LoadLockedReq MSHR hits 71410726SN/Asystem.cpu.dcache.demand_mshr_hits::cpu.data 37134 # number of demand (read+write) MSHR hits 71510726SN/Asystem.cpu.dcache.demand_mshr_hits::total 37134 # number of demand (read+write) MSHR hits 71610726SN/Asystem.cpu.dcache.overall_mshr_hits::cpu.data 37134 # number of overall MSHR hits 71710726SN/Asystem.cpu.dcache.overall_mshr_hits::total 37134 # number of overall MSHR hits 71810726SN/Asystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 5299807 # number of ReadReq MSHR misses 71910726SN/Asystem.cpu.dcache.ReadReq_mshr_misses::total 5299807 # number of ReadReq MSHR misses 72010726SN/Asystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 2197927 # number of WriteReq MSHR misses 72110726SN/Asystem.cpu.dcache.WriteReq_mshr_misses::total 2197927 # number of WriteReq MSHR misses 72210726SN/Asystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1295520 # number of SoftPFReq MSHR misses 72310726SN/Asystem.cpu.dcache.SoftPFReq_mshr_misses::total 1295520 # number of SoftPFReq MSHR misses 72410726SN/Asystem.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1232796 # number of WriteInvalidateReq MSHR misses 72510726SN/Asystem.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1232796 # number of WriteInvalidateReq MSHR misses 72610726SN/Asystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233657 # number of LoadLockedReq MSHR misses 72710726SN/Asystem.cpu.dcache.LoadLockedReq_mshr_misses::total 233657 # number of LoadLockedReq MSHR misses 72810628SN/Asystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 72910628SN/Asystem.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 73010726SN/Asystem.cpu.dcache.demand_mshr_misses::cpu.data 7497734 # number of demand (read+write) MSHR misses 73110726SN/Asystem.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses 73210726SN/Asystem.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses 73310726SN/Asystem.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses 73410827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 73510827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable 73610827Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 73710827Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 73810827Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 73910827Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses 74010726SN/Asystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles 74110726SN/Asystem.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles 74210726SN/Asystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles 74310726SN/Asystem.cpu.dcache.WriteReq_mshr_miss_latency::total 62224351540 # number of WriteReq MSHR miss cycles 74410726SN/Asystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20153084274 # number of SoftPFReq MSHR miss cycles 74510726SN/Asystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20153084274 # number of SoftPFReq MSHR miss cycles 74610726SN/Asystem.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31000318995 # number of WriteInvalidateReq MSHR miss cycles 74710726SN/Asystem.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 31000318995 # number of WriteInvalidateReq MSHR miss cycles 74810726SN/Asystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2998156750 # number of LoadLockedReq MSHR miss cycles 74910726SN/Asystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2998156750 # number of LoadLockedReq MSHR miss cycles 75010726SN/Asystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles 75110726SN/Asystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles 75210726SN/Asystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065 # number of demand (read+write) MSHR miss cycles 75310726SN/Asystem.cpu.dcache.demand_mshr_miss_latency::total 137713909065 # number of demand (read+write) MSHR miss cycles 75410726SN/Asystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339 # number of overall MSHR miss cycles 75510726SN/Asystem.cpu.dcache.overall_mshr_miss_latency::total 157866993339 # number of overall MSHR miss cycles 75610726SN/Asystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751194250 # number of ReadReq MSHR uncacheable cycles 75710726SN/Asystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751194250 # number of ReadReq MSHR uncacheable cycles 75810726SN/Asystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5618584250 # number of WriteReq MSHR uncacheable cycles 75910726SN/Asystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5618584250 # number of WriteReq MSHR uncacheable cycles 76010726SN/Asystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369778500 # number of overall MSHR uncacheable cycles 76110726SN/Asystem.cpu.dcache.overall_mshr_uncacheable_latency::total 11369778500 # number of overall MSHR uncacheable cycles 76210726SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032700 # mshr miss rate for ReadReq accesses 76310726SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032700 # mshr miss rate for ReadReq accesses 76410726SN/Asystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014946 # mshr miss rate for WriteReq accesses 76510726SN/Asystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014946 # mshr miss rate for WriteReq accesses 76610726SN/Asystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766206 # mshr miss rate for SoftPFReq accesses 76710726SN/Asystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766206 # mshr miss rate for SoftPFReq accesses 76810726SN/Asystem.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786625 # mshr miss rate for WriteInvalidateReq accesses 76910726SN/Asystem.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786625 # mshr miss rate for WriteInvalidateReq accesses 77010726SN/Asystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058760 # mshr miss rate for LoadLockedReq accesses 77110726SN/Asystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058760 # mshr miss rate for LoadLockedReq accesses 77210726SN/Asystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 77310726SN/Asystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 77410726SN/Asystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024254 # mshr miss rate for demand accesses 77510726SN/Asystem.cpu.dcache.demand_mshr_miss_rate::total 0.024254 # mshr miss rate for demand accesses 77610726SN/Asystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028290 # mshr miss rate for overall accesses 77710726SN/Asystem.cpu.dcache.overall_mshr_miss_rate::total 0.028290 # mshr miss rate for overall accesses 77810726SN/Asystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14243.831431 # average ReadReq mshr miss latency 77910726SN/Asystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14243.831431 # average ReadReq mshr miss latency 78010726SN/Asystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28310.472341 # average WriteReq mshr miss latency 78110726SN/Asystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28310.472341 # average WriteReq mshr miss latency 78210726SN/Asystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15555.980822 # average SoftPFReq mshr miss latency 78310726SN/Asystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15555.980822 # average SoftPFReq mshr miss latency 78410726SN/Asystem.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 25146.349433 # average WriteInvalidateReq mshr miss latency 78510726SN/Asystem.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25146.349433 # average WriteInvalidateReq mshr miss latency 78610726SN/Asystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168 # average LoadLockedReq mshr miss latency 78710726SN/Asystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168 # average LoadLockedReq mshr miss latency 78810726SN/Asystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency 78910726SN/Asystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency 79010726SN/Asystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 # average overall mshr miss latency 79110726SN/Asystem.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency 79210726SN/Asystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency 79310726SN/Asystem.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency 79410827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170628.204177 # average ReadReq mshr uncacheable latency 79510827Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.204177 # average ReadReq mshr uncacheable latency 79610827Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166674.110056 # average WriteReq mshr uncacheable latency 79710827Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.110056 # average WriteReq mshr uncacheable latency 79810827Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168651.039813 # average overall mshr uncacheable latency 79910827Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168651.039813 # average overall mshr uncacheable latency 80010585SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 80110726SN/Asystem.cpu.icache.tags.replacements 13753173 # number of replacements 80210726SN/Asystem.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use 80310726SN/Asystem.cpu.icache.tags.total_refs 880276980 # Total number of references to valid blocks. 80410726SN/Asystem.cpu.icache.tags.sampled_refs 13753685 # Sample count of references to valid blocks. 80510726SN/Asystem.cpu.icache.tags.avg_refs 64.002991 # Average number of references to valid blocks. 80610726SN/Asystem.cpu.icache.tags.warmup_cycle 35133104250 # Cycle when the warmup percentage was hit. 80710726SN/Asystem.cpu.icache.tags.occ_blocks::cpu.inst 511.880059 # Average occupied blocks per requestor 80810726SN/Asystem.cpu.icache.tags.occ_percent::cpu.inst 0.999766 # Average percentage of cache occupancy 80910726SN/Asystem.cpu.icache.tags.occ_percent::total 0.999766 # Average percentage of cache occupancy 81010585SN/Asystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 81110628SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 81210726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id 81310726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id 81410726SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 81510585SN/Asystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 81610726SN/Asystem.cpu.icache.tags.tag_accesses 907784360 # Number of tag accesses 81710726SN/Asystem.cpu.icache.tags.data_accesses 907784360 # Number of data accesses 81810726SN/Asystem.cpu.icache.ReadReq_hits::cpu.inst 880276980 # number of ReadReq hits 81910726SN/Asystem.cpu.icache.ReadReq_hits::total 880276980 # number of ReadReq hits 82010726SN/Asystem.cpu.icache.demand_hits::cpu.inst 880276980 # number of demand (read+write) hits 82110726SN/Asystem.cpu.icache.demand_hits::total 880276980 # number of demand (read+write) hits 82210726SN/Asystem.cpu.icache.overall_hits::cpu.inst 880276980 # number of overall hits 82310726SN/Asystem.cpu.icache.overall_hits::total 880276980 # number of overall hits 82410726SN/Asystem.cpu.icache.ReadReq_misses::cpu.inst 13753690 # number of ReadReq misses 82510726SN/Asystem.cpu.icache.ReadReq_misses::total 13753690 # number of ReadReq misses 82610726SN/Asystem.cpu.icache.demand_misses::cpu.inst 13753690 # number of demand (read+write) misses 82710726SN/Asystem.cpu.icache.demand_misses::total 13753690 # number of demand (read+write) misses 82810726SN/Asystem.cpu.icache.overall_misses::cpu.inst 13753690 # number of overall misses 82910726SN/Asystem.cpu.icache.overall_misses::total 13753690 # number of overall misses 83010726SN/Asystem.cpu.icache.ReadReq_miss_latency::cpu.inst 184520052183 # number of ReadReq miss cycles 83110726SN/Asystem.cpu.icache.ReadReq_miss_latency::total 184520052183 # number of ReadReq miss cycles 83210726SN/Asystem.cpu.icache.demand_miss_latency::cpu.inst 184520052183 # number of demand (read+write) miss cycles 83310726SN/Asystem.cpu.icache.demand_miss_latency::total 184520052183 # number of demand (read+write) miss cycles 83410726SN/Asystem.cpu.icache.overall_miss_latency::cpu.inst 184520052183 # number of overall miss cycles 83510726SN/Asystem.cpu.icache.overall_miss_latency::total 184520052183 # number of overall miss cycles 83610726SN/Asystem.cpu.icache.ReadReq_accesses::cpu.inst 894030670 # number of ReadReq accesses(hits+misses) 83710726SN/Asystem.cpu.icache.ReadReq_accesses::total 894030670 # number of ReadReq accesses(hits+misses) 83810726SN/Asystem.cpu.icache.demand_accesses::cpu.inst 894030670 # number of demand (read+write) accesses 83910726SN/Asystem.cpu.icache.demand_accesses::total 894030670 # number of demand (read+write) accesses 84010726SN/Asystem.cpu.icache.overall_accesses::cpu.inst 894030670 # number of overall (read+write) accesses 84110726SN/Asystem.cpu.icache.overall_accesses::total 894030670 # number of overall (read+write) accesses 84210726SN/Asystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015384 # miss rate for ReadReq accesses 84310726SN/Asystem.cpu.icache.ReadReq_miss_rate::total 0.015384 # miss rate for ReadReq accesses 84410726SN/Asystem.cpu.icache.demand_miss_rate::cpu.inst 0.015384 # miss rate for demand accesses 84510726SN/Asystem.cpu.icache.demand_miss_rate::total 0.015384 # miss rate for demand accesses 84610726SN/Asystem.cpu.icache.overall_miss_rate::cpu.inst 0.015384 # miss rate for overall accesses 84710726SN/Asystem.cpu.icache.overall_miss_rate::total 0.015384 # miss rate for overall accesses 84810726SN/Asystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13416.039782 # average ReadReq miss latency 84910726SN/Asystem.cpu.icache.ReadReq_avg_miss_latency::total 13416.039782 # average ReadReq miss latency 85010726SN/Asystem.cpu.icache.demand_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency 85110726SN/Asystem.cpu.icache.demand_avg_miss_latency::total 13416.039782 # average overall miss latency 85210726SN/Asystem.cpu.icache.overall_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency 85310726SN/Asystem.cpu.icache.overall_avg_miss_latency::total 13416.039782 # average overall miss latency 85410585SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 85510585SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85610585SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 85710585SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 85810585SN/Asystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 85910585SN/Asystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 86010585SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 86110585SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 86210726SN/Asystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 13753690 # number of ReadReq MSHR misses 86310726SN/Asystem.cpu.icache.ReadReq_mshr_misses::total 13753690 # number of ReadReq MSHR misses 86410726SN/Asystem.cpu.icache.demand_mshr_misses::cpu.inst 13753690 # number of demand (read+write) MSHR misses 86510726SN/Asystem.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses 86610726SN/Asystem.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses 86710726SN/Asystem.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses 86810827Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 86910827Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 87010827Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 87110827Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 87210726SN/Asystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles 87310726SN/Asystem.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles 87410726SN/Asystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles 87510726SN/Asystem.cpu.icache.demand_mshr_miss_latency::total 163860958817 # number of demand (read+write) MSHR miss cycles 87610726SN/Asystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 163860958817 # number of overall MSHR miss cycles 87710726SN/Asystem.cpu.icache.overall_mshr_miss_latency::total 163860958817 # number of overall MSHR miss cycles 87810726SN/Asystem.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3211087000 # number of ReadReq MSHR uncacheable cycles 87910726SN/Asystem.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3211087000 # number of ReadReq MSHR uncacheable cycles 88010726SN/Asystem.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3211087000 # number of overall MSHR uncacheable cycles 88110726SN/Asystem.cpu.icache.overall_mshr_uncacheable_latency::total 3211087000 # number of overall MSHR uncacheable cycles 88210726SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for ReadReq accesses 88310726SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.015384 # mshr miss rate for ReadReq accesses 88410726SN/Asystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for demand accesses 88510726SN/Asystem.cpu.icache.demand_mshr_miss_rate::total 0.015384 # mshr miss rate for demand accesses 88610726SN/Asystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for overall accesses 88710726SN/Asystem.cpu.icache.overall_mshr_miss_rate::total 0.015384 # mshr miss rate for overall accesses 88810726SN/Asystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11913.963367 # average ReadReq mshr miss latency 88910726SN/Asystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11913.963367 # average ReadReq mshr miss latency 89010726SN/Asystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency 89110726SN/Asystem.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency 89210726SN/Asystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency 89310726SN/Asystem.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency 89410827Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average ReadReq mshr uncacheable latency 89510827Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74459.988406 # average ReadReq mshr uncacheable latency 89610827Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average overall mshr uncacheable latency 89710827Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74459.988406 # average overall mshr uncacheable latency 89810585SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 89910726SN/Asystem.cpu.l2cache.tags.replacements 1292250 # number of replacements 90010726SN/Asystem.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use 90110726SN/Asystem.cpu.l2cache.tags.total_refs 27666738 # Total number of references to valid blocks. 90210726SN/Asystem.cpu.l2cache.tags.sampled_refs 1355280 # Sample count of references to valid blocks. 90310726SN/Asystem.cpu.l2cache.tags.avg_refs 20.414038 # Average number of references to valid blocks. 90410726SN/Asystem.cpu.l2cache.tags.warmup_cycle 7588597000 # Cycle when the warmup percentage was hit. 90510726SN/Asystem.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923 # Average occupied blocks per requestor 90610726SN/Asystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 308.197317 # Average occupied blocks per requestor 90710726SN/Asystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.773838 # Average occupied blocks per requestor 90810726SN/Asystem.cpu.l2cache.tags.occ_blocks::cpu.inst 6468.758735 # Average occupied blocks per requestor 90910726SN/Asystem.cpu.l2cache.tags.occ_blocks::cpu.data 19751.242576 # Average occupied blocks per requestor 91010726SN/Asystem.cpu.l2cache.tags.occ_percent::writebacks 0.585064 # Average percentage of cache occupancy 91110726SN/Asystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004703 # Average percentage of cache occupancy 91210726SN/Asystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006420 # Average percentage of cache occupancy 91310726SN/Asystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.098705 # Average percentage of cache occupancy 91410726SN/Asystem.cpu.l2cache.tags.occ_percent::cpu.data 0.301380 # Average percentage of cache occupancy 91510726SN/Asystem.cpu.l2cache.tags.occ_percent::total 0.996273 # Average percentage of cache occupancy 91610726SN/Asystem.cpu.l2cache.tags.occ_task_id_blocks::1023 297 # Occupied blocks per task id 91710726SN/Asystem.cpu.l2cache.tags.occ_task_id_blocks::1024 62733 # Occupied blocks per task id 91810726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 91910726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id 92010726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 92110726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id 92210726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2458 # Occupied blocks per task id 92310726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 5452 # Occupied blocks per task id 92410726SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 54401 # Occupied blocks per task id 92510726SN/Asystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.004532 # Percentage of cache occupancy per task id 92610726SN/Asystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.957230 # Percentage of cache occupancy per task id 92710726SN/Asystem.cpu.l2cache.tags.tag_accesses 264471216 # Number of tag accesses 92810726SN/Asystem.cpu.l2cache.tags.data_accesses 264471216 # Number of data accesses 92910726SN/Asystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 371629 # number of ReadReq hits 93010726SN/Asystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250715 # number of ReadReq hits 93110726SN/Asystem.cpu.l2cache.ReadReq_hits::cpu.inst 13674158 # number of ReadReq hits 93210726SN/Asystem.cpu.l2cache.ReadReq_hits::cpu.data 6553954 # number of ReadReq hits 93310726SN/Asystem.cpu.l2cache.ReadReq_hits::total 20850456 # number of ReadReq hits 93410726SN/Asystem.cpu.l2cache.Writeback_hits::writebacks 7878976 # number of Writeback hits 93510726SN/Asystem.cpu.l2cache.Writeback_hits::total 7878976 # number of Writeback hits 93610726SN/Asystem.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 723057 # number of WriteInvalidateReq hits 93710726SN/Asystem.cpu.l2cache.WriteInvalidateReq_hits::total 723057 # number of WriteInvalidateReq hits 93810726SN/Asystem.cpu.l2cache.UpgradeReq_hits::cpu.data 9863 # number of UpgradeReq hits 93910726SN/Asystem.cpu.l2cache.UpgradeReq_hits::total 9863 # number of UpgradeReq hits 94010726SN/Asystem.cpu.l2cache.ReadExReq_hits::cpu.data 1639498 # number of ReadExReq hits 94110726SN/Asystem.cpu.l2cache.ReadExReq_hits::total 1639498 # number of ReadExReq hits 94210726SN/Asystem.cpu.l2cache.demand_hits::cpu.dtb.walker 371629 # number of demand (read+write) hits 94310726SN/Asystem.cpu.l2cache.demand_hits::cpu.itb.walker 250715 # number of demand (read+write) hits 94410726SN/Asystem.cpu.l2cache.demand_hits::cpu.inst 13674158 # number of demand (read+write) hits 94510726SN/Asystem.cpu.l2cache.demand_hits::cpu.data 8193452 # number of demand (read+write) hits 94610726SN/Asystem.cpu.l2cache.demand_hits::total 22489954 # number of demand (read+write) hits 94710726SN/Asystem.cpu.l2cache.overall_hits::cpu.dtb.walker 371629 # number of overall hits 94810726SN/Asystem.cpu.l2cache.overall_hits::cpu.itb.walker 250715 # number of overall hits 94910726SN/Asystem.cpu.l2cache.overall_hits::cpu.inst 13674158 # number of overall hits 95010726SN/Asystem.cpu.l2cache.overall_hits::cpu.data 8193452 # number of overall hits 95110726SN/Asystem.cpu.l2cache.overall_hits::total 22489954 # number of overall hits 95210726SN/Asystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4157 # number of ReadReq misses 95310726SN/Asystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4054 # number of ReadReq misses 95410726SN/Asystem.cpu.l2cache.ReadReq_misses::cpu.inst 79532 # number of ReadReq misses 95510726SN/Asystem.cpu.l2cache.ReadReq_misses::cpu.data 275030 # number of ReadReq misses 95610726SN/Asystem.cpu.l2cache.ReadReq_misses::total 362773 # number of ReadReq misses 95710726SN/Asystem.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 509738 # number of WriteInvalidateReq misses 95810726SN/Asystem.cpu.l2cache.WriteInvalidateReq_misses::total 509738 # number of WriteInvalidateReq misses 95910726SN/Asystem.cpu.l2cache.UpgradeReq_misses::cpu.data 35651 # number of UpgradeReq misses 96010726SN/Asystem.cpu.l2cache.UpgradeReq_misses::total 35651 # number of UpgradeReq misses 96110628SN/Asystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 96210628SN/Asystem.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 96310726SN/Asystem.cpu.l2cache.ReadExReq_misses::cpu.data 512916 # number of ReadExReq misses 96410726SN/Asystem.cpu.l2cache.ReadExReq_misses::total 512916 # number of ReadExReq misses 96510726SN/Asystem.cpu.l2cache.demand_misses::cpu.dtb.walker 4157 # number of demand (read+write) misses 96610726SN/Asystem.cpu.l2cache.demand_misses::cpu.itb.walker 4054 # number of demand (read+write) misses 96710726SN/Asystem.cpu.l2cache.demand_misses::cpu.inst 79532 # number of demand (read+write) misses 96810726SN/Asystem.cpu.l2cache.demand_misses::cpu.data 787946 # number of demand (read+write) misses 96910726SN/Asystem.cpu.l2cache.demand_misses::total 875689 # number of demand (read+write) misses 97010726SN/Asystem.cpu.l2cache.overall_misses::cpu.dtb.walker 4157 # number of overall misses 97110726SN/Asystem.cpu.l2cache.overall_misses::cpu.itb.walker 4054 # number of overall misses 97210726SN/Asystem.cpu.l2cache.overall_misses::cpu.inst 79532 # number of overall misses 97310726SN/Asystem.cpu.l2cache.overall_misses::cpu.data 787946 # number of overall misses 97410726SN/Asystem.cpu.l2cache.overall_misses::total 875689 # number of overall misses 97510726SN/Asystem.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 357827500 # number of ReadReq miss cycles 97610726SN/Asystem.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 356872250 # number of ReadReq miss cycles 97710726SN/Asystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6528298780 # number of ReadReq miss cycles 97810726SN/Asystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 22994549799 # number of ReadReq miss cycles 97910726SN/Asystem.cpu.l2cache.ReadReq_miss_latency::total 30237548329 # number of ReadReq miss cycles 98010726SN/Asystem.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 123996 # number of WriteInvalidateReq miss cycles 98110726SN/Asystem.cpu.l2cache.WriteInvalidateReq_miss_latency::total 123996 # number of WriteInvalidateReq miss cycles 98210726SN/Asystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 554901623 # number of UpgradeReq miss cycles 98310726SN/Asystem.cpu.l2cache.UpgradeReq_miss_latency::total 554901623 # number of UpgradeReq miss cycles 98410726SN/Asystem.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles 98510726SN/Asystem.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles 98610726SN/Asystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41601774937 # number of ReadExReq miss cycles 98710726SN/Asystem.cpu.l2cache.ReadExReq_miss_latency::total 41601774937 # number of ReadExReq miss cycles 98810726SN/Asystem.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 357827500 # number of demand (read+write) miss cycles 98910726SN/Asystem.cpu.l2cache.demand_miss_latency::cpu.itb.walker 356872250 # number of demand (read+write) miss cycles 99010726SN/Asystem.cpu.l2cache.demand_miss_latency::cpu.inst 6528298780 # number of demand (read+write) miss cycles 99110726SN/Asystem.cpu.l2cache.demand_miss_latency::cpu.data 64596324736 # number of demand (read+write) miss cycles 99210726SN/Asystem.cpu.l2cache.demand_miss_latency::total 71839323266 # number of demand (read+write) miss cycles 99310726SN/Asystem.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 357827500 # number of overall miss cycles 99410726SN/Asystem.cpu.l2cache.overall_miss_latency::cpu.itb.walker 356872250 # number of overall miss cycles 99510726SN/Asystem.cpu.l2cache.overall_miss_latency::cpu.inst 6528298780 # number of overall miss cycles 99610726SN/Asystem.cpu.l2cache.overall_miss_latency::cpu.data 64596324736 # number of overall miss cycles 99710726SN/Asystem.cpu.l2cache.overall_miss_latency::total 71839323266 # number of overall miss cycles 99810726SN/Asystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 375786 # number of ReadReq accesses(hits+misses) 99910726SN/Asystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 254769 # number of ReadReq accesses(hits+misses) 100010726SN/Asystem.cpu.l2cache.ReadReq_accesses::cpu.inst 13753690 # number of ReadReq accesses(hits+misses) 100110726SN/Asystem.cpu.l2cache.ReadReq_accesses::cpu.data 6828984 # number of ReadReq accesses(hits+misses) 100210726SN/Asystem.cpu.l2cache.ReadReq_accesses::total 21213229 # number of ReadReq accesses(hits+misses) 100310726SN/Asystem.cpu.l2cache.Writeback_accesses::writebacks 7878976 # number of Writeback accesses(hits+misses) 100410726SN/Asystem.cpu.l2cache.Writeback_accesses::total 7878976 # number of Writeback accesses(hits+misses) 100510726SN/Asystem.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1232795 # number of WriteInvalidateReq accesses(hits+misses) 100610726SN/Asystem.cpu.l2cache.WriteInvalidateReq_accesses::total 1232795 # number of WriteInvalidateReq accesses(hits+misses) 100710726SN/Asystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 45514 # number of UpgradeReq accesses(hits+misses) 100810726SN/Asystem.cpu.l2cache.UpgradeReq_accesses::total 45514 # number of UpgradeReq accesses(hits+misses) 100910628SN/Asystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 101010628SN/Asystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 101110726SN/Asystem.cpu.l2cache.ReadExReq_accesses::cpu.data 2152414 # number of ReadExReq accesses(hits+misses) 101210726SN/Asystem.cpu.l2cache.ReadExReq_accesses::total 2152414 # number of ReadExReq accesses(hits+misses) 101310726SN/Asystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 375786 # number of demand (read+write) accesses 101410726SN/Asystem.cpu.l2cache.demand_accesses::cpu.itb.walker 254769 # number of demand (read+write) accesses 101510726SN/Asystem.cpu.l2cache.demand_accesses::cpu.inst 13753690 # number of demand (read+write) accesses 101610726SN/Asystem.cpu.l2cache.demand_accesses::cpu.data 8981398 # number of demand (read+write) accesses 101710726SN/Asystem.cpu.l2cache.demand_accesses::total 23365643 # number of demand (read+write) accesses 101810726SN/Asystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 375786 # number of overall (read+write) accesses 101910726SN/Asystem.cpu.l2cache.overall_accesses::cpu.itb.walker 254769 # number of overall (read+write) accesses 102010726SN/Asystem.cpu.l2cache.overall_accesses::cpu.inst 13753690 # number of overall (read+write) accesses 102110726SN/Asystem.cpu.l2cache.overall_accesses::cpu.data 8981398 # number of overall (read+write) accesses 102210726SN/Asystem.cpu.l2cache.overall_accesses::total 23365643 # number of overall (read+write) accesses 102310726SN/Asystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011062 # miss rate for ReadReq accesses 102410726SN/Asystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.015912 # miss rate for ReadReq accesses 102510726SN/Asystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005783 # miss rate for ReadReq accesses 102610726SN/Asystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.040274 # miss rate for ReadReq accesses 102710726SN/Asystem.cpu.l2cache.ReadReq_miss_rate::total 0.017101 # miss rate for ReadReq accesses 102810726SN/Asystem.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.413482 # miss rate for WriteInvalidateReq accesses 102910726SN/Asystem.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.413482 # miss rate for WriteInvalidateReq accesses 103010726SN/Asystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783297 # miss rate for UpgradeReq accesses 103110726SN/Asystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.783297 # miss rate for UpgradeReq accesses 103210585SN/Asystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 103310585SN/Asystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 103410726SN/Asystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238298 # miss rate for ReadExReq accesses 103510726SN/Asystem.cpu.l2cache.ReadExReq_miss_rate::total 0.238298 # miss rate for ReadExReq accesses 103610726SN/Asystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.011062 # miss rate for demand accesses 103710726SN/Asystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.015912 # miss rate for demand accesses 103810726SN/Asystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.005783 # miss rate for demand accesses 103910726SN/Asystem.cpu.l2cache.demand_miss_rate::cpu.data 0.087731 # miss rate for demand accesses 104010726SN/Asystem.cpu.l2cache.demand_miss_rate::total 0.037478 # miss rate for demand accesses 104110726SN/Asystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.011062 # miss rate for overall accesses 104210726SN/Asystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.015912 # miss rate for overall accesses 104310726SN/Asystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.005783 # miss rate for overall accesses 104410726SN/Asystem.cpu.l2cache.overall_miss_rate::cpu.data 0.087731 # miss rate for overall accesses 104510726SN/Asystem.cpu.l2cache.overall_miss_rate::total 0.037478 # miss rate for overall accesses 104610726SN/Asystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86078.301660 # average ReadReq miss latency 104710726SN/Asystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88029.662062 # average ReadReq miss latency 104810726SN/Asystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82083.925715 # average ReadReq miss latency 104910726SN/Asystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83607.423914 # average ReadReq miss latency 105010726SN/Asystem.cpu.l2cache.ReadReq_avg_miss_latency::total 83351.154383 # average ReadReq miss latency 105110726SN/Asystem.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 0.243254 # average WriteInvalidateReq miss latency 105210726SN/Asystem.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 0.243254 # average WriteInvalidateReq miss latency 105310726SN/Asystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15564.826316 # average UpgradeReq miss latency 105410726SN/Asystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15564.826316 # average UpgradeReq miss latency 105510726SN/Asystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 105610726SN/Asystem.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 105710726SN/Asystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81108.358751 # average ReadExReq miss latency 105810726SN/Asystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 81108.358751 # average ReadExReq miss latency 105910726SN/Asystem.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency 106010726SN/Asystem.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency 106110726SN/Asystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency 106210726SN/Asystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency 106310726SN/Asystem.cpu.l2cache.demand_avg_miss_latency::total 82037.485073 # average overall miss latency 106410726SN/Asystem.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency 106510726SN/Asystem.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency 106610726SN/Asystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency 106710726SN/Asystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency 106810726SN/Asystem.cpu.l2cache.overall_avg_miss_latency::total 82037.485073 # average overall miss latency 106910585SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 107010585SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 107110585SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 107210585SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 107310585SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 107410585SN/Asystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 107510585SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 107610585SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 107710726SN/Asystem.cpu.l2cache.writebacks::writebacks 1107523 # number of writebacks 107810726SN/Asystem.cpu.l2cache.writebacks::total 1107523 # number of writebacks 107910726SN/Asystem.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4157 # number of ReadReq MSHR misses 108010726SN/Asystem.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4054 # number of ReadReq MSHR misses 108110726SN/Asystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 79532 # number of ReadReq MSHR misses 108210726SN/Asystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 275030 # number of ReadReq MSHR misses 108310726SN/Asystem.cpu.l2cache.ReadReq_mshr_misses::total 362773 # number of ReadReq MSHR misses 108410726SN/Asystem.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 509738 # number of WriteInvalidateReq MSHR misses 108510726SN/Asystem.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 509738 # number of WriteInvalidateReq MSHR misses 108610726SN/Asystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35651 # number of UpgradeReq MSHR misses 108710726SN/Asystem.cpu.l2cache.UpgradeReq_mshr_misses::total 35651 # number of UpgradeReq MSHR misses 108810628SN/Asystem.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 108910628SN/Asystem.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 109010726SN/Asystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 512916 # number of ReadExReq MSHR misses 109110726SN/Asystem.cpu.l2cache.ReadExReq_mshr_misses::total 512916 # number of ReadExReq MSHR misses 109210726SN/Asystem.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4157 # number of demand (read+write) MSHR misses 109310726SN/Asystem.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4054 # number of demand (read+write) MSHR misses 109410726SN/Asystem.cpu.l2cache.demand_mshr_misses::cpu.inst 79532 # number of demand (read+write) MSHR misses 109510726SN/Asystem.cpu.l2cache.demand_mshr_misses::cpu.data 787946 # number of demand (read+write) MSHR misses 109610726SN/Asystem.cpu.l2cache.demand_mshr_misses::total 875689 # number of demand (read+write) MSHR misses 109710726SN/Asystem.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4157 # number of overall MSHR misses 109810726SN/Asystem.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4054 # number of overall MSHR misses 109910726SN/Asystem.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses 110010726SN/Asystem.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses 110110726SN/Asystem.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses 110210827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 110310827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 110410827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable 110510827Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 110610827Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 110710827Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 110810827Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 110910827Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses 111010726SN/Asystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles 111110726SN/Asystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles 111210726SN/Asystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles 111310726SN/Asystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19548409701 # number of ReadReq MSHR miss cycles 111410726SN/Asystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 25690889671 # number of ReadReq MSHR miss cycles 111510726SN/Asystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16058529504 # number of WriteInvalidateReq MSHR miss cycles 111610726SN/Asystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16058529504 # number of WriteInvalidateReq MSHR miss cycles 111710726SN/Asystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 625079648 # number of UpgradeReq MSHR miss cycles 111810726SN/Asystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 625079648 # number of UpgradeReq MSHR miss cycles 111910726SN/Asystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles 112010726SN/Asystem.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles 112110726SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35188398563 # number of ReadExReq MSHR miss cycles 112210726SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35188398563 # number of ReadExReq MSHR miss cycles 112310726SN/Asystem.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 305614500 # number of demand (read+write) MSHR miss cycles 112410726SN/Asystem.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 305848750 # number of demand (read+write) MSHR miss cycles 112510726SN/Asystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5531016720 # number of demand (read+write) MSHR miss cycles 112610726SN/Asystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54736808264 # number of demand (read+write) MSHR miss cycles 112710726SN/Asystem.cpu.l2cache.demand_mshr_miss_latency::total 60879288234 # number of demand (read+write) MSHR miss cycles 112810726SN/Asystem.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 305614500 # number of overall MSHR miss cycles 112910726SN/Asystem.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 305848750 # number of overall MSHR miss cycles 113010726SN/Asystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5531016720 # number of overall MSHR miss cycles 113110726SN/Asystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54736808264 # number of overall MSHR miss cycles 113210726SN/Asystem.cpu.l2cache.overall_mshr_miss_latency::total 60879288234 # number of overall MSHR miss cycles 113310726SN/Asystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2585776000 # number of ReadReq MSHR uncacheable cycles 113410726SN/Asystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279091500 # number of ReadReq MSHR uncacheable cycles 113510726SN/Asystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7864867500 # number of ReadReq MSHR uncacheable cycles 113610726SN/Asystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5180093000 # number of WriteReq MSHR uncacheable cycles 113710726SN/Asystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5180093000 # number of WriteReq MSHR uncacheable cycles 113810726SN/Asystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2585776000 # number of overall MSHR uncacheable cycles 113910726SN/Asystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10459184500 # number of overall MSHR uncacheable cycles 114010726SN/Asystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 13044960500 # number of overall MSHR uncacheable cycles 114110726SN/Asystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for ReadReq accesses 114210726SN/Asystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for ReadReq accesses 114310726SN/Asystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for ReadReq accesses 114410726SN/Asystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.040274 # mshr miss rate for ReadReq accesses 114510726SN/Asystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017101 # mshr miss rate for ReadReq accesses 114610726SN/Asystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413482 # mshr miss rate for WriteInvalidateReq accesses 114710726SN/Asystem.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413482 # mshr miss rate for WriteInvalidateReq accesses 114810726SN/Asystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783297 # mshr miss rate for UpgradeReq accesses 114910726SN/Asystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783297 # mshr miss rate for UpgradeReq accesses 115010585SN/Asystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 115110585SN/Asystem.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 115210726SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238298 # mshr miss rate for ReadExReq accesses 115310726SN/Asystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238298 # mshr miss rate for ReadExReq accesses 115410726SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for demand accesses 115510726SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for demand accesses 115610726SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for demand accesses 115710726SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for demand accesses 115810726SN/Asystem.cpu.l2cache.demand_mshr_miss_rate::total 0.037478 # mshr miss rate for demand accesses 115910726SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for overall accesses 116010726SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for overall accesses 116110726SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for overall accesses 116210726SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for overall accesses 116310726SN/Asystem.cpu.l2cache.overall_mshr_miss_rate::total 0.037478 # mshr miss rate for overall accesses 116410726SN/Asystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average ReadReq mshr miss latency 116510726SN/Asystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average ReadReq mshr miss latency 116610726SN/Asystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586 # average ReadReq mshr miss latency 116710726SN/Asystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290 # average ReadReq mshr miss latency 116810726SN/Asystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437 # average ReadReq mshr miss latency 116910726SN/Asystem.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902 # average WriteInvalidateReq mshr miss latency 117010726SN/Asystem.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902 # average WriteInvalidateReq mshr miss latency 117110726SN/Asystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150 # average UpgradeReq mshr miss latency 117210726SN/Asystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150 # average UpgradeReq mshr miss latency 117310726SN/Asystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency 117410726SN/Asystem.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency 117510726SN/Asystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021 # average ReadExReq mshr miss latency 117610726SN/Asystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021 # average ReadExReq mshr miss latency 117710726SN/Asystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency 117810726SN/Asystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency 117910726SN/Asystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency 118010726SN/Asystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency 118110726SN/Asystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency 118210726SN/Asystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency 118310726SN/Asystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency 118410726SN/Asystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency 118510726SN/Asystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency 118610726SN/Asystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency 118710827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average ReadReq mshr uncacheable latency 118810827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156621.714235 # average ReadReq mshr uncacheable latency 118910827Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102365.809374 # average ReadReq mshr uncacheable latency 119010827Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153666.360131 # average WriteReq mshr uncacheable latency 119110827Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153666.360131 # average WriteReq mshr uncacheable latency 119210827Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average overall mshr uncacheable latency 119310827Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155143.949508 # average overall mshr uncacheable latency 119410827Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 118010.154603 # average overall mshr uncacheable latency 119510585SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 119610726SN/Asystem.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution 119710726SN/Asystem.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution 119810726SN/Asystem.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution 119910726SN/Asystem.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution 120010726SN/Asystem.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution 120110726SN/Asystem.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution 120210726SN/Asystem.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution 120310726SN/Asystem.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution 120410628SN/Asystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 120510726SN/Asystem.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution 120610726SN/Asystem.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution 120710726SN/Asystem.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution 120810726SN/Asystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes) 120910726SN/Asystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes) 121010726SN/Asystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes) 121110726SN/Asystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes) 121210726SN/Asystem.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes) 121310726SN/Asystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes) 121410726SN/Asystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes) 121510726SN/Asystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes) 121610726SN/Asystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes) 121710726SN/Asystem.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes) 121810726SN/Asystem.cpu.toL2Bus.snoops 470306 # Total snoops (count) 121910827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 33102923 # Request fanout histogram 122010827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1.033230 # Request fanout histogram 122110827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.179236 # Request fanout histogram 122210585SN/Asystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 122310585SN/Asystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 122410827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 32002916 96.68% 96.68% # Request fanout histogram 122510827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 1100007 3.32% 100.00% # Request fanout histogram 122610585SN/Asystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 122710827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 122810827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 122910827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 33102923 # Request fanout histogram 123010726SN/Asystem.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks) 123110585SN/Asystem.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 123210726SN/Asystem.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks) 123310585SN/Asystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 123410726SN/Asystem.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks) 123510585SN/Asystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 123610726SN/Asystem.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks) 123710585SN/Asystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 123810726SN/Asystem.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks) 123910585SN/Asystem.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 124010726SN/Asystem.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks) 124110585SN/Asystem.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 124210726SN/Asystem.iobus.trans_dist::ReadReq 40333 # Transaction distribution 124310726SN/Asystem.iobus.trans_dist::ReadResp 40333 # Transaction distribution 124410726SN/Asystem.iobus.trans_dist::WriteReq 136571 # Transaction distribution 124510726SN/Asystem.iobus.trans_dist::WriteResp 29907 # Transaction distribution 124610585SN/Asystem.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution 124710726SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 124810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 124910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 125010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 125110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 125210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 125310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 125410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 125510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 125610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 125710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 125810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 125910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 126010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 126110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 126210726SN/Asystem.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 126310726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes) 126410726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes) 126510585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 126610585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 126710726SN/Asystem.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes) 126810726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 126910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 127010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 127110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 127210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 127310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 127410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 127510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 127610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 127710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 127810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 127910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 128010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 128110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 128210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 128310726SN/Asystem.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 128410726SN/Asystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes) 128510726SN/Asystem.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes) 128610585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 128710585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 128810726SN/Asystem.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes) 128910726SN/Asystem.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) 129010585SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 129110585SN/Asystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 129210585SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 129310585SN/Asystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 129410585SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 129510585SN/Asystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 129610585SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 129710585SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 129810585SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 129910585SN/Asystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 130010585SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 130110585SN/Asystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 130210585SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 130310585SN/Asystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 130410585SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 130510585SN/Asystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 130610585SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 130710585SN/Asystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 130810585SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 130910585SN/Asystem.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 131010585SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 131110585SN/Asystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 131210585SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 131310585SN/Asystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 131410585SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 131510585SN/Asystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 131610585SN/Asystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 131710726SN/Asystem.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks) 131810585SN/Asystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 131910585SN/Asystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 132010585SN/Asystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 132110726SN/Asystem.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 132210585SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 132310726SN/Asystem.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks) 132410585SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 132510726SN/Asystem.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) 132610585SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 132710726SN/Asystem.iocache.tags.replacements 115493 # number of replacements 132810726SN/Asystem.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use 132910585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 133010726SN/Asystem.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks. 133110585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 133210726SN/Asystem.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit. 133310726SN/Asystem.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor 133410726SN/Asystem.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor 133510726SN/Asystem.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy 133610726SN/Asystem.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy 133710726SN/Asystem.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy 133810585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 133910585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 134010585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 134110726SN/Asystem.iocache.tags.tag_accesses 1039965 # Number of tag accesses 134210726SN/Asystem.iocache.tags.data_accesses 1039965 # Number of data accesses 134310585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 134410726SN/Asystem.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses 134510726SN/Asystem.iocache.ReadReq_misses::total 8885 # number of ReadReq misses 134610585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 134710585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 134810585SN/Asystem.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses 134910585SN/Asystem.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses 135010585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 135110726SN/Asystem.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses 135210726SN/Asystem.iocache.demand_misses::total 8888 # number of demand (read+write) misses 135310585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 135410726SN/Asystem.iocache.overall_misses::realview.ide 8848 # number of overall misses 135510726SN/Asystem.iocache.overall_misses::total 8888 # number of overall misses 135610726SN/Asystem.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles 135710726SN/Asystem.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles 135810726SN/Asystem.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles 135910726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles 136010726SN/Asystem.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles 136110726SN/Asystem.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles 136210726SN/Asystem.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles 136310726SN/Asystem.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles 136410726SN/Asystem.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles 136510726SN/Asystem.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles 136610726SN/Asystem.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles 136710726SN/Asystem.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles 136810726SN/Asystem.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles 136910585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 137010726SN/Asystem.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses) 137110726SN/Asystem.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses) 137210585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 137310585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 137410585SN/Asystem.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) 137510585SN/Asystem.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) 137610585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 137710726SN/Asystem.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses 137810726SN/Asystem.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses 137910585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 138010726SN/Asystem.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses 138110726SN/Asystem.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses 138210585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 138310585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 138410585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 138510585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 138610585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 138710585SN/Asystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 138810585SN/Asystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 138910585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 139010585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 139110585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 139210585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 139310585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 139410585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 139510726SN/Asystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency 139610726SN/Asystem.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency 139710726SN/Asystem.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency 139810726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency 139910726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency 140010726SN/Asystem.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency 140110726SN/Asystem.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency 140210726SN/Asystem.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency 140310726SN/Asystem.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency 140410726SN/Asystem.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency 140510726SN/Asystem.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency 140610726SN/Asystem.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency 140710726SN/Asystem.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency 140810726SN/Asystem.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked 140910585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 141010726SN/Asystem.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked 141110585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 141210726SN/Asystem.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked 141310585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 141410585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 141510585SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 141610628SN/Asystem.iocache.writebacks::writebacks 106630 # number of writebacks 141710628SN/Asystem.iocache.writebacks::total 106630 # number of writebacks 141810585SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 141910726SN/Asystem.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses 142010726SN/Asystem.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses 142110585SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 142210585SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 142310585SN/Asystem.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses 142410585SN/Asystem.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses 142510585SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 142610726SN/Asystem.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses 142710726SN/Asystem.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses 142810585SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 142910726SN/Asystem.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses 143010726SN/Asystem.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses 143110726SN/Asystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles 143210726SN/Asystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles 143310726SN/Asystem.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles 143410726SN/Asystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles 143510726SN/Asystem.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles 143610726SN/Asystem.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles 143710726SN/Asystem.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles 143810726SN/Asystem.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles 143910726SN/Asystem.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles 144010726SN/Asystem.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles 144110726SN/Asystem.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles 144210726SN/Asystem.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles 144310726SN/Asystem.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles 144410585SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 144510585SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 144610585SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 144710585SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 144810585SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 144910585SN/Asystem.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 145010585SN/Asystem.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 145110585SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 145210585SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 145310585SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 145410585SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 145510585SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 145610585SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 145710726SN/Asystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency 145810726SN/Asystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency 145910726SN/Asystem.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency 146010726SN/Asystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency 146110726SN/Asystem.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency 146210726SN/Asystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency 146310726SN/Asystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency 146410726SN/Asystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency 146510726SN/Asystem.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency 146610726SN/Asystem.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency 146710726SN/Asystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency 146810726SN/Asystem.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency 146910726SN/Asystem.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency 147010585SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 147110726SN/Asystem.membus.trans_dist::ReadReq 448489 # Transaction distribution 147210726SN/Asystem.membus.trans_dist::ReadResp 448489 # Transaction distribution 147310726SN/Asystem.membus.trans_dist::WriteReq 33710 # Transaction distribution 147410726SN/Asystem.membus.trans_dist::WriteResp 33710 # Transaction distribution 147510726SN/Asystem.membus.trans_dist::Writeback 1214153 # Transaction distribution 147610726SN/Asystem.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution 147710726SN/Asystem.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution 147810726SN/Asystem.membus.trans_dist::UpgradeReq 36221 # Transaction distribution 147910628SN/Asystem.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 148010726SN/Asystem.membus.trans_dist::UpgradeResp 36223 # Transaction distribution 148110726SN/Asystem.membus.trans_dist::ReadExReq 512353 # Transaction distribution 148210726SN/Asystem.membus.trans_dist::ReadExResp 512353 # Transaction distribution 148310726SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 148410515SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 148510585SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) 148610726SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes) 148710726SN/Asystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes) 148810726SN/Asystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes) 148910726SN/Asystem.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes) 149010726SN/Asystem.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes) 149110726SN/Asystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 149210515SN/Asystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 149310585SN/Asystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) 149410726SN/Asystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes) 149510726SN/Asystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes) 149610726SN/Asystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes) 149710726SN/Asystem.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes) 149810726SN/Asystem.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes) 149910726SN/Asystem.membus.snoops 3324 # Total snoops (count) 150010827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2861471 # Request fanout histogram 150110515SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 150210515SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 150310515SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 150410515SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 150510827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 2861471 100.00% 100.00% # Request fanout histogram 150610515SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 150710515SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 150810515SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 150910515SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 151010827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2861471 # Request fanout histogram 151110726SN/Asystem.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks) 151210515SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 151310726SN/Asystem.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 151410515SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 151510726SN/Asystem.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks) 151610515SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 151710726SN/Asystem.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks) 151810515SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 151910726SN/Asystem.membus.respLayer2.occupancy 5433894864 # Layer occupancy (ticks) 152010515SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 152110726SN/Asystem.membus.respLayer3.occupancy 151694929 # Layer occupancy (ticks) 152210515SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 152310515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 152410515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 152510515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 152610515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 152710515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 152810515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 152910515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 153010515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 153110515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 153210515SN/Asystem.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 153310515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 153410515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 153510515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 153610515SN/Asystem.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 153710515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 153810515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 153910515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 154010515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 154110515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 154210515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 154310515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 154410515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 154510515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 154610515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 154710515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 154810515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 154910515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 155010515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 155110515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 155210515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 155310515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 155410515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 155510515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 155610515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 155710515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 155810515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 155910515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 156010515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 156110515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 156210515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 156310515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 156410515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 156510515SN/A 156610515SN/A---------- End Simulation Statistics ---------- 1567