stats.txt revision 10585
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.821204 # Number of seconds simulated 4sim_ticks 51821203872000 # Number of ticks simulated 5final_tick 51821203872000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 797175 # Simulator instruction rate (inst/s) 8host_op_rate 936716 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 46008450754 # Simulator tick rate (ticks/s) 10host_mem_usage 656028 # Number of bytes of host memory used 11host_seconds 1126.34 # Real time elapsed on the host 12sim_insts 897890420 # Number of instructions simulated 13sim_ops 1055061464 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 274944 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 280896 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5219828 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 52654408 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 402752 # Number of bytes read from this memory 21system.physmem.bytes_read::total 58832828 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 5219828 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 5219828 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 79485888 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 79506468 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 4296 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 4389 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 121967 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 822738 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6293 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 959683 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1241967 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1244540 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 5306 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 5420 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 100728 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1016078 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7772 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1135304 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 100728 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 100728 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1533849 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1534246 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1533849 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 5306 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 5420 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 100728 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1016476 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7772 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 2669550 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 959683 # Number of read requests accepted 55system.physmem.writeReqs 1860672 # Number of write requests accepted 56system.physmem.readBursts 959683 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1860672 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 61376064 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 43648 # Total number of bytes read from write queue 60system.physmem.bytesWritten 118595648 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 58832828 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 118938916 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 682 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 7593 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 36288 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 56975 # Per bank write bursts 67system.physmem.perBankRdBursts::1 58359 # Per bank write bursts 68system.physmem.perBankRdBursts::2 58716 # Per bank write bursts 69system.physmem.perBankRdBursts::3 57264 # Per bank write bursts 70system.physmem.perBankRdBursts::4 61545 # Per bank write bursts 71system.physmem.perBankRdBursts::5 66145 # Per bank write bursts 72system.physmem.perBankRdBursts::6 57228 # Per bank write bursts 73system.physmem.perBankRdBursts::7 52937 # Per bank write bursts 74system.physmem.perBankRdBursts::8 52189 # Per bank write bursts 75system.physmem.perBankRdBursts::9 99547 # Per bank write bursts 76system.physmem.perBankRdBursts::10 57680 # Per bank write bursts 77system.physmem.perBankRdBursts::11 61393 # Per bank write bursts 78system.physmem.perBankRdBursts::12 54506 # Per bank write bursts 79system.physmem.perBankRdBursts::13 60286 # Per bank write bursts 80system.physmem.perBankRdBursts::14 51564 # Per bank write bursts 81system.physmem.perBankRdBursts::15 52667 # Per bank write bursts 82system.physmem.perBankWrBursts::0 114739 # Per bank write bursts 83system.physmem.perBankWrBursts::1 115397 # Per bank write bursts 84system.physmem.perBankWrBursts::2 117633 # Per bank write bursts 85system.physmem.perBankWrBursts::3 119136 # Per bank write bursts 86system.physmem.perBankWrBursts::4 120318 # Per bank write bursts 87system.physmem.perBankWrBursts::5 121968 # Per bank write bursts 88system.physmem.perBankWrBursts::6 116613 # Per bank write bursts 89system.physmem.perBankWrBursts::7 113695 # Per bank write bursts 90system.physmem.perBankWrBursts::8 109286 # Per bank write bursts 91system.physmem.perBankWrBursts::9 116370 # Per bank write bursts 92system.physmem.perBankWrBursts::10 115629 # Per bank write bursts 93system.physmem.perBankWrBursts::11 118249 # Per bank write bursts 94system.physmem.perBankWrBursts::12 111968 # Per bank write bursts 95system.physmem.perBankWrBursts::13 117797 # Per bank write bursts 96system.physmem.perBankWrBursts::14 110347 # Per bank write bursts 97system.physmem.perBankWrBursts::15 113912 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 100system.physmem.totGap 51821201316000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 43101 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 916567 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 1858099 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 925038 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 28111 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 2104 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 593 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 706 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 405 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 375 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 306 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 221 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 147 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 137 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 124 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 112 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 112 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 64 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 58079 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 70983 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 101652 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 104342 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 108305 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 122410 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 126456 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 111805 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 113098 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 110863 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 108761 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 105735 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 102887 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 101533 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 96838 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 95973 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 95806 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 94380 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 3424 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 2906 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 2427 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 2200 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 1880 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 1660 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 1358 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 1197 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 1022 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 916 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 704 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 565 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 435 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 412 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 367 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 308 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 295 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 258 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 234 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 181 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 92 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 68 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 40 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 617611 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 291.399266 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 166.446996 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 330.841680 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 256797 41.58% 41.58% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 151085 24.46% 66.04% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 51876 8.40% 74.44% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 29038 4.70% 79.14% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 19766 3.20% 82.34% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 13229 2.14% 84.49% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 10059 1.63% 86.11% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 9064 1.47% 87.58% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 76697 12.42% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 617611 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 92036 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 10.419705 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 106.178395 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-1023 92034 100.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 92036 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 92036 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.134045 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 19.130429 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 10.695121 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-23 84651 91.98% 91.98% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-31 3801 4.13% 96.11% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::32-39 1276 1.39% 97.49% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::40-47 446 0.48% 97.98% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-55 607 0.66% 98.64% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::56-63 136 0.15% 98.78% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::64-71 198 0.22% 99.00% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-79 105 0.11% 99.11% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-87 166 0.18% 99.29% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::88-95 53 0.06% 99.35% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::96-103 197 0.21% 99.57% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-111 35 0.04% 99.60% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::112-119 54 0.06% 99.66% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::120-127 56 0.06% 99.72% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::128-135 137 0.15% 99.87% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::136-143 24 0.03% 99.90% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::144-151 33 0.04% 99.93% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::152-159 9 0.01% 99.94% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::160-167 16 0.02% 99.96% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::168-175 5 0.01% 99.97% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::176-183 6 0.01% 99.97% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::184-191 4 0.00% 99.98% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::192-199 2 0.00% 99.98% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::216-223 8 0.01% 99.99% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::224-231 2 0.00% 99.99% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::232-239 1 0.00% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 92036 # Writes before turning the bus around for reads 268system.physmem.totQLat 12714966775 # Total ticks spent queuing 269system.physmem.totMemAccLat 30696235525 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 4795005000 # Total ticks spent in databus transfers 271system.physmem.avgQLat 13258.55 # Average queueing delay per DRAM burst 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 273system.physmem.avgMemAccLat 32008.55 # Average memory access latency per DRAM burst 274system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s 275system.physmem.avgWrBW 2.29 # Average achieved write bandwidth in MiByte/s 276system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s 277system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 279system.physmem.busUtil 0.03 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 281system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 282system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 283system.physmem.avgWrQLen 23.23 # Average write queue length when enqueuing 284system.physmem.readRowHits 722338 # Number of row buffer hits during reads 285system.physmem.writeRowHits 1472108 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 75.32 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes 288system.physmem.avgGap 18373999.48 # Average gap between requests 289system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined 290system.physmem.memoryStateTime::IDLE 49686658091000 # Time in different power states 291system.physmem.memoryStateTime::REF 1730423760000 # Time in different power states 292system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 293system.physmem.memoryStateTime::ACT 404121645500 # Time in different power states 294system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 295system.physmem.actEnergy::0 2414648880 # Energy for activate commands per rank (pJ) 296system.physmem.actEnergy::1 2254490280 # Energy for activate commands per rank (pJ) 297system.physmem.preEnergy::0 1317516750 # Energy for precharge commands per rank (pJ) 298system.physmem.preEnergy::1 1230128625 # Energy for precharge commands per rank (pJ) 299system.physmem.readEnergy::0 3659518200 # Energy for read commands per rank (pJ) 300system.physmem.readEnergy::1 3820650600 # Energy for read commands per rank (pJ) 301system.physmem.writeEnergy::0 6087953520 # Energy for write commands per rank (pJ) 302system.physmem.writeEnergy::1 5919855840 # Energy for write commands per rank (pJ) 303system.physmem.refreshEnergy::0 3384708874560 # Energy for refresh commands per rank (pJ) 304system.physmem.refreshEnergy::1 3384708874560 # Energy for refresh commands per rank (pJ) 305system.physmem.actBackEnergy::0 1312804436175 # Energy for active background per rank (pJ) 306system.physmem.actBackEnergy::1 1305168623550 # Energy for active background per rank (pJ) 307system.physmem.preBackEnergy::0 29941137312000 # Energy for precharge background per rank (pJ) 308system.physmem.preBackEnergy::1 29947835393250 # Energy for precharge background per rank (pJ) 309system.physmem.totalEnergy::0 34652130260085 # Total energy per rank (pJ) 310system.physmem.totalEnergy::1 34650938016705 # Total energy per rank (pJ) 311system.physmem.averagePower::0 668.686370 # Core power per rank (mW) 312system.physmem.averagePower::1 668.663363 # Core power per rank (mW) 313system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 314system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 315system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 316system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 317system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 318system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 319system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 320system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 321system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 328system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) 329system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 330system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 331system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 332system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 333system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 334system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 335system.cpu_clk_domain.clock 500 # Clock period in ticks 336system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 337system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 338system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 339system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 340system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 341system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 342system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 343system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 344system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 345system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 346system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 347system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 348system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 349system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 350system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 351system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 352system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 353system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 354system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 355system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 356system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 357system.cpu.dtb.inst_hits 0 # ITB inst hits 358system.cpu.dtb.inst_misses 0 # ITB inst misses 359system.cpu.dtb.read_hits 168646043 # DTB read hits 360system.cpu.dtb.read_misses 158497 # DTB read misses 361system.cpu.dtb.write_hits 153371607 # DTB write hits 362system.cpu.dtb.write_misses 56347 # DTB write misses 363system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 364system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 365system.cpu.dtb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID 366system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 367system.cpu.dtb.flush_entries 74830 # Number of entries that have been flushed from TLB 368system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 369system.cpu.dtb.prefetch_faults 7977 # Number of TLB faults due to prefetch 370system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 371system.cpu.dtb.perms_faults 19966 # Number of TLB faults due to permissions restrictions 372system.cpu.dtb.read_accesses 168804540 # DTB read accesses 373system.cpu.dtb.write_accesses 153427954 # DTB write accesses 374system.cpu.dtb.inst_accesses 0 # ITB inst accesses 375system.cpu.dtb.hits 322017650 # DTB hits 376system.cpu.dtb.misses 214844 # DTB misses 377system.cpu.dtb.accesses 322232494 # DTB accesses 378system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 379system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 380system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 381system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 382system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 383system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 384system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 385system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 386system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 387system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 388system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 389system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 390system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 391system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 392system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 394system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 395system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 396system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 397system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 398system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 399system.cpu.itb.inst_hits 898442559 # ITB inst hits 400system.cpu.itb.inst_misses 123457 # ITB inst misses 401system.cpu.itb.read_hits 0 # DTB read hits 402system.cpu.itb.read_misses 0 # DTB read misses 403system.cpu.itb.write_hits 0 # DTB write hits 404system.cpu.itb.write_misses 0 # DTB write misses 405system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 406system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 407system.cpu.itb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID 408system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 409system.cpu.itb.flush_entries 53017 # Number of entries that have been flushed from TLB 410system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 411system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 414system.cpu.itb.read_accesses 0 # DTB read accesses 415system.cpu.itb.write_accesses 0 # DTB write accesses 416system.cpu.itb.inst_accesses 898566016 # ITB inst accesses 417system.cpu.itb.hits 898442559 # DTB hits 418system.cpu.itb.misses 123457 # DTB misses 419system.cpu.itb.accesses 898566016 # DTB accesses 420system.cpu.numCycles 103642407744 # number of cpu cycles simulated 421system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 422system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 423system.cpu.committedInsts 897890420 # Number of instructions committed 424system.cpu.committedOps 1055061464 # Number of ops (including micro ops) committed 425system.cpu.num_int_alu_accesses 968615704 # Number of integer alu accesses 426system.cpu.num_fp_alu_accesses 900077 # Number of float alu accesses 427system.cpu.num_func_calls 53165114 # number of times a function call or return occured 428system.cpu.num_conditional_control_insts 137212632 # number of instructions that are conditional controls 429system.cpu.num_int_insts 968615704 # number of integer instructions 430system.cpu.num_fp_insts 900077 # number of float instructions 431system.cpu.num_int_register_reads 1413530400 # number of times the integer registers were read 432system.cpu.num_int_register_writes 768471074 # number of times the integer registers were written 433system.cpu.num_fp_register_reads 1450010 # number of times the floating registers were read 434system.cpu.num_fp_register_writes 764580 # number of times the floating registers were written 435system.cpu.num_cc_register_reads 236283447 # number of times the CC registers were read 436system.cpu.num_cc_register_writes 235682818 # number of times the CC registers were written 437system.cpu.num_mem_refs 322001322 # number of memory refs 438system.cpu.num_load_insts 168639088 # Number of load instructions 439system.cpu.num_store_insts 153362234 # Number of store instructions 440system.cpu.num_idle_cycles 100472196154.122070 # Number of idle cycles 441system.cpu.num_busy_cycles 3170211589.877939 # Number of busy cycles 442system.cpu.not_idle_fraction 0.030588 # Percentage of non-idle cycles 443system.cpu.idle_fraction 0.969412 # Percentage of idle cycles 444system.cpu.Branches 200577010 # Number of branches fetched 445system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 446system.cpu.op_class::IntAlu 731218910 69.27% 69.27% # Class of executed instruction 447system.cpu.op_class::IntMult 2226806 0.21% 69.48% # Class of executed instruction 448system.cpu.op_class::IntDiv 99223 0.01% 69.49% # Class of executed instruction 449system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction 450system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction 451system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction 452system.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction 453system.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction 454system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction 455system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction 456system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction 457system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction 458system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction 459system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction 460system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction 461system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction 462system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction 463system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction 464system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction 465system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction 466system.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction 467system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction 468system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction 469system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction 470system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction 471system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.50% # Class of executed instruction 472system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction 473system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction 474system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction 475system.cpu.op_class::MemRead 168639088 15.97% 85.47% # Class of executed instruction 476system.cpu.op_class::MemWrite 153362234 14.53% 100.00% # Class of executed instruction 477system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 478system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 479system.cpu.op_class::total 1055656727 # Class of executed instruction 480system.cpu.kern.inst.arm 0 # number of arm instructions executed 481system.cpu.kern.inst.quiesce 16365 # number of quiesce instructions executed 482system.cpu.dcache.tags.replacements 10282368 # number of replacements 483system.cpu.dcache.tags.tagsinuse 511.969706 # Cycle average of tags in use 484system.cpu.dcache.tags.total_refs 311548704 # Total number of references to valid blocks. 485system.cpu.dcache.tags.sampled_refs 10282880 # Sample count of references to valid blocks. 486system.cpu.dcache.tags.avg_refs 30.297806 # Average number of references to valid blocks. 487system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit. 488system.cpu.dcache.tags.occ_blocks::cpu.data 511.969706 # Average occupied blocks per requestor 489system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy 490system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy 491system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 492system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id 493system.cpu.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id 494system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 495system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 496system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 497system.cpu.dcache.tags.tag_accesses 1298012717 # Number of tag accesses 498system.cpu.dcache.tags.data_accesses 1298012717 # Number of data accesses 499system.cpu.dcache.ReadReq_hits::cpu.data 157556193 # number of ReadReq hits 500system.cpu.dcache.ReadReq_hits::total 157556193 # number of ReadReq hits 501system.cpu.dcache.WriteReq_hits::cpu.data 145511723 # number of WriteReq hits 502system.cpu.dcache.WriteReq_hits::total 145511723 # number of WriteReq hits 503system.cpu.dcache.SoftPFReq_hits::cpu.data 396994 # number of SoftPFReq hits 504system.cpu.dcache.SoftPFReq_hits::total 396994 # number of SoftPFReq hits 505system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits 506system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits 507system.cpu.dcache.LoadLockedReq_hits::cpu.data 3698345 # number of LoadLockedReq hits 508system.cpu.dcache.LoadLockedReq_hits::total 3698345 # number of LoadLockedReq hits 509system.cpu.dcache.StoreCondReq_hits::cpu.data 4003149 # number of StoreCondReq hits 510system.cpu.dcache.StoreCondReq_hits::total 4003149 # number of StoreCondReq hits 511system.cpu.dcache.demand_hits::cpu.data 303067916 # number of demand (read+write) hits 512system.cpu.dcache.demand_hits::total 303067916 # number of demand (read+write) hits 513system.cpu.dcache.overall_hits::cpu.data 303464910 # number of overall hits 514system.cpu.dcache.overall_hits::total 303464910 # number of overall hits 515system.cpu.dcache.ReadReq_misses::cpu.data 5344087 # number of ReadReq misses 516system.cpu.dcache.ReadReq_misses::total 5344087 # number of ReadReq misses 517system.cpu.dcache.WriteReq_misses::cpu.data 2236666 # number of WriteReq misses 518system.cpu.dcache.WriteReq_misses::total 2236666 # number of WriteReq misses 519system.cpu.dcache.SoftPFReq_misses::cpu.data 1310162 # number of SoftPFReq misses 520system.cpu.dcache.SoftPFReq_misses::total 1310162 # number of SoftPFReq misses 521system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1231947 # number of WriteInvalidateReq misses 522system.cpu.dcache.WriteInvalidateReq_misses::total 1231947 # number of WriteInvalidateReq misses 523system.cpu.dcache.LoadLockedReq_misses::cpu.data 306495 # number of LoadLockedReq misses 524system.cpu.dcache.LoadLockedReq_misses::total 306495 # number of LoadLockedReq misses 525system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses 526system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses 527system.cpu.dcache.demand_misses::cpu.data 7580753 # number of demand (read+write) misses 528system.cpu.dcache.demand_misses::total 7580753 # number of demand (read+write) misses 529system.cpu.dcache.overall_misses::cpu.data 8890915 # number of overall misses 530system.cpu.dcache.overall_misses::total 8890915 # number of overall misses 531system.cpu.dcache.ReadReq_miss_latency::cpu.data 83712196260 # number of ReadReq miss cycles 532system.cpu.dcache.ReadReq_miss_latency::total 83712196260 # number of ReadReq miss cycles 533system.cpu.dcache.WriteReq_miss_latency::cpu.data 64378240535 # number of WriteReq miss cycles 534system.cpu.dcache.WriteReq_miss_latency::total 64378240535 # number of WriteReq miss cycles 535system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27514486506 # number of WriteInvalidateReq miss cycles 536system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27514486506 # number of WriteInvalidateReq miss cycles 537system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4474608500 # number of LoadLockedReq miss cycles 538system.cpu.dcache.LoadLockedReq_miss_latency::total 4474608500 # number of LoadLockedReq miss cycles 539system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251501 # number of StoreCondReq miss cycles 540system.cpu.dcache.StoreCondReq_miss_latency::total 251501 # number of StoreCondReq miss cycles 541system.cpu.dcache.demand_miss_latency::cpu.data 148090436795 # number of demand (read+write) miss cycles 542system.cpu.dcache.demand_miss_latency::total 148090436795 # number of demand (read+write) miss cycles 543system.cpu.dcache.overall_miss_latency::cpu.data 148090436795 # number of overall miss cycles 544system.cpu.dcache.overall_miss_latency::total 148090436795 # number of overall miss cycles 545system.cpu.dcache.ReadReq_accesses::cpu.data 162900280 # number of ReadReq accesses(hits+misses) 546system.cpu.dcache.ReadReq_accesses::total 162900280 # number of ReadReq accesses(hits+misses) 547system.cpu.dcache.WriteReq_accesses::cpu.data 147748389 # number of WriteReq accesses(hits+misses) 548system.cpu.dcache.WriteReq_accesses::total 147748389 # number of WriteReq accesses(hits+misses) 549system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707156 # number of SoftPFReq accesses(hits+misses) 550system.cpu.dcache.SoftPFReq_accesses::total 1707156 # number of SoftPFReq accesses(hits+misses) 551system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1568634 # number of WriteInvalidateReq accesses(hits+misses) 552system.cpu.dcache.WriteInvalidateReq_accesses::total 1568634 # number of WriteInvalidateReq accesses(hits+misses) 553system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4004840 # number of LoadLockedReq accesses(hits+misses) 554system.cpu.dcache.LoadLockedReq_accesses::total 4004840 # number of LoadLockedReq accesses(hits+misses) 555system.cpu.dcache.StoreCondReq_accesses::cpu.data 4003153 # number of StoreCondReq accesses(hits+misses) 556system.cpu.dcache.StoreCondReq_accesses::total 4003153 # number of StoreCondReq accesses(hits+misses) 557system.cpu.dcache.demand_accesses::cpu.data 310648669 # number of demand (read+write) accesses 558system.cpu.dcache.demand_accesses::total 310648669 # number of demand (read+write) accesses 559system.cpu.dcache.overall_accesses::cpu.data 312355825 # number of overall (read+write) accesses 560system.cpu.dcache.overall_accesses::total 312355825 # number of overall (read+write) accesses 561system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032806 # miss rate for ReadReq accesses 562system.cpu.dcache.ReadReq_miss_rate::total 0.032806 # miss rate for ReadReq accesses 563system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015138 # miss rate for WriteReq accesses 564system.cpu.dcache.WriteReq_miss_rate::total 0.015138 # miss rate for WriteReq accesses 565system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767453 # miss rate for SoftPFReq accesses 566system.cpu.dcache.SoftPFReq_miss_rate::total 0.767453 # miss rate for SoftPFReq accesses 567system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.785363 # miss rate for WriteInvalidateReq accesses 568system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.785363 # miss rate for WriteInvalidateReq accesses 569system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076531 # miss rate for LoadLockedReq accesses 570system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076531 # miss rate for LoadLockedReq accesses 571system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 572system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 573system.cpu.dcache.demand_miss_rate::cpu.data 0.024403 # miss rate for demand accesses 574system.cpu.dcache.demand_miss_rate::total 0.024403 # miss rate for demand accesses 575system.cpu.dcache.overall_miss_rate::cpu.data 0.028464 # miss rate for overall accesses 576system.cpu.dcache.overall_miss_rate::total 0.028464 # miss rate for overall accesses 577system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15664.452368 # average ReadReq miss latency 578system.cpu.dcache.ReadReq_avg_miss_latency::total 15664.452368 # average ReadReq miss latency 579system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28783.126553 # average WriteReq miss latency 580system.cpu.dcache.WriteReq_avg_miss_latency::total 28783.126553 # average WriteReq miss latency 581system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 22334.147902 # average WriteInvalidateReq miss latency 582system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22334.147902 # average WriteInvalidateReq miss latency 583system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14599.287101 # average LoadLockedReq miss latency 584system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14599.287101 # average LoadLockedReq miss latency 585system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 62875.250000 # average StoreCondReq miss latency 586system.cpu.dcache.StoreCondReq_avg_miss_latency::total 62875.250000 # average StoreCondReq miss latency 587system.cpu.dcache.demand_avg_miss_latency::cpu.data 19535.056319 # average overall miss latency 588system.cpu.dcache.demand_avg_miss_latency::total 19535.056319 # average overall miss latency 589system.cpu.dcache.overall_avg_miss_latency::cpu.data 16656.377526 # average overall miss latency 590system.cpu.dcache.overall_avg_miss_latency::total 16656.377526 # average overall miss latency 591system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 592system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 593system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 594system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 595system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 596system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 597system.cpu.dcache.fast_writes 0 # number of fast writes performed 598system.cpu.dcache.cache_copies 0 # number of cache copies performed 599system.cpu.dcache.writebacks::writebacks 7918344 # number of writebacks 600system.cpu.dcache.writebacks::total 7918344 # number of writebacks 601system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7198 # number of ReadReq MSHR hits 602system.cpu.dcache.ReadReq_mshr_hits::total 7198 # number of ReadReq MSHR hits 603system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21104 # number of WriteReq MSHR hits 604system.cpu.dcache.WriteReq_mshr_hits::total 21104 # number of WriteReq MSHR hits 605system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70788 # number of LoadLockedReq MSHR hits 606system.cpu.dcache.LoadLockedReq_mshr_hits::total 70788 # number of LoadLockedReq MSHR hits 607system.cpu.dcache.demand_mshr_hits::cpu.data 28302 # number of demand (read+write) MSHR hits 608system.cpu.dcache.demand_mshr_hits::total 28302 # number of demand (read+write) MSHR hits 609system.cpu.dcache.overall_mshr_hits::cpu.data 28302 # number of overall MSHR hits 610system.cpu.dcache.overall_mshr_hits::total 28302 # number of overall MSHR hits 611system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5336889 # number of ReadReq MSHR misses 612system.cpu.dcache.ReadReq_mshr_misses::total 5336889 # number of ReadReq MSHR misses 613system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2215562 # number of WriteReq MSHR misses 614system.cpu.dcache.WriteReq_mshr_misses::total 2215562 # number of WriteReq MSHR misses 615system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1308413 # number of SoftPFReq MSHR misses 616system.cpu.dcache.SoftPFReq_mshr_misses::total 1308413 # number of SoftPFReq MSHR misses 617system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1231947 # number of WriteInvalidateReq MSHR misses 618system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1231947 # number of WriteInvalidateReq MSHR misses 619system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 235707 # number of LoadLockedReq MSHR misses 620system.cpu.dcache.LoadLockedReq_mshr_misses::total 235707 # number of LoadLockedReq MSHR misses 621system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses 622system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses 623system.cpu.dcache.demand_mshr_misses::cpu.data 7552451 # number of demand (read+write) MSHR misses 624system.cpu.dcache.demand_mshr_misses::total 7552451 # number of demand (read+write) MSHR misses 625system.cpu.dcache.overall_mshr_misses::cpu.data 8860864 # number of overall MSHR misses 626system.cpu.dcache.overall_mshr_misses::total 8860864 # number of overall MSHR misses 627system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72465482990 # number of ReadReq MSHR miss cycles 628system.cpu.dcache.ReadReq_mshr_miss_latency::total 72465482990 # number of ReadReq MSHR miss cycles 629system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59129774715 # number of WriteReq MSHR miss cycles 630system.cpu.dcache.WriteReq_mshr_miss_latency::total 59129774715 # number of WriteReq MSHR miss cycles 631system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19473134500 # number of SoftPFReq MSHR miss cycles 632system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19473134500 # number of SoftPFReq MSHR miss cycles 633system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 25050592494 # number of WriteInvalidateReq MSHR miss cycles 634system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 25050592494 # number of WriteInvalidateReq MSHR miss cycles 635system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2902318500 # number of LoadLockedReq MSHR miss cycles 636system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2902318500 # number of LoadLockedReq MSHR miss cycles 637system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 243499 # number of StoreCondReq MSHR miss cycles 638system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 243499 # number of StoreCondReq MSHR miss cycles 639system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131595257705 # number of demand (read+write) MSHR miss cycles 640system.cpu.dcache.demand_mshr_miss_latency::total 131595257705 # number of demand (read+write) MSHR miss cycles 641system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151068392205 # number of overall MSHR miss cycles 642system.cpu.dcache.overall_mshr_miss_latency::total 151068392205 # number of overall MSHR miss cycles 643system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5727938750 # number of ReadReq MSHR uncacheable cycles 644system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727938750 # number of ReadReq MSHR uncacheable cycles 645system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5573388000 # number of WriteReq MSHR uncacheable cycles 646system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5573388000 # number of WriteReq MSHR uncacheable cycles 647system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11301326750 # number of overall MSHR uncacheable cycles 648system.cpu.dcache.overall_mshr_uncacheable_latency::total 11301326750 # number of overall MSHR uncacheable cycles 649system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032762 # mshr miss rate for ReadReq accesses 650system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032762 # mshr miss rate for ReadReq accesses 651system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014996 # mshr miss rate for WriteReq accesses 652system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014996 # mshr miss rate for WriteReq accesses 653system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766428 # mshr miss rate for SoftPFReq accesses 654system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766428 # mshr miss rate for SoftPFReq accesses 655system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.785363 # mshr miss rate for WriteInvalidateReq accesses 656system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.785363 # mshr miss rate for WriteInvalidateReq accesses 657system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058856 # mshr miss rate for LoadLockedReq accesses 658system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058856 # mshr miss rate for LoadLockedReq accesses 659system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 660system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 661system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for demand accesses 662system.cpu.dcache.demand_mshr_miss_rate::total 0.024312 # mshr miss rate for demand accesses 663system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028368 # mshr miss rate for overall accesses 664system.cpu.dcache.overall_mshr_miss_rate::total 0.028368 # mshr miss rate for overall accesses 665system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13578.225627 # average ReadReq mshr miss latency 666system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13578.225627 # average ReadReq mshr miss latency 667system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26688.386385 # average WriteReq mshr miss latency 668system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26688.386385 # average WriteReq mshr miss latency 669system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14883.018206 # average SoftPFReq mshr miss latency 670system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14883.018206 # average SoftPFReq mshr miss latency 671system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 20334.147893 # average WriteInvalidateReq mshr miss latency 672system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20334.147893 # average WriteInvalidateReq mshr miss latency 673system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12313.246955 # average LoadLockedReq mshr miss latency 674system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12313.246955 # average LoadLockedReq mshr miss latency 675system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 60874.750000 # average StoreCondReq mshr miss latency 676system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 60874.750000 # average StoreCondReq mshr miss latency 677system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17424.178946 # average overall mshr miss latency 678system.cpu.dcache.demand_avg_mshr_miss_latency::total 17424.178946 # average overall mshr miss latency 679system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17048.946040 # average overall mshr miss latency 680system.cpu.dcache.overall_avg_mshr_miss_latency::total 17048.946040 # average overall mshr miss latency 681system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 682system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 683system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 684system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 685system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 686system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 687system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 688system.cpu.icache.tags.replacements 13856298 # number of replacements 689system.cpu.icache.tags.tagsinuse 511.892935 # Cycle average of tags in use 690system.cpu.icache.tags.total_refs 884585744 # Total number of references to valid blocks. 691system.cpu.icache.tags.sampled_refs 13856810 # Sample count of references to valid blocks. 692system.cpu.icache.tags.avg_refs 63.837618 # Average number of references to valid blocks. 693system.cpu.icache.tags.warmup_cycle 31832974250 # Cycle when the warmup percentage was hit. 694system.cpu.icache.tags.occ_blocks::cpu.inst 511.892935 # Average occupied blocks per requestor 695system.cpu.icache.tags.occ_percent::cpu.inst 0.999791 # Average percentage of cache occupancy 696system.cpu.icache.tags.occ_percent::total 0.999791 # Average percentage of cache occupancy 697system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 698system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 699system.cpu.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id 700system.cpu.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id 701system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 702system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 703system.cpu.icache.tags.tag_accesses 912299374 # Number of tag accesses 704system.cpu.icache.tags.data_accesses 912299374 # Number of data accesses 705system.cpu.icache.ReadReq_hits::cpu.inst 884585744 # number of ReadReq hits 706system.cpu.icache.ReadReq_hits::total 884585744 # number of ReadReq hits 707system.cpu.icache.demand_hits::cpu.inst 884585744 # number of demand (read+write) hits 708system.cpu.icache.demand_hits::total 884585744 # number of demand (read+write) hits 709system.cpu.icache.overall_hits::cpu.inst 884585744 # number of overall hits 710system.cpu.icache.overall_hits::total 884585744 # number of overall hits 711system.cpu.icache.ReadReq_misses::cpu.inst 13856815 # number of ReadReq misses 712system.cpu.icache.ReadReq_misses::total 13856815 # number of ReadReq misses 713system.cpu.icache.demand_misses::cpu.inst 13856815 # number of demand (read+write) misses 714system.cpu.icache.demand_misses::total 13856815 # number of demand (read+write) misses 715system.cpu.icache.overall_misses::cpu.inst 13856815 # number of overall misses 716system.cpu.icache.overall_misses::total 13856815 # number of overall misses 717system.cpu.icache.ReadReq_miss_latency::cpu.inst 185267091485 # number of ReadReq miss cycles 718system.cpu.icache.ReadReq_miss_latency::total 185267091485 # number of ReadReq miss cycles 719system.cpu.icache.demand_miss_latency::cpu.inst 185267091485 # number of demand (read+write) miss cycles 720system.cpu.icache.demand_miss_latency::total 185267091485 # number of demand (read+write) miss cycles 721system.cpu.icache.overall_miss_latency::cpu.inst 185267091485 # number of overall miss cycles 722system.cpu.icache.overall_miss_latency::total 185267091485 # number of overall miss cycles 723system.cpu.icache.ReadReq_accesses::cpu.inst 898442559 # number of ReadReq accesses(hits+misses) 724system.cpu.icache.ReadReq_accesses::total 898442559 # number of ReadReq accesses(hits+misses) 725system.cpu.icache.demand_accesses::cpu.inst 898442559 # number of demand (read+write) accesses 726system.cpu.icache.demand_accesses::total 898442559 # number of demand (read+write) accesses 727system.cpu.icache.overall_accesses::cpu.inst 898442559 # number of overall (read+write) accesses 728system.cpu.icache.overall_accesses::total 898442559 # number of overall (read+write) accesses 729system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015423 # miss rate for ReadReq accesses 730system.cpu.icache.ReadReq_miss_rate::total 0.015423 # miss rate for ReadReq accesses 731system.cpu.icache.demand_miss_rate::cpu.inst 0.015423 # miss rate for demand accesses 732system.cpu.icache.demand_miss_rate::total 0.015423 # miss rate for demand accesses 733system.cpu.icache.overall_miss_rate::cpu.inst 0.015423 # miss rate for overall accesses 734system.cpu.icache.overall_miss_rate::total 0.015423 # miss rate for overall accesses 735system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13370.106441 # average ReadReq miss latency 736system.cpu.icache.ReadReq_avg_miss_latency::total 13370.106441 # average ReadReq miss latency 737system.cpu.icache.demand_avg_miss_latency::cpu.inst 13370.106441 # average overall miss latency 738system.cpu.icache.demand_avg_miss_latency::total 13370.106441 # average overall miss latency 739system.cpu.icache.overall_avg_miss_latency::cpu.inst 13370.106441 # average overall miss latency 740system.cpu.icache.overall_avg_miss_latency::total 13370.106441 # average overall miss latency 741system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 742system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 744system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 746system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.cpu.icache.fast_writes 0 # number of fast writes performed 748system.cpu.icache.cache_copies 0 # number of cache copies performed 749system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13856815 # number of ReadReq MSHR misses 750system.cpu.icache.ReadReq_mshr_misses::total 13856815 # number of ReadReq MSHR misses 751system.cpu.icache.demand_mshr_misses::cpu.inst 13856815 # number of demand (read+write) MSHR misses 752system.cpu.icache.demand_mshr_misses::total 13856815 # number of demand (read+write) MSHR misses 753system.cpu.icache.overall_mshr_misses::cpu.inst 13856815 # number of overall MSHR misses 754system.cpu.icache.overall_mshr_misses::total 13856815 # number of overall MSHR misses 755system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 157525292015 # number of ReadReq MSHR miss cycles 756system.cpu.icache.ReadReq_mshr_miss_latency::total 157525292015 # number of ReadReq MSHR miss cycles 757system.cpu.icache.demand_mshr_miss_latency::cpu.inst 157525292015 # number of demand (read+write) MSHR miss cycles 758system.cpu.icache.demand_mshr_miss_latency::total 157525292015 # number of demand (read+write) MSHR miss cycles 759system.cpu.icache.overall_mshr_miss_latency::cpu.inst 157525292015 # number of overall MSHR miss cycles 760system.cpu.icache.overall_mshr_miss_latency::total 157525292015 # number of overall MSHR miss cycles 761system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2831639000 # number of ReadReq MSHR uncacheable cycles 762system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2831639000 # number of ReadReq MSHR uncacheable cycles 763system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2831639000 # number of overall MSHR uncacheable cycles 764system.cpu.icache.overall_mshr_uncacheable_latency::total 2831639000 # number of overall MSHR uncacheable cycles 765system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015423 # mshr miss rate for ReadReq accesses 766system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015423 # mshr miss rate for ReadReq accesses 767system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015423 # mshr miss rate for demand accesses 768system.cpu.icache.demand_mshr_miss_rate::total 0.015423 # mshr miss rate for demand accesses 769system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015423 # mshr miss rate for overall accesses 770system.cpu.icache.overall_mshr_miss_rate::total 0.015423 # mshr miss rate for overall accesses 771system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11368.073545 # average ReadReq mshr miss latency 772system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11368.073545 # average ReadReq mshr miss latency 773system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11368.073545 # average overall mshr miss latency 774system.cpu.icache.demand_avg_mshr_miss_latency::total 11368.073545 # average overall mshr miss latency 775system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11368.073545 # average overall mshr miss latency 776system.cpu.icache.overall_avg_mshr_miss_latency::total 11368.073545 # average overall mshr miss latency 777system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 778system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 779system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 780system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 781system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 782system.cpu.l2cache.tags.replacements 1326931 # number of replacements 783system.cpu.l2cache.tags.tagsinuse 65218.833700 # Cycle average of tags in use 784system.cpu.l2cache.tags.total_refs 27835482 # Total number of references to valid blocks. 785system.cpu.l2cache.tags.sampled_refs 1389841 # Sample count of references to valid blocks. 786system.cpu.l2cache.tags.avg_refs 20.027818 # Average number of references to valid blocks. 787system.cpu.l2cache.tags.warmup_cycle 6373825000 # Cycle when the warmup percentage was hit. 788system.cpu.l2cache.tags.occ_blocks::writebacks 38602.265871 # Average occupied blocks per requestor 789system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 305.289253 # Average occupied blocks per requestor 790system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 445.157205 # Average occupied blocks per requestor 791system.cpu.l2cache.tags.occ_blocks::cpu.inst 6377.971996 # Average occupied blocks per requestor 792system.cpu.l2cache.tags.occ_blocks::cpu.data 19488.149376 # Average occupied blocks per requestor 793system.cpu.l2cache.tags.occ_percent::writebacks 0.589024 # Average percentage of cache occupancy 794system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004658 # Average percentage of cache occupancy 795system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006793 # Average percentage of cache occupancy 796system.cpu.l2cache.tags.occ_percent::cpu.inst 0.097320 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::cpu.data 0.297366 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_percent::total 0.995160 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_task_id_blocks::1023 246 # Occupied blocks per task id 800system.cpu.l2cache.tags.occ_task_id_blocks::1024 62664 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id 804system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2454 # Occupied blocks per task id 805system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5481 # Occupied blocks per task id 806system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54290 # Occupied blocks per task id 807system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003754 # Percentage of cache occupancy per task id 808system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956177 # Percentage of cache occupancy per task id 809system.cpu.l2cache.tags.tag_accesses 266276553 # Number of tag accesses 810system.cpu.l2cache.tags.data_accesses 266276553 # Number of data accesses 811system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 378716 # number of ReadReq hits 812system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250963 # number of ReadReq hits 813system.cpu.l2cache.ReadReq_hits::cpu.inst 13777936 # number of ReadReq hits 814system.cpu.l2cache.ReadReq_hits::cpu.data 6592157 # number of ReadReq hits 815system.cpu.l2cache.ReadReq_hits::total 20999772 # number of ReadReq hits 816system.cpu.l2cache.Writeback_hits::writebacks 7918344 # number of Writeback hits 817system.cpu.l2cache.Writeback_hits::total 7918344 # number of Writeback hits 818system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 722474 # number of WriteInvalidateReq hits 819system.cpu.l2cache.WriteInvalidateReq_hits::total 722474 # number of WriteInvalidateReq hits 820system.cpu.l2cache.UpgradeReq_hits::cpu.data 9882 # number of UpgradeReq hits 821system.cpu.l2cache.UpgradeReq_hits::total 9882 # number of UpgradeReq hits 822system.cpu.l2cache.ReadExReq_hits::cpu.data 1634882 # number of ReadExReq hits 823system.cpu.l2cache.ReadExReq_hits::total 1634882 # number of ReadExReq hits 824system.cpu.l2cache.demand_hits::cpu.dtb.walker 378716 # number of demand (read+write) hits 825system.cpu.l2cache.demand_hits::cpu.itb.walker 250963 # number of demand (read+write) hits 826system.cpu.l2cache.demand_hits::cpu.inst 13777936 # number of demand (read+write) hits 827system.cpu.l2cache.demand_hits::cpu.data 8227039 # number of demand (read+write) hits 828system.cpu.l2cache.demand_hits::total 22634654 # number of demand (read+write) hits 829system.cpu.l2cache.overall_hits::cpu.dtb.walker 378716 # number of overall hits 830system.cpu.l2cache.overall_hits::cpu.itb.walker 250963 # number of overall hits 831system.cpu.l2cache.overall_hits::cpu.inst 13777936 # number of overall hits 832system.cpu.l2cache.overall_hits::cpu.data 8227039 # number of overall hits 833system.cpu.l2cache.overall_hits::total 22634654 # number of overall hits 834system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4296 # number of ReadReq misses 835system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4389 # number of ReadReq misses 836system.cpu.l2cache.ReadReq_misses::cpu.inst 78879 # number of ReadReq misses 837system.cpu.l2cache.ReadReq_misses::cpu.data 288852 # number of ReadReq misses 838system.cpu.l2cache.ReadReq_misses::total 376416 # number of ReadReq misses 839system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 509473 # number of WriteInvalidateReq misses 840system.cpu.l2cache.WriteInvalidateReq_misses::total 509473 # number of WriteInvalidateReq misses 841system.cpu.l2cache.UpgradeReq_misses::cpu.data 35727 # number of UpgradeReq misses 842system.cpu.l2cache.UpgradeReq_misses::total 35727 # number of UpgradeReq misses 843system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses 844system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses 845system.cpu.l2cache.ReadExReq_misses::cpu.data 535071 # number of ReadExReq misses 846system.cpu.l2cache.ReadExReq_misses::total 535071 # number of ReadExReq misses 847system.cpu.l2cache.demand_misses::cpu.dtb.walker 4296 # number of demand (read+write) misses 848system.cpu.l2cache.demand_misses::cpu.itb.walker 4389 # number of demand (read+write) misses 849system.cpu.l2cache.demand_misses::cpu.inst 78879 # number of demand (read+write) misses 850system.cpu.l2cache.demand_misses::cpu.data 823923 # number of demand (read+write) misses 851system.cpu.l2cache.demand_misses::total 911487 # number of demand (read+write) misses 852system.cpu.l2cache.overall_misses::cpu.dtb.walker 4296 # number of overall misses 853system.cpu.l2cache.overall_misses::cpu.itb.walker 4389 # number of overall misses 854system.cpu.l2cache.overall_misses::cpu.inst 78879 # number of overall misses 855system.cpu.l2cache.overall_misses::cpu.data 823923 # number of overall misses 856system.cpu.l2cache.overall_misses::total 911487 # number of overall misses 857system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 336423500 # number of ReadReq miss cycles 858system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345754750 # number of ReadReq miss cycles 859system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 5888588734 # number of ReadReq miss cycles 860system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22037305240 # number of ReadReq miss cycles 861system.cpu.l2cache.ReadReq_miss_latency::total 28608072224 # number of ReadReq miss cycles 862system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 117495 # number of WriteInvalidateReq miss cycles 863system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 117495 # number of WriteInvalidateReq miss cycles 864system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 416260719 # number of UpgradeReq miss cycles 865system.cpu.l2cache.UpgradeReq_miss_latency::total 416260719 # number of UpgradeReq miss cycles 866system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 239499 # number of SCUpgradeReq miss cycles 867system.cpu.l2cache.SCUpgradeReq_miss_latency::total 239499 # number of SCUpgradeReq miss cycles 868system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 39649987439 # number of ReadExReq miss cycles 869system.cpu.l2cache.ReadExReq_miss_latency::total 39649987439 # number of ReadExReq miss cycles 870system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 336423500 # number of demand (read+write) miss cycles 871system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345754750 # number of demand (read+write) miss cycles 872system.cpu.l2cache.demand_miss_latency::cpu.inst 5888588734 # number of demand (read+write) miss cycles 873system.cpu.l2cache.demand_miss_latency::cpu.data 61687292679 # number of demand (read+write) miss cycles 874system.cpu.l2cache.demand_miss_latency::total 68258059663 # number of demand (read+write) miss cycles 875system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 336423500 # number of overall miss cycles 876system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345754750 # number of overall miss cycles 877system.cpu.l2cache.overall_miss_latency::cpu.inst 5888588734 # number of overall miss cycles 878system.cpu.l2cache.overall_miss_latency::cpu.data 61687292679 # number of overall miss cycles 879system.cpu.l2cache.overall_miss_latency::total 68258059663 # number of overall miss cycles 880system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 383012 # number of ReadReq accesses(hits+misses) 881system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 255352 # number of ReadReq accesses(hits+misses) 882system.cpu.l2cache.ReadReq_accesses::cpu.inst 13856815 # number of ReadReq accesses(hits+misses) 883system.cpu.l2cache.ReadReq_accesses::cpu.data 6881009 # number of ReadReq accesses(hits+misses) 884system.cpu.l2cache.ReadReq_accesses::total 21376188 # number of ReadReq accesses(hits+misses) 885system.cpu.l2cache.Writeback_accesses::writebacks 7918344 # number of Writeback accesses(hits+misses) 886system.cpu.l2cache.Writeback_accesses::total 7918344 # number of Writeback accesses(hits+misses) 887system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1231947 # number of WriteInvalidateReq accesses(hits+misses) 888system.cpu.l2cache.WriteInvalidateReq_accesses::total 1231947 # number of WriteInvalidateReq accesses(hits+misses) 889system.cpu.l2cache.UpgradeReq_accesses::cpu.data 45609 # number of UpgradeReq accesses(hits+misses) 890system.cpu.l2cache.UpgradeReq_accesses::total 45609 # number of UpgradeReq accesses(hits+misses) 891system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) 892system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) 893system.cpu.l2cache.ReadExReq_accesses::cpu.data 2169953 # number of ReadExReq accesses(hits+misses) 894system.cpu.l2cache.ReadExReq_accesses::total 2169953 # number of ReadExReq accesses(hits+misses) 895system.cpu.l2cache.demand_accesses::cpu.dtb.walker 383012 # number of demand (read+write) accesses 896system.cpu.l2cache.demand_accesses::cpu.itb.walker 255352 # number of demand (read+write) accesses 897system.cpu.l2cache.demand_accesses::cpu.inst 13856815 # number of demand (read+write) accesses 898system.cpu.l2cache.demand_accesses::cpu.data 9050962 # number of demand (read+write) accesses 899system.cpu.l2cache.demand_accesses::total 23546141 # number of demand (read+write) accesses 900system.cpu.l2cache.overall_accesses::cpu.dtb.walker 383012 # number of overall (read+write) accesses 901system.cpu.l2cache.overall_accesses::cpu.itb.walker 255352 # number of overall (read+write) accesses 902system.cpu.l2cache.overall_accesses::cpu.inst 13856815 # number of overall (read+write) accesses 903system.cpu.l2cache.overall_accesses::cpu.data 9050962 # number of overall (read+write) accesses 904system.cpu.l2cache.overall_accesses::total 23546141 # number of overall (read+write) accesses 905system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011216 # miss rate for ReadReq accesses 906system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.017188 # miss rate for ReadReq accesses 907system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005692 # miss rate for ReadReq accesses 908system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.041978 # miss rate for ReadReq accesses 909system.cpu.l2cache.ReadReq_miss_rate::total 0.017609 # miss rate for ReadReq accesses 910system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.413551 # miss rate for WriteInvalidateReq accesses 911system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.413551 # miss rate for WriteInvalidateReq accesses 912system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783332 # miss rate for UpgradeReq accesses 913system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783332 # miss rate for UpgradeReq accesses 914system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 915system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 916system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.246582 # miss rate for ReadExReq accesses 917system.cpu.l2cache.ReadExReq_miss_rate::total 0.246582 # miss rate for ReadExReq accesses 918system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.011216 # miss rate for demand accesses 919system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.017188 # miss rate for demand accesses 920system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005692 # miss rate for demand accesses 921system.cpu.l2cache.demand_miss_rate::cpu.data 0.091032 # miss rate for demand accesses 922system.cpu.l2cache.demand_miss_rate::total 0.038711 # miss rate for demand accesses 923system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.011216 # miss rate for overall accesses 924system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.017188 # miss rate for overall accesses 925system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005692 # miss rate for overall accesses 926system.cpu.l2cache.overall_miss_rate::cpu.data 0.091032 # miss rate for overall accesses 927system.cpu.l2cache.overall_miss_rate::total 0.038711 # miss rate for overall accesses 928system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78310.870577 # average ReadReq miss latency 929system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78777.568922 # average ReadReq miss latency 930system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74653.440510 # average ReadReq miss latency 931system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76292.721671 # average ReadReq miss latency 932system.cpu.l2cache.ReadReq_avg_miss_latency::total 76001.212021 # average ReadReq miss latency 933system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 0.230621 # average WriteInvalidateReq miss latency 934system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 0.230621 # average WriteInvalidateReq miss latency 935system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.152322 # average UpgradeReq miss latency 936system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.152322 # average UpgradeReq miss latency 937system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 59874.750000 # average SCUpgradeReq miss latency 938system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 59874.750000 # average SCUpgradeReq miss latency 939system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74102.291918 # average ReadExReq miss latency 940system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74102.291918 # average ReadExReq miss latency 941system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78310.870577 # average overall miss latency 942system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78777.568922 # average overall miss latency 943system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74653.440510 # average overall miss latency 944system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74870.215638 # average overall miss latency 945system.cpu.l2cache.demand_avg_miss_latency::total 74886.487315 # average overall miss latency 946system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78310.870577 # average overall miss latency 947system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78777.568922 # average overall miss latency 948system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74653.440510 # average overall miss latency 949system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74870.215638 # average overall miss latency 950system.cpu.l2cache.overall_avg_miss_latency::total 74886.487315 # average overall miss latency 951system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 952system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 953system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 954system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 955system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 956system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 957system.cpu.l2cache.fast_writes 0 # number of fast writes performed 958system.cpu.l2cache.cache_copies 0 # number of cache copies performed 959system.cpu.l2cache.writebacks::writebacks 1135338 # number of writebacks 960system.cpu.l2cache.writebacks::total 1135338 # number of writebacks 961system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4296 # number of ReadReq MSHR misses 962system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4389 # number of ReadReq MSHR misses 963system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 78879 # number of ReadReq MSHR misses 964system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 288852 # number of ReadReq MSHR misses 965system.cpu.l2cache.ReadReq_mshr_misses::total 376416 # number of ReadReq MSHR misses 966system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 509473 # 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number of overall MSHR miss cycles 1006system.cpu.l2cache.overall_mshr_miss_latency::total 56862971337 # number of overall MSHR miss cycles 1007system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2248902500 # number of ReadReq MSHR uncacheable cycles 1008system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5287986500 # number of ReadReq MSHR uncacheable cycles 1009system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7536889000 # number of ReadReq MSHR uncacheable cycles 1010system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5166017500 # number of WriteReq MSHR uncacheable cycles 1011system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5166017500 # number of WriteReq MSHR uncacheable cycles 1012system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2248902500 # number of overall MSHR uncacheable cycles 1013system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10454004000 # number of overall MSHR uncacheable cycles 1014system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12702906500 # number of overall MSHR uncacheable cycles 1015system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for ReadReq accesses 1016system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for ReadReq accesses 1017system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for ReadReq accesses 1018system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.041978 # mshr miss rate for ReadReq accesses 1019system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017609 # mshr miss rate for ReadReq accesses 1020system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413551 # mshr miss rate for WriteInvalidateReq accesses 1021system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413551 # mshr miss rate for WriteInvalidateReq accesses 1022system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783332 # mshr miss rate for UpgradeReq accesses 1023system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783332 # mshr miss rate for UpgradeReq accesses 1024system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1025system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1026system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246582 # mshr miss rate for ReadExReq accesses 1027system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246582 # mshr miss rate for ReadExReq accesses 1028system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for demand accesses 1029system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for demand accesses 1030system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for demand accesses 1031system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091032 # mshr miss rate for demand accesses 1032system.cpu.l2cache.demand_mshr_miss_rate::total 0.038711 # mshr miss rate for demand accesses 1033system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for overall accesses 1034system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for overall accesses 1035system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for overall accesses 1036system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091032 # mshr miss rate for overall accesses 1037system.cpu.l2cache.overall_mshr_miss_rate::total 0.038711 # mshr miss rate for overall accesses 1038system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average ReadReq mshr miss latency 1039system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average ReadReq mshr miss latency 1040system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62136.636697 # average ReadReq mshr miss latency 1041system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63764.581031 # average ReadReq mshr miss latency 1042system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63475.943573 # average ReadReq mshr miss latency 1043system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21568.658213 # average WriteInvalidateReq mshr miss latency 1044system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21568.658213 # average WriteInvalidateReq mshr miss latency 1045system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.590282 # average UpgradeReq mshr miss latency 1046system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.590282 # average UpgradeReq mshr miss latency 1047system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 47500.250000 # average SCUpgradeReq mshr miss latency 1048system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 47500.250000 # average SCUpgradeReq mshr miss latency 1049system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61617.263057 # average ReadExReq mshr miss latency 1050system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61617.263057 # average ReadExReq mshr miss latency 1051system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency 1052system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency 1053system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency 1054system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency 1055system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency 1056system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency 1057system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency 1058system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency 1059system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency 1060system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency 1061system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1062system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1063system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1064system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1065system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1066system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1067system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1068system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1069system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1070system.cpu.toL2Bus.trans_dist::ReadReq 21819690 # Transaction distribution 1071system.cpu.toL2Bus.trans_dist::ReadResp 21811671 # Transaction distribution 1072system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution 1073system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution 1074system.cpu.toL2Bus.trans_dist::Writeback 7918344 # Transaction distribution 1075system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1338611 # Transaction distribution 1076system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1231947 # Transaction distribution 1077system.cpu.toL2Bus.trans_dist::UpgradeReq 45612 # Transaction distribution 1078system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution 1079system.cpu.toL2Bus.trans_dist::UpgradeResp 45616 # Transaction distribution 1080system.cpu.toL2Bus.trans_dist::ReadExReq 2169953 # Transaction distribution 1081system.cpu.toL2Bus.trans_dist::ReadExResp 2169953 # Transaction distribution 1082system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27799880 # Packet count per connected master and slave (bytes) 1083system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28711563 # Packet count per connected master and slave (bytes) 1084system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624328 # Packet count per connected master and slave (bytes) 1085system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1010117 # Packet count per connected master and slave (bytes) 1086system.cpu.toL2Bus.pkt_count::total 58145888 # Packet count per connected master and slave (bytes) 1087system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 887008660 # Cumulative packet size per connected master and slave (bytes) 1088system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1165125804 # Cumulative packet size per connected master and slave (bytes) 1089system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2042816 # Cumulative packet size per connected master and slave (bytes) 1090system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3064096 # Cumulative packet size per connected master and slave (bytes) 1091system.cpu.toL2Bus.pkt_size::total 2057241376 # Cumulative packet size per connected master and slave (bytes) 1092system.cpu.toL2Bus.snoops 474114 # Total snoops (count) 1093system.cpu.toL2Bus.snoop_fanout::samples 33215302 # Request fanout histogram 1094system.cpu.toL2Bus.snoop_fanout::mean 5.003479 # Request fanout histogram 1095system.cpu.toL2Bus.snoop_fanout::stdev 0.058876 # Request fanout histogram 1096system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1097system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1098system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1099system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1100system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1101system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1102system.cpu.toL2Bus.snoop_fanout::5 33099762 99.65% 99.65% # Request fanout histogram 1103system.cpu.toL2Bus.snoop_fanout::6 115540 0.35% 100.00% # Request fanout histogram 1104system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1105system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1106system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1107system.cpu.toL2Bus.snoop_fanout::total 33215302 # Request fanout histogram 1108system.cpu.toL2Bus.reqLayer0.occupancy 25772593750 # Layer occupancy (ticks) 1109system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1110system.cpu.toL2Bus.snoopLayer0.occupancy 1282500 # Layer occupancy (ticks) 1111system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1112system.cpu.toL2Bus.respLayer0.occupancy 20852498735 # Layer occupancy (ticks) 1113system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1114system.cpu.toL2Bus.respLayer1.occupancy 14430330552 # Layer occupancy (ticks) 1115system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1116system.cpu.toL2Bus.respLayer2.occupancy 369475750 # Layer occupancy (ticks) 1117system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1118system.cpu.toL2Bus.respLayer3.occupancy 627605250 # Layer occupancy (ticks) 1119system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1120system.iobus.trans_dist::ReadReq 40402 # Transaction distribution 1121system.iobus.trans_dist::ReadResp 40402 # Transaction distribution 1122system.iobus.trans_dist::WriteReq 136733 # Transaction distribution 1123system.iobus.trans_dist::WriteResp 30069 # Transaction distribution 1124system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution 1125system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) 1126system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1127system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1128system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1129system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1130system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1131system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1132system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1133system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1134system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1135system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1136system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1137system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1138system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1139system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1140system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) 1141system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231000 # Packet count per connected master and slave (bytes) 1142system.iobus.pkt_count_system.realview.ide.dma::total 231000 # Packet count per connected master and slave (bytes) 1143system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1144system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1145system.iobus.pkt_count::total 354270 # Packet count per connected master and slave (bytes) 1146system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) 1147system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1148system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1149system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1150system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1151system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1152system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1153system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1154system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1155system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1156system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1157system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 1158system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1159system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 1160system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1161system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) 1162system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334432 # Cumulative packet size per connected master and slave (bytes) 1163system.iobus.pkt_size_system.realview.ide.dma::total 7334432 # Cumulative packet size per connected master and slave (bytes) 1164system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1165system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1166system.iobus.pkt_size::total 7492838 # Cumulative packet size per connected master and slave (bytes) 1167system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) 1168system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1169system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1170system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1171system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 1172system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1173system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 1174system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1175system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1176system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1177system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1178system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1179system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1180system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1181system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1182system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1183system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 1184system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1185system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1186system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1187system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 1188system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1189system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 1190system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1191system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 1192system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1193system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 1194system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1195system.iobus.reqLayer27.occupancy 1042392405 # Layer occupancy (ticks) 1196system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1197system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1198system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1199system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) 1200system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1201system.iobus.respLayer3.occupancy 179042528 # Layer occupancy (ticks) 1202system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1203system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) 1204system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1205system.iocache.tags.replacements 115480 # number of replacements 1206system.iocache.tags.tagsinuse 10.457351 # Cycle average of tags in use 1207system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1208system.iocache.tags.sampled_refs 115496 # Sample count of references to valid blocks. 1209system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1210system.iocache.tags.warmup_cycle 13153949219000 # Cycle when the warmup percentage was hit. 1211system.iocache.tags.occ_blocks::realview.ethernet 3.511147 # Average occupied blocks per requestor 1212system.iocache.tags.occ_blocks::realview.ide 6.946204 # Average occupied blocks per requestor 1213system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy 1214system.iocache.tags.occ_percent::realview.ide 0.434138 # Average percentage of cache occupancy 1215system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy 1216system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1217system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1218system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1219system.iocache.tags.tag_accesses 1039857 # Number of tag accesses 1220system.iocache.tags.data_accesses 1039857 # Number of data accesses 1221system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1222system.iocache.ReadReq_misses::realview.ide 8836 # number of ReadReq misses 1223system.iocache.ReadReq_misses::total 8873 # number of ReadReq misses 1224system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1225system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1226system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses 1227system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses 1228system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1229system.iocache.demand_misses::realview.ide 8836 # number of demand (read+write) misses 1230system.iocache.demand_misses::total 8876 # number of demand (read+write) misses 1231system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1232system.iocache.overall_misses::realview.ide 8836 # number of overall misses 1233system.iocache.overall_misses::total 8876 # number of overall misses 1234system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles 1235system.iocache.ReadReq_miss_latency::realview.ide 1916450860 # number of ReadReq miss cycles 1236system.iocache.ReadReq_miss_latency::total 1921935860 # number of ReadReq miss cycles 1237system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles 1238system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles 1239system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28823836017 # number of WriteInvalidateReq miss cycles 1240system.iocache.WriteInvalidateReq_miss_latency::total 28823836017 # number of WriteInvalidateReq miss cycles 1241system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles 1242system.iocache.demand_miss_latency::realview.ide 1916450860 # number of demand (read+write) miss cycles 1243system.iocache.demand_miss_latency::total 1922274860 # number of demand (read+write) miss cycles 1244system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles 1245system.iocache.overall_miss_latency::realview.ide 1916450860 # number of overall miss cycles 1246system.iocache.overall_miss_latency::total 1922274860 # number of overall miss cycles 1247system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1248system.iocache.ReadReq_accesses::realview.ide 8836 # number of ReadReq accesses(hits+misses) 1249system.iocache.ReadReq_accesses::total 8873 # number of ReadReq accesses(hits+misses) 1250system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1251system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1252system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) 1253system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) 1254system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1255system.iocache.demand_accesses::realview.ide 8836 # number of demand (read+write) accesses 1256system.iocache.demand_accesses::total 8876 # number of demand (read+write) accesses 1257system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1258system.iocache.overall_accesses::realview.ide 8836 # number of overall (read+write) accesses 1259system.iocache.overall_accesses::total 8876 # number of overall (read+write) accesses 1260system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1261system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1262system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1263system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1264system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1265system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1266system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1267system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1268system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1269system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1270system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1271system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1272system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1273system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency 1274system.iocache.ReadReq_avg_miss_latency::realview.ide 216891.224536 # average ReadReq miss latency 1275system.iocache.ReadReq_avg_miss_latency::total 216604.965626 # average ReadReq miss latency 1276system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency 1277system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency 1278system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270230.218415 # average WriteInvalidateReq miss latency 1279system.iocache.WriteInvalidateReq_avg_miss_latency::total 270230.218415 # average WriteInvalidateReq miss latency 1280system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency 1281system.iocache.demand_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency 1282system.iocache.demand_avg_miss_latency::total 216569.948175 # average overall miss latency 1283system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency 1284system.iocache.overall_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency 1285system.iocache.overall_avg_miss_latency::total 216569.948175 # average overall miss latency 1286system.iocache.blocked_cycles::no_mshrs 223291 # number of cycles access was blocked 1287system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1288system.iocache.blocked::no_mshrs 27458 # number of cycles access was blocked 1289system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1290system.iocache.avg_blocked_cycles::no_mshrs 8.132093 # average number of cycles each access was blocked 1291system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1292system.iocache.fast_writes 0 # number of fast writes performed 1293system.iocache.cache_copies 0 # number of cache copies performed 1294system.iocache.writebacks::writebacks 106629 # number of writebacks 1295system.iocache.writebacks::total 106629 # number of writebacks 1296system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1297system.iocache.ReadReq_mshr_misses::realview.ide 8836 # number of ReadReq MSHR misses 1298system.iocache.ReadReq_mshr_misses::total 8873 # number of ReadReq MSHR misses 1299system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1300system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1301system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses 1302system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses 1303system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1304system.iocache.demand_mshr_misses::realview.ide 8836 # number of demand (read+write) MSHR misses 1305system.iocache.demand_mshr_misses::total 8876 # number of demand (read+write) MSHR misses 1306system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1307system.iocache.overall_mshr_misses::realview.ide 8836 # number of overall MSHR misses 1308system.iocache.overall_mshr_misses::total 8876 # number of overall MSHR misses 1309system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles 1310system.iocache.ReadReq_mshr_miss_latency::realview.ide 1456881862 # number of ReadReq MSHR miss cycles 1311system.iocache.ReadReq_mshr_miss_latency::total 1460442862 # number of ReadReq MSHR miss cycles 1312system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles 1313system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles 1314system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23277254071 # number of WriteInvalidateReq MSHR miss cycles 1315system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23277254071 # number of WriteInvalidateReq MSHR miss cycles 1316system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles 1317system.iocache.demand_mshr_miss_latency::realview.ide 1456881862 # number of demand (read+write) MSHR miss cycles 1318system.iocache.demand_mshr_miss_latency::total 1460625862 # number of demand (read+write) MSHR miss cycles 1319system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles 1320system.iocache.overall_mshr_miss_latency::realview.ide 1456881862 # number of overall MSHR miss cycles 1321system.iocache.overall_mshr_miss_latency::total 1460625862 # number of overall MSHR miss cycles 1322system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1323system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1324system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1325system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1326system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1327system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1328system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1329system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1330system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1331system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1332system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1333system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1334system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1335system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency 1336system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164880.246944 # average ReadReq mshr miss latency 1337system.iocache.ReadReq_avg_mshr_miss_latency::total 164594.033810 # average ReadReq mshr miss latency 1338system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency 1339system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 1340system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.712658 # average WriteInvalidateReq mshr miss latency 1341system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.712658 # average WriteInvalidateReq mshr miss latency 1342system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency 1343system.iocache.demand_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency 1344system.iocache.demand_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency 1345system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency 1346system.iocache.overall_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency 1347system.iocache.overall_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency 1348system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1349system.membus.trans_dist::ReadReq 462201 # Transaction distribution 1350system.membus.trans_dist::ReadResp 462201 # Transaction distribution 1351system.membus.trans_dist::WriteReq 33872 # Transaction distribution 1352system.membus.trans_dist::WriteResp 33872 # Transaction distribution 1353system.membus.trans_dist::Writeback 1241967 # Transaction distribution 1354system.membus.trans_dist::WriteInvalidateReq 616132 # Transaction distribution 1355system.membus.trans_dist::WriteInvalidateResp 616132 # Transaction distribution 1356system.membus.trans_dist::UpgradeReq 36293 # Transaction distribution 1357system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution 1358system.membus.trans_dist::UpgradeResp 36297 # Transaction distribution 1359system.membus.trans_dist::ReadExReq 534513 # Transaction distribution 1360system.membus.trans_dist::ReadExResp 534513 # Transaction distribution 1361system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) 1362system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1363system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) 1364system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4139437 # Packet count per connected master and slave (bytes) 1365system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4269627 # Packet count per connected master and slave (bytes) 1366system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335126 # Packet count per connected master and slave (bytes) 1367system.membus.pkt_count_system.iocache.mem_side::total 335126 # Packet count per connected master and slave (bytes) 1368system.membus.pkt_count::total 4604753 # Packet count per connected master and slave (bytes) 1369system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) 1370system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1371system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) 1372system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163718240 # Cumulative packet size per connected master and slave (bytes) 1373system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163888576 # Cumulative packet size per connected master and slave (bytes) 1374system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14053504 # Cumulative packet size per connected master and slave (bytes) 1375system.membus.pkt_size_system.iocache.mem_side::total 14053504 # Cumulative packet size per connected master and slave (bytes) 1376system.membus.pkt_size::total 177942080 # Cumulative packet size per connected master and slave (bytes) 1377system.membus.snoops 3244 # Total snoops (count) 1378system.membus.snoop_fanout::samples 2814199 # Request fanout histogram 1379system.membus.snoop_fanout::mean 1 # Request fanout histogram 1380system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1381system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1382system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1383system.membus.snoop_fanout::1 2814199 100.00% 100.00% # Request fanout histogram 1384system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1385system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1386system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1387system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1388system.membus.snoop_fanout::total 2814199 # Request fanout histogram 1389system.membus.reqLayer0.occupancy 106092500 # Layer occupancy (ticks) 1390system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1391system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) 1392system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1393system.membus.reqLayer2.occupancy 5680000 # Layer occupancy (ticks) 1394system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1395system.membus.reqLayer5.occupancy 17856822743 # Layer occupancy (ticks) 1396system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1397system.membus.respLayer2.occupancy 9254301682 # Layer occupancy (ticks) 1398system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1399system.membus.respLayer3.occupancy 186599472 # Layer occupancy (ticks) 1400system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1401system.realview.ethernet.txBytes 966 # Bytes Transmitted 1402system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1403system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1404system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1405system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1406system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1407system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1408system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1409system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1410system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 1411system.realview.ethernet.totPackets 3 # Total Packets 1412system.realview.ethernet.totBytes 966 # Total Bytes 1413system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1414system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 1415system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1416system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1417system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1418system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1419system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1420system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1421system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1422system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1423system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1424system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1425system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1426system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1427system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1428system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1429system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1430system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1431system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1432system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1433system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1434system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1435system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1436system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1437system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1438system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1439system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1440system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1441system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1442system.realview.ethernet.droppedPackets 0 # number of packets dropped 1443 1444---------- End Simulation Statistics ---------- 1445